INA849
INA849
SBOS945B – NOVEMBER 2020 – REVISED APRIL
2021
SBOS945B – NOVEMBER 2020 – REVISED APRIL 2021
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INA849 Ultra-Low-Noise (1 nV/√Hz), High-Bandwidth, Instrumentation Amplifier
1 Features
3 Description
•
The INA849 is an ultra-low noise instrumentation
amplifier optimized for maximum accuracy in highresolution systems and operation over a wide singlesupply or dual-supply range. The device offers
significantly lower input bias current than competitors
as a result of super-beta input transistors. A state-ofthe-art manufacturing process provides exceptionally
low voltage noise, input offset voltage, and offset
voltage drift.
•
•
•
•
•
•
•
Ultra-low noise: 1-nV/√Hz input voltage noise
(typical)
Precision super-beta input performance:
– Low offset voltage: 35 µV (maximum)
– Low offset voltage drift: 0.4 μV/°C (maximum)
– Low input bias current: 20 nA (maximum)
– Low gain drift: 5 ppm/°C for G = 1 (maximum)
Bandwidth: 28 MHz (G = 1), 8 MHz (G = 100)
Slew rate: 35 V/µs
Common-mode rejection: 120 dB (minimum) for
maximum gain
Supply range:
– Single supply: 8 V to 36 V
– Dual supply: ±4 V to ±18 V
Specified temperature range:
–40°C to +125°C
Packages: 8-pin SOIC and VSSOP
Precisely matched integrated resistors provide a high,
92-dB (G = 1) common-mode rejection across the full
input common-mode range. A single external resistor
sets any gain from 1 to 10,000. The current-feedback
topology of the INA849 provides wide bandwidth at
higher gains for very-small, fast-moving signals. For
example, the device provides 8 MHz of bandwidth
at G = 100, and 28 MHz at a G = 1, with a fast
0.4-µs settling time (0.01%) for directly driving highresolution, analog-to-digital converters (ADCs).
2 Applications
•
•
•
•
•
•
•
•
Analog input module
Microphone preamplifier
Flow transmitter
Battery test
LCD test
Electrocardiogram (ECG)
Surgical equipment
Process analytics (pH, gas, concentration, force
and humidity)
Device Information
PART NUMBER
INA849
(1)
PACKAGE(1)
BODY SIZE (NOM)
SOIC (8)
4.90 mm × 3.91 mm
VSSOP (8)
3.00 mm × 3.00 mm
See the package option addendum at the end of the data
sheet for all available packages.
+VS
100 nF
+VS
íIN
+
RG
±
5k
5k
3k
±
3k
+
RG
RG
+IN
OUT
VO
G V
IN
V
IN
VREF
±
+
5k
íVS
5k
REF
100 nF
íVS
INA849 Simplified Internal Schematic
Input-Referred Voltage Noise Spectral Density vs
Frequency
An©IMPORTANT
NOTICEIncorporated
at the end of this data sheet addresses availability, warranty, changes, use in
safety-critical
applications,
Copyright
2021 Texas Instruments
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SBOS945B – NOVEMBER 2020 – REVISED APRIL 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings ....................................... 4
7.2 ESD Ratings .............................................................. 4
7.3 Recommended Operating Conditions ........................4
7.4 Thermal Information ...................................................5
7.5 Electrical Characteristics ............................................5
7.6 Typical Characteristics................................................ 8
8 Detailed Description......................................................16
8.1 Overview................................................................... 16
8.2 Functional Block Diagram......................................... 16
8.3 Feature Description...................................................17
8.4 Device Functional Modes..........................................18
9 Application and Implementation.................................. 19
9.1 Application Information............................................. 19
9.2 Typical Application.................................................... 23
10 Power Supply Recommendations..............................25
11 Layout........................................................................... 25
11.1 Layout Guidelines................................................... 25
11.2 Layout Example...................................................... 26
12 Device and Documentation Support..........................27
12.1 Documentation Support.......................................... 27
12.2 Receiving Notification of Documentation Updates..27
12.3 Support Resources................................................. 27
12.4 Trademarks............................................................. 27
12.5 Electrostatic Discharge Caution..............................27
12.6 Glossary..................................................................27
13 Mechanical, Packaging, and Orderable
Information.................................................................... 27
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (December 2020) to Revision B (April 2021)
Page
• Changed DGK (VSSOP-8) package from advanced information (preview) to production data (active) ............1
• Changed typical value of current noise from 1.6 pA/√Hz to 1.1 pA/√(Hz).......................................................... 5
• Added note 9...................................................................................................................................................... 5
• Changed Figure 7-25, Current Noise Spectral Density vs Frequency (RTI) ......................................................8
• Changed Figure 7-42, Total Harmonic Distortion vs Frequency ........................................................................ 8
• Changed Figure 7-43, Total Harmonic Distortion vs Frequency at Different Loads ...........................................8
• Changed Figure 7-44, Second Harmonic Distortion vs Frequency ................................................................... 8
• Changed Figure 7-45, Third Harmonic Distortion vs Frequency ....................................................................... 8
Changes from Revision * (November 2020) to Revision A (December 2020)
Page
• Changed INA849 device from advanced information (preview) to production data (active)...............................1
• Added preview DGK package and associated content.......................................................................................1
2
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5 Device Comparison Table
DEVICE
DESCRIPTION
GAIN EQUATION
RG PINS AT PIN
G = 0.2 V/V
N/A
35-µV offset, 0.4-µV/°C VOS drift, 8-nV/√Hz noise, low-power, precision
instrumentation amplifier
G = 1 + 50 kΩ / RG
2, 3
INA818
35-µV offset, 0.4-µV/°C VOS drift, 8-nV/√Hz noise, low-power, precision
instrumentation amplifier
G = 1 + 50 kΩ / RG
1, 8
INA821
35-µV offset, 0.4-µV/°C VOS drift, 7-nV/√Hz noise, high-bandwidth,
precision instrumentation amplifier
G = 1 + 49.4 kΩ / RG
2, 3
INA828
50-µV offset, 0.5-µV/°C VOS drift, 7-nV/√Hz noise, low-power, precision
instrumentation amplifier
G = 1 + 50 kΩ / RG
1, 8
INA333
25-µV VOS, 0.1-µV/°C VOS drift, 1.8-V to 5-V, RRO, 50-µA IQ, chopperstabilized INA
G = 1 + 100 kΩ / RG
1, 8
INA848
Ultra-low-noise (1.5-nV/√Hz), high-bandwidth instrumentation amplifier with
fixed gain of 2000
G = 2000 V/V
N/A
PGA280
Zero-drift, high-voltage programmable gain instrumentation amplifier with
signal integrity test capability (overload detection, input switch matrix, wire
break test, SPI with checksum, GPIO ports)
Digitally programmable
N/A
PGA112
Precision programmable gain op amp with SPI
Digitally programmable
N/A
INA159
G = 0.2 V differential amplifier for ±10-V to 3-V and 5-V conversion
INA819
6 Pin Configuration and Functions
±IN
1
8
+VS
RG
2
7
OUT
RG
3
6
REF
+IN
4
5
±VS
Not to scale
Figure 6-1. D Package (8-Pin SOIC) and DGK Package (8-Pin VSSOP), Top View
Table 6-1. Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
–IN
1
I
Negative (inverting) input
+IN
4
I
Positive (noninverting) input
OUT
7
O
Output
RG
2, 3
—
Gain setting pin. Place a gain resistor between pin 2 and pin 3.
REF
6
I
–VS
5
—
Negative supply
+VS
8
—
Positive supply
Reference input. This pin must be driven by a low impedance source.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
VS
Supply voltage
VI
Signal input pins
MAX
Single supply, VS = (+VS)
40
Dual supply, VS = (+VS) – (–VS)
±20
Voltage
(–VS ) – 0.5
(+VS) + 0.5
Current
–10
+10
Gain ≤ 4
Signal differential input voltage
4 < Gain < 50
–VS
+VS
(–VS) / Gain
(+VS) / Gain
–1 V
+1 V
Gain > 50
UNIT
V
V
mA
V
VREF
Reference input voltage
(–VS ) – 0.5
(+VS) + 0.5
V
VO
Signal output voltage
(–VS) – 0.5
(+VS) + 0.5
V
IS
Output short-circuit(2)
Continuous
TA
Operating temperature(3)
–40
125
°C
TJ
Junction temperature(3)
–40
175
°C
Tstg
Storage temperature
–65
150
°C
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
Short-circuit to VS / 2.
As a result of the quiescent current, the supply voltage and load-dependent self-heating of the device must be considered.
7.2 ESD Ratings
UNIT
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V
±750
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
4
VS
Supply voltage
TA
Specified temperature
Single supply, VS = (+VS)
Dual supply, VS = (+VS) – (–VS)
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MIN
MAX
8
36
±4
±18
–40
125
UNIT
V
°C
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7.4 Thermal Information
THERMAL METRIC(1)
INA849
INA849
D (SOIC)
DGK (VSSOP)
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
119.6
168.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
66.3
61.4
°C/W
RθJB
Junction-to-board thermal resistance
61.9
90.0
°C/W
ψJT
Junction-to-top characterization parameter
20.5
8.4
°C/W
ψJB
Junction-to-board characterization parameter
61.4
88.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, connected to ground, VREF = 0 V, VCM = 0 V, and G = 1 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
10
35
UNIT
INPUT
VOSI
Input stage offset voltage(1) (3)
Input stage offset voltage drift
VOSO
Output stage offset voltage(1) (3)
Output stage offset voltage drift
TA = –40°C to +125°C(2)
TA = –40°C to +125°C
Power-supply rejection ratio
Zin
Input impedance
CMRR
Operating input range(4)
Common-mode rejection ratio
0.4
50
500
2000
TA = –40°C to +125°C(2)
15
106
120
G = 10, RTI
114
120
G = 100, RTI
121
126
G = 1000, RTI
123
RFI filter, –3-dB frequency
VCM
0.1
TA = –40°C to +125°C(2)
G = 1, RTI
PSRR
75
µV/°C
µV
µV/°C
dB
128
1 || 7
GΩ || pF
220
MHz
(–VS) + 2.5
VS = ±4 V to ±18 V
µV
(+VS) – 2.5
See Figure 8-2 and Figure 8-3
At dc to 60 Hz, RTI,
VCM = (V–) + 2.5 V to (V+) – 2.5 V,
G=1
92
110
At dc to 60 Hz, RTI,
VCM = (V–) + 2.5 V to (V+) – 2.5 V,
G = 10
112
125
At dc to 60 Hz, RTI,
VCM = (V–) + 2.5 V to (V+) – 2.5 V,
G = 100
120
127
At dc to 60 Hz, RTI,
VCM = (V–) + 2.5 V to (V+) – 2.5 V,
G = 1000
120
127
V
dB
BIAS CURRENT
IB
IOS
Input bias current
VCM = VS / 2
Input bias current drift
TA = –40°C to +125°C
Input offset current
VCM = VS / 2
Input offset current drift
TA = –40°C to +125°C
10
20
nA
80
pA/°C
6
5
nA
pA/°C
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7.5 Electrical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, connected to ground, VREF = 0 V, VCM = 0 V, and G = 1 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
NOISE VOLTAGE
eNI
Input stage voltage
noise(8)
Output stage voltage noise(8)
eNO
iN
Current noise
f = 1 kHz, G = 1000,
RS = 0 Ω
1
fB = 0.1 Hz to 10 Hz, G = 1000,
RS = 0 Ω
nV/√Hz
0.06
µVPP
f = 1 kHz, RS = 0 Ω
45
nV/√Hz
fB = 0.1 Hz to 10 Hz,
RS = 0 Ω
5
µVPP
f=1
kHz(9)
fB = 0.1 Hz to 10 Hz
1.1
pA/√Hz
100
pAPP
GAIN
G
Gain equation
1 + (6 kΩ / RG)
Gain
GE
Gain error
1
(7)
Gain error drift(5)
Gain nonlinearity
V/V
10000
G = 1, VO = ±10 V
±0.005
G = 10, VO = ±10 V
±0.025
±0.1
G = 100, VO = ±10 V
±0.025
±0.1
G = 1000, VO = ±10 V
±0.05
G = 1, TA = –40°C to +125°C
±5
G > 1, TA = –40°C to +125°C
±35
G = 1, VO = –10 V to +10 V
3
(6)
G = 10 , VO = –10 V to +10 V
V/V
±0.025
%
ppm/°C
ppm
10
THD
Total harmonic distortion
f = 1 kHz, VO = 10 VPP
127
dBc
HD2
Second-order harmonic distortion
f = 1 kHz, VO = 10 VPP
127
dBc
HD3
Third-order harmonic distortion
f = 1 kHz, VO = 10 VPP
157
dBc
THD
Total harmonic distortion
f = 10 kHz, VO = 10 VPP
119
dBc
HD2
Second-order harmonic distortion
f = 10 kHz, VO = 10 VPP
130
dBc
HD3
Third-order harmonic distortion
f = 10 kHz, VO = 10 VPP
120
dBc
Voltage swing
RL = 10 kΩ
OUTPUT
Load capacitance stability
(V–) + 0.15
(V+) – 0.15
200
V
pF
ZO
Closed-loop output impedance
f = 1 MHz
1.5
Ω
ISC
Short-circuit current
Continuous to VS / 2
±34
mA
FREQUENCY RESPONSE
BW
Bandwidth, –3 dB
G=1
28
G = 10
13
G = 100
8
G = 1000
SR
tS
6
Slew rate
Settling time
1.25
G = 1, VSTEP = 10 V
35
0.01%, G = 1 to 100,
VSTEP = 10 V
0.4
0.01%, G = 1000,
VSTEP = 10 V
0.4
0.001%, G = 1 to 100,
VSTEP = 10 V
0.6
0.001%, G = 1000,
VSTEP = 10 V
1.5
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V/µs
µs
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7.5 Electrical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, connected to ground, VREF = 0 V, VCM = 0 V, and G = 1 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
REFERENCE INPUT
RIN
Input impedance
10
Input current
80
Reference input voltage
(V–)
Gain to output
kΩ
µA
(V+)
1
Reference gain error
VO = ±10 V, inside the voltage swing
range
0.01
V
V/V
0.05
%
POWER SUPPLY
IQ
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
Quiescent current
(7)
VIN = 0 V
TA = –40°C to +125°C
6.2
6.6
8.9
mA
Total offset, referred-to-input (RTI): VOS = (VOSI) + (VOSO / G).
Specified by characterization. Not tested in production.
Offset drifts are uncorrelated. Input-referred offset drift is calculated using: ΔVOS(RTI) = √[ΔVOSI 2 + (ΔVOSO / G)2].
Input voltage range of the input stage. The input range depends on the common-mode voltage, differential voltage, gain, and reference
voltage; see Figure 7-12.
The values specified for G > 1 do not include the effects of the external gain resistor, RG.
Thermal effects can degrade input stage nonlinearity and thus can scale with gain; See Figure 9-5.
This parameter is tested in a high speed automatic test environment and does not measure the thermal effects with a longer a time
constant. The thermal effect depends on supply voltage, layout, heat sinking and air flow conditions.
Total RTI voltage noise is equal to: eN(RTI) = √[eNI 2 + (eNO / G)2].
Input current noise density specified for unbalanced input impedance. Bias current cancellation improves noise performance for
balanced systems; See Figure 7-25.
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7.6 Typical Characteristics
at TA = 25°C, VS = ±15 V, VCM at mid-supply, VRL = 10 kΩ, connected to ground, VREF = 0 V, and G = 1 (unless otherwise
noted)
N = 1695, mean = 0.26 µV, std dev = 5.85 µV
N = 30, mean = 0.10 µV/°C, std dev = 0.08 µV/°C
Figure 7-1. Typical Distribution of Input Offset Voltage
N = 1695, mean = -43.83 µV, std dev = 111.74 µV
Figure 7-3. Typical Distribution of Output Offset Voltage
N = 120, mean = 7.58 nA, std dev = 1.84 nA
N = 120, mean = -4.14 µV/°C, std dev = 2.00 µV/°C
Figure 7-4. Typical Distribution of Output Offset Voltage Drift
N = 120, mean = 7.24 nA, std dev = 1.80 nA
Figure 7-5. Typical Distribution of Input Bias Current
8
Figure 7-2. Typical Distribution of Input Offset Voltage Drift
Figure 7-6. Typical Distribution of Input Bias Current at 85°C
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7.6 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, VCM at mid-supply, VRL = 10 kΩ, connected to ground, VREF = 0 V, and G = 1 (unless otherwise
noted)
N = 120, mean = -0.11 nA, std dev = 1.01 nA
N = 120, mean = 3.08 µV/V, std dev = 5.57 µV/V
Figure 7-7. Typical Distribution of Input Offset Current
Figure 7-8. Typical CMRR Distribution G = 1
N = 120, mean = -0.375 µV/V, std dev = 0.043 µV/V
Figure 7-9. Typical CMRR Distribution G = 100
N = 120
Figure 7-10. Input Stage Offset Voltage vs Temperature
N = 120
VREF = 0 V
Figure 7-11. Output Stage Offset Voltage vs Temperature
Figure 7-12. Boundary Plot - Input Common-Mode Voltage vs
Output Voltage
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7.6 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, VCM at mid-supply, VRL = 10 kΩ, connected to ground, VREF = 0 V, and G = 1 (unless otherwise
noted)
10
Figure 7-13. Output-referred Offset Voltage vs Negative Input
Common-Mode Voltage
Figure 7-14. Output-referred Offset Voltage vs Positive Input
Common-Mode Voltage
Figure 7-15. Positive Input Bias Current vs Input CommonMode Voltage
Figure 7-16. Negative Input Bias Current vs Input CommonMode Voltage
Figure 7-17. Input Offset Current vs Input Common-Mode
Voltage
Figure 7-18. Input Bias Current vs Temperature
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7.6 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, VCM at mid-supply, VRL = 10 kΩ, connected to ground, VREF = 0 V, and G = 1 (unless otherwise
noted)
Figure 7-19. Input Offset Current vs Temperature
Figure 7-20. CMRR vs Frequency (RTI)
Figure 7-21. CMRR vs Frequency (1-kΩ source imbalance)
Figure 7-22. Positive PSRR vs Frequency (RTI)
Figure 7-23. Negative PSRR vs Frequency (RTI)
Figure 7-24. Voltage Noise Spectral Density vs Frequency (RTI)
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7.6 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, VCM at mid-supply, VRL = 10 kΩ, connected to ground, VREF = 0 V, and G = 1 (unless otherwise
noted)
G=1
Figure 7-25. Current Noise Spectral Density vs Frequency (RTI)
Figure 7-26. 0.1-Hz to 10-Hz RTI Voltage Noise
G = 1000
Figure 7-27. 0.1-Hz to 10-Hz RTI Voltage Noise
Figure 7-28. 0.1-Hz to 10-Hz RTI Current Noise
G=1
G = 10
Figure 7-29. Gain Nonlinearity vs Output Voltage
12
Figure 7-30. Gain Nonlinearity vs Output Voltage
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7.6 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, VCM at mid-supply, VRL = 10 kΩ, connected to ground, VREF = 0 V, and G = 1 (unless otherwise
noted)
Figure 7-31. Closed-Loop Gain vs Frequency
Figure 7-32. Closed-Loop Output Impedance vs Frequency
Figure 7-33. Large-Signal Frequency Response
Figure 7-34. Overshoot vs Capacitive Loads
G = 1, CL = 100 pF
G = 10, CL = 100 pF
Figure 7-35. Small-Signal Step Response at G = 1
Figure 7-36. Small-Signal Step Response at G = 10
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7.6 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, VCM at mid-supply, VRL = 10 kΩ, connected to ground, VREF = 0 V, and G = 1 (unless otherwise
noted)
G = 100, CL = 100 pF
G = 1000, CL = 100 pF
Figure 7-37. Small-Signal Step Response at G = 100
G=1
VSTEP = 10 V
Figure 7-38. Small-Signal Step Response at G = 1000
G = 100
Figure 7-39. Settling Time for G = 1
G = 1000
Figure 7-40. Settling Time for G = 100
VSTEP = 10 V
Figure 7-41. Settling Time for G = 1000
14
VSTEP = 10 V
Figure 7-42. Total Harmonic Distortion vs Frequency
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7.6 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, VCM at mid-supply, VRL = 10 kΩ, connected to ground, VREF = 0 V, and G = 1 (unless otherwise
noted)
0.001
-100
0.0001
-120
0.00001
20
200
2k
Amplitude (dB)
Amplitude (% of Fundamental)
HD2 (%), G = 1
HD2 (%), G = 10
-140
20k
Frequency (Hz)
Figure 7-44. Second Harmonic Distortion vs Frequency
Figure 7-43. Total Harmonic Distortion vs Frequency at
Different Loads
0.001
-100
0.0001
-120
0.00001
-140
0.000001
20
200
2k
Amplitude (dB)
Amplitude (% of Fundamental)
HD3 (%), G = 1
HD3 (%), G = 10
-160
20k
Frequency (Hz)
Figure 7-45. Third Harmonic Distortion vs Frequency
Figure 7-46. Supply Current vs Temperature
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8 Detailed Description
8.1 Overview
The INA849 is a monolithic, precision, instrumentation amplifier that incorporates a current-feedback input stage
and a four-resistor difference amplifier output stage. The functional block diagram in the next section shows how
the differential input voltage is buffered by Q1 and Q 2, and is forced across RG, which causes a signal current to
flow through RG, R1, and R2. The output difference amplifier, A3, removes the common-mode component of the
input signal and refers the output signal to the REF pin. The VBE and voltage drop across R1 and R2 produce
output voltages on A1 and A2 that are approximately 0.8 V lower than the input voltages.
8.2 Functional Block Diagram
+VS
VB
RB
IB Cancellation
RB
IB Cancellation
+VS
R3
5k
A2
C1
íVS
±
A1
±
+
A3
C2
OUT
+
±
+
R5
5k
R4
5k
REF
R6
5k
+VS
+VS
íVS
Q1
íIN
SuperNPN
+VS
+VS
SuperNPN
Q2
+IN
R2
3k
R1
3k
íVS
íVS
RG
íVS
16
+VS
RG
RG
íVS
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8.3 Feature Description
8.3.1 Adjustable Gain Setting
Figure 8-1 shows that the gain of the INA849 is set by a single external resistor (RG) connected between the RG
pins (pins 2 and 3).
+VS
100 nF
+VS
íIN
+
RG
±
5k
5k
3k
±
3k
+
RG
RG
+IN
OUT
VO
G V
IN
V
IN
VREF
±
+
5k
íVS
REF
5k
100 nF
íVS
Figure 8-1. Simplified Diagram of the INA849 with Output Equation
The value of RG is selected according to the following equation:
G = 1+
6 NŸ
RG
(1)
Table 8-1 lists several commonly used gains and resistor values. The 6-kΩ term in Equation 1 is a result of the
sum of the two internal 3-kΩ feedback resistors. These on-chip resistors are laser-trimmed to accurate, absolute
values. The accuracy and temperature coefficients of these resistors are included in the gain accuracy and drift
specifications of the INA849.
Table 8-1. Commonly Used Gains and Resistor Values
DESIRED GAIN (V/V)
STANDARD 1% RG (Ω)
CALCULATED GAIN
(V/V)
CALCULATED GAIN
ERROR (%)
1
Not connected
N/A
N/A
2
6.04 k
1.9933
0.33
5
1.50 k
5
0
10
665
10.022
–0.23
20
316
19.987
0.06
50
121
50.586
–1.17
100
60.4
100.337
–0.34
200
30.1
200.335
–0.17
500
12.1
496.867
0.63
1000
6.04
994.377
0.56
The 5-kΩ feedback resistors in the output stage are ratiometrically matched to achieve unity-gain stability. These
resistors may shift up to 15% depending on production.
As shown in Figure 8-1 and explained in more detail in Figure 11-1, make sure to connect low-ESR, 0.1-µF,
ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible.
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8.3.2 Gain Drift
The stability and temperature drift of external gain setting resistor RG also affects gain. The contribution of RG to
gain accuracy and drift is determined from Equation 1.
The best gain drift of 5 ppm/℃ (maximum) is achieved when the INA849 uses G = 1 without RG connected. In
this case, gain drift is limited by the mismatch of the temperature coefficient of the integrated 5-kΩ resistors in
differential amplifier A3. At gains greater than 1, gain drift increases as a result of the individual drift of the 3-kΩ
resistors in the feedback of A1 and A2, relative to the drift of external gain resistor RG.
The low temperature coefficient of the internal feedback resistors improves the overall temperature stability of
applications using gains greater than 1 V/V over alternate solutions.
The low resistor values required for high gain make wiring resistance an important consideration. Sockets add
to the wiring resistance and contribute additional gain error (such as a possible unstable gain error) at gains of
approximately 100 or greater.
To maintain stability, avoid parasitic capacitance of more than a few picofarads at the RG connections. Careful
matching of any parasitics on the RG pins maintains optimal CMRR over frequency.
8.3.3 Wide Input Common-Mode Range
The linear input voltage range of the INA849 input circuitry extends within 2.5 V (maximum) of both power
supplies, and maintains excellent common-mode rejection throughout this range. The common-mode range
for the most common operating conditions are shown in Figure 8-2 and Figure 8-3. The common-mode
range for other operating conditions is best calculated using the Common-Mode Input Range Calculator for
Instrumentation Amplifiers.
VS = ±5 V, ±12 V, ±18 V
G=1
VS = ±5 V, ±12 V, ±18 V
G = 100
Figure 8-2. Input Common-Mode Voltage vs Output Figure 8-3. Input Common-Mode Voltage vs Output
Voltage
Voltage
8.4 Device Functional Modes
The INA849 has a single functional mode and is operational when the power-supply voltage is greater than 8 V
(±4 V). The maximum power-supply voltage for the INA849 is 36 V (±18 V).
18
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
9.1.1 Reference Pin
The output voltage of the INA849 is developed with respect to the voltage on reference pin REF.
Use the REF pin to offset the output signal to a precise midsupply level. Typically, this offset is 2.5 V in a
5-V supply environment. To accomplish this level shift, a voltage source must be connected to the REF pin to
level-shift the output so that the INA849 drives a single-supply analog-to-digital converter (ADC).
For dual-supply operation, the reference pin is typically connected to the low-impedance system ground.
The voltage source applied to the reference pin must have a low output impedance. As shown in Figure 9-1,
any resistance at the reference pin (shown as RREF) is in series with an internal 5-kΩ resistor that creates an
imbalance in the four resistors of the internal difference amplifier.
+VS
C2
+VS
íIN
íRG
5k
+
5k
±
3k
±
3k
+
RG
+RG
+IN
OUT
C3
R2
±
+
5k
5k
REF
R1
íVS
C1
íVS
Figure 9-1. Parasitic Resistance Shown at the Reference Pin
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This imbalance results in a degraded common-mode rejection ratio (CMRR). Figure 9-2 shows how the
common-mode rejection ratio degrades depending on the source resistance on the reference pin. For best
performance, keep the dc CMRR greater than 100 dB by keeping the source impedance to the REF pin
(represented as R1) to less than 0.1 Ω.
Figure 9-2. Effect of Parasitic Resistance at the Reference Pin
Voltage-reference devices are an excellent option for providing a low-impedance voltage source for the
reference pin. However, if a resistor voltage divider generates a reference voltage, the divider must be buffered
by an op amp (as Figure 9-3 shows) to avoid CMRR degradation.
5V
+IN
+
íIN
±
INA849
OUT
5V
REF
í5 V
5V
100 k
±
+
OPA320
1 …F
100 k
Figure 9-3. Using an Op Amp to Buffer Reference Voltages
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9.1.2 Input Bias Current Return Path
The input impedance of the INA849 is extremely high (approximately 100 GΩ). However, a path must be
provided for the input bias current of both inputs. This input bias current is typically 6 nA. High input impedance
means that this input bias current changes little with varying input voltage.
Input circuitry must provide a path for this input bias current for proper operation. Figure 9-4 shows various
provisions for an input bias current path. Without a bias current path, the inputs float to a potential that exceeds
the common-mode range of the INA849, and the input amplifiers saturate. If the differential source resistance is
low, the bias current return path connects to one input (as shown in the thermocouple example). With a higher
source impedance, using two equal resistors provides a balanced input with possible advantages of a lower
input offset voltage as a result of bias current, and better high-frequency common-mode rejection.
C1
R1
+VS
AC Coupling
C2
+
INA849
±
REF
R2
í VS
+VS
Microphone,
Hydrophone,
and more
+
L1
±
INA849
REF
R4 í VS
R3
+VS
+
Thermocouple
±
R5
10 NŸ
INA849
REF
í VS
+VS
+
Transformer
T1
±
INA849
REF
í VS
NOTE: Center tap in the transformer provides bias current return.
Figure 9-4. Providing an Input Common-Mode Current Path
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9.1.3 Thermal Effects due to Power Dissipation
The INA849 dissipates approximately 200 mW of power under quiescent conditions at a ±15-V supply voltage.
The internal resistor network and output load drive causes an additional power dissipation that depends on
the input signal. The small silicon area of the INA849 causes the internal circuitry to experience temperature
gradients that might adversely affect the electrical performance.
Precision parameters, such as offset voltage, linearity, common-mode rejection ratio, and total harmonic
distortion, can be impacted as a result of these thermal effects in the silicon. The thermal gradient particularly
affects the performance of low-frequency input signals with higher gains (> 10) and large output voltage
variation. As shown in the measurement Figure 9-5, the thermal effect can be minimized by lowering the supply
voltage, if the application permits.
Figure 9-5. Linearity vs Supply Voltage for G = 1000
22
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9.2 Typical Application
9.2.1 Sensor Conditioning Circuit
Figure 9-6 shows a typical application for the INA849.
+VS
C4
0.1 …F
+IN
R1
1k
C2
470 pF
C3
47 pF
+
RG
INA849
RG
REF
±
RG
C1
470 pF
R6
10 k
íIN
5V
C3
0.1 …F
R2
1k
+VS
R4
100 k
±
C7
100 pF
OPA192
+
íVS
íVS
C6
0.1 …F
R5
100 k
Figure 9-6. Sensor Conditioning Circuit
9.2.1.1 Design Requirements
For the typical application, the design requirements are:
•
•
•
•
•
Power-supply voltage of VS = ± 15 V
AC-coupled input signal
– Capacitor tolerance of 5%
Reference voltage buffered to VREF = 2.5 V
Output range within 0 V to 5 V
First-order filter stage with ‒3-dB frequency of 27 kHz
9.2.1.2 Detailed Design Procedure
If the instrumentation amplifier is used to drive ac-coupled input signals, an input bias current path must be
provided as described in Section 9.1.2, represented with resistors R1 and R2 in Figure 9-6. For the selection of
the resistor value, a trade-off must be made between input current noise that increases at lower values and input
voltage noise that increases at higher values.
Section 9.1.1 states that the reference pin must be connected to a low-impedance reference, as shown in the
application circuit example of the Sensor Conditioning Circuit. The reference pin must be connected to a 2.5-V
reference voltage established through a high-resistive divider. The OPA192 helps to buffer the reference voltage.
The effective output impedance of the OPA192 is derived as follows. The dc open-loop impedance of the
OPA192 amplifier is approximately 3 kΩ. In a buffer configuration (AV = 1), the output impedance of an amplifier
degrades by the open-loop voltage gain. The OPA192 specifies a typical AOL of 126 dB, thereby resulting in an
output impedance of ROUT = 1.5 mΩ.
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9.2.2 Phantom Power in Microphone Preamplifier Circuit
48-V
R3
47 k
GND
VS
R1
6.2 k
R2
6.2 k
C6
0.1 μF
C3
47 µF
+VS
+
IN+
C4
47 µF
3 k
R5
+
R6
2 k
RG
+VS
GND
INA849
R7
VOUT
RG
–
VS
+
IN
R4
3 k
REF
0.1 μF
C5
VS
Figure 9-7. Phantom Power in Microphone Preamplifier Circuit
Figure 9-7 shows a typical application circuit for a microphone input amplifier used to generate phantom power.
Phantom power is a technique that provides power and the audio signal using the same signal path.
R1 and R2 connected to the 48-V supply define the current path in the case when the microphone must
be powered. Therefore, C3 and C4 are used as blocking capacitors to protect the INA849. When the input
connections are shorted In a fault scenario, a large surge current discharges the dc blocking capacitor through
the Shottky diodes. For 48-V phantom power, the surge current exceeds 4 A for a short duration of time. Make
sure to use Shottky diodes that are specified for at least a 10-A surge current. Additional series resistance with
the dc blocking capacitor limits the surge current, but must be traded off because these add noise to the circuit.
One of the key criteria for high-performance microphones is to enable an optimum source impedance throughout
the audible frequency range. The exceptional ultra-low noise performance of the INA849 permits direct input
without the need for a transformer.
R4 and R5 in parallel with R1 and R2 provide the bias current path for the INA849. The input bias current
(maximum of 20 nA) provides a dc differential input voltage that reflects as an voltage error on the output. Use
the lowest possible value resistors to make sure that the thermal noise of these resistors does not dominate.
The mismatch of the input ac-coupling capacitors (C3 and C4) can reduce the common-mode rejection ratio
significantly at low frequencies. An additional resistor (R6) connected to both of the bias resistors (R4 and R5)
can mitigate this effect.
Use the TINA TI™ simulation software for a detailed analysis.
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10 Power Supply Recommendations
The nominal performance of the INA849 is specified with a supply voltage of ±15 V and midsupply reference
voltage. The device also operates using power supplies from ±4 V (8 V) to ±18 V (36 V) and non-midsupply
reference voltages with excellent performance. Section 7.6 shows the parameters that can vary significantly with
operating voltage and reference voltage.
11 Layout
11.1 Layout Guidelines
Use good PCB layout practices for best operational performance of the device, including:
• To avoid converting common-mode signals into differential signals and thermal electromotive forces (EMFs),
make sure that both input paths are symmetrical and well-matched for source impedance and capacitance.
• Place the external gain resistor close to the RG pins to keep the loop inductance as low as possible and
to avoid a potential parasitic coupling path, but also so that capacitance mismatch between the RG pins is
minimized.
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and of the device.
Bypass capacitors reduce the coupled noise by providing low-impedance power sources local to the analog
circuitry.
– Connect low-ESR, 0.1-µF, ceramic bypass capacitors between each supply pin and ground, placed as
close as possible to the device.
– A single bypass capacitor from V+ to ground is applicable for single-supply applications.
• To reduce parasitic coupling, run the input traces as far away as possible from the supply or output traces.
If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better than in
parallel with the noisy trace.
• Keep traces as short as possible.
• Minimize the number of thermal junctions. Ideally, the signal path is routed within a single layer without vias.
• Keep sufficient distance from major thermal energy sources (circuits with high power dissipation). If not
possible, place the device such that it matches the thermal energy source on the differential signal path.
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11.2 Layout Example
+V
C2
RG
INA849
RG
íIN
OUT
±VS
R3
REF
+IN
+VS
R2
R1
C1
íV
+V
Use ground pours for
shielding the input
signal pairs
Place bypass
capacitors as close to
IC as possible
GND
C2
R1
±IN
1
±IN
+VS
8
2
RG
OUT
7
3
RG
REF
6
4
+IN
íVS
5
OUT
R3
+IN
Low-impedance
connection for
reference terminal
R2
GND
C1
REF
íV
Figure 11-1. Example Schematic and Associated PCB Layout
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Comprehensive Error Calculation for Instrumentation Amplifiers application note
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TINA TI™ and TI E2E™ are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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12-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
INA849DGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
2ENJ
INA849DGKT
ACTIVE
VSSOP
DGK
8
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
2ENJ
INA849DR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
INA849
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
