ISO1044
SLLSFB0A – MARCH 2020 – REVISED ISO1044
JULY 2020
SLLSFB0A – MARCH 2020 – REVISED JULY 2020
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ISO1044 Isolated CAN FD Transceiver in Small Package
1 Features
3 Description
•
The ISO1044B device is a galvanically-isolated
controller area network (CAN) transceiver that meets
the specifications of the ISO11898-2 (2016) standard.
The ISO1044B device offers ±58-V DC bus fault
protection and ±12-V common-mode voltage range.
The device supports up to 5-Mbps data rate in CAN
FD mode allowing much faster transfer of payload
compared to classic CAN. This device uses a silicon
dioxide (SiO2) insulation barrier with a withstand
voltage of 3000 VRMS and a working voltage of 450
VRMS. Electromagnetic compatibility has been
significantly enhanced to enable system-level ESD,
EFT, surge, and emissions compliance. Used in
conjunction with isolated power supplies, the device
protects against high voltage, and prevents noise
currents from the bus from entering the local ground.
The ISO1044B device supports a wide ambient
temperature range of –40°C to +125°C. The device is
available in the small SOIC-8 (D) package which
significantly reduces the solution size compared to a
traditional approach using optocouplers to isolate the
CAN transceiver.
•
•
•
•
•
•
•
•
•
•
•
Meets the ISO 11898-2:2016 physical layer
standard
Supports classic CAN up to 1 Mbps and FD
(flexible data rate) up to 5 Mbps
Protection features
– DC Bus Fault Protection Voltage: ±58 V
– IEC ESD tolerance on bus pins: ±8 kV
– HBM ESD tolerance on bus pins: ±10 kV
– Driver dominant time out (TXD DTO)
– Undervoltage protection on VCC1 and VCC2
Common-mode voltage range: ±12 V
Ideal passive, high impedance bus terminals when
unpowered
High CMTI: 85 kV/µs minimum
VCC1 voltage range: 1.71 V to 5.5 V
– Supports 1.8-V, 2.5-V, 3.3-V and 5.0-V logic
interface to the CAN controller
VCC2 voltage range: 4.5 V to 5.5 V
Robust electromagnetic compatibility (EMC)
– System-Level ESD, EFT, and surge Immunity
– Low Emissions
Ambient temperature range: –40°C to +125°C
8-SOIC package
Safety-related certifications:
– All certifications planned
– VDE reinforced insulation per DIN VDE V
0884-11:2017-01
– UL 1577 component recognition program
– IEC 60950-1, IEC 62368-1, IEC 61010-1 and
GB 4943.1-2011 certifications
2 Applications
•
•
•
•
•
•
AC and servo drives
Solar inverters
PLC and DCS communication modules
Elevators and escalators
Industrial power supplies
Battery charging and management
Device Information
PART
NUMBER(1)
PACKAGE
ISO1044B
(1)
BODY SIZE (NOM)
SOIC (8)
4.90 mm × 3.91 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
VCC1
1
VDD
TXD
MCU
RXD
DGND
2
3
4
Digital
Gro und
VCC2
VCC1
TXD
8
CANH 6
ISO104 4 CANL 5
VCC2
CAN B us
RXD
GND1
GND2 7
Gal van ic
Isol atio n B arrier
ISO
Gro und
Copyright © 201 7, Texas Instrumen ts Incorpor ate d
Application Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
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intellectual
property
matters
and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
Pin Functions—8 Pins.......................................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Power Ratings.............................................................5
6.6 Insulation Specifications............................................. 6
6.7 Safety-Related Certifications...................................... 7
6.8 Safety Limiting Values.................................................7
6.9 Electrical Characteristics - DC Specification...............8
6.10 Switching Characteristics........................................ 11
6.11 Insulation Characteristics Curves............................12
6.12 Typical Characteristics............................................ 12
7 Parametric Measurement Information......................... 15
8 Detailed Description......................................................18
8.1 Overview................................................................... 18
8.2 Functional Block Diagram......................................... 18
8.3 Feature Description...................................................18
8.4 Device Functional Modes..........................................22
9 Application and Implementation.................................. 23
9.1 Application Information............................................. 23
9.2 Typical Application.................................................... 23
10 Power Supply Recommendations..............................25
11 Layout........................................................................... 26
11.1 Layout Guidelines................................................... 26
11.2 Layout Example...................................................... 26
12 Device and Documentation Support..........................28
12.1 Documentation Support.......................................... 28
12.2 Receiving Notification of Documentation Updates..28
12.3 Support Resources................................................. 28
12.4 Trademarks............................................................. 28
12.5 Electrostatic Discharge Caution..............................28
12.6 Glossary..................................................................28
13 Mechanical, Packaging, and Orderable
Information.................................................................... 28
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
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VCC1
1
TXD
2
RXD
3
GND1
4
ISOLATION
5 Pin Configuration and Functions
8
VCC2
7
GND2
6
CANH
5
CANL
Not to scale
Figure 5-1. D Package 8-Pin SOIC Top View
Pin Functions—8 Pins
PIN
NAME
I/O
DESCRIPTION
1
VCC1
—
2
TXD
I
CAN transmit data input (LOW for dominant and HIGH for recessive bus states)
Digital-side supply voltage, Side 1
3
RXD
O
CAN receive data output (LOW for dominant and HIGH for recessive bus states)
4
GND1
—
Digital-side ground connection, Side 1
5
CANL
I/O
Low-level CAN bus line
6
CANH
I/O
High-level CAN bus line
7
GND2
—
Transceiver-side ground connection, Side 2
8
VCC2
—
Transceiver-side supply voltage, Side 2
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN
MAX
Supply voltage, side 1
-0.5
6
V
VCC2
Supply voltage, side 2
-0.5
6
V
VIO
Logic input and output voltage range (TXD and
RXD)
-0.5
VCC1+0.5(3)
V
IO
Output current on RXD pin
-15
15
mA
VBUS
Voltage on bus pins (CANH, CANL)
-58
58
V
VBUS_DIFF
Differential voltage on bus pins (CANH-CANL)
-45
45
V
TJ
Junction temperature
-40
150
℃
TSTG
Storage temperature
-65
150
℃
VCC1
(1)
(2)
(3)
UNIT
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak
voltage values.
Maximum voltage must not exceed 6 V
6.2 ESD Ratings
V(ESD)
V(IEC_ESD)
(1)
(2)
(3)
Electrostatic discharge
Human body model (HBM), per ANSI/
ESDA/JEDEC JS-001
All
pins(1)
CANH and CANL to
Electrostatic discharge
Charged device model (CDM), per
JEDEC specification JESD22-C101
GND2(1)
All pins(2)
Powered, CANH, CANL to bus side
IEC 61000-4-2 System Level Electrostatic ground (GND2)
discharge (tested directly on device pins
with no external components on PCB) (3) Unpowered, CANH, CANL to bus side
ground (GND2)
VALUE
UNIT
±4000
V
±10000
V
±750
±8000
V
±12000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
External components on bus pins may lead to different results
6.3 Recommended Operating Conditions
VCC1
VCC2
MIN
MAX
Supply Voltage, Side 1, 1.8 V operation
1.71
1.89
V
Supply Voltage, Side 1, 2.5 V, 3.3 V and 5.5 V operation
2.25
5.5
V
4.5
5.5
Supply Voltage, Side 2
IOH(RXD)
IOL(RXD)
4
V
High-Level Output current, VCC1 = 5 V
-4
mA
High-Level Output current, VCC1 = 3.3 V
-2
mA
High-Level Output current, VCC1 = 2.5 V, 1.8 V
-1
mA
Low-level output current, VCC1 = 5 V
4
mA
Low-level output current, VCC1 = 3.3 V
2
mA
1
mA
125
°C
Low-level output current, VCC1 = 2.5 V, 1.8 V
TA
UNIT
Operating ambient temperature
-40
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6.4 Thermal Information
ISO1044B
THERMAL METRIC(1)
UNIT
D (SOIC)
8 PINS
RΘJA
Junction-to-ambient thermal resistance
119.5
°C/W
RΘJC(top)
Junction-to-case (top) thermal resistance
44.8
°C/W
RΘJB
Junction-to-board thermal resistance
56.1
°C/W
ΨJT
Junction-to-top characterization parameter
28.7
°C/W
ΨJB
Junction-to-board characterization parameter
55.3
°C/W
RΘJC(bot)
Junction-to-case (bottom) thermal resistance
-
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Power Ratings
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PD
Maximum power dissipation (both sides)
VCC1 = VCC2 = 5.5 V, TJ = 150°C, RL =
60 Ω , TXD with 5V, 5Mbps 50% duty
square wave
146
mW
PD1
Maximum power dissipation (side-1)
VCC1 = VCC2 = 5.5 V, TJ = 150°C, RL =
60 Ω , TXD with 5V, 5Mbps 50% duty
square wave
15
mW
PD2
Maximum power dissipation (side-2)
VCC1 = VCC2 = 5.5 V, TJ = 150°C, RL =
60 Ω , TXD with 5V, 5Mbps 50% duty
square wave
131
mW
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6.6 Insulation Specifications
PARAMETER
TEST CONDITIONS
SPECIFIC
ATIONS
UNIT
D-8
IEC 60664-1
CLR
External clearance(1)
Side 1 to side 2 distance through air
>4
mm
CPG
External Creepage(1)
Side 1 to side 2 distance across package surface > 4
mm
DTI
Distance through the insulation
Minimum internal gap (internal clearance)
>17
µm
CTI
Comparative tracking index
IEC 60112; UL 746A
>600
V
Material Group
According to IEC 60664-1
I
Rated mains voltage ≤ 150 VRMS
I-IV
Rated mains voltage ≤ 300 VRMS
I-III
Maximum repetitive peak isolation voltage
AC voltage (bipolar)
637
Maximum isolation working voltage
AC voltage (sine wave); time-dependent dielectric
450
breakdown (TDDB) test;
VRMS
DC voltage
637
VDC
4242
VPK
VPK
Overvoltage category
DIN VDE V 0884-11:2017-01(2)
VIORM
VIOWM
VIOTM
Maximum transient isolation voltage
VTEST = VIOTM , t = 60 s (qualification); VTEST =
1.2 × VIOTM, t = 1 s (100% production)
VIOSM
Maximum surge isolation voltage(3)
Test method per IEC 62368-1, 1.2/50 µs
waveform, VTEST = 1.6 × VIOSM = 8 kVPK
(qualification)
5000
Method a: After I/O safety test subgroup 2/3, Vini
= VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM , tm = 10
s
≤5
Method a: After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.6 × VIORM , tm = 10 s
≤5
Apparent charge(4)
qpd
VPK
pC
Method b1: At routine test (100% production) and
preconditioning (type test), Vini = VIOTM, tini = 1 s; ≤ 5
Vpd(m) = 1.875 × VIORM , tm = 1 s
Barrier capacitance, input to output(5)
CIO
Insulation resistance, input to output(5)
RIO
VIO = 0.4 × sin (2 πft), f = 1 MHz
~1
VIO = 500 V, TA = 25°C
>
VIO = 500 V, 100°C ≤ TA ≤ 150°C
> 1011
VIO = 500 V at TS = 150°C
>
pF
1012
Ω
109
Pollution degree
2
Climatic category
40/125/
21
UL 1577
VISO
(1)
(2)
(3)
(4)
(5)
6
Withstand isolation voltage
VTEST = VISO , t = 60 s (qualification); VTEST = 1.2
× VISO , t = 1 s (100% production)
3000
VRMS
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application.
Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the
isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in
certain cases. Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these
specifications.
ISO1044B is suitable for safe electrical insulation within the safety ratings. Compliance with the safety ratings shall be ensured by
means of suitable protective circuits.
Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
Apparent charge is electrical discharge caused by a partial discharge (pd).
All pins on each side of the barrier tied together creating a two-pin device.
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6.7 Safety-Related Certifications
VDE
CSA
UL
CQC
Plan to certify according to DIN V Plan to certify according to IEC
VDE V 0884-11:2017- 01
60950-1, IEC 62368-1
Plan to certify according to UL
1577 Component Recognition
Program
Plan to certify according to
GB4943.1-2011
Maximum transient isolation
voltage,
4242 VPK;
Maximum repetitive peak
isolation voltage,
637 VPK;
Maximum surge isolation voltage,
5000 VPK
Single protection,
3000 VRMS
Basic Insulation, Altitude ≤ 5000
m, Tropical Climate, 400 VRMS
maximum working voltage
Certificate planned
Certificate planned
Certificate planned
400 VRMS basic insulation
working voltage per CSA
60950-1-07+A1+A2 and IEC
60950-1 2nd Ed., for pollution
degree 2, material group I
Certificate planned
6.8 Safety Limiting Values
Safety limiting(1) intends to minimize potential damage to the isolation barrier upon failure of input or output
circuitry.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RθJA = 119.5 °C/W, VI = 5.5 V, TJ =
150°C, TA = 25°C, see Figure 6-1
190
mA
RθJA = 119.5 °C/W, VI = 3.6 V, TJ =
150°C, TA = 25°C, see Figure 6-1
290
mA
RθJA = 119.5 °C/W, VI = 2.75 V, TJ =
150°C, TA = 25°C, see Figure 6-1
380
mA
RθJA = 119.5 °C/W, VI = 1.89 V, TJ =
150°C, TA = 25°C, see Figure 6-1
553
mA
RθJA = 119.5 °C/W, TJ = 150°C, TA =
25°C, see Figure 6-2
1044
mW
150
°C
SOIC-8 PACKAGE
IS
Safety input, output, or supply current
PS
Safety input, output, or total power
TS
Maximum safety temperature
(1)
The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS
and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be
exceeded. These limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the table is that of a device installed on a high-K test board for leaded surface-mount
packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum allowed junction temperature.
PS = IS × VI, where VI is the maximum input voltage.
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6.9 Electrical Characteristics - DC Specification
Typical specifications are at VCC1 = 3.3 V, VCC2 = 5 V, Min/Max are over recommended operating conditions
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCC1 =1.71 V to 1.89 V, TXD = 0 V, bus
dominant
2.3
3.5
mA
VCC1 = 2.25 V to 5.5 V, TXD = 0 V, bus
dominant
2.4
3.5
mA
VCC1 = 1.71 V to 1.89 V, TXD = VCC1, bus
recessive
1.2
2.1
mA
VCC1 = 2.25 V to 5.5 V, TXD = VCC1, bus
recessive
1.3
2.1
mA
VCC1=4.5 to 5.5V, TXD= 1Mbps 50% duty
square wave
1.8
2.7
mA
VCC1=4.5 to 5.5V, TXD= 5Mbps 50% duty
square wave
1.8
2.7
mA
TXD = 0 V, bus dominant, RL = 60 Ω
52
70
mA
TXD = VCC1, bus recessive, RL = 60 Ω
SUPPLY CHARACTERISTICS
ICC1
Supply current Side 1
ICC2
Supply current Side 2
UVVCC1+
Rising under voltage detection, Side
1
UVVCC1-
Falling under voltage detection, Side
1
VHYS(UVCC1)
Hysterisis voltage on VCC1
undervoltage lock-out
UVVCC2+
Rising under voltage detection, side 2
UVVCC2-
Falling under voltage detection, side
2
VHYS(UVCC2)
Hysterisis voltage on
VCC2 undervoltage lock-out
5.9
9
mA
VCC2=4.5 to 5.5V, TXD= 1Mbps 50% duty
square wave, RL= 60 ohm
29.5
38
mA
VCC2=4.5 to 5.5V, TXD= 5Mbps 50% duty
square wave, RL= 60 ohm
29.5
39
mA
1.7
V
1.0
80.0
3.8
V
125
mV
4.2
4.45
V
4.0
4.25
V
200
mV
TXD TERMINAL
VIH
High level input voltage
VIL
Low level input voltage
0.7×VCC1
IIH
High level input leakage current
TXD = VCC1
IIL
Low level input leakage current
TXD = 0V
CI
Input capacitance
VIN = 0.4 x sin(2 x π x 1E+6 x t) + 1.65 V,
VCC1 = 3.3 V
V
0.3×VCC1
1
-20
V
µA
µA
2
pF
RXD TERMINAL
VOH - VCC1
8
High level output voltage
See Figure 7-4, IO = -4 mA for 4.5 V ≤
VCC1 ≤ 5.5 V
-0.4
-0.2
V
See Figure 7-4, IO = -2 mA for 3.0 V ≤
VCC1 ≤ 3.6 V
-0.2
-0.06
V
See Figure 7-4, IO = -1 mA for 2.25 V ≤
VCC1 ≤ 2.75 V
-0.1
-0.04
V
See Figure 7-4, IO = -1 mA for 1.71 V ≤
VCC1 ≤ 1.89 V
-0.1
-0.04
V
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PARAMETER
VOL
Low level output voltage
TYP
MAX
See Figure 7-4, IO = 4 mA for 4.5 V ≤
VCC1 ≤ 5.5 V
TEST CONDITIONS
MIN
UNIT
0.2
0.4
V
See Figure 7-4, IO = 2 mA for 3.0 V ≤
VCC1 ≤ 3.6 V
0.07
0.2
V
See Figure 7-4, IO = 1 mA for 2.25 V ≤
VCC1 ≤ 2.75 V
0.035
0.1
V
See Figure 7-4, IO = 1 mA for 1.71 V ≤
VCC1 ≤ 1.89 V
0.04
0.1
V
DRIVER ELECTRICAL CHARACTERISTICS
Bus output voltage(Dominant), CANH
See Figure 7-1 and Figure 7-2 , TXD = 0
V, 50 Ω ≤ RL ≤ 65 Ω, and CL = open
2.75
4.5
V
Bus output voltage(Dominant), CANL
See Figure 7-1 and Figure 7-2 ,TXD = 0
V, 50 Ω ≤ RL ≤ 65 Ω, and CL = open
0.5
2.25
V
3.0
V
VO(DOM)
VO(REC)
Bus output voltage(recessive), CANH See Figure 7-1 and Figure 7-2 ,TXD =
and CANL
VCC1 and RL = open
2.0
0.5 x
VCC2
Differential output voltage(dominant)
See Figure 7-1 and Figure 7-2 ,TXD = 0
V, 45 Ω ≤ RL ≤ 70 Ω, and CL = open
1.4
3.3
V
Differential output voltage(dominant)
See Figure 7-1 and Figure 7-2 ,TXD = 0
V, 50 Ω ≤ RL ≤ 65 Ω, and CL = open
1.5
3.0
V
Differential output voltage(dominant)
See Figure 7-1 and Figure 7-2 ,TXD = 0
V, RL = 2240 Ω, and CL = open
1.5
5.0
V
Differential output voltage(recessive)
See Figure 7-1 and Figure 7-2 ,TXD =
VCC1, RL = 60 Ω, and CL = open
-120.0
12.0
mV
Differential output voltage(recessive)
See Figure 7-1 and Figure 7-2 ,TXD =
VCC1, RL = open, and CL = open
-50.0
50.0
mV
VSYM_DC
Output symmetry (VCC2 - VO(CANH) VO(CANL))
See Figure 7-1 and Figure 7-2 ,RL = 60
Ω and CL = open
-400.0
400.0
mV
See Figure 7-8 , -15 V < CANH < 40 V,
CANL = open, and TXD = 0V
-115.0
IOS(SS_DOM)
Short circuit current steady state
output current, dominant
VOD(DOM)
VOD(REC)
IOS(SS_REC)
Short circuit current steady state
output current, recessive
mA
See Figure 7-8 , -15 V < CANL < 40 V,
CANH = open, and TXD = 0V
See Figure 7-8 , -27 V < VBUS < 32 V,
VBUS = CANH = CANL, and TXD = VCC1
115.0
mA
-5.0
5.0
mA
500.0
900.0
mV
RECEIVER ELECTRICAL CHARACTERISTICS
VIT
Differential input threshold voltage
See Figure 7-4 and Table 7-1 , -12 V ≤
VCM ≤ 12 V
VHYS
Hysteresis voltage for differential
input threshold
See Figure 7-4 and Table 7-1 , -12 V ≤
VCM ≤ 12 V
VDIFF(DOM)
Dominant state differential input
voltage range
See Figure 7-4 and Table 7-1 , -12 V ≤
VCM ≤ 12 V
0.9
9
V
VDIFF(REC)
Recessive state differential input
voltage range
See Figure 7-4 and Table 7-1 , -12 V ≤
VCM ≤ 12 V
-4
0.5
V
VCM
Input common mode range
See Figure 7-4 and Table 7-1
-12
12
V
IOFF(LKG)
power-off bus input leakage current
CANH = CANL = 5V, VCC to GND via 0Ω
and 47kΩ resistor
5
µA
CI
Input capacitance to ground (CANH
or CANL)
TXD = VCC1
20
pF
CID
Differential input capacitance
TXD = VCC1
10
pF
RID
Differential input resistance
TXD = VCC1 ; -12 V ≤ VCM ≤ +12 V ; RID
= RCAN_H + RCAN_L
40
90
kΩ
RIN
Input resistance (CANH or CANL)
TXD = VCC1 ; -12 V ≤ VCM ≤ +12 V ;
RCAN_H or RCAN_L = Δ V / Δ I
20
45
kΩ
RIN(M)
Input resistance matching: (1 RIN(CANH)/RIN(CANL)) x 100%
VCANH = VCANL = 5 V
-1
1
%
100
mV
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PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
THERMAL SHUTDOWN
TTSD
Thermal shutdown temperature
TTSD_HYST
Thermal shutdown hysteresis
10
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℃
8
℃
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6.10 Switching Characteristics
Typical specifications are at VCC1 = 3.3 V, VCC2 = 5 V, Min/Max are over recommended operating conditions
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
See Figure 7-6 , RL = 60 Ω, CL = 100 pF,
CL(RXD) = 15 pF; input rise/fall time (10%
to 90%) on TXD =1 ns; 1.71 V ≤
VCC1 ≤ 1.89 V
150
203
ns
See Figure 7-6 , RL = 60 Ω, CL = 100 pF,
CL(RXD) = 15 pF; input rise/fall time (10%
to 90%) on TXD =1 ns; 2.25 V ≤ VCC1 ≤
5.5 V
150
199
ns
See Figure 7-6 , RL = 60 Ω, CL = 100 pF,
CL(RXD) = 15 pF; input rise/fall time (10%
to 90%) on TXD =1 ns; 1.71 V ≤ VCC1 ≤
1.89 V
175
219
ns
See Figure 7-6 , RL = 60 Ω, CL = 100 pF,
CL(RXD) = 15 pF; input rise/fall time (10%
to 90%) on TXD =1 ns; 2.25 V ≤ VCC1 ≤
5.5 V
175
212
ns
300.0
µs
DEVICE SWITCHING CHARACTERISTICS
tPROP(LOOP1)
tPROP(LOOP2)
Total loop delay, driver input TXD to
receiver RXD, recessive to dominant
Total loop delay, driver input TXD to
receiver RXD, dominant to recessive
tUV_RE_ENABLE
Re-enable time after Undervoltage
event
Time for device to return to normal
operation from VCC1 or VCC2 under
voltage event
CMTI
Common mode transient immunity
TXD=VCC1 or GND1, VCM =
1200VPK , See Figure 7-9
85
kV/µs
DRIVER SWITCHING CHARACTERISTICS
tpHR
Propagation delay time, Low-to-High
TXD edge to driver recessive
tpLD
Propagation delay time, High-to-Low
TXD edge to driver dominant
tsk(p)
pulse skew (|tpHR - tpLD|)
tR
Differential output signal rise time
27
tF
Differential output signal fall time
42
VSYM
Driver symmetry (VO(CANH) +
VO(CANL))/VCC
See Figure 7-3 and Figure 9-3 ,
RTERM =60 Ω, CL =open, CSPLIT= 4.7nF,
TXD= Dominant or receissive or toggling
at 250 kHz, 1 MHz
0.9
1.1
V/V
tTXD_DTO
Dominant time out
See Figure 7-7 , RL = 60 Ω and CL = open
1.2
3.8
ms
90
130
ns
71
110
ns
See Figure 7-3 , RL = 60 Ω and CL = 100
pF; input rise/fall time (10% to 90%) on
TXD =1 ns
85
105
70
105
ns
12.5
RECEIVER SWITCHING CHARACTERISTICS
tpRH
Propagation delay time, bus
dominant-to-recessive input edge to
RXD high output
tpDL
Propogation delay time, bus
recessive-to-dominant input edge to
RXD low output
See Figure 7-5 , CL(RXD) = 15 pF,
tR
Output signal rise time(RXD)
1
ns
tF
Output signal fall time(RXD)
1
ns
FD TIMING PARAMETERS
Bit time on CAN bus output pins with
tBIT(TXD) = 500 ns
See Figure 7-6 , RL = 60 Ω, CL = 100 pF,
CL(RXD) = 15 pF; input rise/fall time (10%
to 90%) on TXD =1 ns
435.0
530.0
ns
Bit time on CAN bus output pins with
tBIT(TXD) = 200 ns
See Figure 7-6 , RL = 60 Ω, CL = 100 pF,
CL(RXD) = 15 pF; input rise/fall time (10%
to 90%) on TXD =1 ns
155.0
210.0
ns
tBIT(BUS)
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PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
400
550.0
ns
See Figure 7-6 , RL = 60 Ω, CL = 100 pF,
CL(RXD) = 15 pF; input rise/fall time (10%
to 90%) on TXD =1 ns
120.0
220.0
ns
Receiver timing symmetry with
tBIT(TXD) = 500 ns
See Figure 7-6 , RL = 60 Ω, CL = 100 pF,
CL(RXD) = 15 pF; input rise/fall time (10%
to 90%) on TXD =1 ns; ΔtREC = tBIT(RXD)
- tBIT(BUS)
-65.0
40.0
ns
Receiver timing symmetry with
tBIT(TXD) = 200 ns
See Figure 7-6 , RL = 60 Ω, CL = 100 pF,
CL(RXD) = 15 pF; input rise/fall time (10%
to 90%) on TXD =1 ns; ΔtREC = tBIT(RXD)
- tBIT(BUS)
-45.0
15.0
ns
Bit time on RXD output pin with
tBIT(TXD) = 500 ns
See Figure 7-6 , RL = 60 Ω, CL = 100 pF,
CL(RXD) = 15 pF; input rise/fall time (10%
to 90%) on TXD =1 ns
Bit time on RXD output pin with
tBIT(TXD) = 200 ns
tBIT(RXD)
∆tREC
TYP
6.11 Insulation Characteristics Curves
1200
VCC = 5.5 V
VCC = 3.6 V
VCC = 2.75 V
VCC = 1.89 V
500
Safety Limiting Power (mW)
Safety Limiting Current (mA)
600
400
300
200
100
1000
800
600
400
200
0
0
0
50
100
150
Ambient Temperature (qC)
200
D001
Figure 6-1. Thermal Derating Curve for Limiting
Current per VDE for 8-D Package
0
50
100
150
Ambient Temperature (qC)
200
D002
Figure 6-2. Thermal Derating Curve for Limiting
Power per VDE for 8-D Package
6.12 Typical Characteristics
40
2.3
2.2
2
36
Supply Current (mA)
Supply Current (mA)
2.1
1.9
1.8
1.7
1.6
34
32
30
28
26
24
1.5
22
1.4
20
0
0.5
1
1.5
2
2.5
3
3.5
Data Rate (Mbps)
4
4.5
5
0
D001
VCC2 = 5V, Temp = 25°C, RL = 60 Ω , CL(RXD) = 15pF
Figure 6-3. Side 1 Supply Current vs Datarate
12
ICC2 (VCC2 = 4.5V)
ICC2 (VCC2 = 5V)
ICC2 (VCC2 = 5.5V)
38
ICC1 (VCC1 = 1.8V)
ICC1 (VCC1 = 2.5V)
ICC1 (VCC1 = 3.3V)
ICC1 (VCC1 = 5V)
0.5
1
1.5
2
2.5
3
3.5
Data Rate (Mbps)
4
4.5
5
D002
VCC1 = 5V, Temp = 25°C, RL = 60 Ω, CL(RXD) = 15pF
Figure 6-4. Side 2 Supply Current vs Datarate
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40
3
Supply Current ICC1 (mA)
2.5
2 Mbps
5 Mbps
36
Supply Current ICC2 (mA)
Recessive
250 kbps
500 kbps
1 Mbps
2.75
2.25
2
1.75
1.5
1.25
1
-40
28
24
20
Recessive
250 kbps
500 kbps
16
12
1 Mbps
2 Mbps
5 Mbps
8
4
-20
0
20
40
60
80
Temperature (qC)
100
120
0
-40
140
-20
0
D003
VCC1 = VCC2 = 5V, RL = 60 Ω, CL(RXD) = 15pF
Figure 6-5. Side 1 Supply Current vs Ambient
Temperature
20
40
60
80
Temperature (°C)
100
120
140
D004
VCC1 = VCC2 = 5V, RL = 60 Ω, CL(RXD) = 15pF
Figure 6-6. Side 2 Supply Current vs Ambient
Temperature
2.4
170
Differential voltage (Dominant)
165
160
Loop Delay (ns)
32
155
tPROP(LOOP1)
tPROP(LOOP2)
150
145
140
2.3
2.2
2.1
135
130
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
Figure 6-7. Loop Delay vs Ambient Temperature
2.6
VOD(DOM)
2.4
2.2
2
1.8
1.6
1.4
1.2
4.7
4.8
4.9
5
5.1
VCC2 (V)
5.2
0
20
5.3
5.4
100
120
140
D006
Figure 6-8. Dominant state differential output
voltage vs Ambient Temperature
5.5
D007
VCC1 = 5V, Temp = 25°C, RL = 60 Ω
40
60
80
Temperature (°C)
VCC1 = VCC2 = 5V, RL = 60 Ω
Receiver Differential threshold voltage (V)
3
2.8
4.6
-20
D005
VCC1 = VCC2 = 5V, Bus Load = 60 Ω || 100 pF, CL(RXD)
= 15pF
1
4.5
2
-40
140
1
0.9
0.8
0.7
0.6
0.5
VIT(falling)
VIT(rising)
VHYS
0.4
0.3
0.2
0.1
0
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
140
D008
VCC1 = VCC2 = 5V, TXD = Floating
Figure 6-9. Dominant state differential output
voltage vs Side2 supply voltage
Figure 6-10. Receiver differential threshold voltage
vs Ambient Temperature
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2.5
tTXD_DTO (ms)
2.45
2.4
2.35
2.3
-40
-20
0
20
40
60
80
100
Ambient Temperature (qC)
120
140
D009
VCC1 = VCC2 = 5V, RL = 60Ω
Figure 6-11. Dominant timeout vs Ambient
Temperature
Figure 6-12. Glitch Free Power Up on VCC1 – CAN
Bus Remains Recessive
Figure 6-13. Glitch Free Power Up on VCC2 – CAN
Bus Remains Recessive
Figure 6-14. Typical TXD, RXD, CANH and CANL
Waveforms at 2 Mbps
Figure 6-15. Typical TXD, RXD, CANH and CANL Waveforms at 500 kbps
14
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7 Parametric Measurement Information
IO(CANH)
CANH
II
0 or
Vcc 1
TXD
VOD
CANL
GND1
RL
VO(CANH) + VO(CANL )
2
IO(CANL )
GND2
VI
VOC
VO(CANL )
GND1
VO(CANH)
GND2
Figure 7-1. Driver Voltage, Current and Test Definitions
Dominant
VO (CANH)
» 3.5 V
Recessive
» 2.5 V
» 1.5 V
VO (CANL)
Figure 7-2. Bus Logic State Voltage Definitions
Vcc
VI
CANH
TXD
VO
RL
Vcc /2
0V
CL
CANL
VI
t PLH
t PHL
VO(D)
90%
0.9V
VO
(SEE NOTE A)
Vcc /2
0.5V
10%
tr
tf
VO(R)
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO =
50 Ω.
Figure 7-3. Driver Test Circuit and Voltage Waveforms
CANH
VIC
=
VI(CANH) + VI(CANL)
2
RXD
VID
IO
CANL
VI(CANH)
VO
VI(CANL)
GND2
GND1
Figure 7-4. Receiver Voltage and Current Definitions
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CANH
IO
3.5 V
RXD
V
I
2.4 V
2 V
CANL
1.5 V
t pHL
t pLH
VO
VI
(SEE NOTE A )
C L(RXD)
1 .5 V
V OH
90 %
0.7 Vcc 1
0.3 Vcc 1
V
O
10 %
tf
tr
V OL
GND 1
GND 2
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty cycle,
tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω.
Figure 7-5. Receiver Test Circuit and Voltage Waveforms
Table 7-1. Receiver Differential Input Voltage Threshold Test
INPUT
OUTPUT
VCANH
VCANL
|VID|
RXD
-11.5 V
-12.5 V
1000 mV
L
12.5 V
11.5 V
1000 mV
L
-8.55 V
-9.45 V
900 mV
L
9.45 V
8.55 V
900 mV
L
-8.75 V
-9.25 V
500 mV
H
9.25 V
8.75 V
500 mV
H
-11.8 V
-12.2 V
400 mV
H
12.2 V
11.8 V
400 mV
H
Open
Open
X
H
VOL
VOH
VI
70%
TXD
CANH
TXD
VI
RL
30%
30%
5 x tBIT
CL
0V
tBIT(TXD)
CANL
tBIT(BUS)
900 mV
VDIFF
RXD
VO
500 mV
CL(RXD)
VOH
GND1
70%
RXD
tBIT(RXD)
30%
VOL
Figure 7-6. tLOOP and CAN FD Timing Parameter Measurement
16
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Vcc
VI
CANH
TXD
RL
0V
VOD
CL
V OD (D)
CANL
V I (see Note A )
VOD
900 mV
t TXD_DTO
500 mV
0V
GND 1
A. The input pulse is supplied by a generator having the following characteristics: tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω.
Figure 7-7. Dominant Time-out Test Circuit and Voltage Waveforms
IOS
200 s
IOS
CANH
TXD
VBUS
IOS
+
VBUS
CANL
VBUS
0V
±
GND2
or
0V
VBUS
VBUS
Figure 7-8. Driver Short-Circuit Current Test Circuit and Waveforms
C = 0.1 mF
± 1%
VCC 1
VCC 1
VCC2
CANH
C = 0.1 mF ±1%
+
GND1
GND2
TXD
60 W
S1
VOH or VOL
CANL
0V
RXD
VOH or VOL
GND 1
GND 2
CL = 15 pF
(includes probe and
jig capacitance )
V CM
Figure 7-9. Common-Mode Transient Immunity Test Circuit
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8 Detailed Description
8.1 Overview
The ISO1044B device is a digitally isolated CAN transceiver that offers ±58-V DC bus fault protection and ±12-V
common-mode voltage range. The device supports up to 5-Mbps data rate in CAN FD mode allowing much
faster transfer of payload compared to classic CAN. The ISO1044B device has an isolation withstand voltage of
3000 VRMS with a surge isolation voltage of 5kVPK. The device can operate from 1.8-V, 2.5-V, 3.3-V, and 5-V
supplies on side 1 and a 5-V supply on side 2. This supply range is of particular advantage for applications
operating in harsh industrial environments because the low voltage on side 1 enables the connection to lowvoltage microcontrollers for power conservation, whereas the 5 V on side 2 maintains a high signal-to-noise ratio
of the bus signals.
8.2 Functional Block Diagram
VCC1
TXD
+
GALVANIC ISOLATION
RXD
VCC2
±
GND1
CANH
CANL
GND2
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8.3 Feature Description
8.3.1 CAN Bus States
The CAN bus has two states during operation: dominant and recessive. A dominant bus state, equivalent to logic
low, is when the bus is driven differentially by a driver. A recessive bus state is when the bus is biased to a
common mode of VCC / 2 through the high-resistance internal input resistors of the receiver, equivalent to a logic
high. The host microprocessor of the CAN node uses the TXD pin to drive the bus and receives data from the
bus on the RXD pin. See Figure 8-1 and Figure 8-2.
18
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Typical Bus Voltage (V)
4
CANH
3
Vdiff(D)
2
Vdiff(R)
CANL
1
Time (t)
Recessive
Logic H
Dominant
Logic L
Recessive
Logic H
Figure 8-1. Bus States (Physical Bit Representation)
GALVANIC
ISOLATION
CANH
VCC / 2
RXD
CANL
Figure 8-2. Simplified Recessive Common Mode Bias and Receiver
8.3.2 Digital Inputs and Outputs: TXD (Input) and RXD (Output)
The VCC1 supply for the isolated digital input and output side of the device can be supplied by 1.8-V, 2.5-V, 3.3-V,
and 5-V supplies and therefore the digital inputs and outputs are 1.8-V, 2.5-V, 3.3-V, and 5-V compatible.
8.3.3 Protection Features
8.3.3.1 TXD Dominant Timeout (DTO)
The TXD DTO circuit prevents the transceiver from blocking network communication in the event of a hardware
or software failure where the TXD pin is held dominant longer than the timeout period, tTXD_DTO. The DTO circuit
timer starts on a falling edge on the TXD pin. The DTO circuit disables the CAN bus driver if no rising edge
occurs before the timeout period expires, which frees the bus for communication between other nodes on the
network. The CAN driver is activated again when a recessive signal occurs on the TXD pin, clearing the TXD
DTO condition. The receiver and RXD pin still reflect activity on the CAN bus, and the bus terminals are biased
to the recessive level during a TXD dominant timeout.
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TXD fault stuck dominant
Example: PCB failure or bad software
TXD
(driver)
tTXD_DTO
Fault is repaired and transmission
capability is restored
Driver disabled freeing bus for other nodes
Bus would be stuck dominant, blocking communication for the
whole network but TXD DTO prevents this and frees the bus for
communication after the tTXD_DTO time.
Normal CAN
communication
CAN
Bus
Signal
tTXD_DTO
Communication from
repaired nodes
Communication from
other bus nodes
RXD
(receiver)
Communication from
local node
Communication from
other bus nodes
Communication from
repaired nodes
Figure 8-3. Example Timing Diagram for TXD DTO
Note
The minimum dominant TXD time (tTXD_DTO) allowed by the TXD DTO circuit limits the minimum
possible transmitted data rate of the device. The CAN protocol allows a maximum of eleven
successive dominant bits (on TXD) for the worst case, where five successive dominant bits are
followed immediately by an error frame. This, along with the tTXD_DTO minimum, limits the minimum
data rate. Calculate the minimum transmitted data rate with Equation 1.
Minimum Data Rate = 11 / tTXD_DTO
(1)
8.3.3.2 Thermal Shutdown (TSD)
If the junction temperature of the device exceeds the thermal shutdown threshold (TTSD), the device turns off the
CAN driver circuits, blocking the TXD-to-bus transmission path. The CAN bus terminals are biased to the
recessive level during a thermal shutdown, and the receiver-to-RXD path remains operational. The shutdown
condition is cleared when the junction temperature drops at least the thermal shutdown hysteresis temperature
(TTSD_HYST) below the thermal shutdown temperature (TTSD) of the device.
8.3.3.3 Undervoltage Lockout and Default State
The supply pins have undervoltage detection that places the device in protected or default mode which protects
the bus during an undervoltage event on the VCC1 or VCC2 supply pins. If the bus-side power supply, VCC2, is
less than about 4 V, the power shutdown circuits in the ISO1044B device disable the transceiver to prevent false
transmissions because of an unstable supply. If the VCC1 supply is still active when this occurs, the receiver
output (RXD) goes to a default HIGH (recessive) value. Table 8-1 summarizes the undervoltage lockout and failsafe behavior.
Table 8-1. Undervoltage Lockout and Default State
20
VCC1
VCC2
DEVICE STATE
BUS OUTPUT
> UVVCC1
> UVVCC2
Functional
Per Device State and TXD
Mirrors Bus
UVVCC2
Protected
Recessive
Undetermined
>UVVCC1
< UVVCC2
Protected
High Impedance
Recessive (Default High)
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Note
After an undervoltage condition is cleared and the supplies have returned to valid levels, the device
typically resumes normal operation in 300 µs.
8.3.3.4 Floating Pins
The ISO1044B has internal pull-ups on critical pins which places the device into known states if the pin floats.
This internal bias should not be relied upon by design though, especially in noisy environments, but instead
should be considered a failsafe protection feature.
When a CAN controller supporting open drain outputs is used, an adequate external pull-up resistor must be
used to ensure that the TXD output of the CAN controller maintains adequate bit timing to the input of the CAN
transceiver.
8.3.3.5 Unpowered Device
The device is designed to be ideal passive or no load to the CAN bus if it is unpowered. The bus pins (CANH,
CANL) have extremely low leakage currents when the device is unpowered to avoid loading down the bus which
is critical if some nodes of the network are unpowered while the rest of the of network remains in operation.
8.3.3.6 CAN Bus Short Circuit Current Limiting
The device has two protection features that limit the short circuit current when a CAN bus line has a short-circuit
fault condition. The first protection feature is driver current limiting (both dominant and recessive states) and the
second feature is TXD dominant state time out to prevent permanent higher short circuit current of the dominant
state during a system fault. During CAN communication the bus switches between dominant and recessive
states, therefore the short circuit current may be viewed either as the instantaneous current during each bus
state or as an average current of the two states. For system current (power supply) and power considerations in
the termination resistors and common-mode choke ratings, use the average short circuit current. Determine the
ratio of dominant and recessive bits by the data in the CAN frame plus the following factors of the protocol and
PHY that force either recessive or dominant at certain times:
•
•
•
•
Control fields with set bits
Bit stuffing
Interframe space
TXD dominant time out (fault case limiting)
These factors ensure a minimum recessive amount of time on the bus even if the data field contains a high
percentage of dominant bits. The short circuit current of the bus depends on the ratio of recessive to dominant
bits and their respective short circuit currents. Use Equation 2 to calculate the average short circuit current.
IOS(AVG) = %Transmit × [(%REC_Bits × IOS(SS)_REC) + (%DOM_Bits × IOS(SS)_DOM)] + [%Receive ×
IOS(SS)_REC]
(2)
where
•
•
•
•
•
•
•
IOS(AVG) is the average short circuit current
%Transmit is the percentage the node is transmitting CAN messages
%Receive is the percentage the node is receiving CAN messages
%REC_Bits is the percentage of recessive bits in the transmitted CAN messages
%DOM_Bits is the percentage of dominant bits in the transmitted CAN messages
IOS(SS)_REC is the recessive steady state short circuit current
IOS(SS)_DOM is the dominant steady state short circuit current
Note
Consider the short circuit current and possible fault cases of the network when sizing the power
ratings of the termination resistance and other network components.
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8.4 Device Functional Modes
Table 8-2 and Table 8-3 list the driver and receiver functions. Table 8-4 lists the functional modes for the
ISO1044B device.
Table 8-2. Driver Function Table
INPUT
(1)
OUTPUTS
DRIVEN BUS STATE
TXD(1)
CANH(1)
CANL(1)
L
H
L
Dominant
H
Z
Z
Recessive
H = high level, L = low level, Z = common mode (recessive) bias to VCC / 2. See Figure 8-1 and
Figure 8-2 for bus state and common mode bias information.
Table 8-3. Receiver Function Table
DEVICE MODE
CAN DIFFERENTIAL INPUTS
VID = VCANH – VCANL (3)
BUS STATE
RXD PIN(1)
VID ≥ VIT(MAX)
Dominant
L
VIT(MIN) < VID < VIT(MAX)
Undefined
Undefined
VID ≤ VIT(MIN)
Recessive
H
Open (VID ≈ 0 V)
Open
H
Normal
(1)
H = high level, L = low level
Table 8-4. Function Table
DRIVER(1)
INPUTS
OUTPUTS
TXD
CANH
CANL
L(2)
H
L
RECEIVER
BUS STATE
DIFFERENTIAL INPUTS
VID = CANH–CANL(3)
OUTPUT
RXD
BUS STATE
DOMINANT
VID ≥ VIT(MAX)
L
DOMINANT
H
Z
Z
RECESSIVE
VIT(MIN) < VID < VIT(MAX)
Undefined
Undefined
Open
Z
Z
RECESSIVE
VID ≤ VIT(MIN)
H
RECESSIVE
X if VCC1 supply
< UVVCC1
Z
Z
RECESSIVE
Open (VID ≈ 0 V)
H
RECESSIVE
(1)
(2)
(3)
22
H = high level; L = low level; X = irrelevant; Z = high impedance
Logic low pulses to prevent dominant time-out.
See Receiver Electrical Characteristics section for input thresholds.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The ISO1044B device can be used with other components from Texas Instruments such as a microcontroller, a
transformer driver, and a linear voltage regulator to form a fully isolated CAN interface.
9.2 Typical Application
GND
4
D2
EN
VCC
CLK
D1
1
3
SN6505
3.3 V
8
3
2
7
6
1
5
2
3.3 V
1
TXD
MCU
RXD
DGND
5
EN
TPS76350
GND
NC
4
VCC2
TXD
GND2 7
6
100 nF
2
3
4
Digital
Ground
OUT
8
VCC1
100 nF
VDD
IN
ISO1044
RXD
ISO
Ground
CANH
GND1
Optional bus
protection
circuitry
CANL 5
Galvanic
Isolation Barrier
CANH
CMC
Optional bus
protection
circuitry
CANL
Figure 9-1. Application Circuit With ISO1044 in 8-SOIC Package
ISO1044B is optimized for small solution size and meets 8 kV contact ESD (Electrostatic discharge) per IEC
61000-4-2 standalone with no external components on bus. If the application requires the usage of Common
mode choke (CMC) as shown in Figure 9-1, then use of Transient voltage suppressor (TVS) is a must to achieve
8kV IEC ESD. Test results with CMC Part number: ACT45B-101-2P-TL003 and TVS Part number: CPDT-12V
show 8 kV IEC ESD (Level 4) pass.
9.2.1 Design Requirements
Unlike an optocoupler-based solution, which requires several external components to improve performance,
provide bias, or limit current, the ISO1044B device only requires external bypass capacitors to operate.
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9.2.2 Detailed Design Procedure
9.2.2.1 Bus Loading, Length and Number of Nodes
The ISO 11898-2 Standard specifies a maximum bus length of 40 m and maximum stub length of 0.3 m.
However, with careful design, users can have longer cables, longer stub lengths, and many more nodes to a
bus. A large number of nodes requires transceivers with high input impedance such as the ISO1044B
transceiver.
Many CAN organizations and standards have scaled the use of CAN for applications outside the original ISO
11898-2 Standard. These organizations and standards have made system-level trade-offs for data rate, cable
length, and parasitic loading of the bus. Examples of some of these specifications are ARINC825, CANopen,
DeviceNet, and NMEA2000.
The ISO1044B device is specified to meet the 1.5-V requirement with a 50-Ω load, incorporating the worst case
including parallel transceivers. The differential input resistance of the ISO1044B device is a minimum of 30 kΩ. If
100 ISO1044B transceivers are in parallel on a bus, this requirement is equivalent to a 300-Ω differential load
worst case. That transceiver load of 300 Ω in parallel with the 60 Ω gives an equivalent loading of 50 Ω.
Therefore, the ISO1044B device theoretically supports up to 100 transceivers on a single bus segment.
However, for CAN network design margin must be given for signal loss across the system and cabling, parasitic
loadings, network imbalances, ground offsets and signal integrity, therefore a practical maximum number of
nodes is typically much lower. Bus length may also be extended beyond the original ISO 11898 standard of 40 m
by careful system design and data-rate tradeoffs. For example, CANopen network design guidelines allow the
network to be up to 1 km with changes in the termination resistance, cabling, less than 64 nodes, and a
significantly lowered data rate.
This flexibility in CAN network design is one of the key strengths of the various extensions and additional
standards that have been built on the original ISO 11898-2 CAN standard. Using this flexibility requires the
responsibility of good network design and balancing these tradeoffs.
9.2.2.2 CAN Termination
The ISO11898 standard specifies the interconnect to be a single twisted pair cable (shielded or unshielded) with
120-Ω characteristic impedance (ZO). Resistors equal to the characteristic impedance of the line should be used
to terminate both ends of the cable to prevent signal reflections. Unterminated drop-lines (stubs) connecting
nodes to the bus should be kept as short as possible to minimize signal reflections. The termination may be in a
node, but if nodes are removed from the bus, the termination must be carefully placed so that it is not removed
from the bus.
Node 1
Node 2
Node 3
Node n
(with termination)
MCU or DSP
MCU or DSP
MCU or DSP
MCU or DSP
CAN
Controller
CAN
Controller
CAN
Controller
CAN
Controller
CAN
Transceiver
CAN
Transceiver
CAN
Transceiver
CAN
Transceiver
RTERM
RTERM
Figure 9-2. Typical CAN Bus
Termination may be a single 120-Ω resistor at the end of the bus, either on the cable or in a terminating node. If
filtering and stabilization of the common-mode voltage of the bus is desired, then split termination can be used.
24
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(See Figure 9-3). Split termination improves the electromagnetic emissions behavior of the network by
eliminating fluctuations in the bus common-mode voltages at the start and end of message transmissions.
Standard Termination
Split Termination
CANH
CANH
RTERM / 2
CAN
Transceiver
RTERM
CAN
Transceiver
CSPLIT
RTERM / 2
CANL
CANL
Figure 9-3. CAN Bus Termination Concepts
10 Power Supply Recommendations
To make sure operation is reliable at all data rates and supply voltages, a 0.1-µF bypass capacitor is
recommended at the input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to
the supply pins as possible. In addition, a bulk capacitance, typically 4.7 μF, can be placed near the VCC2 supply
pin. If only a single primary-side power supply is available in an application, isolated power can be generated for
the secondary-side with the help of a transformer driver such as TI's SN6505B. For such applications, detailed
power supply design, and transformer selection recommendations are available in the SN6505 Low-Noise 1-A
Transformer Drivers for Isolated Power Supplies data sheet.
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11 Layout
11.1 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see Section 11.2 Figure 11-1). Layer
stacking should be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and
low-frequency signal layer.
•
•
•
•
Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/in2.
Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
Suggested placement and routing of ISO1044B bypass capacitors and optional TVS diodes is shown in Figure
11-2. In particular, place the VCC2 bypass capacitors on the top layer, as close to the device pins as possible,
and complete the connection to the VCC2 and GND2 pins without using vias.
If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to
the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also
the power and ground plane of each power system can be placed closer together, thus increasing the highfrequency bypass capacitance significantly.
For detailed layout recommendations, refer to the Digital Isolator Design Guide.
11.1.1 PCB Material
For digital circuit boards operating at less than 150 Mbps, (or rise and fall times greater than 1 ns), and trace
lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over lowercost alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater
strength and stiffness, and the self-extinguishing flammability-characteristics.
11.2 Layout Example
High-speed traces
10 mils
Ground plane
40 mils
Keep this space
free from planes,
traces, pads, and
vias
FR-4
0r ~ 4.5
Power plane
10 mils
Low-speed traces
Figure 11-1. Recommended Layer Stack
26
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Figure 11-2. 8-D Layout Example
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
•
•
•
•
•
•
•
Texas Instruments, Digital Isolator Design Guide
Texas Instruments, ISO1044 Isolated CAN Transceiver Evaluation Module User's Guide
Texas Instruments, Isolate your CAN systems without compromising on performance or space TI TechNote
Texas Instruments, Isolation Glossary
Texas Instruments, High-voltage reinforced isolation: Definitions and test methodologies
Texas Instruments, How to Isolate Signal and Power in Isolated CAN Systems TI TechNote
Texas Instruments, How to Design Isolated CAN Systems With Correct Bus Protection Application Report
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
28
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PACKAGE OUTLINE
D0008B
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.150-.157
[3.81-3.98]
NOTE 4
.010 [0.25]
C A B
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
.041
[1.04]
TYPICAL
4221445/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15], per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008B
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
8X (.055)
[1.4]
SEE
DETAILS
SYMM
SEE
DETAILS
SYMM
1
1
8
8X (.024)
[0.6]
8
SYMM
5
4
6X (.050 )
[1.27]
8X (.024)
[0.6]
(R.002 ) TYP
[0.05]
SYMM
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
(R.002 )
[0.05]
TYP
(.217)
[5.5]
HV / ISOLATION OPTION
.162 [4.1] CLEARANCE / CREEPAGE
IPC-7351 NOMINAL
.150 [3.85] CLEARANCE / CREEPAGE
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:6X
METAL
SOLDER MASK
OPENING
EXPOSDE
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221445/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
D0008B
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
8X (.055)
[1.4]
SYMM
SYMM
1
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
8
SYMM
5
4
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(R.002 )
[0.05]
TYP
(.217)
[5.5]
(.213)
[5.4]
HV / ISOLATION OPTION
.162 [4.1] CLEARANCE / CREEPAGE
IPC-7351 NOMINAL
.150 [3.85] CLEARANCE / CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.127 MM] THICK STENCIL
SCALE:6X
4221445/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
ISO1044BD
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
1044B
ISO1044BDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
1044B
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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