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ISO1050
SLLS983I – JUNE 2009 – REVISED JANUARY 2015
ISO1050 Isolated CAN Transceiver
1 Features
3 Description
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The ISO1050 is a galvanically isolated CAN
transceiver that meets the specifications of the
ISO11898-2 standard. The device has the logic input
and output buffers separated by a silicon oxide (SiO2)
insulation barrier that provides galvanic isolation of up
to 5000 VRMS for ISO1050DW and 2500 VRMS for
ISO1050DUB. Used in conjunction with isolated
power supplies, the device prevents noise currents on
a data bus or other circuits from entering the local
ground and interfering with or damaging sensitive
circuitry.
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Meets the Requirements of ISO11898-2
5000-VRMS Isolation (ISO1050DW)
2500-VRMS Isolation (ISO1050DUB)
Fail-Safe Outputs
Low Loop Delay: 150 ns (Typical), 210 ns
(Maximum)
50-kV/μs Typical Transient Immunity
Bus-Fault Protection of –27 V to 40 V
Driver (TXD) Dominant Time-out Function
I/O Voltage Range Supports 3.3-V and 5-V
Microprocessors
VDE Approval per DIN V VDE V 0884-10 (VDE V
0884-10):2006-12 and DIN EN 61010-1
UL 1577 Approved
CSA Approved for IEC 60950-1, IEC 61010-1,
IEC 60601-1 3rd Ed (Medical) and Component
Acceptance Notice 5A
TUV 5-KVRMS Reinforced Insulation Approval for
EN/UL/CSA 60950-1 (ISO1050DW-Only)
CQC Reinforced Insulation per GB4843.1-2011
(ISO1050DW-Only)
Typical 25-Year Life at Rated Working Voltage
(see Application Report SLLA197 and Life
Expectancy vs Working Voltage)
2 Applications
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•
•
•
•
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Industrial Automation, Control, Sensors, and Drive
Systems
Building and Climate Control (HVAC) Automation
Security Systems
Transportation
Medical
Telecom
CAN Bus Standards Such as CANopen,
DeviceNet, NMEA2000, ARINC825, ISO11783,
CAN Kingdom, CANaerospace
As a CAN transceiver, the device provides differential
transmit capability to the bus and differential receive
capability to a CAN controller at signaling rates up to
1 megabit per second (Mbps). The device is designed
for operation in especially harsh environments, and it
features cross-wire, overvoltage and loss of ground
protection from –27 V to 40 V and overtemperature
shutdown, as well as –12-V to 12-V common-mode
range.
The ISO1050 is characterized for operation over the
ambient temperature range of –55°C to 105°C.
Device Information(1)
PART NUMBER
ISO1050
PACKAGE
BODY SIZE (NOM)
SOP (8)
9.50 mm × 6.57 mm
SOIC (16)
10.30 mm × 7.50 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
CANH
RXD
TXD
Isolation Capacitor
1
CANL
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ISO1050
SLLS983I – JUNE 2009 – REVISED JANUARY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
5
6
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6
6
6
7
7
7
8
8
8
9
9
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics: Supply Current.................
Electrical Characteristics: Driver ...............................
Electrical Characteristics: Receiver ..........................
Switching Characteristics: Device .............................
Switching Characteristics: Driver ..............................
Switching Characteristics: Receiver........................
Typical Characteristics ............................................
Parameter Measurement Information ................ 10
8
Detailed Description ............................................ 15
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
15
15
15
20
Application and Implementation ........................ 22
9.1 Application Information............................................ 22
9.2 Typical Application .................................................. 22
10 Power Supply Recommendations ..................... 25
11 Layout................................................................... 25
11.1 Layout Guidelines ................................................. 25
11.2 Layout Example .................................................... 25
12 Device and Documentation Support ................. 26
12.1
12.2
12.3
12.4
Documentation Support ........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
26
26
26
26
13 Mechanical, Packaging, and Orderable
Information ........................................................... 26
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision H (June 2013) to Revision I
•
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
Changes from Revision G (March 2013) to Revision H
•
Page
Page
Changed title From: LIFE EXPECTANCY vs WORKING VOLTAGE (ISO1050DW To: LIFE EXPECTANCY vs
WORKING VOLTAGE (ISO1050DUB) ................................................................................................................................. 21
Changes from Revision F (January 2013) to Revision G
Page
•
Clarified clearance and creepage measurement method in ISOLATOR CHARACTERISTICS .......................................... 15
•
Clarified test methods for voltage ratings in INSULATION CHARACTERISTICS ............................................................... 16
•
Changed UL Single Protection Certification pending to Single Protection in REGULATORY INFORMATION
SECTION (certificate available)............................................................................................................................................ 17
Changes from Revision E (December 2011) to Revision F
Page
•
Deleted ISO1050L device....................................................................................................................................................... 1
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Deleted ISO1050LDW from Features list ............................................................................................................................... 1
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Deleted ISO1050LDW in first paragraph of DESCRIPTION .................................................................................................. 1
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Added the PIN FUNCTIONS section...................................................................................................................................... 5
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Added Note 1 to the DRIVER SWITCHING CHARACTERISTICS table ............................................................................... 8
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Deleted ISO1050LDW from INSULATION CHARACTERISTICS ........................................................................................ 16
•
Deleted ISO1050LDW from REGULATORY INFORMATION.............................................................................................. 17
•
Added the FUNCTIONAL DESCRIPTION section ............................................................................................................... 17
2
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•
Deleted ISO1050LDW from LIFE EXPECTANCY vs WORKING VOLTAGE ..................................................................... 21
•
Deleted 40V from the CANH and CANL input diagrams and output diagrams in the EQUIVALENT I/O
SCHEMATICS ..................................................................................................................................................................... 21
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Changed the APPLICATION INFORMATION section.......................................................................................................... 22
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Changed the BUS LOADING, LENGHT AND NUMBER OF NODES section ..................................................................... 22
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Added the CAN TERMINATION section .............................................................................................................................. 23
Changes from Revision D (June 2011) to Revision E
Page
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Added device ISO1050L......................................................................................................................................................... 1
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Changed (DW Package) in the Features list to (ISO1050DW) .............................................................................................. 1
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Changed (DUB Package) in the Features list to (ISO1050DUB and ISO1050LDW)............................................................. 1
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Deleted IEC 60950-1 from the CSA Approvals Feature bullet ............................................................................................... 1
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From: IEC 60601-1 (Medical) and CSA Approvals Pending To: IEC 60601-1 (Medical) and CSA Approved ...................... 1
•
Added Feature - 5 KVRMS Reinforced.. ................................................................................................................................ 1
•
Changed DW Package to ISO105DW and DUB package to ISO1050DUB and ISO1050LDW in the first paragraph
of DESCRIPTION ................................................................................................................................................................... 1
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Added Note 1 to the INSULATION CHARACTERISTICS table ........................................................................................... 16
•
Changed VIORM From: 8-DUB Package to ISO1050DUB and ISO1050LDW ...................................................................... 16
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Changed VIORM From: 16-DW to ISO1050DW .................................................................................................................... 16
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Changed the VISO Isolation voltage per UL section of the INSULATION CHARACTERISTICS table. ................................ 16
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Changed the IEC 60664-1 Ratings Table ............................................................................................................................ 16
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Changed the REGULATORY INFORMATION table ............................................................................................................ 17
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Changed in note (1) 3000 to 2500 and 6000 to 5000 .......................................................................................................... 17
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Changed From: File Number: 220991 (Approval Pending) To: File Number: 220991......................................................... 17
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Changed in LIFE EXPECTANCY vs WORKING VOLTAGE (8-DUB PACKAGE TO: LIFE.....(ISO1050DW and
ISO1050LDW) ...................................................................................................................................................................... 21
Changes from Revision C (July 2010) to Revision D
Page
•
Changed the SUPPLY CURRENT table for ICC1 1st row From: Typ = 1 To: 1.8 and MAX = 2 To: 2.8................................. 7
•
Changed the SUPPLY CURRENT table for ICC1 2nd row From: Typ = 2 To: 2.8 and MAX = 3 To: 3.6 ............................... 7
•
Changed the REGULATORY INFORMATION table ............................................................................................................ 17
Changes from Revision B (June 2009) to Revision C
Page
•
Changed the IEC 60747-5-2 Features bullet From: DW package Approval Pending To: VDE approved for both DUB
and DW packages .................................................................................................................................................................. 1
•
Changed the Minimum Internal Gap value from 0.008 to 0.014 in the Isolator Characteristics table.................................. 15
•
Changed VIORM Specification From: 1300 To: 1200 per VDE certification ........................................................................... 16
•
Changed VPR Specification From 2438 To: 2250 ................................................................................................................. 16
•
Added the Bus Loading paragraph to the Application Information section .......................................................................... 22
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SLLS983I – JUNE 2009 – REVISED JANUARY 2015
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Changes from Revision A (Sept 2009) to Revision B
Page
•
Added information that IEC 60747-5-2 and IEC61010-1 have been approved...................................................................... 1
•
Changed DW package from preview to production data........................................................................................................ 5
•
Added Insulation Characteristics and IEC 60664-1 Ratings tables...................................................................................... 16
•
Added IEC file number ......................................................................................................................................................... 17
Changes from Original (June 2009) to Revision A
Page
•
Added Typical 25-Year Life at Rated Working Voltage to Features....................................................................................... 1
•
Added LIFE EXPECTANCY vs WORKING VOLTAGE section ........................................................................................... 21
4
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SLLS983I – JUNE 2009 – REVISED JANUARY 2015
5 Pin Configuration and Functions
16-Pin
DW Package
Top View
8-Pin
DUB Package
Top View
Pin Functions
PIN
NAME
DW
DUB
TYPE
DESCRIPTION
VCC1
1
1
Supply
Digital-side supply voltage (3 to 5.5 V)
GND1
2
—
Ground
Digital-side ground connection
RXD
3
2
O
NC
4
—
NC
No connect
NC
5
—
NC
No connect
TXD
6
3
I
GND1
7
4
Ground
Digital-side ground connection
GND1
8
—
Ground
Digital-side ground connection
GND2
9
5
Ground
Transceiver-side ground connection
GND2
10
—
Ground
Transceiver-side ground connection
NC
11
—
NC
No connect
CANL
12
6
I/O
Low-level CAN bus line
CANH
13
7
I/O
High-level CAN bus line
NC
14
—
NC
No connect
GND2
15
—
Ground
Transceiver-side ground connection
VCC2
16
8
Supply
Transceiver-side supply voltage (5 V)
CAN receive data output (LOW for dominant and HIGH for recessive bus states)
CAN transmit data input (LOW for dominant and HIGH for recessive bus states)
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SLLS983I – JUNE 2009 – REVISED JANUARY 2015
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6 Specifications
6.1 Absolute Maximum Ratings (1) (2)
MIN
MAX
UNIT
–0.5
6
V
Voltage input (TXD)
–0.5
VCC1+ 0.5 (4)
V
VCANH or
VCANL
Voltage at any bus terminal (CANH, CANL)
–27
40
V
IO
Receiver output current
–15
15
mA
TJ
Junction temperature
–55
150
°C
Tstg
Storage temperature
–65
150
°C
VCC1, VCC2
Supply voltage
VI
(1)
(2)
(3)
(4)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
This isolator is suitable for isolation within the safety limiting data. Maintenance of the safety data must be ensured by means of
protective circuitry.
All input and output logic voltage values are measured with respect to the GND1 logic side ground. Differential bus-side voltages are
measured to the respective bus-side GND2 ground terminal.
Maximum voltage must not exceed 6 V.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
±4000
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2)
±1500
Machine model, ANSI/ESDS5.2-1996, all pins
±200
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
VCC1
Supply voltage, controller side
VCC2
Supply voltage, bus side
NOM
3
UNIT
5.5
V
5.25
V
(1)
4.75
–12
MAX
5
VI or VIC
Voltage at bus pins (separately or common mode)
12
V
VIH
High-level input voltage
TXD
2
5.25
V
VIL
Low-level input voltage
TXD
0
0.8
V
VID
Differential input voltage
–7
7
V
Driver
–70
IOH
High-level output current
IOL
Low-level output current
TA
Ambient Temperature
–55
105
°C
TJ
Junction temperature (see Thermal Information)
–55
125
°C
PD
Total power dissipation
PD1
Power dissipation by Side-1
PD2
Power dissipation by Side-2
Tj shutdown
Thermal shutdown temperature (2)
(1)
(2)
6
Receiver
mA
–4
Driver
70
Receiver
4
mA
200
VCC1= 5.5V, VCC2= 5.25V, TA=105°C, RL= 60Ω,
TXD input is a 500kHz 50% duty-cycle square wave
25
mW
175
190
°C
The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
Extended operation in thermal shutdown may affect device reliability.
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6.4 Thermal Information
ISO1050
THERMAL METRIC (1)
DW
DUB
16 PINS
8 PINS
76.0
73.3
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
41
63.2
RθJB
Junction-to-board thermal resistance
47.7
43.0
ψJT
Junction-to-top characterization parameter
14.4
27.4
ψJB
Junction-to-board characterization parameter
38.2
42.7
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
n/a
(1)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
6.5 Electrical Characteristics: Supply Current
over recommended operating conditions (unless otherwise noted)
PARAMETER
ICC1
VCC1 Supply current
ICC2
VCC2 Supply current
(1)
MIN TYP (1) MAX
TEST CONDITIONS
VI = 0 V or VCC1 , VCC1 = 3.3V
1.8
2.8
VI = 0 V or VCC1 , VCC1 = 5V
2.3
3.6
Dominant
VI = 0 V, 60-Ω Load
52
73
Recessive
VI = VCC1
8
12
UNIT
mA
mA
All typical values are at 25°C with VCC1 = VCC2 = 5 V.
6.6 Electrical Characteristics: Driver
over recommended operating conditions (unless otherwise noted)
PARAMETER
VO(D)
Bus output voltage (Dominant)
VO(R)
Bus output voltage (Recessive)
VOD(D)
TEST CONDITIONS
CANH
CANL
Differential output voltage (Dominant)
MIN
TYP
MAX
2.9
3.5
4.5
0.8
1.2
1.5
See Figure 7 and Figure 8, VI = 2 V, RL= 60 Ω
2
2.3
3
See Figure 7, Figure 8 and Figure 9, VI = 0 V,
RL = 60 Ω
1.5
3
See Figure 7, Figure 8, and Figure 9 VI = 0 V,
RL = 45Ω, Vcc > 4.8 V
1.4
3
–0.12
0.012
–0.5
0.05
See Figure 7 and Figure 8, VI = 0 V, RL = 60 Ω
See Figure 7 and Figure 8, VI = 3 V, RL = 60 Ω
VOD(R)
Differential output voltage (Recessive)
VOC(D)
Common-mode output voltage (Dominant)
VOC(pp)
Peak-to-peak common-mode output voltage
IIH
High-level input current, TXD input
VI at 2 V
IIL
Low-level input current, TXD input
VI at 0.8 V
IO(off)
Power-off TXD leakage current
VCC1, VCC2 at 0 V, TXD at 5 V
VI = 3 V, No Load
IOS(ss)
Short-circuit steady-state output current
5
–105
See receiver input capacitance
Common-mode transient immunity
See Figure 19, VI = VCC or 0 V
1
–0.5
71
25
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V
μA
μA
mA
105
50
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V
–72
0.36
–1
See Figure 17, VCANL = 12 V, CANH Open
Output capacitance
V
μA
10
See Figure 17, VCANL =–12 V, CANH Open
CMTI
3
–5
See Figure 17, VCANH = 12 V, CANL Open
CO
2.3
0.3
See Figure 17, VCANH = –12 V, CANL Open
V
V
2
See Figure 14
UNIT
kV/μs
7
ISO1050
SLLS983I – JUNE 2009 – REVISED JANUARY 2015
www.ti.com
6.7 Electrical Characteristics: Receiver
over recommended operating conditions (unless otherwise noted)
PARAMETER
VIT+
Positive-going bus input threshold voltage
VIT–
Negative-going bus input threshold voltage
Vhys
Hysteresis voltage (VIT+ – VIT–)
VOH
High-level output voltage with Vcc = 5 V
VOH
High-level output voltage with Vcc1 = 3.3 V
VOL
Low-level output voltage
CI
TEST CONDITIONS
See Table 1
MIN
TYP (1)
MAX
UNIT
750
900
mV
500
650
mV
150
mV
IOH = –4 mA, See Figure 12
VCC – 0.8
4.6
IOH = –20 μA, See Figure 12
VCC – 0.1
5
IOL = 4 mA, See Figure 12
VCC – 0.8
3.1
IOL = 20 μA, See Figure 12
VCC – 0.1
3.3
V
V
IOL = 4 mA, See Figure 12
0.2
0.4
IOL = 20 μA, See Figure 12
0
0.1
Input capacitance to ground, (CANH or CANL)
TXD at 3 V, VI = 0.4 sin (4E6πt) + 2.5 V
6
CID
Differential input capacitance
TXD at 3 V, VI = 0.4 sin (4E6πt)
RID
Differential input resistance
TXD at 3 V
30
RIN
Input resistance (CANH or CANL)
TXD at 3 V
15
RI(m)
Input resistance matching
(1 – [RIN (CANH) / RIN (CANL)]) × 100%
VCANH = VCANL
CMTI
Common-mode transient immunity
VI = VCC or 0 V, See Figure 19
(1)
V
pF
3
pF
80
kΩ
30
40
kΩ
–3%
0%
3%
25
50
kV/μs
All typical values are at 25°C with VCC1 = VCC2 = 5 V.
6.8 Switching Characteristics: Device
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tloop1
Total loop delay, driver input to receiver output, Recessive to
Dominant
tloop2
Total loop delay, driver input to receiver output, Dominant to
Recessive
MIN
TYP
MAX
UNIT
See Figure 15
112
150
210
ns
See Figure 15
112
150
210
ns
UNIT
6.9 Switching Characteristics: Driver
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
tPLH
Propagation delay time, recessive-to-dominant output
31
74
110
tPHL
Propagation delay time, dominant-to-recessive output
25
44
75
tr
Differential output signal rise time
20
50
20
50
450
700
tf
Differential output signal fall time
tTXD_DTO
(1)
8
See Figure 10
(1)
Dominant time-out
↓ CL=100 pF, See Figure 16
300
ns
μs
The TXD dominant time out (tTXD_DTO) disables the driver of the transceiver once the TXD has been dominant longer than (tTXD_DTO)
which releases the bus lines to recessive preventing a local failure from locking the bus dominant. The driver may only transmit
dominant again after TXD has been returned HIGH (recessive). While this protects the bus from local faults locking the bus dominant it
limits the minimum data rate possible. The CAN protocol allows a maximum of eleven successive dominant bits (on TXD) for the worst
case where five successive dominant bits are followed immediately by an error frame. This along with the (tTXD_DTO) minimum limits the
minimum bit rate. The minimum bit rate may be calculated by: Minimum Bit Rate = 11/ (tTXD_DTO) = 11 bits / 300 µs = 37 kbps.
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6.10 Switching Characteristics: Receiver
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
tPLH
Propagation delay time, low-to-high-level output
66
90
130
tPHL
Propagation delay time, high-to-low-level output
51
80
105
tr
Output signal rise time
3
6
tf
Output signal fall time
3
6
tfs
Fail-Safe output delay time from bus-side power loss
TXD at 3 V, See Figure 12
VCC1 at 5 V, See Figure 18
6
UNIT
ns
μs
6.11 Typical Characteristics
163
200
161
VCC1 = 3 V,
VCC2 = 4.75 V
190
159
VCC1 = 3 V,
VCC2 = 4.75 V
157
Loop Time - ns
Loop Time - ns
180
VCC1 = 5 V,
VCC2 = 5 V
170
160
155
VCC1 = 5.5 V,
VCC2 = 5.25 V
153
151
149
150
140
-60
VCC1 = 5.5 V,
VCC2 = 5.25 V
-40
147
VCC1 = 5 V,
VCC2 = 5 V
145
-60
-20
0
20 40 60
80 100 120
TA - Free-Air Temperature - °C
Figure 1. Recessive-to-Dominant Loop Time vs Free-Air
Temperature (Across Vcc)
-40
-20
0
20 40 60
80 100 120
TA - Free-Air Temperature - °C
Figure 2. Dominant-to-Recessive Loop Time vs Free-Air
Temperature (Across Vcc)
100
3.5
VO = CANH
3
VO - Output Voltage - V
ICC - Supply Current - mA
ICC2 = 5 V
10
ICC1 = 5 V
1
250
450
550
650
750
850
2
1.5
ICC1 = 3.3 V
350
2.5
1
-60
950
Signaling Rate - kbps
VO = CANL
-40
-20
0
20 40 60
80 100 120
TA - Free-Air Temperature - °C
Figure 3. Supply Current (RMS) vs Signaling Rate (kbps)
Figure 4. Driver Output Voltage vs Free-Air Temperature
Figure 5. Emissions Spectrum to 10 MHz
Figure 6. Emissions Spectrum to 50 MHz
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7 Parameter Measurement Information
IO(CANH)
CANH
II
0 or
Vcc1
TXD
GND1
VOD
CANL
RL
VO(CANH) + VO(CANL)
2
IO(CANL)
GND2
VOC
VI
VO(CANL )
GND1
VO(CANH)
GND2
Figure 7. Driver Voltage, Current and Test Definitions
Dominant
VO (CANH)
» 3.5 V
Recessive
» 2.5 V
VO (CANL)
» 1.5 V
Figure 8. Bus Logic State Voltage Definitions
330 W ±1%
CANH
0V
TXD
VOD
60 W ±1%
CANL
+
_
-2 V < V test < 7 V
GND2
330 W ±1%
Figure 9. Driver VOD With Common-Mode Loading Test Circuit
Vcc
VI
CANH
TXD
60 W ±1% VO
CANL
VI
Vcc/2
0V
CL = 100 pF
± 20%
(SEE NOTE B)
t PLH
VO
(SEE NOTE A)
Vcc/2
t PHL
0.9V
VO(D)
90%
0.5V
10%
tr
tf
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty cycle,
tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω.
B.
CL includes instrumentation and fixture capacitance within ±20%.
VO(R)
Figure 10. Driver Test Circuit and Voltage Waveforms
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Parameter Measurement Information (continued)
CANH
VIC
=
VI(CANH) + VI(CANL)
IO
RXD
VID
2
CANL
VI(CANH)
VO
VI(CANL)
GND1
GND2
Figure 11. Receiver Voltage and Current Definitions
CANH
IO
3.5 V
RXD
V
I
2.4 V
2 V
CANL
1.5 V
t pHL
t pLH
VI
CL = 15 pF
± 20 %
(SEE NOTE B)
VO
(SEE NOTE A) 1 .5 V
0.3 Vcc 1
V
O
10 %
tf
tr
GND 2
V OH
90 %
0.7 Vcc 1
V OL
GND 1
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty cycle,
tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω.
B.
CL includes instrumentation and fixture capacitance within ±20%.
Figure 12. Receiver Test Circuit and Voltage Waveforms
Table 1. Differential Input Voltage Threshold Test
INPUT
OUTPUT
VCANH
VCANL
|VID|
–11.1 V
–12 V
900 mV
L
R
12 V
11.1 V
900 mV
L
–6 V
–12 V
6V
L
12 V
6V
6V
L
–11.5 V
–12 V
500 mV
H
12 V
11.5 V
500 mV
H
–12 V
–6 V
–6 V
H
6V
12 V
–6 V
H
Open
Open
X
H
VOL
VOH
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1 nF
CANH
RXD
CANL
15 pF
1 nF
TXD
+
VI
_
GND1
GND2
The waveforms of the applied transients are in accordance
with ISO 7637 part 1, test pulses 1, 2, 3a, and 3b.
Figure 13. Transient Overvoltage Test Circuit
27 W ±1 %
CANH
TXD
CANL
47 nF
VI
27 W ±1 %
GND 1
V OC
± 20%
=
V (CANH) + V (CANL)
O
O
2
GND 2
V
OC(pp)
V
OC
Figure 14. Peak-to-Peak Output Voltage Test Circuit and Waveform
CANH
VI
TXD
60 W ±1%
CANL
Vcc
TXD Input
50%
0V
tloop
2
RXD
RXD Output
+
VO
_
t loop1
50%
VOH
50%
VOL
15 pF ± 20%
GND1
Figure 15. tLOOP Test Circuit and Voltage Waveforms
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Vcc
VI
CANH
TXD
RL= 60 W ± 1 %
CL
0V
VOD
V OD (D)
(see Note B )
CANH
(see Note A )
900 mV
VOD
VI
500 mV
0V
t TXD_DTO
GND 1
A.
The input pulse is supplied by a generator having the following characteristics: tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω.
B.
CL includes instrumentation and fixture capacitance within ±20%.
Figure 16. Dominant Time-out Test Circuit and Voltage Waveforms
IOS (SS)
I OS (P)
I OS
15 s
CANH
TXD
0V
0 V or VCC 1
12 V
CANL
VI
-12 V or 12 V
VI
0V
GND2
or
10 ms
0V
VI
-12 V
Figure 17. Driver Short-Circuit Current Test Circuit and Waveforms
VI
VCC 2
CANH
0V
TXD
VCC2
CL
60 W ±1%
VI
+
VO
0V
t fs
CANL
VO
RXD
2.7 V
VOH
50%
VOL
15pF ± 20%
GND 1
NOTE: CL = 100pF
includes instrumentation
and fixture capacitance
within ± 20%.
Figure 18. Fail-Safe Delay Time Test Circuit and Voltage Waveforms
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C = 0.1 mF
± 1%
2.0 V
www.ti.com
VCC 1
VCC2
CANH
C = 0.1 mF ±1%
GND2
GND1
TXD
60 W
S1
VOH or VOL
CANL
0.8 V
RXD
VOH or VOL
1 kW
GND 1
GND 2
CL = 15 pF
(includes probe and
jig capacitance)
V TEST
Figure 19. Common-Mode Transient Immunity Test Circuit
CANH
ISO1050
30 W
47nF
Spectrum Analyzer
6.2 kW
10 nF
30 W
TXD
500kbps
CANL
6.2 kW
Figure 20. Electromagnetic Emissions Measurement Setup
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8 Detailed Description
8.1 Overview
The ISO1050 is a digitally isolated CAN transceiver with a typical transient immunity of 50 kV/µs. The device can
operate from 3.3-V supply on side 1 and 5-V supply on side 2. This is of particular advantage for applications
operating in harsh industrial environments because the 3.3 V on side 1 enables the connection to low-volt
microcontrollers for power preservation, whereas the 5 V on side 2 maintains a high signal-to-noise ratio of the
bus signals.
8.2 Functional Block Diagram
VCC1
VCC2
CANH
GALVANIC ISOLATION
RXD
TXD
GND1
CANL
GND2
8.3 Feature Description
Table 2. Isolator Characteristics (1) (2)
PARAMETER
L(I01)
Minimum air gap (Clearance)
TEST CONDITIONS
Shortest pin-to-pin distance through air, per JEDEC
package dimensions
L(I02)
Minimum external tracking
(Creepage)
Shortest pin-to-pin distance across the package
surface, per JEDEC package dimensions
L(I01)
Minimum air gap (Clearance)
Shortest pin-to-pin distance through air, per JEDEC
package dimensions
L(I02)
RIO
Minimum external tracking
(Creepage)
Shortest pin-to-pin distance across the package
surface, per JEDEC package dimensions
Minimum Internal Gap (Internal
Clearance)
Distance through the insulation
Isolation resistance
MIN
TYP MAX
UNIT
6.1
mm
6.8
mm
8.34
mm
8.10
mm
0.014
mm
DUB-8
DW-16
Input to output, VIO = 500 V, all pins on each side of the
barrier tied together creating a two-pin device,
TA = 25°C
>1012
Ω
Input to output, VIO = 500 V, 100°C ≤TA ≤TA max
>1011
Ω
CIO
Barrier capacitance
VI = 0.4 sin (4E6πt)
1.9
pF
CI
Input capacitance to ground
VI = 0.4 sin (4E6πt)
1.3
pF
(1)
(2)
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care
should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on
the printed-circuit-board do not reduce this distance.
Creepage and clearance on a printed-circuit-board become equal according to the measurement techniques shown in the Isolation
Glossary. Techniques such as inserting grooves and/or ribs on a printed-circuit-board are used to help increase these specifications.
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Table 3. Insulation Characteristics
PARAMETER
TEST CONDITIONS
SPECIFICATION
ISO1050DUB
560
VIORM
Maximum working insulation
voltage per DIN V VDE V 0884-10
(VDE V 0884-10):2006-12
ISO1050DW
1200
Input to output test voltage per
DIN V VDE V 0884-10 (VDE V
0884-10):2006-12
ISO1050DUB
VPR
VIOTM
Transient overvoltage per DIN V
VDE V 0884-10 (VDE V 088410):2006-12
VP R = 1.875 x VIORM, t = 1
sec (100% production)
Partial discharge < 5 pC
ISO1050DW
1050
Vpeak
2250
4000
t = 1 sec (100% production)
Isolation voltage per UL 1577
ISO1050DW - Single Protection
RS
Vpeak
t = 60 sec (qualification)
ISO1050DUB - Double Protection
VISO
UNIT
Isolation resistance
t = 60 sec (qualification)
2500
t = 1 sec (100% production)
3000
t = 60 sec (qualification)
4243
t = 1 sec (100% production)
5092
VIO = 500 V at TS
> 109
Pollution Degree
Vpeak
Vrms
Vrms
Ω
2
Table 4. IEC 60664-1 Ratings
PARAMETER
Basic isolation group
Installation classification
TEST CONDITIONS
SPECIFICATION
Material group
II
Rated mains voltage ≤ 150 Vrms
I–IV
Rated mains voltage ≤ 300 Vrms
I–III
Rated mains voltage ≤ 400 Vrms
I–II
Rated mains voltage ≤ 600 Vrms (ISO1050DW only)
I-II
Rated mains voltage ≤ 848 Vrms (ISO1050DW only)
I
Table 5. IEC Safety Limiting Values (1)
PARAMETER
TEST CONDITIONS
DUB-8
IS
Safety input, output, or supply current
DW-16
TS
(1)
MIN
TYP
MAX UNIT
θJA = 73.3 °C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C
310
θJA = 73.3 °C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C
474
θJA = 76 °C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C
299
θJA = 76 °C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C
457
Maximum case temperature
150
mA
mA
°C
Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the I/O can
allow low resistance to ground or the supply and, without current limiting dissipate sufficient power to overheat the die and damage the
isolation barrier potentially leading to secondary system failures.
The safety-limiting constraint is the absolute maximum junction temperature specified in the absolute maximum
ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the
application hardware determines the junction temperature. The assured junction-to-air thermal resistance in
Thermal Information is that of a device installed on a High-K Test Board for Leaded Surface Mount Packages.
The power is the recommended maximum input voltage times the current. The junction temperature is then the
ambient temperature plus the power times the junction-to-air thermal resistance.
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500
500
VCC1 = 3.6 V
VCC1 = VCC2 = 5.5 V
Safety Limiting Current (mA)
Safety Limiting Current (mA)
VCC1 = 3.6 V
VCC1 = VCC2 = 5.5 V
400
300
200
100
0
400
300
200
100
0
0
50
100
150
Case Temperature (°C)
200
0
50
D001
Figure 21. DUB-8 θJC Thermal Derating Curve per
VDE
100
150
Case Temperature (°C)
200
D002
Figure 22. DW-16 θJC Thermal Derating Curve per
VDE
Table 6. Regulatory Information
VDE
TUV
CSA
UL
CQC
Certified according to DIN V
VDE V 0884-10 (VDE V
0884-10):2006-12 & DIN EN
61010-1
Certified according to EN/UL/CSA Approved under CSA
60950-1
Component Acceptance
Notice 5A
Recognized under 1577
Component Recognition
Program (1)
Certified according to
GB4943.1-2011
Basic Insulation
Transient Overvoltage, 4000
VPK
Surge Voltage, 4000 VPK
Maximum Working Voltage,
1200 VPK (ISO1050DW) and
560 VPK (ISO1050DUB)
ISO1050DW:
5000 VRMS Reinforced Insulation,
400 VRMS maximum working
voltage
5000 VRMS Basic Insulation,
600 VRMS maximum working
voltage
ISO1050DUB:
2500 VRMS Reinforced Insulation,
400 VRMS maximum working
voltage
2500 VRMS Basic Insulation,
600 VRMS maximum working
voltage
5000 VRMS Reinforced
Insulation
2 Means of Patient
Protection at 125 VRMS per
IEC 60601-1 (3rd Ed.)
ISO1050DUB: 2500 VRMS
Double Protection
ISO1050DW: 3500 VRMS
Double Protection,
4243 VRMS Single Protection
ISO1050DW:
Reinforced Insulation,
Altitude ≤ 5000 m, Tropical
Climate, 250 VRMS maximum
working voltage
Certificate number:
40016131
Certificate number: U8V 11 09
77311 008
Master contract number:
220991
File number: E181974
Certificate number:
CQC14001109541
(1)
Production tested ≥ 3000 VRMS (ISO1050DUB) and 5092 VRMS (ISO1050DW) for 1 second in accordance with UL 1577.
8.3.1 CAN Bus States
The CAN bus has two states during operation: dominant and recessive. A dominant bus state, equivalent to logic
low, is when the bus is driven differentially by a driver. A recessive bus state is when the bus is biased to a
common mode of VCC / 2 through the high-resistance internal input resistors of the receiver, equivalent to a logic
high. The host microprocessor of the CAN node will use the TXD pin to drive the bus and will receive data from
the bus on the RXD pin. See Figure 23 and Figure 24.
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Typical Bus Voltage (V)
Normal & Silent Mode
4
CANH
3
Vdiff(D)
2
Vdiff(R)
CANL
1
Recessive
Logic H
Dominant
Logic L
Recessive
Logic H
Time, t
Figure 23. Bus States (Physical Bit Representation)
GALVANIC
ISOLATION
CANH
VCC/2
RXD
CANL
Figure 24. Simplified Recessive Common Mode Bias and Receiver
8.3.2 Digital Inputs and Outputs
TXD (Input) and RXD (Output):
VCC1 for the isolated digital input and output side of the device maybe supplied by a 3.3-V or 5-V supply and thus
the digital inputs and outputs are 3.3-V and 5-V compatible.
NOTE
TXD is very weakly internally pulled up to VCC1. An external pullup resistor should be used
to make sure that TXD is biased to recessive (high) level to avoid issues on the bus if the
microprocessor doesn't control the pin and TXD floats. TXD pullup strength and CAN bit
timing require special consideration when the device is used with an open-drain TXD
output on the CAN controller of the microprocessor. An adequate external pullup resistor
must be used to ensure that the TXD output of the microprocessor maintains adequate bit
timing input to the input on the transceiver.
8.3.3 Protection Features
8.3.3.1 TXD Dominant Time-Out (DTO)
TXD DTO circuit prevents the local node from blocking network communication in the event of a hardware or
software failure where TXD is held dominant longer than the time-out period tTXD_DTO. The TXD DTO circuit timer
starts on a falling edge on TXD. The TXD DTO circuit disables the CAN bus driver if no rising edge is seen
before the time-out period expires. This frees the bus for communication between other nodes on the network.
The CAN driver is re-activated when a recessive signal is seen on the TXD pin, thus clearing the TXD DTO
condition. The receiver and RXD pin still reflect the CAN bus, and the bus pins are biased to recessive level
during a TXD dominant time-out.
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NOTE
The minimum dominant TXD time allowed by the TXD DTO circuit limits the minimum
possible transmitted data rate of the device. The CAN protocol allows a maximum of
eleven successive dominant bits (on TXD) for the worst case, where five successive
dominant bits are followed immediately by an error frame. This, along with the tTXD_DTO
minimum, limits the minimum data rate. Calculate the minimum transmitted data rate by:
Minimum Data Rate = 11 / tTXD_DTO.
Fault is repaired and local node
transmission capability restored
TXD INPUT
TXD fault stuck dominant: example PCB failure or
bad software
CAN BUS OUTPUT
WITH TXD DTO
TXD
%XV ZRXOG EH ³VWXFN GRPLQDQW´ EORFNLQJ
communication for the whole network but
TXD DTO prevents this and frees the bus
for communication after the time tTXD_DTO.
Normal CAN
communication
CAN
Bus
Signal
tTXD_DTO
Communication from other
network nodes
Communication from
repaired local node
Figure 25. Example Timing Diagram for Devices With TXD DTO
8.3.3.2 Thermal Shutdown
If the junction temperature of the device exceeds the thermal shut down threshold the device turns off the CAN
driver circuits thus blocking the TXD to bus transmission path. The shutdown condition is cleared when the
junction temperature drops below the thermal shutdown temperature of the device. If the fault condition is still
present, the temperature may rise again and the device would enter thermal shut down again. Prolonged
operation with thermal shutdown conditions may affect device reliability.
NOTE
During thermal shutdown the CAN bus drivers turn off; thus no transmission is possible
from TXD to the bus. The CAN bus pins are biased to recessive level during a thermal
shutdown, and the receiver to RXD path remains operational.
8.3.3.3 Undervoltage Lockout and Fail-Safe
The supply pins have undervoltage detection that places the device in protected or fail-safe mode. This protects
the bus during an undervoltage event on VCC1 or VCC2 supply pins. If the bus-side power supply Vcc2 is lower
than about 2.7V, the power shutdown circuits in the ISO1050 will disable the transceiver to prevent false
transmissions due to an unstable supply. If Vcc1 is still active when this occurs, the receiver output (RXD) will go
to a fail-safe HIGH (recessive) value in about 6 microseconds.
Table 7. Undervoltage Lockout and Fail-Safe
VCC1
VCC2
DEVICE STATE
BUS OUTPUT
RXD
GOOD
GOOD
Functional
Per Device State and TXD
Mirrors Bus
BAD
GOOD
Protected
Recessive
High Impedance (3-state)
GOOD
BAD
Protected
High Impedance
Recessive (Fail-Safe High)
space
NOTE
After an undervoltage condition is cleared and the supplies have returned to valid levels,
the device typically resumes normal operation in 300 µs
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8.3.3.4 Floating Pins
Pullups and pulldowns should be used on critical pins to place the device into known states if the pins float. The
TXD pin should be pulled up through a resistor to VCC1 to force a recessive input level if the microprocessor
output to the pin floats.
8.3.3.5 CAN Bus Short-Circuit Current Limiting
The device has several protection features that limit the short-circuit current when a CAN bus line is shorted.
These include driver current limiting (dominant and recessive). The device has TXD dominant state time out to
prevent permanent higher short-circuit current of the dominant state during a system fault. During CAN
communication the bus switches between dominant and recessive states with the data and control fields bits,
thus the short-circuit current may be viewed either as the instantaneous current during each bus state, or as a
DC average current. For system current (power supply) and power considerations in the termination resistors
and common-mode choke ratings, use the average short-circuit current. Determine the ratio of dominant and
recessive bits by the data in the CAN frame plus the following factors of the protocol and PHY that force either
recessive or dominant at certain times:
• Control fields with set bits
• Bit-stuffing
• Interframe space
• TXD dominant time-out (fault case limiting)
These ensure a minimum recessive amount of time on the bus even if the data field contains a high percentage
of dominant bits.
NOTE
The short-circuit current of the bus depends on the ratio of recessive to dominant bits and
their respective short-circuit currents. The average short-circuit current may be calculated
with the following formula:
IOS(AVG) = %Transmit × [(%REC_Bits × IOS(SS)_REC) + (%DOM_Bits × IOS(SS)_DOM)] +
[%Receive × IOS(SS)_REC]
Where
• IOS(AVG) is the average short-circuit current.
• %Transmit is the percentage the node is transmitting CAN messages.
• %Receive is the percentage the node is receiving CAN messages.
• %REC_Bits is the percentage of recessive bits in the transmitted CAN messages.
• %DOM_Bits is the percentage of dominant bits in the transmitted CAN messages.
• IOS(SS)_REC is the recessive steady state short-circuit current.
• IOS(SS)_DOM is the dominant steady state short-circuit current.
NOTE
Consider the short.circuit current and possible fault cases of the network when sizing the
power ratings of the termination resistance and other network components.
8.4 Device Functional Modes
Table 8. Driver Function Table
INPUT
(1)
20
OUTPUTS
DRIVEN BUS STATE
TXD (1)
CANH (1)
CANL (1)
L
H
L
Dominant
H
Z
Z
Recessive
H = high level, L = low level, Z = common mode (recessive) bias to VCC / 2. See Figure 23 and
Figure 24 for bus state and common mode bias information.
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Table 9. Receiver Function Table
DEVICE MODE
CAN DIFFERENTIAL INPUTS
VID = VCANH – VCANL
BUS STATE
RXD PIN (1)
L
Normal or Silent
(1)
VID ≥ 0.9 V
Dominant
0.5 V < VID < 0.9 V
?
?
VID ≤ 0.5 V
Recessive
H
Open (VID ≈ 0 V)
Open
H
H = high level, L = low level, ? = indeterminate.
Table 10. Function Table (1)
DRIVER
INPUTS
(1)
(2)
RECEIVER
OUTPUTS
BUS STATE
CANL
DIFFERENTIAL INPUTS
VID = CANH–CANL
OUTPUT
RXD
BUS STATE
TXD
CANH
L (2)
H
L
DOMINANT
VID ≥ 0.9 V
L
DOMINANT
H
Z
Z
RECESSIVE
0.5 V < VID < 0.9 V
?
?
Open
Z
Z
RECESSIVE
VID ≤ 0.5 V
H
RECESSIVE
X
Z
Z
RECESSIVE
Open
H
RECESSIVE
H = high level; L = low level; X = irrelevant; ? = indeterminate; Z = high impedance
Logic low pulses to prevent dominant time-out.
TXD Input
VCC1
RXD Output
VCC1
VCC1
VCC1
1 MW
IN
8W
500 W
OUT
13 W
CANL Input
CANH Input
Vcc2
Vcc2
10 kW
10 kW
20 kW
20 kW
Input
Input
10 kW
10 kW
CANH and CANL Outputs
Vcc2
CANH
CANL
Figure 26. Equivalent I/O Schematics
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
ISO1050 can be used with other components from TI such as a microcontroller, a transformer driver, and a linear
voltage regulator to form a fully isolated CAN interface.
9.2 Typical Application
SN6501
GND2
D2
VCC
4
8
3
2
7
6
TPS76350
1
IN
OUT
3
2
1
D1
GND1
5
5
EN
GND
NC
4
ISO1050
1
2
4
3
Vdd
L1
RXD
3.3V
TXD
N
MCU
PSU
PE
0V
5
6
7
8
VCC1
VCC2
16
GND1
NC
RXD
NC
CANH
NC
CANL
TXD
NC
14
13
12
11
15
GND1
GND1
GND2
Optional Bus
protection
function
9,10
DGND
Protective
Earth
Chasis
Ground
Galvanic
Isolation
Barrier
Digital
Ground
ISO
Ground
Figure 27. Application Circuit
9.2.1 Design Requirements
Unlike optocoupler-based solution, which needs several external components to improve performance, provide
bias, or limit current, ISO1050 only needs two external bypass capacitors to operate.
9.2.2 Detailed Design Procedure
9.2.2.1 Bus Loading, Length and Number of Nodes
The ISO11898 Standard specifies a maximum bus length of 40 m and maximum stub length of 0.3 m with a
maximum of 30 nodes. However, with careful design, users can have longer cables, longer stub lengths, and
many more nodes to a bus. A high number of nodes requires a transceiver with high input impedance such as
the ISO1050.
22
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Typical Application (continued)
Many CAN organizations and standards have scaled the use of CAN for applications outside the original
ISO11898 standard. They have made system level trade offs for data rate, cable length, and parasitic loading of
the bus. Examples of some of these specifications are ARINC825, CANopen, CAN Kingdom, DeviceNet and
NMEA200.
A CAN network design is a series of tradeoffs, but these devices operate over wide –12-V to 12-V commonmode range. In ISO11898-2 the driver differential output is specified with a 60-Ω load (the two 120-Ω termination
resistors in parallel) and the differential output must be greater than 1.5 V. The ISO1050 is specified to meet the
1.5-V requirement with a 60-Ω load, and additionally specified with a differential output of 1.4 V with a 45-Ω load.
The differential input resistance of the ISO1050 is a minimum of 30 kΩ. If 167 ISO1050 transceivers are in
parallel on a bus, this is equivalent to a 180-Ω differential load. That transceiver load of 180 Ω in parallel with the
60 Ω gives a total 45 Ω. Therefore, the ISO1050 theoretically supports over 167 transceivers on a single bus
segment with margin to the 1.2-V minimum differential input at each node. However for CAN network design
margin must be given for signal loss across the system and cabling, parasitic loadings, network imbalances,
ground offsets and signal integrity thus a practical maximum number of nodes is typically much lower. Bus length
may also be extended beyond the original ISO11898 standard of 40 m by careful system design and data rate
tradeoffs. For example, CAN open network design guidelines allow the network to be up to 1km with changes in
the termination resistance, cabling, less than 64 nodes and significantly lowered data rate.
This flexibility in CAN network design is one of the key strengths of the various extensions and additional
standards that have been built on the original ISO11898 CAN standard. In using this flexibility comes the
responsibility of good network design.
9.2.2.2 CAN Termination
The ISO11898 standard specifies the interconnect to be a single twisted pair cable (shielded or unshielded) with
120-Ω characteristic impedance (ZO). Resistors equal to the characteristic impedance of the line should be used
to terminate both ends of the cable to prevent signal reflections. Unterminated drop-lines (stubs) connecting
nodes to the bus should be kept as short as possible to minimize signal reflections. The termination may be in a
node, but if nodes may be removed from the bus, the termination must be carefully placed so that it is not
removed from the bus.
Node 1
Node 2
Node 3
MCU or DSP
MCU or DSP
MCU or DSP
CAN
Controller
CAN
Controller
CAN
Controller
CAN
Transceiver
CAN
Transceiver
CAN
Transceiver
Node n
(with termination)
MCU or DSP
CAN
Controller
CAN
Transceiver
RTERM
RTERM
Figure 28. Typical CAN Bus
Termination may be a single 120-Ω resistor at the end of the bus, either on the cable or in a terminating node. If
filtering and stabilization of the common mode voltage of the bus is desired, then split termination may be used.
(See Figure 29). Split termination improves the electromagnetic emissions behavior of the network by eliminating
fluctuations in the bus common-mode voltages at the start and end of message transmissions.
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Typical Application (continued)
Split Termination
Standard Termination
CANH
CANH
RTERM/2
CAN
CAN
RTERM
Transceiver
Transceiver
CSPLIT
RTERM/2
CANL
CANL
Figure 29. CAN Bus Termination Concepts
9.2.3 Application Curve
Life Expectancy – Years
100
VIORM at 560 V
28 Years
10
0
120
250
500
750
880
1000
VIORM – Working Voltage – V
G001
Figure 30. Life Expectancy vs Working Voltage (ISO1050DUB)
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10 Power Supply Recommendations
To ensure reliable operation at all data rates and supply voltages, a 0.1-µF bypass capacitor is recommended at
input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins as
possible. If only a single primary-side power supply is available in an application, isolated power can be
generated for the secondary-side with the help of a transformer driver such as TI's SN6501. For such
applications, detailed power supply design and transformer selection recommendations are available in SN6501
data sheet (SLLSEA0).
11 Layout
11.1 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 31). Layer stacking should
be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency
signal layer.
• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/in2.
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power / ground plane system to the
stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the
power and ground plane of each power system can be placed closer together, thus increasing the high-frequency
bypass capacitance significantly.
For detailed layout recommendations, see Application Note SLLA284, Digital Isolator Design Guide.
11.1.1 PCB Material
For digital circuit boards operating below 150 Mbps, (or rise and fall times higher than 1 ns), and trace lengths of
up to 10 inches, use standard FR-4 epoxy-glass as PCB material. FR-4 (Flame Retardant 4) meets the
requirements of Underwriters Laboratories UL94-V0, and is preferred over cheaper alternatives due to its lower
dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and its selfextinguishing flammability-characteristics.
11.2 Layout Example
High-speed traces
10 mils
Ground plane
40 mils
Keep this
space free
from planes,
traces, pads,
and vias
FR-4
0r ~ 4.5
Power plane
10 mils
Low-speed traces
Figure 31. Recommended Layer Stack
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
• High-Voltage Lifetime of the ISO72x Family of Digital Isolators (SLLA197)
• Transformer Driver for Isolated Power Supplies (SLLSEA0)
• Digital Isolator Design Guide (SLLA284)
• Isolation Glossary (SLLA353)
12.2 Trademarks
All trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
26
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PACKAGE OUTLINE
DW0016B
SOIC - 2.65 mm max height
SCALE 1.500
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
14X 1.27
16
1
2X
8.89
10.5
10.1
NOTE 3
8
9
0.51
0.31
0.25
C A
16X
B
7.6
7.4
NOTE 4
2.65 MAX
B
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 -8
1.27
0.40
DETAIL A
(1.4)
TYPICAL
4221009/B 07/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
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EXAMPLE BOARD LAYOUT
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (2)
16X (1.65)
SEE
DETAILS
1
SEE
DETAILS
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
9
8
9
8
R0.05 TYP
R0.05 TYP
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
LAND PATTERN EXAMPLE
SCALE:4X
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
0.07 MAX
ALL AROUND
METAL
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221009/B 07/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
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EXAMPLE STENCIL DESIGN
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (1.65)
16X (2)
1
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
9
8
9
8
R0.05 TYP
R0.05 TYP
(9.3)
(9.75)
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
4221009/B 07/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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29
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ISO1050DUB
ACTIVE
SOP
DUB
8
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
-55 to 105
ISO1050
ISO1050DUBR
ACTIVE
SOP
DUB
8
350
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
-55 to 105
ISO1050
ISO1050DW
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-55 to 105
ISO1050
ISO1050DWR
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-55 to 105
ISO1050
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2014
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
ISO1050DUBR
SOP
DUB
8
350
330.0
24.4
10.9
10.01
5.85
16.0
24.0
Q1
ISO1050DWR
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
ISO1050DUBR
SOP
DUB
ISO1050DWR
SOIC
DW
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
8
350
346.0
346.0
41.0
16
2000
350.0
350.0
43.0
Pack Materials-Page 2
PACKAGE OUTLINE
DUB0008A
SOP - 4.85 mm max height
SCALE 1.200
SMALL OUTLINE PACKAGE
C
10.7
TYP
10.1
SEATING PLANE
PIN 1 ID
A
0.1 C
8
1
6X 2.54
9.55
9.02
NOTE 3
2X
7.62
4X
(1.524)
4
5
4X (0.99)
B
6.87
6.37
8X
0.555
0.355
0.1 C A B
6.82
6.32
TOP MOLD
0.355
TYP
0.204
SEE DETAIL A
4.85 MAX
0.635
GAGE PLANE
0 -8
1.45
1.15
0.38 MIN
DETAIL A
TYPICAL
4222355/G 04/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.254 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DUB0008A
SOP - 4.85 mm max height
SMALL OUTLINE PACKAGE
8X (2.35)
8X (2.35)
SYMM
SYMM
1
1
8
8
(R0.05)
TYP
8X (0.65)
(R0.05)
TYP
8X (0.65)
SYMM
SYMM
6X (2.54)
6X (2.54)
5
4
5
4
(9.1)
(9.45)
IPC-7351 NOMINAL
6.75 mm CLEARANCE/CREEPAGE
HV / ISOLATION OPTION
7.1 mm CLEARANCE/CREEPAGE
LAND PATTERN EXAMPLES
EXPOSED METAL SHOWN
SCALE:5X
SOLDER MASK
OPENING
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED METAL
0.07 MIN
ALL AROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4222355/G 04/2019
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DUB0008A
SOP - 4.85 mm max height
SMALL OUTLINE PACKAGE
8X (2.35)
8X (2.35)
SYMM
1
SYMM
1
8
8
(R0.05)
TYP
8X (0.65)
(R0.05)
TYP
8X (0.65)
SYMM
SYMM
6X (2.54)
6X (2.54)
5
4
5
4
(9.1)
(9.45)
IPC-7351 NOMINAL
6.75 mm CLEARANCE/CREEPAGE
HV / ISOLATION OPTION
7.1 mm CLEARANCE/CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:5X
4222355/G 04/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
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