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ISO1410, ISO1412, ISO1430, ISO1432
ISO1450, ISO1452
SLLSF22G – APRIL 2018 – REVISED JUNE 2020
ISO14xx 5-kVRMS Isolated RS-485/RS-422 Transceiver
with Robust EMC
1 Features
3 Description
•
•
•
The ISO14xx devices are galvanically-isolated
differential line transceivers for TIA/EIA RS-485 and
RS-422
applications.
These
noise-immune
transceivers are designed to operate in harsh
industrial environments. The bus pins of these
devices can endure high levels of IEC electrostatic
discharge (ESD) and IEC electrical fast transient
(EFT) events which eliminates the need for additional
components on bus for system-level protection. The
devices are available for both basic and reinforced
isolation (see Reinforced and Basic Isolation
Options).
1
•
•
•
•
•
•
•
•
•
•
Compatible with TIA/EIA-485-A
PROFIBUS compatible at 5-V bus-side supply
Bus I/O protection
– ± 30 kV HBM
– ±16 kV IEC 61000-4-2 Contact discharge
– ± 4 kV IEC 61000-4-4 Electrical fast transient
Low-EMI 500-kbps, 12 Mbps and 50 Mbps Data
Rates
1.71-V to 5.5-V logic-side supply (VCC1), 3-V to
5.5-V bus-side supply (VCC2)
Failsafe receiver for bus open, short, and idle
1/8 Unit load up to 256 nodes on bus
100-kV/µs (typical) high common-mode transient
immunity
Extended temperature range from –40°C to
+125°C
Glitch-free power-up and power-down for hot plugin
Wide-body SOIC-16 package
Pin compatible to most isolated RS-485
transceivers
Safety-related certifications:
– 7071-VPK VIOTM and 1500-VPK VIORM
(reinforced and basic options) per DIN VDE V
0884-11:2017-01
– 5000-VRMS isolation for 1 minute per UL 1577
– IEC 60950-1, IEC 62368-1, IEC 60601-1 and
IEC 61010-1 certifications
– CQC, TUV, and CSA approvals
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
ISO1410, ISO1410B
ISO1412, ISO1412B
ISO1430, ISO1430B
ISO1432, ISO1432B
SOIC (16)
10.30 mm × 7.50 mm
ISO1450, ISO1450B
ISO1452, ISO1452B
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Reinforced and Basic Isolation Options
Feature
ISO14xx
ISO14xxB
Protection level
Reinforced
Basic
Surge test voltage per
VDE
10000 VPK
6000 VPK
Isolation rating per UL
5000 VRMS
5000VRMS
Working voltage per VDE
1060 VRMS /
1500 VPK
1060 VRMS /
1500 VPK
Simplified Application Schematic
2 Applications
•
•
•
•
•
Grid infrastructure
Solar inverter
Factory automation & control
Motor drives
HVAC systems and building automation
Logic Supply
VCC2
VCC1
Bus-Side Supply
VDD
DE
MCU
TI Isolated
Transceiver
A
D
B
RS485 Bus
R
DGND
RE
GND1
GND2
Isolated Ground
Logic Ground
Galvanic Isolation
Barrier
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
ISO1410, ISO1412, ISO1430, ISO1432
ISO1450, ISO1452
SLLSF22G – APRIL 2018 – REVISED JUNE 2020
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description Continued ..........................................
Device Options.......................................................
Pin Configuration and Functions .........................
Specifications.........................................................
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
8.11
8.12
8.13
8.14
8.15
1
1
1
2
4
4
5
7
Absolute Maximum Ratings ...................................... 7
ESD Ratings.............................................................. 7
Recommended Operating Conditions....................... 7
Thermal Information .................................................. 8
Power Ratings........................................................... 8
Insulation Specifications............................................ 9
Safety-Related Certifications................................... 10
Safety Limiting Values ............................................ 10
Electrical Characteristics: Driver ............................. 11
Electrical Characteristics: Receiver ...................... 11
Supply Current Characteristics: Side 1 (ICC1) ....... 13
Supply Current Characteristics: Side 2 (ICC2) ....... 14
Switching Characteristics: Driver .......................... 15
Switching Characteristics: Receiver...................... 15
Insulation Characteristics Curves ......................... 16
8.16 Typical Characteristics .......................................... 17
9 Parameter Measurement Information ................ 23
10 Detailed Description ........................................... 26
10.1
10.2
10.3
10.4
Overview ...............................................................
Functional Block Diagram .....................................
Feature Description...............................................
Device Functional Modes......................................
26
26
27
28
11 Application and Implementation........................ 31
11.1 Application Information.......................................... 31
11.2 Typical Application ................................................ 32
12 Power Supply Recommendations ..................... 35
13 Layout................................................................... 35
13.1 Layout Guidelines ................................................. 35
13.2 Layout Example .................................................... 36
14 Device and Documentation Support ................. 37
14.1
14.2
14.3
14.4
14.5
14.6
14.7
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resource............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
37
37
37
37
37
37
38
15 Mechanical, Packaging, and Orderable
Information ........................................................... 38
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (February 2020) to Revision G
•
Page
Added minimum driver rise/fall time specification of 240 ns to 8.13 Switching characteristics: Driver (500kbps devices).. 15
Changes from Revision E (October 2019) to Revision F
•
Page
Added updated certification information in Safety-Related Certifications............................................................................. 10
Changes from Revision D (May 2019) to Revision E
•
Page
Added footnote to Pin functions table for NC pins ................................................................................................................ 5
Changes from Revision C (April 2019) to Revision D
•
Page
Added B part numbers throughout datasheet ....................................................................................................................... 1
Changes from Revision B (November 2018) to Revision C
Page
•
Added ISO1430, ISO1432, ISO1450, ISO1452 in Device Information table ......................................................................... 1
•
Changed the position of Device Features tabels .................................................................................................................. 4
•
Added footnote to Pin Functions: Full-Duplex Device ............................................................................................................ 5
•
Added footnote to Pin Functions: Half-Duplex Device ........................................................................................................... 6
•
Added Typical curves for ISO143x and ISO145x in Typical Characteristics ...................................................................... 17
2
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•
SLLSF22G – APRIL 2018 – REVISED JUNE 2020
Added Section 11.2.3 Application Curves and Section 11.2.3.1 Insulation Lifetime............................................................ 33
Changes from Revision A (August 2018) to Revision B
•
Page
Changed status to production data ....................................................................................................................................... 1
Changes from Original (July 2018) to Revision A
Page
•
Changed the designator of common mode voltage in Recommended operating condition to VI .......................................... 7
•
Added test condition for CMTI in Electrical characteristics: Driver
•
Added test condition for CMTI in Electrical characteristics: Receiver .................................................................................. 12
•
Changed VTEST to VCM in the Common Mode Transient Immunity (CMTI)—Full Duplex and Common Mode Transient
Immunity (CMTI)—Half Duplex figures in the Parameter Measurement Information section .............................................. 23
•
Changed tPLH to tPZH and tPLZ to tPHZ in the first Driver Enable and Disable Times timing diagram in the Parameter
Measurement Information section ........................................................................................................................................ 24
•
Added tPHZ to the first Receiver Enable and Disable Times timing diagram in the Parameter Measurement
Information section .............................................................................................................................................................. 25
Copyright © 2018–2020, Texas Instruments Incorporated
................................................................................... 11
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5 Description Continued
These devices are used for long distance communications. Isolation breaks the ground loop between the
communicating nodes, allowing for a much larger common mode voltage range. The symmetrical isolation barrier
of each device is tested to provide 5000 VRMS of isolation for 1 minute per UL 1577 between the bus-line
transceiver and the logic-level interface.
The ISO14xx devices can operate from 1.71 V to 5.5 V on side 1 which lets the devices be interfaced with low
voltage FPGAs and ASICs. The wide supply voltage on side 2 from 3 V to 5.5 V eliminates the need for a
regulated supply voltage on the isolated side. These devices support a wide operating ambient temperature
range from –40°C to +125°C.
6 Device Options
Table 1 shows an overview of the options available for this family of devices.
Table 1. Device Features
DUPLEX
DATA RATE
PACKAGE
ISO1410, ISO1410B
PART NUMBER
Half
500 Kbps
16-pin DW
ISO1412, ISO1412B
Full
500 Kbps
16-pin DW
Half
12 Mbps
16-pin DW
Full
12 Mbps
16-pin DW
ISO1450, ISO1450B
Half
50 Mbps
16-pin DW
ISO1452, ISO1452B
Full
50 Mbps
16-pin DW
ISO1430, ISO1430B
ISO1432, ISO1432B
4
ISOLATION
Reinforced, Basic
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SLLSF22G – APRIL 2018 – REVISED JUNE 2020
7 Pin Configuration and Functions
DW Package
16-Pin SOIC
Full-Duplex Device Top View
1
16
VCC2
GND1
2
15
GND2
R
3
14
A
RE
4
13
B
DE
5
12
Z
D
6
11
Y
NC
7
10
NC
GND1
8
9
ISOLATION
VCC1
GND2
Not to scale
Pin Functions: Full-Duplex Device
PIN
NAME
NO.
I/O
DESCRIPTION
A
14
I
Receiver non-inverting input on the bus side
B
13
I
Receiver inverting input on the bus side
D
6
I
Driver input
DE
5
I
Driver enable. This pin enables the driver output when high and disables the driver
output when low or open.
GND1 (1)
2
—
Ground connection for VCC1
GND1 (1)
8
—
Ground connection for VCC1
GND2 (1)
9
—
Ground connection for VCC2
GND2
(1)
15
—
Ground connection for VCC2
NC (2)
7
—
No internal connection
NC (2)
10
—
No internal connection
R
3
O
Receiver output
RE
4
I
Receiver enable. This pin disables the receiver output when high or open and
enables the receiver output when low.
VCC1
1
—
Logic-side power supply
VCC2
16
—
Transceiver-side power supply
Y
11
O
Driver non-inverting output
Z
12
O
Driver inverting output
(1)
(2)
For Logic side, both Pin 2 and Pin 8 must be connected to GND1. For Bus side, both Pin 9 and Pin 15 must be connected to GND2.
Device functionality is not affected if NC pins are connected to supply or ground on PCB
Copyright © 2018–2020, Texas Instruments Incorporated
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DW Package
16-Pin SOIC
Half-Duplex Device Top View
1
16
VCC2
GND1
2
15
GND2
R
3
14
NC
RE
4
13
B
DE
5
12
A
D
6
11
NC
NC
7
10
NC
GND1
8
9
ISOLATION
VCC1
GND2
Not to scale
Pin Functions: Half-Duplex Device
PIN
NAME
I/O
NO.
DESCRIPTION
A
12
I/O
Transceiver non-inverting input or output (I/O) on the bus side
B
13
I/O
Transceiver inverting input or output (I/O) on the bus side
D
6
I
Driver input
DE
5
I
Driver enable. This pin enables the driver output when high and disables the driver
output when low or open.
GND1 (1)
2
—
Ground connection for VCC1
GND1 (1)
8
—
Ground connection for VCC1
GND2 (1)
9
—
Ground connection for VCC2
GND2
(1)
15
—
Ground connection for VCC2
NC (2)
7
—
No internal connection
NC (2)
10
—
No internal connection
(2)
11
—
No internal connection
NC (2)
14
—
No internal connection
R
3
O
Receiver output
RE
4
I
Receiver enable. This pin disables the receiver output when high or open and
enables the receiver output when low.
VCC1
1
—
Logic-side power supply
VCC2
16
—
Transceiver-side power supply
NC
(1)
(2)
6
For Logic side, both Pin 2 and Pin 8 must be connected to GND1. For Bus side, both Pin 9 and Pin 15 must be connected to GND2.
Device functionality is not affected if NC pins are connected to supply or ground on PCB
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SLLSF22G – APRIL 2018 – REVISED JUNE 2020
8 Specifications
8.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN
MAX
VCC1
Supply voltage, side 1
-0.5
6
V
VCC2
Supply voltage, side 2
-0.5
6
V
VIO
Logic voltage level (D, DE, RE, R)
-0.5
VCC1+0.5 (3)
IO
Output current on R pin
-15
15
VBUS
Voltage on bus pins (A, B, Y, Z w.r.t GND2)
-18
18
V
TJ
Junction temperature
-40
150
℃
TSTG
Storage temperature
-65
150
℃
(1)
(2)
(3)
UNIT
V
mA
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak
voltage values.
Maximum voltage must not exceed 6 V
8.2 ESD Ratings
VALUE
UNIT
Contact Discharge, per IEC 61000-4-2
Pins Bus terminals and GND2
±16000
V
V(ESD)
Contact Discharge, per IEC 61000-4-2
ISO141x, Pins Bus terminals and GND1
(across isolation barrier)
±8000
V
V(ESD)
Contact Discharge, per IEC 61000-4-2
ISO143x, Pins Bus terminals and GND1
(across isolation barrier)
±8000
V
All pins except bus pins (1)
±6000
V
Bus terminals to GND2 (1)
±30000
All pins (2)
±1500
V(ESD)
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001
Electrostatic discharge
Charged device model (CDM), per
JEDEC specification JESD22-C101
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
VCC1
MIN
MAX
UNIT
Supply Voltage, Side 1, 1.8-V operation
1.71
1.89
V
Supply Voltage, Side 1, 2.5-V, 3.3-V and 5.5-V operation
2.25
5.5
V
VCC2
Supply Voltage, Side 2
VI
Common Mode voltage at any bus terminal: A or B
3
5.5
V
-7
12
VIH
V
High-level input voltage (D, DE, RE inputs)
0.7*Vcc1
Vcc1
V
VIL
Low-level input voltage (D, DE, RE inputs)
0
0.3*Vcc1
V
VID
Differential input voltage, A with respect to B
-15
15
V
IO
Output current, Driver
-60
60
mA
IOR
Output current, Receiver
-4
4
mA
RL
Differential load resistance
54
1/tUI
Signaling rate ISO141x
500
kbps
1/tUI
Signaling Rate ISO143x
12
Mbps
1/tUI
Signaling rate ISO145x
50
Mbps
TA
Operating ambient temperature
125
°C
Copyright © 2018–2020, Texas Instruments Incorporated
-40
Ω
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8.4 Thermal Information
ISO14xx
THERMAL METRIC (1)
DW (SOIC)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
67.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
27.7
°C/W
RθJB
Junction-to-board thermal resistance
29.4
°C/W
ψJT
Junction-to-top characterization parameter
12.9
°C/W
ψJB
Junction-to-board characterization parameter
28.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
8.5 Power Ratings
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCC1 = VCC2 = 5.5 V, TJ = 150°C, A-B
load = 54 Ω ||50pF, Load on R=15pF
Input a 250kHz 50% duty cycle square
wave to D pin with
VDE=VCC1, VRE=GND1
556
mW
28
mW
528
mW
VCC1 = VCC2 = 5.5 V, TJ = 150°C, A-B
load = 54 Ω ||50pF, Load on R=15pF
Input a 6MHz 50% duty cycle square
wave to D pin with
VDE=VCC1, VRE=GND1
352
mW
33
mW
319
mW
VCC1 = VCC2 = 5.5 V, TJ = 150°C, A-B
load = 54 Ω ||50pF, Load on R=15pF
Input a 25MHz 50% duty cycle square
wave to D pin with
VDE=VCC1, VRE=GND1
588
mW
49
mW
539
mW
ISO1410_ISO1412
PD
Maximum power dissipation (both sides)
PD1
Maximum power dissipation (side-1)
PD2
Maximum power dissipation (side-2)
ISO1430_ISO1432
PD
Maximum power dissipation (both sides)
PD1
Maximum power dissipation (side-1)
PD2
Maximum power dissipation (side-2)
ISO1450_ISO1452
PD
Maximum power dissipation (both sides)
PD1
Maximum power dissipation (side-1)
PD2
Maximum power dissipation (side-2)
8
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8.6 Insulation Specifications
PARAMETER
SPECIFICATIONS
TEST CONDITIONS
DW-16
UNIT
IEC 60664-1
External clearance
(1)
Side 1 to side 2 distance through air
>8
mm
CPG
External creepage
(1)
Side 1 to side 2 distance across package surface >8
mm
DTI
Distance through the insulation
Minimum internal gap (internal clearance)
>17
µm
CTI
Comparative tracking index
IEC 60112; UL 746A
>600
V
Material Group
According to IEC 60664-1
I
Rated mains voltage ≤ 600 VRMS
I-IV
Rated mains voltage ≤ 1000 VRMS
I-III
CLR
Overvoltage category
(2)
DIN VDE V 0884-11:2017-01
VIORM
VIOWM
VIOTM
Maximum repetitive peak isolation voltage AC voltage (bipolar)
1500
VPK
AC voltage (sine wave); time-dependent
dielectric breakdown (TDDB) test; see Figure 56
1060
VRMS
DC voltage
1500
VDC
Maximum transient isolation voltage
VTEST = VIOTM , t = 60 s (qualification); VTEST =
1.2 × VIOTM, t = 1 s (100% production)
7071
VPK
Maximum surge isolation voltage
ISO141x (3)
Test method per IEC 62368-1, 1.2/50 µs
waveform, VTEST = 1.6 × VIOSM = 10000 VPK
(qualification)
6250
VPK
Maximum surge isolation voltage
ISO141xB (3)
Test method per IEC 62368-1, 1.2/50 µs
waveform, VTEST = 1.3 × VIOSM = 6000 VPK
(qualification)
4615
VPK
Method a: After I/O safety test subgroup 2/3, Vini
= VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM , tm = 10
s
≤5
Method a: After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
ISO14xx: Vpd(m) = 1.6 × VIORM , tm = 10 s
ISO14xxB: Vpd(m) = 1.2 × VIORM , tm = 10 s
≤5
Maximum working isolation voltage
VIOSM
qpd
Apparent charge
(4)
pC
Method b1: At routine test (100% production)
and preconditioning (type test), Vini = VIOTM, tini =
1 s;
≤5
ISO14xx: Vpd(m) = 1.875 × VIORM , tm = 1 s
ISO14xxB: Vpd(m) = 1.5 × VIORM , tm = 1 s
CIO
Barrier capacitance, input to output
RIO
(5)
Insulation resistance, input to output
(5)
VIO = 0.4 × sin (2 πft), f = 1 MHz
1
pF
12
VIO = 500 V, TA = 25°C
> 10
VIO = 500 V, 100°C ≤ TA ≤ 150°C
> 1011
VIO = 500 V at TS = 150°C
> 109
Pollution degree
2
Climatic category
40/125/21
Ω
UL 1577
VISO
(1)
(2)
(3)
(4)
(5)
Withstand isolation voltage
VTEST = VISO , t = 60 s (qualification);
VTEST = 1.2 × VISO , t = 1 s (100% production)
5000
VRMS
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care
should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on
the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications.
ISO14xx is suitable for safe electrical insulation and ISO14xxB is suitable for basic electrical insulation only within the safety ratings.
Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
Apparent charge is electrical discharge caused by a partial discharge (pd).
All pins on each side of the barrier tied together creating a two-pin device.
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8.7 Safety-Related Certifications
VDE
CSA
UL
CQC
TUV
Certified according to
GB4943.1-2011
Certified according to EN
61010-1:2010/A1:2019,
EN 609501:2006/A2:2013 and EN
62368-1:2014
Maximum transient
isolation voltage,
7071 VPK;
Maximum repetitive peak
isolation voltage,
1500 VPK;
Maximum surge isolation
voltage,
ISO141x, ISO143x,
ISO145x: 6250 VPK
(Reinforced)
ISO141xB, ISO143xB,
ISO145xB: 4600 VPK
(Basic)
CSA 60950-1-07+A1+A2,
IEC 60950-1 2nd
Ed.+A1+A2, CSA 623681-14, and IEC 62368-1
2nd Ed., for pollution
degree 2, material group I
ISO141x, ISO143x,
ISO145x: 800 VRMS
reinforced isolation
ISO141xB, ISO143xB,
Single protection,
ISO145xB: 800 VRMS
5000 VRMS
basic isolation
---------------CSA 60601- 1:14 and IEC
60601-1 Ed. 3.1,
ISO141x, ISO143x,
ISO145x: 2 MOPP
(Means of Patient
Protection) 250 VRMS (354
VPK) maximum working
voltage
Reinforced insulation,
Altitude ≤ 5000 m,
Tropical Climate,
700 VRMS maximum
working voltage
EN 610101:2010 /A1:2019
ISO141x, ISO143x,
ISO145x: 600 VRMS
reinforced isolation
ISO141xB, ISO143xB,
ISO145xB: 1000 VRMS
basic isolation
---------------EN 609501:2006/A2:2013 and EN
62368-1:2014
ISO141x, ISO143x,
ISO145x: 800 VRMS
reinforced isolation
ISO141xB, ISO143xB,
ISO145xB: 1060 VRMS
basic isolation
Reinforced
certificate:40040142
Basic certificate:
40047657
Master contract number:
220991
Certificate number:
CQC15001121716
Client ID number: 77311
Certified according to DIN
VDE V 0884-11:2017- 01
Certified according to IEC
60950-1, IEC 62368-1
and IEC 60601-1
Recognized under UL
1577 Component
Recognition Program
File number: E181974
8.8 Safety Limiting Values
Safety limiting (1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DW-16 PACKAGE
IS
Safety input, output, or supply current
PS
Safety input, output, or total power
TS
Maximum safety temperature
(1)
10
RθJA = 67.9°C/W, VI = 5.5 V, TJ = 150°C,
TA = 25°C, see Figure 1
334
RθJA = 67.9°C/W, VI = 3.6 V, TJ = 150°C,
TA = 25°C, see Figure 1
511
RθJA = 67.9°C/W, VI = 2.75 V, TJ =
150°C, TA = 25°C, see Figure 1
669
RθJA = 67.9°C/W, VI = 1.89 V, TJ =
150°C, TA = 25°C, see Figure 1
974
RθJA = 67.9°C/W, TJ = 150°C, TA = 25°C,
see Figure 2
mA
1837
mW
150
°C
The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS
and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be
exceeded. These limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the table is that of a device installed on a high-K test board for leaded surface-mount
packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum allowed junction temperature.
PS = IS × VI, where VI is the maximum input voltage.
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8.9 Electrical Characteristics: Driver
All typical specs are at VCC1=3.3V, VCC2=5V, TA=27°C, (Min/Max specs are over recommended operating conditions unless
otherwise noted)
PARAMETER
|VOD|
TEST CONDITIONS
Driver differential-output voltage
magnitude
MIN
TYP
MAX
UNIT
Open circuit voltage, unloaded bus,
3 V ≤ VCC2 ≤ 5.5 V
1.5
5
VCC2
V
RL = 60 Ω, –7 V ≤ VTEST ≤ 12 V (see Figure 35), 3 V
≤ VCC2 ≤ 3.6 V, TA100C
1.5
2.3
RL = 60 Ω, –7 V ≤ VTEST ≤ 12 V,
4.5 V < VCC2 < 5.5 V (see Figure 35)
2.1
3.7
V
RL = 100 Ω (see Figure 36), RS-422 load
V
2
4.2
V
RL = 54 Ω (see Figure 36), RS-485 load, VCC2 = 3 V
to 3.6 V
1.5
2.3
V
RL = 54 Ω (see Figure 36), RS-485 load,
4.5 V < VCC2 < 5.5 V
2.1
3.7
V
Δ|VOD|
Change in differential output voltage
between two states
RL = 54 Ω or RL = 100 Ω, see Figure 36
–200
VOC
Common-mode output voltage
RL = 54 Ω or RL = 100 Ω, see Figure 36
1
ΔVOC(SS)
change in steady-state common-mode
RL = 54 Ω or RL = 100 Ω, see Figure 36
output voltage between two states
–200
200
mV
–250
250
mA
IOS
Short-circuit output current
Ii
VD = VCC1 or VD = VGND1, VDE = VCC1, VCC2=3.3V ±
10%
–7 V ≤ V ≤ 12 V, see Figure 45
200
0.5 × VCC2
VD = VCC1 or VD = VGND1, VDE = VCC1, VCC2=5V ±
10%
–7 V ≤ V ≤ 12 V, see Figure 45
3
250
mV
V
mA
Input current
VD and VDE = 0 V or VD and VDE = VCC1
CMTI
Common-mode transient immunity
VD=VCC1 or GND1, VCC1 = 1.71 V to 5.5 V, VCM =
1200 V, ISO141x, See Figure 38
–10
10
µA
85
100
kV/µs
CMTI
Common-mode transient immunity
VD=VCC1 or GND1, VCC1 = 1.71 V to 5.5 V, VCM =
1200 V, ISO143x, See Figure 38
85
100
kV/µs
CMTI
Common-mode transient immunity
VD=VCC1 or GND1, VCC1 = 2.25 V to 5.5 V, VCM =
1200 V, ISO145x, See Figure 38
85
100
kV/µs
8.10 Electrical Characteristics: Receiver
All typical specs are at VCC1=3.3V, VCC2=5V, TA=27°C, (Min/Max specs are over recommended operating conditions unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
–100
125
µA
Ii1
Bus input current
VDE = 0 V, VCC2 = 0 V or VCC2 = 5.5 V, 500-kbps
devices, VI = –7 V or VI = 12 V, other input at 0 V
Ii1
Bus input current
VDE = 0 V, VCC2 = 0 V or VCC2 = 5.5 V, 12-Mbps and
50-Mbps devices, VI = –7 V or VI = 12 V,
other input at 0 V
–100
125
µA
Ii1
Bus input current
VDE = 0 V, VCC2 = 0 V or VCC2 = 5.5 V, 500-kbps
devices, VI = –15 V or VI = 15 V, other input at 0 V
-200
125
µA
Ii1
Bus input current
VDE = 0 V, VCC2 = 0 V or VCC2 = 5.5 V, 12-Mbps and
50-Mbps devices, VI = –15 V or VI = 15 V,
other input at 0 V
-200
125
µA
VTH+
Positive-going input threshold voltage
VTH–
Negative-going input threshold
voltage
–15 V ≤ VCM ≤ 15 V
Vhys
Input hysteresis (VTH+ – VTH–)
–15 V ≤ VCM ≤ 15 V
VOH
(1)
Output high voltage on the R pin
–15 V ≤ VCM ≤ 15 V
–7 V ≤ VCM ≤ 12 V
See
(1)
-100
–10
mV
See
(1)
-100
–20
mV
–130
(1)
mV
–200
See
30
mV
VCC1=5V ± 10%, IOH = –4 mA, VID = 200 mV
VCC1 – 0.4
V
VCC1=3.3V ± 10%, IOH = –2 mA, VID = 200 mV
VCC1 – 0.3
V
VCC1=2.5V ± 10%, 1.8V+/-5%, IOH = –1 mA, VID =
200 mV
VCC1 – 0.2
V
Under any specific conditions, VTH+ is ensured to be at least Vhys higher than VTH–.
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Electrical Characteristics: Receiver (continued)
All typical specs are at VCC1=3.3V, VCC2=5V, TA=27°C, (Min/Max specs are over recommended operating conditions unless
otherwise noted)
PARAMETER
VOL
TEST CONDITIONS
Output low voltage on the R pin
MIN
TYP
MAX
UNIT
VCC1=5V ± 10%, IOL = 4 mA, VID = –200 mV
0.4
V
VCC1=3.3V ± 10%, IOL = 2 mA, VID = –200 mV
0.3
V
VCC1=2.5V ± 10%, 1.8V ± 5%, IOL = 1 mA, VID =
–200 mV
0.2
V
–1
1
µA
–10
10
µA
IOZ
Output high-impedance current on
the R pin
VR = 0 V or VR = VCC1, VRE = VCC1
Ii
Input current on the RE pin
VRE = 0 V or VRE = VCC1
CMTI
Common-mode transient immunity
VCC1=1.71 V to 5.5 V, VID = 1.5 V or -1.5 V, VCM =
1200 V, ISO141x, See Figure 38
85
100
kV/µs
CMTI
Common-mode transient immunity
VCC1=1.71 V to 5.5 V, VID = 1.5 V or -1.5 V, VCM =
1200 V, ISO143x, See Figure 38
85
100
kV/µs
CMTI
Common-mode transient immunity
VCC1=2.25 V to 5.5 V, VID = 1.5 V or -1.5 V, VCM =
1200 V, ISO145x, See Figure 38
85
100
kV/µs
12
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SLLSF22G – APRIL 2018 – REVISED JUNE 2020
8.11 Supply Current Characteristics: Side 1 (ICC1)
Bus loaded or unloaded (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DRIVER ENABLED, RECEIVER DISABLED
Logic-side
supply current
VD = VCC1, VCC1 = 5 V ± 10%
2.6
4.4
mA
Logic-side
supply current
VD = VCC1, VCC1 = 3.3 V ± 10%
2.6
4.4
mA
Logic-side
supply current
ISO141x, D = 500-kbps square wave with 50% duty cycle, VCC1 = 5 V ± 10%
3.2
5.1
mA
Logic-side
supply current
ISO141x, D = 500-kbps square wave with 50% duty cycle, VCC1 = 3.3 V ± 10%
3.2
5.1
mA
Logic-side
supply current
ISO143x, D = 12-Mbps square wave with 50% duty cycle, VCC1 = 5 V ± 10%
3.2
5.1
mA
Logic-side
supply current
ISO143x, D = 12-Mbps square wave with 50% duty cycle, VCC1 = 3.3 V ± 10%
3.2
5.1
mA
Logic-side
supply current
ISO145x, D = 50-Mbps square wave with 50% duty cycle, VCC1 = 5 V ± 10%
3.6
5.3
mA
Logic-side
supply current
ISO145x, D = 50-Mbps square wave with 50% duty cycle, VCC1 = 3.3 V ± 10%
3.4
5.2
mA
DRIVER ENABLED, RECEIVER ENABLED
Logic-side
supply current
VRE = VGND1, loopback if full-duplex device, VD = VCC1, VCC1 = 5 V ± 10%
2.6
4.4
mA
Logic-side
supply current
VRE = VGND1, loopback if full-duplex device, VD = VCC1, VCC1 = 3.3 V ± 10%
2.6
4.4
mA
Logic-side
supply current
ISO141x, VRE = VGND1, loopback if full-duplex device, D = 500-kbps square wave with 50% duty cycle,
VCC1 = 5 V ± 10%, CL(R) (1) = 15 pF
3.3
5.1
mA
Logic-side
supply current
ISO141x, VRE = VGND1, loopback if full-duplex device, D = 500-kbps square wave with 50% duty cycle,
VCC1 = 3.3 V ± 10%, CL(R) (1) = 15 pF
3.2
5.1
mA
Logic-side
supply current
ISO143x, VRE = VGND1, loopback if full-duplex device, D = 12-Mbps square wave with 50% duty cycle,
VCC1 = 5 V ± 10%, CL(R) (1) = 15 pF
4.1
6
mA
Logic-side
supply current
ISO143x, VRE = VGND1, loopback if full-duplex device, D= 12-Mbps square wave with 50% duty cycle,
VCC1 = 3.3 V ± 10%, CL(R) (1) = 15 pF
3.8
5.7
mA
Logic-side
supply current
ISO145x, VRE = VGND1, loopback if full-duplex device, D = 50-Mbps square wave with 50% duty cycle,
VCC1 = 5 V ± 10%, CL(R) (1) = 15 pF
6.3
8.9
mA
Logic-side
supply current
ISO145x, VRE = VGND1, loopback if full-duplex device, D= 50-Mbps square wave with 50% duty cycle,
VCC1 = 3.3 V ± 10%, CL(R) (1) = 15 pF
5.3
7.8
mA
1.6
3.1
mA
1.6
3.1
mA
1.7
3.1
mA
1.6
3.1
mA
2.6
4
mA
DRIVER DISABLED, RECEIVER ENABLED
Logic-side
supply current
V(A-B) ≥ 200 mV, VD = VCC1, VCC1 = 5 V ± 10%
Logic-side
supply current
V(A-B) ≥ 200 mV, VD = VCC1, VCC1 = 3.3 V ± 10%
Logic-side
supply current
ISO141x, (A-B) = 500-kbps square wave with 50% duty cycle, VD = VCC1, VCC1 = 5 V ± 10%, CL(R)
15 pF
(1)
=
Logic-side
supply current
ISO141x, (A-B) = 500-kbps square wave with 50% duty cycle, VD = VCC1, VCC1 = 3.3 V ± 10%, CL(R)
= 15 pF
(1)
Logic-side
supply current
ISO143x, (A-B) = 12-Mbps square wave with 50% duty cycle, VD = VCC1, VCC1 = 5 V ± 10%, CL(R)
15 pF
(1)
=
Logic-side
supply current
ISO143x, (A-B) = 12-Mbps square wave with 50% duty cycle, VD = VCC1, VCC1 = 3.3 V ± 10%, CL(R) (1)
= 15 pF
2.2
3.7
mA
Logic-side
supply current
ISO145x, (A-B) = 50-Mbps square wave with 50% duty cycle, VD = VCC1, VCC1 = 5 V ± 10%, CL(R) (1) =
15 pF
4.7
6.7
mA
Logic-side
supply current
ISO145x, (A-B) = 50-Mbps square wave with 50% duty cycle, VD = VCC1, VCC1 = 3.3 V ± 10%, CL(R) (1)
= 15 pF
3.7
5.7
mA
DRIVER DISABLED, RECEIVER DISABLED
Logic-side
supply current
VDE = VGND1, VD = VCC1, VCC1 = 5 V ± 10%
1.6
3.1
mA
Logic-side
supply current
VDE = VGND1, VD = VCC1, VCC1 = 3.3 V ± 10%
1.6
3.1
mA
(1)
CL(R) is the load capacitance on the R pin.
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8.12 Supply Current Characteristics: Side 2 (ICC2)
VRE = VGND1 or VRE = VCC1 (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
4
6.1
mA
4.5
6.6
mA
DRIVER ENABLED, BUS UNLOADED
Bus-side supply
current
VD = VCC1, VCC2 = 3.3 V ± 10%
Bus-side supply
current
VD = VCC1, VCC2 = 5 V ± 10%
DRIVER ENABLED, BUS LOADED
Bus-side supply
current
VD = VCC1, RL = 54 Ω, VCC2 = 3.3 V ± 10%
48
58
mA
Bus-side supply
current
VD = VCC1, RL = 54 Ω, VCC2 = 5 V ± 10%
74
88
mA
Bus-side supply
current
ISO141x, D = 500-kbps square wave with 50% duty cycle, RL = 54 Ω, CL = 50 pF, VCC2 = 3.3 V ±
10%
63
95
mA
Bus-side supply
current
ISO141x, D = 500-kbps square wave with 50% duty cycle, RL = 54 Ω, CL = 50 pF, VCC2 = 5 V ± 10%
113
160
mA
Bus-side supply
current
ISO143x, D = 12-Mbps square wave with 50% duty cycle, RL = 54 Ω, CL = 50 pF, VCC2 = 3.3 V ± 10%
56
75
mA
Bus-side supply
current
ISO143x, D = 12-Mbps square wave with 50% duty cycle, RL = 54 Ω, CL = 50 pF, VCC2 = 5 V ± 10%
97
122
mA
Bus-side supply
current
ISO145x, D = 50-Mbps square wave with 50% duty cycle, RL = 54 Ω, CL = 50 pF, VCC2 = 3.3 V ± 10%
84
103
mA
Bus-side supply
current
ISO145x, D = 50-Mbps square wave with 50% duty cycle, RL = 54 Ω, CL = 50 pF, VCC2 = 5 V ± 10%
134
162
mA
DRIVER DISABLED, BUS LOADED OR UNLOADED
Bus-side supply
current
VD = VCC1, VCC2 = 3.3 V ± 10%
2.6
4.3
mA
Bus-side supply
current
VD = VCC1, VCC2 = 5 V ± 10%
2.8
4.5
mA
14
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8.13 Switching Characteristics: Driver
All typical specs are at VCC1=3.3V, VCC2=5V, TA=27°C, (Min/Max specs are over recommended operating conditions unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
240
500-kbps DEVICES
tr, tf
Differential output rise time and fall time
tPHL, tPLH Propagation delay
PWD
Pulse width distortion (1), |tPHL – tPLH|
RL = 54 Ω, CL = 50 pF, see Figure 37
460
680
ns
RL = 54 Ω, CL = 50 pF, see Figure 37
310
570
ns
RL = 54 Ω, CL = 50 pF, see Figure 37
4
50
ns
tPHZ, tPLZ Disable time
See Figure 40, and Figure 41
125
200
ns
tPZH, tPZL Enable time
See Figure 40, and Figure 41
160
600
ns
10
25
ns
27.8
ns
125
ns
12-Mbps DEVICES
tr, tf
Differential output rise time and fall time
tPHL, tPLH Propagation delay
PWD
RL = 54 Ω, CL = 50 pF, VCC2= 4.5 V to
5.5 V, see Figure 37
RL = 54 Ω, CL = 50 pF, VCC2= 3 V to 3.6
V, see Figure 37
RL = 54 Ω, CL = 50 pF, see Figure 37
Pulse width distortion
(1)
, |tPHL – tPLH|
68
2
10
ns
tPHZ, tPLZ Disable time
RL = 54 Ω, CL = 50 pF, see Figure 37
See Figure 40, and Figure 41
75
125
ns
tPZH, tPZL Enable time
See Figure 40, and Figure 41
75
160
ns
RL = 54 Ω, CL = 50 pF, VCC2= 4.5 V to
5.5 V, see Figure 37
4.7
6
ns
7.8
ns
50-Mbps DEVICES
tr, tf
Differential output rise time and fall time
tPHL, tPLH Propagation delay
PWD
Pulse width distortion (1), |tPHL – tPLH|
RL = 54 Ω, CL = 50 pF, VCC2= 3 V to 3.6
V, see Figure 37
RL = 54 Ω, CL = 50 pF, see Figure 37
19
41
ns
RL = 54 Ω, CL = 50 pF, see Figure 37
1
6
ns
tPHZ, tPLZ Disable time
See Figure 40, and Figure 41
25
46
ns
tPZH, tPZL Enable time
See Figure 40, and Figure 41
32
78
ns
(1)
Also known as pulse skew.
8.14 Switching Characteristics: Receiver
All typical specs are at VCC1=3.3V, VCC2=5V, TA=27°C, (Min/Max specs are over recommended operating conditions unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
500-kbps DEVICES
tr, tf
Differential output rise time and fall time
tPHL, tPLH Propagation delay
PWD
Pulse width distortion (1), |tPHL – tPLH|
CL = 15 pF, see Figure 42
1
4
ns
CL = 15 pF, see Figure 42
92
135
ns
CL = 15 pF, see Figure 42
4.5
12.5
ns
tPHZ, tPLZ Disable time
See Figure 43 and Figure 44
9
30
ns
tPZH, tPZL Enable time
See Figure 43 and Figure 44
5
20
ns
CL = 15 pF, see Figure 42
1
4
ns
CL = 15 pF, see Figure 42
75
120
ns
CL = 15 pF, see Figure 42
1
10
ns
tPHZ, tPLZ Disable time
See Figure 43 and Figure 44
9
30
ns
tPZH, tPZL Enable time
See Figure 43 and Figure 44
5
20
ns
CL = 15 pF, see Figure 42
1
4
ns
CL = 15 pF, see Figure 42
36
60
ns
12-Mbps DEVICES
tr, tf
Differential output rise time and fall time
tPHL, tPLH Propagation delay
PWD
Pulse width distortion (1), |tPHL – tPLH|
50-Mbps DEVICES
tr, tf
Differential output rise time and fall time
tPHL, tPLH Propagation delay
(1)
Also known as pulse skew.
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Switching Characteristics: Receiver (continued)
All typical specs are at VCC1=3.3V, VCC2=5V, TA=27°C, (Min/Max specs are over recommended operating conditions unless
otherwise noted)
PARAMETER
TYP
MAX
CL = 15 pF, Measured with 50kHz, 50%
Duty Clock, see Figure 42
TEST CONDITIONS
2
6
ns
tPHZ, tPLZ Disable time
See Figure 43 and Figure 44
9
30
ns
tPZH, tPZL Enable time
See Figure 43 and Figure 44
5
20
ns
Pulse width distortion (1), |tPHL – tPLH|
PWD
MIN
UNIT
8.15 Insulation Characteristics Curves
2500
VCC = 1.89 V
VCC = 2.75 V
VCC = 3.6 V
VCC = 5.5 V
1000
Safety Limiting Power (mW)
Safety Limiting Current (mA)
1200
800
600
400
200
1500
1000
500
0
0
0
50
100
150
Ambient Temperature (qC)
200
D001
Figure 1. Thermal Derating Curve for Limiting Current per
VDE
16
2000
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0
50
100
150
Ambient Temperature (qC)
200
d002
Figure 2. Thermal Derating Curve for Limiting Power per
VDE
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8.16 Typical Characteristics
70
120
ICC1 (VCC1=3.3V)
ICC2 (VCC2=3.3V)
ICC2 (VCC2=5V)
110
100
50
90
Supply current (mA)
Supply current (mA)
60
40
30
20
80
70
60
50
40
ICC1 (VCC1=3.3V)
ICC2 (VCC2=3.3V)
ICC2 (VCC2=5V)
30
20
10
10
0
0
0
100
200
300
Data rate (kbps)
DE = VCC1
400
500
0
100
200
300
Data rate (kbps)
D001
RE = GND1
TA = 25°C
DE = VCC1
RE = GND1
TA = 25°C
Load On R = 15 pF
400
500
D002
Driver Load = 54 Ω
|| 50pF
Figure 3. ISO141x Supply Current Vs Data Rate- No Load
90
50
80
45
70
40
Supply Current (mA)
Supply current (mA)
Figure 4. ISO141x Supply Current Vs Data Rate- With
54Ω||50pf Load
60
50
40
ICC1 (Vcc1=3.3V)
ICC2 (Vcc2=3.3V)
ICC2 (Vcc2=5V)
30
20
ICC1 (VCC1=3.3V)
ICC2 (VCC2=3.3V)
ICC2 (VCC2=5V)
35
30
25
20
15
10
10
5
0
0
100
200
300
Data rate (kbps)
DE = VCC1
TA = 25°C
400
RE = GND1
500
0
0
D003
Driver Load = 120
Ω || 50pF
2
4
6
8
Data rate (Mbps)
DE = VCC1
10
12
d001
TA = 25°C
RE = GND1
Load On R = 15 pF
Figure 6. ISO143x Supply Current Vs. Data Rate - No Load
Figure 5. ISO141x Supply Current Vs Data Rate- With
120Ω||50pf Load
100
120
ICC1 (VCC1=3.3V)
ICC2 (VCC2=3.3V)
ICC2 (VCC2=5V)
90
Supply Current (mA)
Supply Current (mA)
80
ICC1 (VCC1=3.3V)
ICC2 (VCC2=3.3V)
ICC2 (VCC2=5V)
100
70
60
50
40
30
20
80
60
40
20
10
0
0
0
2
DE = VCC1
Driver Load = 120
Ω || 50pF
4
6
8
Data rate (Mbps)
TA = 25°C
50pF, Load On R =
15pf
10
12
RE = GND1
Figure 7. ISO143x Supply Current Vs. Data Rate 120Ω||50pF Load
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0
2
d002
DE = VCC1
Driver Load = 54 Ω
|| 50pF
4
6
8
Data rate (Mbps)
TA = 25°C
50pF, Load On R =
15pf
10
12
d003
RE = GND1
Figure 8. ISO143x Supply Current Vs Data Rate- 54Ω||50pF
Load
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Typical Characteristics (continued)
120
140
ICC1 (VCC1=3.3V)
ICC2 (VCC2=3.3V)
ICC2 (VCC2=5V)
Supply Current (mA)
Supply Current (mA)
100
ICC1 (VCC1=3.3V)
ICC2 (VCC2=3.3V)
ICC2 (VCC2=5V)
120
80
60
40
20
100
80
60
40
20
0
0
0
5
10
DE = VCC1
15
20
25
30
Data rate (Mbps)
35
40
45
50
0
10
20
30
Data rate (Mbps)
d009
TA = 25°C
RE = GND1
Figure 9. ISO145x Supply Current Vs Data Rate- No Load
DE = VCC1
Driver Load = 120
Ω || 50pF
40
50
d010
TA = 25°C
50pF, Load On R =
15pf
RE = GND1
Figure 10. ISO145x Supply Current Vs Data Rate120Ω||50pF Load
5.35
5
5.3
4.5
Driver output voltage (V)
Driver Rise/fall time (ns)
5.25
5.2
5.15
5.1
5.05
5
4.95
4.9
Voh
Vol
4
3.5
3
2.5
2
1.5
1
0.5
4.85
0
4.8
0
4.75
-40
-20
0
DE = VCC1
Driver Load = 54 Ω
|| 50pF
20
40
60
80
Ambient temp ( qC )
100
120
140
20
DE = VCC1
TA = 25°C
d011
TA = 25°C
50pF, Load On R =
15pf
10
RE = GND1
30
40
50
60
70
Driver output current (mA)
80
90
100
D004
D = GND1
VCC2 = 5 V
VCC1 = 3.3 V
Figure 12. Driver Output Voltage Vs Driver Output Current
Figure 11. ISO145x Supply Current Vs Data Rate- 54Ω||50pF
Load
6
5.5
Differential output voltage (V)
Driver differential output voltage (V)
5
4.5
4
3.5
3
2.5
2
1.5
4
3.5
3
2.5
2
1.5
VOD (3.3 V, 120 :)
VOD (3.3 V, 54 :)
VOD (5V, 120 :)
VOD (5V, 54 :)
1
0.5
1
0
10
20
DE = VCC1
TA = 25°C
30
40
50
60
70
Driver output current (mA)
D = GND1
VCC2 = 5 V
80
90
100
D005
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0
-40
-20
0
20
40
60
80
Ambient temperature (qC)
100
120
140
D006
VCC1 = 3.3 V
Figure 13. Driver Differential Output Voltage Vs Driver
Output Current
18
5
4.5
Figure 14. Driver Differential Output Voltage Vs Temperature
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80
580
70
560
60
540
Driver rise/fall time (ns)
Driver output current (mA)
Typical Characteristics (continued)
50
40
30
20
10
520
500
480
460
440
0
0
0.5
1
1.5
RL = 54 Ω
2 2.5
3 3.5
4
Supply voltage VCC2 (V)
4.5
5
420
-40
5.5
-20
0
D007
DE = D = VCC1
TA = 25°C
VCC1 = 3.3 V
Figure 15. Driver Output Current Vs Supply Voltage (VCC2)
20
40
60
80
Ambient temp ( qC )
100
120
140
D008
VCC2 = 5 V
Figure 16. ISO141x Driver Rise/fall Time (ns) Vs
Temperature (c)
9.5
5.35
9
Driver Rise/fall time (ns)
Driver Rise/Fall time (ns)
5.3
5.25
8.5
8
7.5
5.2
5.15
5.1
5.05
5
4.95
4.9
4.85
4.8
7
-40
-20
0
20
40
60
80
Ambient temp ( qC )
VCC1 = 3.3 V
100
120
4.75
-40
140
VCC2 = 5 V
68.5
Driver Propogation Delay (ns)
Driver propagation delay (ns)
69
345
340
335
330
325
320
315
310
305
VCC1 = 3.3 V
0
20
40
60
80
100
Ambient temperature ( qC )
120
140
D009
VCC2 = 5 V
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100
120
140
d011
VCC2 = 5 V
68
67.5
67
66.5
66
65.5
65
64.5
64
63.5
-40
-20
VCC1 = 3.3 V
Figure 19. ISO141x Driver Propagation Delay (ns) Vs
Temperature (c)
20
40
60
80
Ambient temp ( qC )
Figure 18. ISO145x Driver Rise/Fall Time (ns) Vs
Temperature (C)
350
-20
0
VCC1 = 3.3 V
Figure 17. ISO143x Driver Rise/Fall Time (ns) Vs
Temperature (C)
300
-40
-20
d004
0
20
40
60
80
Ambient temp ( qC )
100
120
140
d005
VCC2 = 5 V
Figure 20. ISO143x Driver Propagation Delay (ns) Vs
Temperature (C)
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Typical Characteristics (continued)
5
21.5
21
High level output voltage (V)
Driver Propogation delay (ns)
4.5
20.5
20
19.5
19
18.5
2
1.5
1
Voh (1.8V)
Voh (3.3V)
Voh (5V)
0
-15
-20
0
20
40
60
Ambient temp ( qC )
VCC1 = 3.3 V
80
100
120
Figure 22. Receiver Buffer High Level Output Voltage Vs
High Level Output Current
88
Receiver propagation delay (ns)
Low level output voltage (V)
0.7
0.6
0.5
0.4
0.3
0.2
VOL (1.8V)
VOL (3.3V)
VOL((5V)
0.1
4
6
8
10
12
Low level output current (mA)
14
16
76
73
-20
0
Receiver Propogation delay (ns)
79
78
77
76
20
40
60
80
Ambient Temp ( qC)
100
120
140
Figure 25. ISO143x Receiver Propagation Delay (ns) Vs.
Temperature (C)
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44.5
44
43.5
43
42.5
42
41.5
41
40.5
40
39.5
39
38.5
38
37.5
-40
-20
120
140
D012
VCC2 = 5 V
0
d006
VCC2 = 5 V
20
40
60
80
100
Ambient temperature ( qC )
Figure 24. ISO141x Receiver Propagation Delay (ns) Vs
Temperature (c)
80
VCC1 = 3.3 V
79
VCC1 = 3.3 V
Figure 23. Receiver Buffer Low Level Output Voltage Vs
Low Level Output Current
0
82
D011
TA = 25°C
-20
85
70
-40
0
75
-40
D010
d012
91
2
0
VCC2 = 5 V
0.8
0
-10
-5
High level output current (mA)
TA = 25° C
Figure 21. ISO145x Driver Propagation Delay (ns) Vs
Temperature (C)
Receiver Propogation delay (ns)
3
2.5
0.5
18
-40
20
4
3.5
VCC1 = 3.3 V
20
40
60
80
100
Ambient temperature ( qC )
120
140
d013
VCC2 = 5 V
Figure 26. ISO145x Receiver Propagation Delay (ns) Vs.
Temperature (C)
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Typical Characteristics (continued)
600
550
Receiver VID (mV)
VID (mV)
500
450
400
350
300
250
200
2
3
4
5
6
7
8
Data Rate (Mbps)
9
10
11
12
5
10
15
20
25
30
35
Data Rate (Mbps)
40
45
50
d014
For PWD ≤±5%
Figure 27. ISO143x Receiver VID vs Signaling Rate
VCC2 = 5 V
TA = 25° C
Figure 29. ISO141x Driver Propagation Delay
VCC1 = 3.3 V
DE = VCC1
0
d007
For PWD ≤±5%
VCC1 = 3.3 V
DE = VCC1
1050
1000
950
900
850
800
750
700
650
600
550
500
450
400
350
300
250
VCC2 = 5 V
TA = 25° C
Figure 31. ISO145x Driver Propagation Delay
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Figure 28. ISO145x Receiver VID vs Signaling Rate
VCC1 = 3.3 V
DE = VCC1
VCC2 = 5 V
TA = 25° C
Figure 30. ISO143x Driver Propagation Delay
VCC1 = 3.3 V
DE = GND1
VCC2 = 5 V
RE = GND1
TA = 25° C
Figure 32. ISO141x Receiver Propagation Delay
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Typical Characteristics (continued)
Figure 33. VCC1 Power Up/Power Down - Glitch Free
Behavior
22
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Figure 34. VCC2 Power Up/Power Down - Glitch Free
Behavior
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9 Parameter Measurement Information
VCC2
DE = VCC1
375
A or Y
RL
VOD
D = 0 or
VCC1
VTEST
B or Z
375
+
±
GND2
Figure 35. Driver Voltages
RL(1) / 2
A or Y
A
VA
B
VB
0 V or D
VCC1
RL(1) / 2
B or Z
VOC
VOC
GND2
ûVOC(SS)
VOC(PP)
(1)
VOD
RL = 100 Ω for RS422, RL = 54 Ω for RS-485
Figure 36. Driver Voltages
VCC1
DE = VCC1
RL
54
D
Input
Generator
50
VI
VI
VOD
A or Y
50%
(1)
CL
50 pF ± 20%
± 1%
tPHL
tPLH
90%
B or Z
VOD
GND1
(1)
90%
0V
10%
tr
tf
VOD (H)
0V
10%
VOD (L)
CL includes fixture and instrumentation capacitance.
Figure 37. Driver Switching Specifications
VCC1
VCC2
10 µF
VCC1
0.1 µF
GND1
DE
Y
D
Z
GND1
54
A
R
+
VOH or VOL
±
10 µF
0.1 µF
1k
CL
15 pF(1)
B
RE
GND1
+
VOH or VOL
±
1.5 V or 0 V
54
0 V or 1.5 V
GND2
+ VCM ±
(1)
Includes probe and fixture capacitance.
Figure 38. Common Mode Transient Immunity (CMTI)—Full Duplex
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Parameter Measurement Information (continued)
VCC1
VCC1
10 µF
0.1 µF
VCC2
DE
0.1 µF
10 µF
A
D
GND1
+
VOH or VOL
±
54
B
GND1
R
+
VOH or VOL
±
CL
15 pF(1)
1k
RE
GND1
GND2
+ VCM ±
(1)
Includes probe and fixture capacitance.
Figure 39. Common Mode Transient Immunity (CMTI)—Half Duplex
A or Y
D
DE B or Z
Input
Generator
VI
S1
VCC1
VO
50 %
VI
CL(1)
50 pF
0V
RL
110
50
50 %
tPZH
90%
VOH
50%
VO
§0V
tPHZ
GND2
GND1
(1)
CL includes fixture and instrumentation capacitance
Figure 40. Driver Enable and Disable Times
VCC2
A or Y
RL
110
D
DE
Input
Generator
VI
VCC1
50 %
VI
S1
B or Z
50 %
0V
CL(1)
50 pF
tPLZ
tPZL
VO
50%
50
VCC2
10%
VOL
GND2
GND1
Figure 41. Driver Enable and Disable Times
24
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Parameter Measurement Information (continued)
3V
50 %
A
R
Input
Generator
1.5 V
50
VI
B
CL(1)
15 pF
RE
50 %
VI
VO
0V
tPHL
tPLH
90%
50%
10%
50%
VO
tr
(1)
tf
VOH
VOL
CL includes fixture and instrumentation capacitance.
Figure 42. Receiver Switching Specifications
VCC1
50%
VI
0V
tPHZ
tPZH
VO
VOH
90%
50%
§0V
tPZL
tPLZ
VO
VCC1
50%
10%
VOL
Figure 43. Receiver Enable and Disable Times
VCC1
VCC1
VI
A
0 V or 1.5 V
R
B
1.5 V or 0 V
RE
Input
Generator
VI
VO
50%
0V
1k
S1
CL
15 pF
tPZH
VOH
VO
A at 1.5 V
B at 0 V
§ 0 V S1 to GND
50%
tPZL
50
VCC1
VO
50%
VOL
A at 0 V
B at 1.5 V
S1 to
VCC1
Figure 44. Receiver Enable and Disable Times
Steady-State
Logic Input
(1 or 0)
A or Y
G
B or Z
G
±7 9 ” 9 ” 12 V
I(1)
B or Z
V
C
C
GND
(1)
A or Y
Steady State
Logic Input
(1 or 0)
GND
The driver should not sustain any damage with this configuration.
Figure 45. Short-Circuit Current Limiting
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10 Detailed Description
10.1 Overview
The ISO14xx devices are isolated RS-485/RS-422 transceivers designed to operate in harsh industrial
environments. ISO141x, ISO143x and ISO145x devices support up to 500 kbps, 12 Mbps and 50 Mbps signaling
rates respectively. This family of devices has a 3-channel digital isolator and an RS-485 transceiver in a 16-pin
wide-body SOIC package. The silicon-dioxide based capacitive isolation barrier supports an isolation withstand
voltage of 5 kVRMS and an isolation working voltage of 1500 VPK. Isolation breaks the ground loop between the
communicating nodes and allows for data transfer in the presence of large ground potential differences. These
devices have a higher typical differential output voltage (VOD) than traditional transceivers for better noise
immunity. A minimum differential output voltage of 2.1 V is specified at a VCC2 voltage of 5 V ±10% which meets
the requirements for Profibus applications. The wide logic supply of the device (VCC1) supports interfacing with
1.8-V, 2.5-V, 3.3-V, and 5-V control logic. The 3-V to 5.5-V bus side supply (VCC2) removes the need of a wellregulated isolated supply in end systems. Figure 46 shows the functional block diagram of the full-duplex devices
and Figure 47 shows the functional block diagram of a half-duplex devices.
10.2 Functional Block Diagram
VCC1
VCC2
VCC2
VCC
DE
Tx
Rx
D
Tx
Rx
R
Rx
Tx
Y
D
Z
B
R
Full duplex
A
RE
GND1
GND2
GND2
Figure 46. Full-Duplex Block Diagram
VCC1
VCC2
VCC2
VCC
DE
Tx
Rx
D
Tx
Rx
R
Rx
Tx
A
D
Half duplex
R
B
RE
GND1
GND2
GND2
Figure 47. Half-Duplex Block Diagram
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10.3 Feature Description
10.3.1 Electromagnetic Compatibility (EMC) Considerations
Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge
(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances
are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level
performance and reliability depends, to a large extent, on the application board design and layout, the ISO14xx
devices incorporate dedicated circuitry to protect the transceiver from ±16 kV ESD per IEC61000-4-2 and ±4 kV
EFT per IEC 61000-4-4. System designers can achieve the ±4-kV EFT Criterion A with careful system design
(data communication between nodes in the presence of transient noise with minimum to no data loss).
10.3.2 Failsafe Receiver
The differential receiver of the ISO14xx devices has failsafe protection from invalid bus states caused by:
• Open bus conditions such as a broken cable or a disconnected connector
• Shorted bus conditions such as insulation breakdown of a cable that shorts the twisted-pair
• Idle bus conditions that occur when no driver on the bus is actively driving
The differential input of the RS-485 receiver is 0 in any of these conditions for a terminated transmission line.
The receiver outputs a failsafe logic-high state so that the output of the receiver is not indeterminate.
The receiver thresholds are offset in the receiver failsafe protection so that the indeterminate range of the does
not include a 0 V differential. The receiver output must generate a logic high when the differential input (VID) is
greater than 200 mV to comply with the RS-485 standard. The receiver output must also generate a output a
logic low when VID is less than –200 mV to comply with the RS-485 standard. The receiver parameters that
determine the failsafe performance are VTH+, VTH–, and VHYS. Differential signals less than –200 mV always
cause a low receiver output as shown in the Electrical Characteristics table. Differential signals greater than 200
mV always cause a high receiver output. A differential input signal that is near zero is still greater than the VTH+
threshold which makes the receiver output logic high. The receiver output goes to a low state only when the
differential input decreases by VHYS to less than VTH+.
The internal failsafe biasing feature removes the need for the two external resistors that are typically required
with traditional isolated RS-485 transceivers as shown in Figure 48.
Traditional
transceiver
VCC1
ISO1410
(R1 and R2 not needed)
VCC2
VCC2
VCC1
VCC2
VCC2
R1
A
A
RT
RS-485
Bus
RT
B
RS-485
Bus
B
R2
GND1
GND2
Galvanic
Isolation Barrier
GND1
ISO
Ground
GND2
Galvanic
Isolation Barrier
ISO
Ground
Figure 48. Failsafe Transceiver
10.3.3 Thermal Shutdown
The ISO14xx devices have a thermal shutdown circuit to protect against damage when a fault condition occurs.
A driver output short circuit or bus contention condition can cause the driver current to increase significantly
which increases the power dissipation inside the device. An increase in the die temperature is monitored and the
device is disabled when the die temperature becomes 170℃ (typical) which lets the device decrease the
temperature. The device is enabled when the junction temperature becomes 165℃ (typical).
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Feature Description (continued)
Bus short circuit for an extended duration and/or beyond voltage levels specified in recommended operating
condition should be avoided. Repeated or prolonged exposure to bus shorts can result in high junction
temperatures and affect device reliability.
10.3.4 Glitch-Free Power Up and Power Down
Communication on the bus that already exist between a master node and slave node in an RS485 network must
not be disturbed when a new node is swapped in or out of the network. No glitches on the bus occur when the
device is:
• Hot plugged into the network in an unpowered state
• Hot plugged into the network in a powered state and disabled state
• Powered up or powered down in a disabled state when already connected to the bus
The ISO14xx devices do not cause any false data toggling on the bus when powered up or powered down in a
disabled state with supply ramp rates from 100 µs to 10 ms.
10.4 Device Functional Modes
Table 2 shows the driver functional modes.
Table 2. Driver Functional table (1)
VCC1
PU
(1)
(2)
(3)
VCC2
OUTPUTS (2)
INPUT D
DRIVER ENABLE
DE
Y, A
H
H
H
L
L
H
L
H
X
L
Hi-Z
Hi-Z
X
Open
Hi-Z
Hi-Z
PU
Z, B
Open
H
H
L
PD (3)
PU
X
X
Hi-Z
Hi-Z
X
PD
X
X
Hi-Z
Hi-Z
PU = Powered Up; PD = Powered Down; H = High Level; L = Low level; X = Irrelevant, Hi-Z = High impedance state
The driver outputs are Y and Z for a full-duplex device. The driver outputs are A and B for a half-duplex device.
A strongly driven input signal can weakly power the floating VCC1 through an internal protection diode and cause an undetermined
output.
The description that follows is specific to half-duplex device but the same logic applies to full-duplex device with
the outputs being Y and Z.
When the driver enable pin, DE, is logic high, the differential outputs, A and B, follow the logic states at data
input, D. A logic high at the D input causes the A output to go high and the B output to go low. Therefore the
differential output voltage defined by Equation 1 is positive.
VOD = VA – VB
(1)
A logic low at the D input causes the B output to go high and the A output to go low. Therefore the differential
output voltage defined by Equation 1 is negative. A logic low at the DE input causes both outputs to go to the
high-impedance (Hi-Z) state. The logic state at the D pin is irrelevant when the DE input is logic low. The DE pin
has an internal pulldown resistor to ground. The driver is disabled (bus outputs are in the Hi-Z) by default when
the DE pin is left open. The D pin has an internal pullup resistor. The A output goes high and the B output goes
low when the D pin is left open while the driver enabled.
Table 3 shows the receiver functional modes.
28
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Table 3. Receiver Functional Table (1)
VCC1
VCC2
DIFFERENTIAL INPUT
RECEIVER ENABLE RE
OUTPUT R
VID = VA – VB
PU
(1)
(2)
PU
–0.02 V ≤ VID
L
H
–0.2 V < VID < 0.02 V
L
Indeterminate
VID≤ –0.2 V
L
L
X
H
Hi-Z
Hi-Z
X
Open
Open, Short, Idle
L
H
X
Hi-Z
PD (2)
PU
X
PU
PD
X
L
H
PD (2)
PD
X
X
Hi-Z
PU = Powered Up; PD = Powered Down; H = Logic High; L= Logic Low; X = Irrelevant, Hi-Z = High Impedance (OFF) state
A strongly driven input signal can weakly power the floating VCC1 through an internal protection diode and cause an undetermined
output.
The receiver is enabled when the receiver enable pin, RE, is logic low. The receiver output, R, goes high when
the differential input voltage defined by Equation 2 is greater than the positive input threshold, VTH+.
VID = VA – VB
(2)
The receiver output, R, goes low when the differential input voltage defined by Equation 2 is less than the
negative input threshold, VTH–. If the VID voltage is between the VTH+ and VTH– thresholds, the output is
indeterminate. The receiver output is in the Hi-Z state and the magnitude and polarity of VID are irrelevant when
the RE pin is logic high or left open. The internal biasing of the receiver inputs causes the output to go to a
failsafe-high when the transceiver is disconnected from the bus (open-circuit), the bus lines are shorted to one
another (short-circuit), or the bus is not actively driven (idle bus).
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10.4.1 Device I/O Schematics
D and RE Inputs
VCC1
VCC1
VCC1
DE Input
VCC1
VCC1
VCC1
VCC1
1.5 M
985
985
Input
Input
1.5 M
R Output
VCC1
~20
R
Figure 49. Device I/O Schematics
30
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11 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
11.1 Application Information
The ISO14xx devices are designed for bidirectional data transfer on multipoint RS-485 networks. The design of
each RS-485 node in the network requires an ISO14xx device and an isolated power supply as shown in
Figure 52.
An RS-485 bus has multiple transceivers that connect in parallel to a bus cable. Both cable ends are terminated
with a termination resistor, RT, to remove line reflections. The value of RT matches the characteristic impedance,
Z0, of the cable. This method, known as parallel termination, lets higher data rates be used over a longer cable
length.
Full-duplex implementation, as shown in Figure 50, requires two signal pairs (four wires). Full-duplex
implementation lets each node to transmit data on one pair while simultaneously receiving data on the other pair.
In half-duplex implementation, as shown in Figure 51, the driver and receiver enable pins let any node at any
given moment be configured in either transmit or receive mode which decreases cable requirements.
Y
RE
DE
ISO1412
Master
RT
RT
B
R
ISO1412
Slave
RE
c
Z
R
A
B
Z
D
DE
D
A
RT
RT
B
Z
Y
D
DE
R
RE
ISO1412
Slave
A
Y
Figure 50. Typical RS-485 Network With Full-Duplex Isolated Transceivers
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Application Information (continued)
Integrated isolation barrier allows for communication between
nodes with ground potential differences of up to 1500 V
R
A
ISO1410
B
R
A
RT
RT
B
ISO1410
RE
DE
D
A
B
R
RE
D
DE
R
RE
D
ISO1410
B
ISO1410
A
DE
RE
DE
D
Figure 51. Typical RS-485 Network With Half-Duplex Isolated Transceivers
11.2 Typical Application
Figure 52 shows the application circuit of the ISO1410 device.
GND
4
D2
3
SN6505
3.3 V
EN
VCC
CLK
D1
1
8
3
2
7
6
1
5
2
1
0.1 …F
2
VDD
GPIO1
MCU
GPIO2
L1
3.3V
GPIO3
DGND
N PSU
PE
3
4
5
6
VCC1
VCC2
IN
OUT
5
EN
TPS76350
GND
NC
4
16
GND1
NC 14
R
RE
B
ISO1410
A
DE
13
12
NC 10,11
D
Optional bus
protection
7 NC
0V
8
Protective Chasis
Earth
Ground
Digital
Ground
GND1
GND2
Galvanic
Isolation Barrier
9,15
ISO
Ground
Figure 52. Application Circuit of ISO1410
11.2.1 Design Requirements
Unlike an optocoupler-based solution, which requires several external components to improve performance,
provide bias, or limit current, the ISO14xx devices only require external bypass capacitors to operate.
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Typical Application (continued)
11.2.2 Detailed Design Procedure
The RS-485 bus is a robust electrical interface suitable for long-distance communications. The RS-485 interface
can be used in a wide range of applications with varying requirements of distance of communication, data rate,
and number of nodes.
11.2.2.1 Data Rate and Bus Length
The RS-485 standard has typical curves similar to those shown in Figure 53. These curves show the inverse
relationship between signaling rate and cable length. If the data rate of the payload between two nodes is lower,
the cable length between the nodes can be longer.
10000
Cable Length (ft)
5%, 10%, and 20% Jitter
1000
Conservative
Characteristics
100
10
100
1k
10 k
100 k
1M
10 M
100 M
Data Rate (bps)
Figure 53. Cable Length vs Data Rate Characteristics
Use Figure 53 as a guideline for cable selection, data rate, cable length and subsequent jitter budgeting.
11.2.2.2 Stub Length
In an RS-485 network, the distance between the transceiver inputs and the cable trunk is known as the stub. The
stub should be as short as possible when a node is connected to the bus. Stubs are a non-terminated piece of
bus line that can introduce reflections of varying phase as the length of the stub increases. The electrical length,
or round-trip delay, of a stub should be less than one-tenth of the rise time of the driver as a general guideline.
Therefore, the maximum physical stub length (L(STUB)) is calculated as shown in Equation 3.
L(STUB) ≤ 0.1 × tr × v × c
where
•
•
•
tr is the 10/90 rise time of the driver.
c is the speed of light (3 × 108 m/s).
v is the signal velocity of the cable or trace as a factor of c.
(3)
11.2.2.3 Bus Loading
The current supplied by the driver must supply into a load because the output of the driver depends on this
current. Add transceivers to the bus to increase the total bus loading. The RS-485 standard specifies a
hypothetical term of a unit load (UL) to estimate the maximum number of possible bus loads. The UL represents
a load impedance of approximately 12 kΩ. Standard-compliant drivers must be able to drive 32 of these ULs.
The ISO14xx devices have 1/8 UL impedance transceiver and can connect up to 256 nodes to the bus.
11.2.3 Application Curves
Below eye diagram of ISO145x device indicates low jitter and wide open eye at maximum data rate of 50 Mbps.
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Typical Application (continued)
Figure 54. Eye Diagram at 50 Mbps Clock, VCC2 = 5 V, 25°C
11.2.3.1 Insulation Lifetime
Insulation lifetime projection data is collected by using industry-standard Time Dependent Dielectric Breakdown
(TDDB) test method. In this test, all pins on each side of the barrier are tied together creating a two-terminal
device and high voltage applied between the two sides; See Figure 55 for TDDB test setup. The insulation
breakdown data is collected at various high voltages switching at 60 Hz over temperature. For reinforced
insulation, VDE standard requires the use of TDDB projection line with failure rate of less than 1 part per million
(ppm). Even though the expected minimum insulation lifetime is 20 years at the specified working isolation
voltage, VDE reinforced certification requires additional safety margin of 20% for working voltage and 87.5% for
lifetime which translates into minimum required insulation lifetime of 37.5 years at a working voltage that's 20%
higher than the specified value.
Figure 56 shows the intrinsic capability of the isolation barrier to withstand high voltage stress over its lifetime.
Based on the TDDB data, the intrinsic capability of the insulation is 1060 VRMS with a lifetime of 220 years. Other
factors, such as package size, pollution degree, material group, etc. can further limit the working voltage of the
component. The working voltage of DW-16 is specified up to 1060 VRMS . At the lower working voltages, the
corresponding insulation lifetime is much longer than 220 years.
A
Vcc 1
Vcc 2
Time Counter
> 1 mA
DUT
GND 1
GND 2
VS
Oven at 150 °C
Figure 55. Test Setup for Insulation Lifetime Measurement
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Typical Application (continued)
Working Isolation Voltage = 1060 VRMS
Projected Insulation Lifetime = 220 Years
TA up to 150°C
Applied Voltage Frequency = 60 Hz
Figure 56. Insulation Lifetime Projection Data
12 Power Supply Recommendations
To make sure device operation is reliable at all data rates and supply voltages, a 0.1-μF bypass capacitor is
recommended at the logic and transceiver supply pins (VCC1 and VCC2). The capacitors should be placed as near
to the supply pins as possible. Additionally, a 10 µF bulk capacitor on VCC2 improves transceiver performance
during bus transitions in transmit mode. If only one primary-side power supply is available in an application,
isolated power can be generated for the secondary-side with the help of a transformer driver such as TI's
SN6505B device. For such applications, detailed power supply design and transformer selection
recommendations are available in the SN6505 Low-Noise 1-A Transformer Drivers for Isolated Power Supplies
data sheet.
13 Layout
13.1 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 57). Layer stacking should
be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency
signal layer.
• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/in2.
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
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Layout Guidelines (continued)
Figure 58 shows the recommended placement and routing of the device bypass capacitors and optional TVS
diodes. Put the VCC2 bypass capacitors on the top layer and as near to the device pins as possible. Do not use
vias to complete the connection to the VCC2 and GND2 pins. If an additional supply voltage plane or signal layer
is needed, add a second power or ground plane system to the stack to keep it symmetrical. This makes the stack
mechanically stable and prevents it from warping. Also the power and ground plane of each power system can
be placed closer together, thus increasing the high-frequency bypass capacitance significantly.
Refer to the Digital Isolator Design Guide for detailed layout recommendations.
13.1.1 PCB Material
For digital circuit boards operating at less than 150 Mbps, (or rise and fall times greater than 1 ns), and trace
lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper
alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater strength and
stiffness, and the self-extinguishing flammability-characteristics.
13.2 Layout Example
High-speed traces
10 mils
Ground plane
Keep this space
free from planes,
traces, pads, and
vias
40 mils
FR-4
0r ~ 4.5
Power plane
10 mils
Low-speed traces
Figure 57. Recommended Layer Stack
Minimize
distance to
supply pins
VCC1
R
RE
x
DE
D
NC
GND1
GND2
C
Optional bus
protection
0.1 µF
NC
B
D1
R
GND1
MCU
VCC2
VCC1
Isolation Capacitor
0.1 µF C
VCC2
A
RS-485
NC
NC
GND2
GND1
Plane
GND2
Plane
Figure 58. Layout Example
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SLLSF22G – APRIL 2018 – REVISED JUNE 2020
14 Device and Documentation Support
14.1 Documentation Support
14.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Digital Isolator Design Guide
• Texas Instruments, Isolation Glossary
• Texas Instruments, Isolated RS-485 Half-Duplex Evaluation Module user's guide
• Texas Instruments, How to isolate signal and power for an RS-485 system TI TechNote
• Texas Instruments, Robust Isolated RS-485 for industrial long-haul communications TI TechNote
14.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 4. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
ISO1410
Click here
Click here
Click here
Click here
Click here
ISO1412
Click here
Click here
Click here
Click here
Click here
ISO1430
Click here
Click here
Click here
Click here
Click here
ISO1432
Click here
Click here
Click here
Click here
Click here
ISO1450
Click here
Click here
Click here
Click here
Click here
ISO1452
Click here
Click here
Click here
Click here
Click here
ISO1410B
Click here
Click here
Click here
Click here
Click here
ISO1412B
Click here
Click here
Click here
Click here
Click here
ISO1430B
Click here
Click here
Click here
Click here
Click here
ISO1432B
Click here
Click here
Click here
Click here
Click here
ISO1450B
Click here
Click here
Click here
Click here
Click here
ISO1452B
Click here
Click here
Click here
Click here
Click here
14.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
14.4 Community Resource
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
14.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
14.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
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14.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
15 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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28-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
ISO1410BDW
ACTIVE
SOIC
DW
16
40
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO1410B
ISO1410BDWR
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO1410B
ISO1410DW
ACTIVE
SOIC
DW
16
40
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO1410
ISO1410DWR
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO1410
ISO1412BDW
ACTIVE
SOIC
DW
16
40
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO1412B
ISO1412BDWR
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO1412B
ISO1412DW
ACTIVE
SOIC
DW
16
40
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO1412
ISO1412DWR
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO1412
ISO1430BDW
ACTIVE
SOIC
DW
16
40
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO1430B
ISO1430BDWR
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO1430B
ISO1430DW
ACTIVE
SOIC
DW
16
40
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO1430
ISO1430DWR
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO1430
ISO1432BDW
ACTIVE
SOIC
DW
16
40
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO1432B
ISO1432BDWR
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO1432B
ISO1432DW
ACTIVE
SOIC
DW
16
40
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO1432
ISO1432DWR
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO1432
ISO1450BDW
ACTIVE
SOIC
DW
16
40
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO1450B
ISO1450BDWR
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO1450B
ISO1450DW
ACTIVE
SOIC
DW
16
40
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO1450
ISO1450DWR
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO1450
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2021
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
ISO1452BDW
ACTIVE
SOIC
DW
16
40
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO1452B
ISO1452BDWR
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO1452B
ISO1452DW
ACTIVE
SOIC
DW
16
40
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO1452
ISO1452DWR
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO1452
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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