ISO1640, ISO1641, ISO1642, ISO1643, ISO1644
SLLSFC2D – DECEMBER 2020 – REVISED SEPTEMBER 2021
ISO164x Hot-Swappable Bidirectional I2C Isolators with Enhanced EMC and GPIOs
1 Features
•
•
•
•
•
•
•
•
•
•
Robust Isolated Bidirectional, I2C Compatible,
Communication
– ISO1640: Bidirectional SDA and SCL
communication
– ISO1641: Bidirectional SDA and unidirectional
SCL communication
– ISO1642/3/4: Bidirectional SDA and SCL
communication with either 2 or 3 unidirectional
GPIO channels
– Hot-Swappable SDA and SCL
Bidirectional data transfer up to 1.7 MHz Operation
Up to 3 additional unidirectional isolated GPIO
channels supporting 50 Mbps speed
Robust isolation barrier with enhanced EMC:
– >100-year projected lifetime at 450 VRMS
working voltage (D-8) and 1500 VRMS working
voltage (DW-16)
– Up to 5000 VRMS isolation rating per UL1577
– Up to 10 kV reinforced surge capability
– ±100 kV/μs typical CMTI
– ±8 kV IEC-ESD 61000-4-2 contact discharge
protection across isolation barrier
– Same side ±8 kV IEC-ESD unpowered contact
discharge on SCL2 and SDA2 (Side 2)
Supply range: 3 V to 5.5 V (Side 1) and 2.25 V to
5.5 V (Side 2)
Open-drain outputs with 3.5-mA (Side 1) and 50mA (Side 2) current-sink capability
Max capacitive load: 80 pF (Side 1) and 400 pF
(Side 2)
16-SOIC (DW-16) and 8-SOIC (D-8) Package
Options
–40°C to +125°C Operating Temperature
Safety-Related Certifications (planned):
– UL 1577 Component Recognition Program
– DIN VDE V 0884-11
– IEC 62368-1, IEC 61010-1, IEC 60601-1 and
GB4943.1-2011 certifications
2 Applications
•
•
•
•
•
•
I2C
Isolated
Buses
Isolated I2C and SPI Buses
SMBus and PMBus Interfaces
Power Over Ethernet (PoE)
Motor Control Systems
Battery Management
.
3 Description
The ISO1640, ISO1641, ISO1642, ISO1643 and
ISO1644 (ISO164x) devices are hot swappable, lowpower, bidirectional isolators that are compatible
with I2C interfaces. The ISO164x supports UL 1577
isolation ratings of 5000 VRMS in the 16-DW package,
and 3000 VRMS in the 8-D package. Each I2C
isolation channel in this low emissions device has
a logic input and open drain output separated by
a double capacitive silicon dioxide (SiO2) insulation
barrier. The ISO1642 and ISO1643 intregrates 2
unidirectional CMOS isolation channels, while the
ISO1644 intregrates 3 unidirectional CMOS isolation
channels which can be used for static GPIO isolation
or to isolate a Serial Peripheral Interface (SPI) bus.
This family includes basic and reinforced insulation
devices certified by VDE, UL, CSA, TUV and CQC.
The ISO1640/2/3/4 have two isolated bidirectional
channels for clock and data lines and the ISO1641
has a bidirectional data and a unidirectional clock
channel. The ISO164x family integrates logic required
to support bidirectional channels, providing a much
simpler design and smaller footprint when compared
to optocoupler-based solutions.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
ISO1640BD
ISO1641BD
SOIC (8)
4.90 mm × 3.91 mm
ISO1640DW
ISO1641DW
ISO1642DW
ISO1643DW
ISO1644DW
SOIC (16)
10.30 mm × 7.50 mm
(1)
For all available packages, see the orderable addendum at
the end of the data sheet.
Isolation Options
PART NUMBER
ISO164xBD
ISO164xDW
Protection Level
Basic
Reinforced
Surge Test Voltage
6500 VPK
10000 VPK
Isolation Rating
3000 VRMS
5000 VRMS
Working Voltage
450 VRMS / 637
VPK
1500 VRMS / 2121
VPK
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ISO1640, ISO1641, ISO1642, ISO1643, ISO1644
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SLLSFC2D – DECEMBER 2020 – REVISED SEPTEMBER 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 8
6.1 Absolute Maximum Ratings ....................................... 8
6.2 ESD Ratings .............................................................. 8
6.3 Recommended Operating Conditions ........................8
6.4 Thermal Information ...................................................9
6.5 Power Ratings ..........................................................10
6.6 Insulation Specifications ...........................................11
6.7 Safety-Related Certifications ................................... 13
6.8 Safety Limiting Values ..............................................13
6.9 Electrical Characteristics ..........................................14
6.10 Supply Current Characteristics .............................. 15
6.11 Timing Requirements ............................................. 18
6.12 I2C Switching Characteristics ................................ 19
6.13 GPIO Switching Characteristics .............................21
6.14 Insulation Characteristics Curves........................... 22
6.15 Typical Characteristics............................................ 23
7 Parameter Measurement Information.......................... 27
7.1 Parameter Measurement Information....................... 27
8 Detailed Description......................................................30
8.1 Overview................................................................... 30
8.2 Functional Block Diagrams....................................... 30
8.3 Isolation Technology Overview................................. 31
8.4 Feature Description...................................................31
8.5 Isolator Functional Principle......................................32
8.6 Device Functional Modes..........................................34
9 Application and Implementation.................................. 35
9.1 Application Information............................................. 35
9.2 Typical Application.................................................... 36
9.3 Insulation Lifetime .................................................... 42
10 Power Supply Recommendations..............................44
11 Layout........................................................................... 45
11.1 Layout Guidelines................................................... 45
11.2 Layout Example...................................................... 45
12 Device and Documentation Support..........................46
12.1 Documentation Support.......................................... 46
12.2 Receiving Notification of Documentation Updates..46
12.3 Support Resources................................................. 46
12.4 Trademarks............................................................. 46
12.5 Electrostatic Discharge Caution..............................46
12.6 Glossary..................................................................46
13 Mechanical, Packaging, and Orderable
Information.................................................................... 46
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (June 2021) to Revision D (September 2021)
Page
• Added ISO1641DW, ISO1642DW and ISO1643DW to the datasheet............................................................... 1
Changes from Revision B (May 2021) to Revision C (June 2021)
Page
• Added ISO1644DW to the datasheet................................................................................................................. 1
Changes from Revision A (December 2020) to Revision B (May 2021)
Page
• Added ISO1641B to the datasheet..................................................................................................................... 1
• Changed minimum input threshold low to 480 mV........................................................................................... 14
• Changed tpLH1-2, tpLH2-1, tLOOP1 max to a lower value for all operating voltages.............................................. 19
2
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5 Pin Configuration and Functions
1
8
VCC2
SDA1
2
7
SDA2
SCL1
3
6
SCL2
GND1
4
5
GND2
Isolation
VCC1
Side 2
Side 1
Not to scale
Figure 5-1. ISO1640B Package 8-Pin SOIC Top View
1
8
VCC2
SDA1
2
7
SDA2
SCL1
3
6
SCL2
GND1
4
5
GND2
Isolation
VCC1
Side 1
Side 2
Not to scale
Figure 5-2. ISO1641B Package 8-Pin SOIC Top View
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1
16
GND2
NC
2
15
NC
VCC1
3
14
VCC2
NC
4
13
NC
SDA1
5
12
SDA2
SCL1
6
11
SCL2
GND1
7
10
NC
NC
8
9
ISOLATION
GND1
Side 1
GND2
Side 2
Not to scale
Figure 5-3. ISO1640 Package 16-Pin SOIC Top View
1
16
GND2
NC
2
15
NC
VCC1
3
14
VCC2
NC
4
13
NC
SDA1
5
12
SDA2
SCL1
6
11
SCL2
GND1
7
10
NC
NC
8
9
ISOLATION
GND1
Side 1
GND2
Side 2
Not to scale
Figure 5-4. ISO1641 Package 16-Pin SOIC Top View
1
16
VCC2
NC
2
15
NC
SDA1
3
14
SDA2
INA
4
13
OUTA
OUTB
5
12
INB
SCL1
6
11
SCL2
NC
7
10
NC
GND1
8
9
ISOLATION
VCC1
Side 1
GND2
Side 2
No t to scale
Figure 5-5. ISO1642 Package 16-Pin SOIC Top View
4
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1
16
VCC2
NC
2
15
NC
SDA1
3
14
SDA2
INA
4
13
OUTA
INB
5
12
OUTB
SCL1
6
11
SCL2
NC
7
10
NC
GND1
8
9
ISOLATION
VCC1
Side 1
GND2
Side 2
No t to scale
Figure 5-6. ISO1643 Package 16-Pin SOIC Top View
1
16
VCC2
GND1
2
15
GND2
SDA1
3
14
SDA2
INA
4
13
OUTA
INB
5
12
OUTB
SCL1
6
11
SCL2
OUTC
7
10
INC
GND1
8
9
ISOLATION
VCC1
Side 1
GND2
Side 2
Not to scale
Figure 5-7. ISO1644 Package 16-Pin SOIC Top View
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Table 5-1. Pin Functions — ISO1640 and ISO1641
PIN
8-D
16-DW
I/O
DESCRIPTION
NAME
NO.
NO.
GND1
4
1, 7
—
Ground, side 1
GND2
5
9, 16
—
Ground, side 2
NC
—
2, 4, 8, 10,
13, 15
—
No Connection
SCL1
3
6
I/O
Serial clock input / output, side 1 (ISO1640 only)
Serial clock input, side 1 (ISO1641 only)
SCL2
6
11
I/O
Serial clock input / output, side 2 (ISO1640 only)
Serial clock output, side 2 (ISO1641 only)
SDA1
2
5
I/O
Serial data input / output, side 1
SDA2
7
12
I/O
Serial data input / output, side 2
VCC1
1
3
—
Supply voltage, side 1
VCC2
8
14
—
Supply voltage, side 2
Table 5-2. Pin Functions — ISO1642 and ISO1643
PIN
16-DW
I/O
DESCRIPTION
NAME
NO.
GND1
8
—
Ground, side 1
GND2
9
—
Ground, side 2
INA
4
INB/OUTB
12
NC
I
Input, channel A
—
Input, channel B (ISO1642)
Output, channel B (ISO1643)
2, 7, 10, 15
—
No Connect
OUTA
13
O
Output, channel A
OUTB/INB
5
—
Output, channel B (ISO1642)
Input, channel B (ISO1643)
SCL1
6
I/O
Serial clock input / output, side 1
SCL2
11
I/O
Serial clock input / output, side 2
SDA1
3
I/O
Serial data input / output, side 1
SDA2
14
I/O
Serial data input / output, side 2
VCC1
1
—
Supply voltage, side 1
VCC2
16
—
Supply voltage, side 2
Table 5-3. Pin Functions — ISO1644
PIN
16-DW
NAME
6
I/O
DESCRIPTION
NO.
GND1
2, 8
—
Ground, side 1
GND2
9, 15
—
Ground, side 2
INA
4
I
Input, channel A
INB
5
I
Input, channel B
INC
10
I
Input, channel C
OUTA
13
O
Output, channel A
OUTB
12
O
Output, channel B
OUTC
7
O
Output, channel C
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Table 5-3. Pin Functions — ISO1644 (continued)
PIN
16-DW
I/O
DESCRIPTION
NAME
NO.
SCL1
6
I/O
Serial clock input / output, side 1
SCL2
11
I/O
Serial clock input / output, side 2
SDA1
3
I/O
Serial data input / output, side 1
SDA2
14
I/O
Serial data input / output, side 2
VCC1
1
—
Supply voltage, side 1
VCC2
16
—
Supply voltage, side 2
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN
Supply Voltage
Input/Output Voltage
VCC1, VCC2
–0.5
6
SDA1, SCL1
–0.5
VCCX + 0.5(3)
SDA2, SCL2
–0.5
VCCX + 0.5(3)
INx (ISO1642/3/4 only)
-0.5
VCCX + 0.5
0
20
0
100
-15
15
SDA1, SCL1
Input/Output Current
SDA2, SCL2
IIO (ISO1642/3/4 only)
Maximum junction temperature, TJ
Temperature
(1)
(2)
(3)
MAX
Storage temperature, Tstg
–65
UNIT
V
V
mA
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
All voltage values are with respect to the local ground pin (GND1 or GND2) and are peak voltage values.
During powered off hotswap, the I2C bus pins can be 0 V < SDAx, SCLx < 6 V.
6.2 ESD Ratings
Human body model (HBM), per ANSI/
ESDA/JEDEC JS-001(1)
Electrostatic
discharge
V(ESD)
VALUE
UNIT
All pins
±6000
V
ISO1640/1: Bus pins (SDA1, SCL1)
±10000
V
ISO1640/1: Bus pins (SDA2, SCL2)
±14000
V
ISO1642/3/4: Bus pins (SDA1, SCL1)
±8000
V
ISO1642/3/4: Bus pins (SDA2, SCL2)
±8000
V
±1500
V
±8000
V
±8000
V
Charged-device model (CDM), per ANSI/ESDA/JEDEC specification JS-002(2)
Contact discharge per IEC 61000-4-2; Isolation barrier withstand
Same side unpowered IEC ESD
contact discharge per IEC 61000-4-2;
Side 2
(1)
(2)
(3)
(4)
test(3) (4)
ISO1640/1: SCL2, SDA2
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
IEC ESD strike is applied across the barrier with all pins on each side tied together creating a two-terminal device.
Testing is carried out in air or oil to determine the intrinsic contact discharge capability of the device.
6.3 Recommended Operating Conditions
MIN
VCC1(UVLO+)
UVLO threshold when supply voltage is rising on Side 1
VCC1(UVLO-)
UVLO threshold when supply voltage is falling on Side 1
VCC2(UVLO+)
UVLO threshold when supply voltage is rising on Side 2
VCC2(UVLO-)
UVLO threshold when supply voltage is falling on Side 2
VHYS1(UVLO)
VHYS2(UVLO)
8
Supply voltage UVLO hysteresis, Side 1
Supply voltage UVLO hysteresis, Side 2
NOM
MAX
2.7
2.9
UNIT
V
2.3
2.6
1.7
1.8
V
100
150
mV
100
150
mV
2
V
2.25
V
VCC1
Supply voltage, Side 1
3.0
5.5
V
VCC2
Supply voltage, Side 2
2.25
5.5
V
VSDA1,
VSCL1
I2C Input and output signal voltages, Side 1
0
VCC1
V
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MIN
MAX
UNIT
0
VCC2
V
I2C Low-level input voltage, Side 1
0
480
mV
VIH1
I2C High-level input voltage, Side 1
0.7 × VCC1
VCC1
V
VIL2
I2C Low-level input voltage, Side 2
0
0.3 × VCC2
V
VIH2
I2C High-level input voltage, Side 2
0.5 × VCC2
VCC2
IOL1
I2C Output current, Side 1
0.5
3.5
mA
IOL2
I2C Output current, Side 2
0.5
50
mA
C1
Capacitive load, Side 1
80
pF
C2
Capacitive load, Side 2
400
pF
fMAX
I2C Operating frequency(1)
1.7
MHz
VILIO
Low-level input voltage, GPIO pins (ISO1642/3/4 only)
0
0.3 × VCC2
V
VIHIO
High-level input voltage, GPIO pins (ISO1642/3/4 only)
0.7 × VCC1
VCC1
V
VSDA2,
VSCL2
I2C Input and output signal voltages, Side 2
VIL1
IOHIO
IOLIO
V
GPIO High-level output current, VCCO = 5 V (ISO1642/3/4
only)
-4
mA
GPIO High-level output current, VCCO = 3.3 V (ISO1642/3/4
only)
-2
mA
GPIO High-level output current, VCCO = 2.5 V (ISO1642/3/4
only)
-1
mA
GPIO Low-level output current, VCCO = 5 V (ISO1642/3/4
only)
4
mA
GPIO Low-level output current, VCCO = 3.3 V (ISO1642/3/4
only)
2
mA
GPIO Low-level output current, VCCO = 2.5 V (ISO1642/3/4
only)
1
mA
50
Mbps
125
°C
fDR
GPIO maximum data rate frequency (ISO1642/3/4 only)
TA
Ambient temperature
(1)
NOM
–40
25
Maximum frequency is a function of the RC time constant on the bus. If the system has less bus capacitance, then higher frequencies
can be achieved.
6.4 Thermal Information
ISO1642/3/
4
ISO1640/1
THERMAL METRIC(1)
D (SOIC)
DW (SOIC) DW (SOIC)
8 PINS
16 PINS
16 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
106.3
62.4
58.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
38.5
29.5
25.5
°C/W
RθJB
Junction-to-board thermal resistance
52.5
33.5
29.7
°C/W
ψJT
Junction-to-top characterization parameter
8.2
11.7
8.9
°C/W
ψJB
Junction-to-board characterization parameter
51.8
32.4
28.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
-
-
-
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Power Ratings
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
96
mW
43
mW
53
mW
ISO1640
PD
Maximum power dissipation (both
sides)
PD1
Maximum power dissipation (side-1)
PD2
Maximum power dissipation (side-2)
VCC1 = VCC2 = 5.5 V, TJ = 150°C, C1 = 20 pF, C2 = 400 pF, R1 =
1.4 kΩ, R2 = 94 Ω, Input a 1.7-MHz 50% duty-cycle clock signal
ISO1641
PD
Maximum power dissipation (both
sides)
VCC1 = VCC2 = 5.5 V, TJ = 150°C, C1 = 20 pF, C2 = 400 pF, R1 =
1.4 kΩ, R2 = 94 Ω, Input a 1.7-MHz 50% duty-cycle clock signal
87
mW
PD1
Maximum power dissipation (side-1)
VCC1 = VCC2 = 5.5 V, TJ = 150°C, C1 = 20 pF, C2 = 400 pF, R1 =
1.4 kΩ, R2 = 94 Ω, Input a 1.7-MHz 50% duty-cycle clock signal
40
mW
PD2
Maximum power dissipation (side-2)
VCC1 = VCC2 = 5.5 V, TJ = 150°C, C1 = 20 pF, C2 = 400 pF, R1 =
1.4 kΩ, R2 = 94 Ω, Input a 1.7-MHz 50% duty-cycle clock signal
47
mW
VCC1 = VCC2 = 5.5 V, TJ = 150°C, C1 = 20 pF, C2 = 400 pF, R1 =
1.4 kΩ, R2 = 94 Ω, Input a 1.7-MHz 50% duty-cycle clock signal
INA = INB = Input at 25-MHz 50% duty cycle square wave, CL =
15pF
185
mW
83
mW
102
mW
VCC1 = VCC2 = 5.5 V, TJ = 150°C, C1 = 20 pF, C2 = 400 pF, R1 =
1.4 kΩ, R2 = 94 Ω, Input a 1.7-MHz 50% duty-cycle clock signal
INA = INB = Input at 25-MHz 50% duty cycle square wave, CL =
15pF
185
mW
67
mW
118
mW
VCC1 = VCC2 = 5.5 V, TJ = 150°C, C1 = 20 pF, C2 = 400 pF, R1 =
1.4 kΩ, R2 = 94 Ω, Input a 1.7-MHz 50% duty-cycle clock signal
INA = INB = INC = Input at 25-MHz 50% duty cycle square wave,
CL = 15pF
210
mW
88
mW
122
mW
ISO1642
PD
Maximum power dissipation (both
sides)
PD1
Maximum power dissipation (side-1)
PD2
Maximum power dissipation (side-2)
ISO1643
PD
Maximum power dissipation (both
sides)
PD1
Maximum power dissipation (side-1)
PD2
Maximum power dissipation (side-2)
ISO1644
PD
Maximum power dissipation (both
sides)
PD1
Maximum power dissipation (side-1)
PD2
Maximum power dissipation (side-2)
10
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6.6 Insulation Specifications
PARAMETER
SPECIFICATIONS
TEST CONDITIONS
DW
D
UNIT
IEC 60664-1
External clearance(1)
Side 1 to side 2 distance through air
>8
4
mm
CPG
External Creepage(1)
Side 1 to side 2 distance across package
surface
>8
4
mm
DTI
Distance through the insulation
Minimum internal gap (internal clearance)
>17
>17
µm
CTI
Comparative tracking index
IEC 60112; UL 746A
>600
>400
V
Material Group
According to IEC 60664-1
I
II
Rated mains voltage ≤ 150 VRMS
I-IV
I-IV
Rated mains voltage ≤ 300 VRMS
I-IV
I-III
Rated mains voltage ≤ 600 VRMS
I-IV
n/a
Rated mains voltage ≤ 1000 VRMS
I-III
n/a
Maximum repetitive peak isolation voltage
AC voltage (bipolar)
2121
637
VPK
Maximum isolation working voltage
AC voltage (sine wave); time-dependent
dielectric breakdown (TDDB) test;
1500
450
VRMS
DC voltage
2121
637
VDC
Maximum transient isolation voltage
VTEST = VIOTM , t = 60 s (qualification); VTEST
= 1.2 × VIOTM, t = 1 s (100% production)
7071
4242
VPK
Maximum surge isolation voltage(3)
Test method per IEC 62368-1, 1.2/50 µs
waveform, VTEST = 1.3 × VIOSM = 6,500 VPK
(Basic qualification) Test method per IEC
6250
62368-1, 1.2/50 µs waveform, VTEST = 1.6 ×
VIOSM = 10,000 VPK (Reinforced qualification)
5000
VPK
Method a: After I/O safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM ,
tm = 10 s
≤5
≤5
Method a: After environmental tests subgroup
1, Vini = VIOTM, tini = 60 s;
≤5
Vpd(m) = 1.6 × VIORM , tm = 10 s
≤5
Method b1: At routine test (100% production)
and preconditioning (type test), Vini = VIOTM,
≤5
tini = 1 s;
Vpd(m) = 1.875 × VIORM , tm = 1 s
≤5
VIO = 0.4 × sin (2 πft), f = 1 MHz
1
1
VIO = 500 V, TA = 25°C
> 1012
> 1012
VIO = 500 V, 100°C ≤ TA ≤ 150°C
> 1011
> 1011
VIO = 500 V at TS = 150°C
> 109
> 109
Pollution degree
2
2
Climatic category
40/125/
21
40/125/
21
CLR
Overvoltage category
DIN V VDE V 0884-11:2017-01(2)
VIORM
VIOWM
VIOTM
VIOSM
qpd
Apparent
charge(4)
Barrier capacitance, input to output(5)
CIO
Insulation resistance, input to output(5)
RIO
pC
pF
Ω
UL 1577
VISO
(1)
(2)
(3)
Withstand isolation voltage
VTEST = VISO , t = 60 s (qualification); VTEST =
5000
1.2 × VISO , t = 1 s (100% production)
3000
VRMS
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application.
Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the
isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal
in certain cases. Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these
specifications.
ISO164xDW is suitable for safe electrical insulation and ISO164xBD is suitable for basic electrical insulation only within the safety
ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
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(4)
(5)
12
Apparent charge is electrical discharge caused by a partial discharge (pd).
All pins on each side of the barrier tied together creating a two-pin device.
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6.7 Safety-Related Certifications
VDE
CSA
UL
CQC
TUV
Certified according to DIN
VDE V 0884-11:2017-01
Certified according to IEC
61010-1, IEC 62368-1 and
IEC 60601-1
Recognized under UL 1577
Component Recognition
Program
Certified according to
GB4943.1-2011
Certified according to EN
61010-1:2010/A1:2019, and EN
62368-1:2014
Maximum transient isolation
voltage, 7071 VPK (DW-16),
and 4242 VPK (D-8);
Maximum repetitive peak
isolation voltage, 1500 VPK
(DW-16), and 637 VPK (D-8);
Maximum surge isolation
voltage, 6250 VPK (DW-16),
and 5000 VPK (D-8)
DW-16: 600 VRMS
reinforced insulation per
CSA 62368-1:19 and IEC
62368-1:2018 , (pollution
degree 2, material group I)
D-8: 400 VRMS basic
insulation per CSA
62368-1:19 and IEC
62368-1:2018, (pollution
degree 2, material group III)
DW-16: Single protection,
5000 VRMS;
D-8: Single protection, 3000
VRMS
DW-16: Reinforced Insulation,
Altitude ≤ 5000 m, Tropical
Climate,700 VRMS maximum
working voltage;
D-8: Basic Insulation, Altitude
≤ 5000 m, Tropical Climate,
250 VRMS maximum working
voltage
5000 VRMS (DW-16) and 3000
VRMS (D-8) Reinforced insulation
per EN 61010- 1:2010/A1:2019 up
to working voltage of 600 VRMS
(DW-16) and 300 VRMS (D-8)
5000 VRMS (DW-16) and 3000 VRMS
(D-8) Reinforced insulation per EN
62368-1:2014 up to working voltage
of 600 VRMS (DW-16) and 400 VRMS
(D-8)
Certification planned
Master contract number
(ISO164xBD): 220991
Certification planned (All
others)
File number (ISO164xBD):
E181974
Certification planned (All
others)
Certification planned
Certification planned
6.8 Safety Limiting Values
Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ISO1640/1 D-8 PACKAGE
IS
Safety input, output, or supply
current(1)
PS
Safety input, output, or total
power(1)
TS
temperature(1)
Safety
RθJA = 106.3 °C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C
214
RθJA = 106.3 °C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C
327
RθJA = 106.3 °C/W, TJ = 150°C, TA = 25°C
mA
1176
mW
150
°C
ISO1640/1 DW-16 PACKAGE
IS
Safety input, output, or supply
current(1)
PS
Safety input, output, or total
power(1)
TS
temperature(1)
Safety
RθJA = 62.4 °C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C
365
RθJA = 62.4 °C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C
557
RθJA = 62.4 °C/W, TJ = 150°C, TA = 25°C,
mA
2004
mW
150
°C
RθJA = 58.3 °C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C
390
mA
RθJA = 58.3 °C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C
596
mA
2145
mW
150
°C
ISO1642/3/4 DW-16 Package
IS
Safety input, output, or supply
current(1)
PS
Safety input, output, or total
power(1)
TS
temperature(1)
(1)
Safety
RθJA = 58.3 °C/W, TJ = 150°C, TA = 25°C
The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The
IS and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be
exceeded. These limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the table is that of a device installed on a high-K test board for leaded surface-mount
packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum allowed junction temperature.
PS = IS × VI, where VI is the maximum input voltage.
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6.9 Electrical Characteristics
over recommended operating conditions, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SIDE 1
VILT1
Voltage input threshold low
(SDA1 and SCL1)
480
560
mV
VIHT1
Voltage input threshold high
(SDA1 and SCL1)
520
620
mV
VHYST1
Voltage input hysteresis
VIHT1 – VILT1
VOL1
Low-level output voltage(1)
(SDA1 and SCL1)
ΔVOIT1
Low-level output voltage to high-level input
voltage threshold difference, SDA1 and
SCL1(2) (3)
50
60
0.5 mA ≤ (ISDA1 and ISCL1) ≤ 3.5 mA
570
650
0.5 mA ≤ (ISDA1 and ISCL1) ≤ 3.5 mA
50
mV
710
mV
mV
SIDE 2
VILT2
Voltage input threshold low
(SDA2 and SCL2)
0.3 × VCC2
0.4 × VCC2
V
VIHT2
Voltage input threshold high
(SDA2 and SCL2)
0.4 × VCC2
0.5 × VCC2
V
VHYST2
Voltage input hysteresis
VIHT2 – VILT2
VOL2
Low-level output voltage
(SDA2 and SCL2)
0.5 mA ≤ (ISDA2 and ISCL2) ≤ 50 mA
0.05 × VCC2
V
0.4
V
10
µA
BOTH SIDES
|II|
Input leakage currents
(SDA1, SCL1, SDA2, and SCL2)
VSDA1, VSCL1 = VCC1,
VSDA2, VSCL2 = VCC2
CI
Input capacitance to local ground
(SDA1, SCL1, SDA2, and SCL2)
VI = 0.4 × sin(2e6*πt) + VDDx / 2
CMTI
Common-mode transient immunity
VCM = 1000 V, see Common-Mode
Transient Immunity Test Circuit
0.01
50
10
pF
100
kV/µs
GPIO Channels
VIOOH
High-level output voltage
VIOOL
Low-level output voltage
VCCx = 5 V, IOH = -4 mA; ISO1642/3/4 only
VCCO - 0.4
V
VCCx = 3.3 V, IOH = -2 mA; ISO1642/3/4
only
VCCO - 0.3
V
VCC1 = 2.5 V, IOH = -1 mA; ISO1642/3/4
only
VCCO - 0.2
V
VCCx = 5 V, IOH = 4 mA; ISO1642/3/4 only
0.4
V
VCCx = 3.3 V, IOH = 2 mA; ISO1642/3/4 only
0.3
V
VCC1 = 2.5 V, IOH = 1 mA; ISO1642/3/4 only
0.2
V
0.7 x VCCI (1)
V
VIT+(IN)
Rising input switching threshold
ISO1642/3/4 only
VIT-(IN)
Falling input switching threshold
ISO1642/3/4 only
0.3 x VCCI
VI(HYS)
Input threshold voltage hysteresis
ISO1642/3/4 only
0.1 x VCCI
IIH
High-level input current
VIH = VCCI (1) at INx. ISO1642/3/4 only
IIL
Low-level input current
VIL = 0 V at INx. ISO1642/3/4 only
(1)
(2)
(3)
14
V
V
10
-10
µA
µA
This parameter does not apply to the SCL1 line of the ISO1641 device because it is unidirectional.
∆VOIT1 = VOL1 – VIHT1. This value represents the minimum difference between a threshold for the low-level output voltage and
a threshold for the high-level input voltage to prevent a permanent latch condition that would otherwise occur with bidirectional
communication.
Any supply voltages on either side that are less than the minimum value make sure that the device does a lockout. Both supply
voltages that are greater than the maximum value keep the device from a lockout.
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6.10 Supply Current Characteristics
over recommended operating conditions, unless otherwise noted. See Test Diagram for more information.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2,
R1 and R2 = Open, C1 and C2 = Open
4.9
6.6
mA
VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2,
R1 and R2 = Open, C1 and C2 = Open
2.7
3.5
mA
VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2,
R1 and R2 = Open, C1 and C2 = Open
3.8
5.2
mA
VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2,
R1 and R2 = Open, C1 and C2 = Open
2.7
3.5
mA
VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 0
6.3
9.2
mA
VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 1
5.5
7.8
mA
VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 0
4.3
6.0
mA
VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 1
7.5
10.5
mA
VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 0
6.8
9.9
mA
VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 1
4.9
7.3
mA
VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 0
4.8
6.7
mA
VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 1
6.9
9.8
mA
VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 0
6.8
10
mA
VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 1
6
8.7
mA
VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 0
4.8
6.7
mA
VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 1
7.9
11.2
mA
VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2,
R1 and R2 = Open, C1 and C2 = Open
5.2
7.1
mA
VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2,
R1 and R2 = Open, C1 and C2 = Open
3
4
mA
VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2,
R1 and R2 = Open, C1 and C2 = Open
4.6
6.1
mA
VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2,
R1 and R2 = Open, C1 and C2 = Open
2.4
3.2
mA
2.25 V ≤ VCC2 ≤ 2.75 V
ICC2
ICC2
ICC2
ICC2
ICC2
Supply current,
Side 2
ISO1640
Supply current,
Side 2
ISO1641
Supply current,
Side 2
Supply current,
Side 2
Supply current,
Side 2
ISO1642
ISO1643
ISO1644
3 V ≤ VCC1, VCC2 ≤ 3.6 V
ICC1
ICC1
Supply current,
Side 1
ISO1640
Supply current,
Side 1
ISO1641
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PARAMETER
ICC1
ICC1
ICC1
ICC2
ICC2
ICC2
16
Supply current,
Side 1
Supply current,
Side 1
Supply current,
Side 1
TEST CONDITIONS
ISO1642
ISO1643
ISO1644
Supply current,
Side 2
ISO1640
Supply current,
Side 2
ISO1641
Supply current,
Side 2
ISO1642
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MIN
TYP
MAX
UNIT
VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 0
7.3
9.6
mA
VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 1
5.8
8.3
mA
VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 0
4.7
6.6
mA
VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 1
8.4
11.6
mA
VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 0
6.9
8.9
mA
VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 1
6.5
8.9
mA
VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 0
4.3
5.9
mA
VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 1
9
12.3
mA
VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 0
7.3
10.1
mA
VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 1
6.9
9.6
mA
VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 0
4.7
6.6
mA
VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 1
9.5
13.1
mA
VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2,
R1 and R2 = Open, C1 and C2 = Open
4.9
6.7
mA
VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2,
R1 and R2 = Open, C1 and C2 = Open
2.8
3.5
mA
VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2,
R1 and R2 = Open, C1 and C2 = Open
3.9
5.2
mA
VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2,
R1 and R2 = Open, C1 and C2 = Open
2.8
3.5
mA
VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 0
6.4
9.2
mA
VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 1
5.6
7.8
mA
VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 0
4.4
6.0
mA
VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 1
7.6
10.5
mA
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over recommended operating conditions, unless otherwise noted. See Test Diagram for more information.
PARAMETER
ICC2
ICC2
Supply current,
Side 2
Supply current,
Side 2
TEST CONDITIONS
ISO1643
ISO1644
MIN
TYP
MAX
UNIT
VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 0
6.8
9.9
mA
VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 1
4.9
7.3
mA
VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 0
4.8
6.7
mA
VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 1
6.9
9.8
mA
VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 0
6.8
10
mA
VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 1
6
8.4
mA
VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 0
4.8
6.7
mA
VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 1
8
11.3
mA
VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2,
R1 and R2 = Open, C1 and C2 = Open
5.3
7.2
mA
VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2,
R1 and R2 = Open, C1 and C2 = Open
3
4.1
mA
VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2,
R1 and R2 = Open, C1 and C2 = Open
4.7
6.2
mA
VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2,
R1 and R2 = Open, C1 and C2 = Open
2.5
3.2
mA
VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 0
7.6
10.4
mA
VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 1
5.9
8.2
mA
VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 0
4.7
6.7
mA
VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 1
8.7
12
mA
VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 0
7.2
9.7
mA
VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 1
6.5
8.9
mA
VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 0
4.3
6
mA
VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 1
9.3
12.7
mA
4.5 V ≤ VCC1, VCC2 ≤ 5.5 V
ICC1
ICC1
ICC1
ICC1
Supply current,
Side 1
Supply current,
Side 1
Supply current,
Side 1
Supply current,
Side 1
ISO1640
ISO1641
ISO1642
ISO1643
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over recommended operating conditions, unless otherwise noted. See Test Diagram for more information.
PARAMETER
ICC1
ICC2
ICC2
ICC2
ICC2
ICC2
Supply current,
Side 1
TEST CONDITIONS
ISO1644
Supply current,
Side 2
ISO1640
Supply current,
Side 2
ISO1641
Supply current,
Side 2
Supply current,
Side 2
Supply current,
Side 2
ISO1642
ISO1643
ISO1644
MIN
TYP
MAX
UNIT
VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 0
7.6
10.4
mA
VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 1
7
9.7
mA
VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 0
4.7
6.7
mA
VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 1
9.6
13.5
mA
VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2,
R1 and R2 = Open, C1 and C2 = Open
5
6.8
mA
VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2,
R1 and R2 = Open, C1 and C2 = Open
2.8
3.6
mA
VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2,
R1 and R2 = Open, C1 and C2 = Open
3.9
5.3
mA
VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2,
R1 and R2 = Open, C1 and C2 = Open
2.8
3.6
mA
VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 0
6.5
9.1
mA
VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 1
5.6
7.7
mA
VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 0
4.5
6.1
mA
VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 1
7.7
10.7
mA
VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 0
6.9
9.8
mA
VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 1
5
7
mA
VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 0
4.9
6.8
mA
VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 1
7
10
mA
VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 0
6.9
9.8
mA
VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 1
6.1
8.5
mA
VSDA1, VSCL1 = VCC1, VSDA2, VSCL2 = VCC2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 0
4.9
6.8
mA
VSDA1, VSCL1 = GND1, VSDA2, VSCL2 = GND2,
R1 and R2 = Open, C1 and C2 = Open
GPIOs = 1
8.1
11.5
mA
6.11 Timing Requirements
tUVLO
18
Time to recover from UVLO
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MIN
NOM
MAX
UNIT
36
95
151
µs
VCC1 > VCC1(UVLO+) or VCC2 > VCC2(UVLO+), I2C bus Idle.
see tUVLO Test Circuit and Timing Diagrams
Copyright © 2022 Texas Instruments Incorporated
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SLLSFC2D – DECEMBER 2020 – REVISED SEPTEMBER 2021
6.12 I2C Switching Characteristics
over recommended operating conditions, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.7 × VCC2 ≥ VO ≥ 0.3 × VCC2, R2 = 72 Ω,
C2 = 400 pF, see Test Diagram
16
26.5
40
0.9 × VCC2 ≥ VO ≥ 400 mV, R2 = 72Ω,
C2 = 400 pF, see Test Diagram
38
53.3
78
UNIT
2.25 V ≤ VCC2 ≤ 2.75 V, 3 V ≤ VCC1 ≤ 3.6 V
tf2
Output signal fall time
(SDA2 and SCL2)
ns
tpLH1-2
Low-to-high propagation delay, side 1
to side 2
VI = 535 mV, VO = 0.7 × VCC2, R1 = 953 Ω, R2 = 72 Ω, C1
and C2 = 10 pF, VCC1 = 3.3 V, see Test Diagram
20
30
ns
tpHL1-2
High-to-low propagation delay, side 1 to VI = 550 mV, VO = 0.3 × VCC2, R1 = 953 Ω, R2 = 72 Ω, C1
side 2
and C2 = 10 pF, VCC1 = 3.3 V, see Test Diagram
80
130
ns
tpLH2-1
Low-to-high propagation delay, side 2
to side 1(1)
VI = 0.4 x VCC2, VO = 0.7 x VCC1, R1 = 953 Ω, R2 = 72 Ω, C1
and C2 = 10 pF, VCC1 = 3.3 V, see Test Diagram
40
48
ns
tpHL2-1
High-to-low propagation delay, side 2 to VI = 0.4 x VCC2, VO = 0.3 × VCC1, R1 = 953 Ω, R2 = 72 Ω, C1
side 1(1)
and C2 = 10 pF, VCC1 = 3.3 V, see Test Diagram
70
100
ns
PWD1-2
Pulse width distortion
|tpHL1-2 – tpLH1-2|
R1 = 953 Ω, R2 = 72 Ω, C1 and C2 = 10 pF, VCC1 = 3.3 V
see Test Diagram
60
104
ns
distortion(1)
PWD2-1
Pulse width
|tpHL2-1 – tpLH2-1|
R1 = 953 Ω, R2 = 72 Ω, C1 and C2 = 10 pF, VCC1 = 3.3 V
see Test Diagram
25
55
ns
tLOOP1
Round-trip propagation delay on side
1(1)
0.4 V ≤ VI ≤ 0.3 × VCC1, R1 = 953 Ω,
C1 = 40 pF, R2 = 72 Ω, C2 = 400 pF, see Test Diagram
62
74
ns
8
17
29
0.9 × VCC1 ≥ VO ≥ 900 mV, R1 = 953 Ω,
C1 = 40 pF, see Test Diagram
15
25
48
0.7 × VCC2 ≥ VO ≥ 0.3 × VCC2, R2 = 95.3 Ω,
C2 = 400 pF, see Test Diagram
14
23
47
0.9 × VCC2 ≥ VO ≥ 400 mV, R2 = 95.3 Ω,
C2 = 400 pF, see Test Diagram
30
50
100
3 V ≤ VCC1, VCC2 ≤ 3.6 V
tf1
tf2
0.7 × VCC1 ≥ VO ≥ 0.3 × VCC1, R1 = 953 Ω,
C1 = 40 pF, R2 = 95.3 Ω, C2 = 400 pF, see Test Diagram
Output signal fall time
(SDA1 and SCL1)
Output signal fall time
(SDA2 and SCL2)
ns
ns
tpLH1-2
Low-to-high propagation delay, side 1
to side 2
VI = 535 mV, VO = 0.7 × VCC2, R1 = 953 Ω, R2 = 95.3 Ω, C1
and C2 = 10 pF, see Test Diagram
21
29
ns
tpHL1-2
High-to-low propagation delay, side 1 to VI = 550 mV, VO = 0.3 × VCC2, R1 = 953 Ω, R2 = 95.3 Ω, C1
side 2
and C2 = 10 pF, see Test Diagram
59
88
ns
tpLH2-1
Low-to-high propagation delay, side 2
to side 1(1)
VI = 0.4 x VCC2, VO = 0.7 x VCC1, R1 = 953 Ω, R2 = 95.3 Ω,
C1 and C2 = 10 pF, see Test Diagram
40
47
ns
tpHL2-1
High-to-low propagation delay, side 2 to VI = 0.4 x VCC2, VO = 0.3 × VCC1, R1 = 953 Ω, R2 = 95.3 Ω,
side 1(1)
C1 and C2 = 10 pF, see Test Diagram
70
100
ns
PWD1-2
Pulse width distortion
|tpHL1-2 – tpLH1-2|
R1 = 953 Ω, R2 = 95.3 Ω, C1 and C2 = 10 pF,
see Test Diagram
39
61
ns
PWD2-1
Pulse width distortion(1)
|tpHL2-1 – tpLH2-1|
R1 = 953 Ω, R2 = 95.3 Ω, C1 and C2 = 10 pF,
see Test Diagram
25
48
ns
tLOOP1
Round-trip propagation delay on side
1(1)
0.4 V ≤ VI ≤ 0.3 × VCC1, R1 = 953 Ω,
C1 = 40 pF, R2 = 95.3 Ω, C2 = 400 pF, see Test Diagram
65
78
ns
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SLLSFC2D – DECEMBER 2020 – REVISED SEPTEMBER 2021
over recommended operating conditions, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
6
16
22
0.9 × VCC1 ≥ VO ≥ 900 mV, R1 = 1430 Ω,
C1 = 40 pF, see Test Diagram
13
32
48
0.7 × VCC2 ≥ VO ≥ 0.3 × VCC2, R2 = 143 Ω,
C2 = 400 pF, see Test Diagram
10
24
30
0.9 × VCC2 ≥ VO ≥ 400 mV, R2 = 143 Ω,
C2 = 400 pF, see Test Diagram
28
48
76
UNIT
4.5 V ≤ VCC1, VCC2 ≤ 5.5 V
0.7 × VCC1 ≥ VO ≥ 0.3 × VCC1, R1 = 1430 Ω,
C1 = 40 pF, R2 = 95.3 Ω, C2 = 400 pF, see Test Diagram
Output signal fall time
(SDA1 and SCL1)
tf1
Output signal fall time
(SDA2 and SCL2)
tf2
ns
ns
tpLH1-2
Low-to-high propagation delay, side 1
to side 2
VI = 535 mV, VO = 0.7 × VCC2, R1 = 1430 Ω, R2 = 143 Ω, C1
and C2 = 10 pF, see Test Diagram
21
28
ns
tpHL1-2
High-to-low propagation delay, side 1 to VI = 550 mV, VO = 0.3 × VCC2, R1 = 1430 Ω, R2 = 143 Ω, C1
side 2
and C2 = 10 pF, see Test Diagram
51
70
ns
tpLH2-1
Low-to-high propagation delay, side 2
to side 1(1)
VI = 0.4 x VCC2, VO = 0.7 x VCC1, R1 = 1430 Ω, R2 = 143 Ω,
C1 and C2 = 10 pF, see Test Diagram
51
57
ns
tpHL2-1
High-to-low propagation delay, side 2 to VI = 0.4 x VCC2, VO = 0.3 × VCC1, R1 = 1430 Ω, R2 = 143 Ω,
side 1(1)
C1 and C2 = 10 pF, see Test Diagram
60
88
ns
PWD1-2
Pulse width distortion
|tpHL1-2 – tpLH1-2|
R1 = 1430 Ω, R2 = 143 Ω, C1 and C2 = 10 pF,
see Test Diagram
30
45
ns
PWD2-1
Pulse width distortion(1)
|tpHL2-1 – tpLH2-1|
R1 = 1430 Ω, R2 = 143 Ω, C1 and C2 = 10 pF,
see Test Diagram
10
34
ns
tLOOP1
Round-trip propagation delay on side
1(1)
0.4 V ≤ VI ≤ 0.3 × VCCI, R1 = 1430 Ω,
C1 = 40 pF, R2 = 143 Ω, C2 = 400 pF, see Test Diagram
84
96
ns
(1)
20
This parameter does not apply to the SCL1 line of the ISO1641 device because it is unidirectional.
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SLLSFC2D – DECEMBER 2020 – REVISED SEPTEMBER 2021
6.13 GPIO Switching Characteristics
over recommended operating conditions, unless otherwise noted. ISO1644 only.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
11
20
UNIT
3 V ≤ VCC1, VCC2 ≤ 3.6 V
tPLH, tPHL
Propagation delay time
tP(dft)
Propagation delay drift
See Test Diagram
tUI
Minimum pulse width
PWD
Pulse width distortion
See Test Diagram
7
ns
tsk(o)
Channel to channel output skew time
Same direction channels
6
ns
tsk(p-p)
Part to part skew time
6
ns
tr
Output signal rise time
See Test Diagram
6.5
ns
tf
Output signal fall time
See Test Diagram
6.5
ns
tDO
Default output delay time from input
power loss
Measured from the time VCC goes below 1.2V. See Test
Diagram
0.3
us
tie
Time interval error
9.2
ns
ps/℃
20
ns
0.1
0.8
ns
4.5 V ≤ VCC1, VCC2 ≤ 5.5 V
tPLH, tPHL
Propagation delay time
tP(dft)
Propagation delay drift
See Test Diagram
11
18
tUI
Minimum pulse width
PWD
Pulse width distortion
See Test Diagram
7
ns
tsk(o)
Channel to channel output skew time
Same direction channels
6
ns
tsk(p-p)
Part to part skew time
6
ns
tr
Output signal rise time
See Test Diagram
6
ns
tf
Output signal fall time
See Test Diagram
6
ns
tDO
Default output delay time from input
power loss
Measured from the time VCC goes below 1.2V. See Test
Diagram
0.3
us
tie
Time interval error
8
20
ns
0.1
0.8
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ns
ps/℃
ns
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SLLSFC2D – DECEMBER 2020 – REVISED SEPTEMBER 2021
6.14 Insulation Characteristics Curves
350
1200
VCC1 = VCC2 = 3.3V
VCC1 = VCC2 = 5.5V
Safety Limiting Power (mW)
Safety Limiting Current (mA)
300
250
200
150
100
50
1000
800
600
400
200
0
0
0
20
40
60
80
100
120
Ambient Temperature (qC)
140
160
SLLS
0
20
40
60
80
100
120
Ambient Temperature (qC)
140
160
SLLS
Figure 6-1. ISO164xB Thermal Derating Curve for
Safety Limiting Current for D-8 Package
Figure 6-2. ISO164xB Thermal Derating Curve for
Safety Limiting Power for D-8 Package
Figure 6-3. ISO1640/1 Thermal Derating Curve for
Safety Limiting Current for DW-16 Package
Figure 6-4. ISO1640/1 Thermal Derating Curve for
Safety Limiting Power for DW-16 Package
Figure 6-5. ISO1642/3/4 Thermal Derating Curve for Figure 6-6. ISO1642/3/4 Thermal Derating Curve for
Safety Limiting Power for DW-16 Package
Safety Limiting Current for DW-16 Package
22
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SLLSFC2D – DECEMBER 2020 – REVISED SEPTEMBER 2021
6.15 Typical Characteristics
20
VCC1 = 3.3 V, IOL1 = 3.5 mA
VCC1 = 3.3 V, IOL1 = 0.5 mA
VCC1 = 5 V, IOL1 = 3.5 mA
VCC1 = 5 V, IOL1 = 0.5 mA
0.74
18
16
Fall Time tf1 (ns)
Output Voltage, VOL1 (V)
0.78
0.7
0.66
0.62
14
12
10
8
6
C1 = 80 pF, R1 = 1.43 k:
C1 = 80 pF, R1 = 2.2 k:
C1 = 40 pF, R1 = 1.43 k:
C1 = 40 pF, R1 = 2.2 k:
4
2
0.58
-40
-25
-10
5
20 35 50 65 80
Free-Air Temperature (qC)
95
0
-40
110 125
-25
-10
5
SLLS
TA = 25°C
20 35 50 65 80
Free-Air Temperature (qC)
25
R2 = 143 :
R2 = 2.2 k:
22
20
20
Fall Time tf2 (ns)
Fall Time tf1 (ns)
18
16
14
12
10
8
C1 - 80 pF, R1 = 953 k:
C1 = 80 pF, R1 = 2.2 k:
C1 - 40 pF, R1 = 953 k:
C1 = 40 pF, R1 = 2.2 k:
6
4
2
-25
-10
5
20 35 50 65 80
Free-Air Temperature (qC)
95
15
10
5
0
-40
110 125
-25
-10
5
SLLS
VCC1 = 3.3 V
20 35 50 65 80
Free-Air Temperature (qC)
VCC2 = 5 V
Figure 6-9. Side 1: Output Fall Time vs Free-Air
Temperature
95
110 125
SLLS
C2 = 400 pF
Figure 6-10. Side 2: Output Fall Time vs Free-Air
Temperature
30
25
R2 = 95.3
R2 = 2.2 k
R2 = 71.4 :
R2 = 2.2 k:
25
Fall Time tf2 (ns)
20
Fall Time tf2 (ns)
SLLS
Figure 6-8. Side 1: Output Fall Time vs Free-Air
Temperature
24
15
10
5
0
-40
110 125
VCC1 = 5 V
Figure 6-7. Side 1: Output Low Voltage vs Free-Air
Temperature
0
-40
95
20
15
10
5
-25
-10
5
20 35 50 65 80
Free-Air Temperature (qC)
VCC2 = 3.3 V
95
110 125
SLLS
C2 = 400 pF
Figure 6-11. Side 2: Output Fall Time vs Free-Air
Temperature
0
-40
-25
-10
5
20 35 50 65 80
Free-Air Temperature (qC)
VCC2 = 2.5 V
95
110 125
SLLS
C2 = 400 pF
Figure 6-12. Side 2: Output Fall Time vs Free-Air
Temperature
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100
590
VCC1 and VCC2 = 3.3 V, R1 and R2 = 2.2 k:
VCC1 and VCC2 = 5 V, R1 and R2 = 2.2 k:
90
585
80
580
tLOOP1 (ns)
tLOOP1 (ns)
70
60
50
40
570
30
20
565
VCC1 and VCC2 = 3.3 V, R1 = 953 :, R2 = 95.3 :
VCC1 and VCC2 = 5 V, R1 = 1430 :, R2 = 143 :
10
0
-40
575
-25
-10
5
20 35 50 65 80
Free-Air Temperature (qC)
C1 = 80 pF
95
560
-40
110 125
-25
-10
SLLS
C2 = 400 pF
5
20 35 50 65 80
Free-Air Temperature (qC)
C1 = 80 pF
Figure 6-13. tLOOP1 vs Free-Air Temperature
95
110 125
SLLS
C2 = 400 pF
Figure 6-14. tLOOP1 vs Free-Air Temperature
30
1200
Propagation Delay, tPLH1-2 (ns)
Propagation Delay, tPLH1-2 (ns)
1180
25
20
15
10
5
0
-40
VCC1 and VCC2 = 5 V, R2 = 143 :, C2 = 10pF
VCC1 and VCC2 = 3.3 V, R2 = 143 :, C2 = 10pF
-25
-10
5
20 35 50 65 80
Free-Air Temperature (qC)
95
1120
1100
1080
1060
1040
1000
-40
110 125
SLLS
70
70
60
60
50
40
30
20
10
0
-40
VCC1 and VCC2 = 5 V, R2 = 143 :, C2 = 10 pF
VCC1 and VCC2 = 3.3 V, R2 = 143 :, C2 = 10 pF
-25
-10
5
20 35 50 65 80
Free-Air Temperature (qC)
95
110 125
SLLS
Figure 6-17. tPHL1-2 Propagation Delay vs Free-Air
Temperature
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VCC1 and VCC2 = 5 V, R2 = 2.2 k:, C2 = 400 pF
VCC1 and VCC2 = 3.3 V, R2 = 2.2 k:, C2 = 400 pF
-25
-10
5
20 35 50 65 80
Free-Air Temperature (qC)
95
110 125
SLLS
Figure 6-16. tPLH1-2 Propagation Delay vs Free-Air
Temperature
Propagation Delay, tPHL1-2 (ns)
Propagation Delay, tPHL1-2 (ns)
1140
1020
Figure 6-15. tPLH1-2 Propagation Delay vs Free-Air
Temperature
24
1160
50
40
30
20
10
0
-40
VCC1 and VCC2 = 5 V, R2 = 2.2 k:, C2 = 400 pF
VCC1 and VCC2 = 3.3 V, R2 = 2.2 k:, C2 = 400 pF
-25
-10
5
20 35 50 65 80
Free-Air Temperature (qC)
95
110120
SLLS
Figure 6-18. tPHL1-2 Propagation Delay vs Free-Air
Temperature
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70
150
60
140
Propagation Delay, t PLH2-1 (ns)
Propagation Delay, tPLH2-1 (ns)
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50
40
30
20
10
VCC1 and VCC2 = 5 V, R1 = 143 :, C1 = 10 pF
VCC1 and VCC2 = 3.3 V, R1 = 143 :, C1 = 10 pF
0
-40
-25
-10
5
20 35 50 65 80
Free-Air Temperature (qC)
95
110
100
90
90
70
80
60
50
40
30
20
VCC1 and VCC2 = 5 V, R1 = 143 :, C1 = 10 pF
VCC1 and VCC2 = 3.3 V, R1 = 143 :, C1 = 10 pF
0
-40
-25
-10
5
20 35 50 65 80
Free-Air Temperature (qC)
-25
-10
5
95
95
110 125
SLLS
70
60
50
40
30
20
VCC1 and VCC2 = 5 V, R1 = 2.2 k:, C1 = 40 pF
VCC1 and VCC2 = 3.3 V, R1 = 2.2 k:, C1 = 40 pF
10
0
-40
110 125
-25
-10
SLLS
Figure 6-21. tPHL2-1 Propagation Delay vs Free-Air
Temperature
20 35 50 65 80
Free-Air Temperature (qC)
Figure 6-20. tPLH2-1 Propagation Delay vs Free-Air
Temperature
80
10
VCC1 and VCC2 = 5 V, R1 = 2.2 k:, C1 = 40 pF
VCC1 and VCC2 = 3.3 V, R1 = 2.2 k:, C1 = 40 pF
SLLS
Propagation Delay, tPHL2-1 (ns)
Propagation Delay, tPHL2-1 (ns)
120
80
-40
110 125
Figure 6-19. tPLH2-1 Propagation Delay vs Free-Air
Temperature
5
20 35 50 65 80
Free-Air Temperature (qC)
95
110 125
SLLS
Figure 6-22. tPHL2-1 Propagation Delay vs Free-Air
Temperature
8.1
9.5
ICC1, I2C = 100 kbps
ICC1, I2C = 400 kbps
ICC1, I2C = 1.7 Mbps
ICC2, I2C = 100 kbps
ICC2, I2C = 400 kbps
ICC2, I2C = 1.7 Mbps
7.5
ICC1, I2C = 100 kbps
ICC1, I2C = 400 kbps
ICC1, I2C = 1.7 Mbps
ICC2, I2C = 100 kbps
ICC2, I2C = 400 kbps
ICC2, I2C = 1.7 Mbps
9
Current Consumption (mA)
7.8
Current Consumption (mA)
130
7.2
6.9
6.6
6.3
8.5
8
7.5
7
6.5
6
6
0
5
10
15
20
25
30
35
GPIO Speed (Mbps)
40
45
50
D020
Figure 6-23. ISO1642: ICC vs GPIO Speed at 3.3V
0
5
10
15
20
25
30
35
GPIO Speed (Mbps)
40
45
50
D021
Figure 6-24. ISO1642: ICC vs GPIO Speed at 5V
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9
10.5
ICC1, I2C = 100 kbps
ICC1, I2C = 400 kbps
ICC1, I2C = 1.7 Mbps
ICC2, I2C = 100 kbps
ICC2, I2C = 400 kbps
ICC2, I2C = 1.7 Mbps
8
7.5
7
6.5
6
9
8.5
8
7.5
7
6.5
5.5
0
5
10
15
20
25
30
35
GPIO Speed (Mbps)
40
45
50
0
5
10
15
D022
Figure 6-25. ISO1643: ICC vs GPIO Speed at 3.3V
20
25
30
35
GPIO Speed (Mbps)
40
45
50
D023
Figure 6-26. ISO1643: ICC vs GPIO Speed at 5V
9.5
11
ICC1, I2C = 100 kbps
ICC1, I2C = 400 kbps
ICC1, I2C = 1.7 Mbps
ICC2, I2C = 100 kbps
ICC2, I2C = 400 kbps
ICC2, I2C = 1.7 Mbps
8.5
ICC1, I2C = 100 kbps
ICC1, I2C = 400 kbps
ICC1, I2C = 1.7 Mbps
ICC2, I2C = 100 kbps
ICC2, I2C = 400 kbps
ICC2, I2C = 1.7 Mbps
10.5
Current Consumption (mA)
9
Current Consumption (mA)
9.5
6
5.5
8
7.5
7
6.5
10
9.5
9
8.5
8
7.5
7
6.5
6
6
0
5
10
15
20
25
30
35
GPIO Speed (MHz)
40
45
50
D024
Figure 6-27. ISO1644: ICC vs GPIO Speed at 3.3V
26
ICC1, I2C = 100 kbps
ICC1, I2C = 400 kbps
ICC1, I2C = 1.7 Mbps
ICC2, I2C = 100 kbps
ICC2, I2C = 400 kbps
ICC2, I2C = 1.7 Mbps
10
Current Consumption (mA)
Current Consumption (mA)
8.5
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5
10
15
20
25
30
35
GPIO Speed (Mbps)
40
45
50
D025
Figure 6-28. ISO1644: ICC vs GPIO Speed at 5V
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7 Parameter Measurement Information
7.1 Parameter Measurement Information
VCC1
R1
±
+
±
+
R1
VCC2
R2
R2
SDA1
SDA2
ISO164x
SCL2
SCL1
C1
C1
C2
C2
Figure 7-1. Test Diagram
VCC2
VCC1
SDA1 or
SCL1
Output
R1
Isolation
VCC1
GND1
C1
tLOOP1
0.3 VCC1
SDA1
SCL1 (ISO1640 only)
0.4 V
GND1
Figure 7-2. tLoop1 Setup and Timing Diagram
VCCx
VCCy
2k
2k
Input
Isolation
+
Output
±
GNDx
GNDy
VCMTI
Figure 7-3. Common-Mode Transient Immunity Test Circuit
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VCCx
VCCy
VCCx
0V
Side x, Side y VCCx,VCCy
Ry
I solatio n
SDAx or
SCLx
Ry
1, 2
3.3 V, 3.3 V 95.3 Ω
2, 1
3.3 V, 3.3 V 953 Ω
+
Output
GNDy
GNDx
or
VCCx
VCCy
VCCy
Ry
SDAx or
SCLx
Isola tion
0V
+
Output
GNDx
GNDy
VCCx or
VCCy
VCCx (UVLO+)
t
UVLO
0 .9 V
Isolation Barrier
Output
IN
Input
Generator
(See Note A)
VI
50
VCCI
VI
OUT
50%
50%
0V
tPLH
VO
tPHL
CL
See Note B
VO
90%
50%
VOH
50%
10%
VOL
tf
tr
Copyright © 2016, Texas Instruments Incorporated
A.
28
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3ns, ZO =
50 Ω. At the input, 50 Ω resistor is required to terminate Input Generator signal. It is not needed in actual application.
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B.
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CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 7-4. GPIO Channel Switching Characteristics Test Circuit and Voltage Waveforms
VI See Note B
VCC
IN = 0 V (Devices without suffix F)
IN = VCC (Devices with suffix F)
IN
Isolation Barrier
VCC
VI
OUT
1.4 V
0V
VO
CL
See Note A
tDO
VO
default high
VOH
50%
VOL
default low
A.
B.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Power Supply Ramp Rate = 10 mV/ns
Figure 7-5. GPIO Channel Default Output Delay Time Test Circuit and Voltage Waveforms
Figure 7-4. tUVLO Test Circuit and Timing Diagrams
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8 Detailed Description
8.1 Overview
The I2C bus consists of a two-wire communication bus that supports bidirectional data transfer between a master
device and several slave devices. The master, or processor, controls the bus, specifically the serial clock (SCL)
line. Data is transferred between the master and slave through a serial data (SDA) line. This data can be
transferred in four speeds: standard mode (0 to 100 kbps), fast mode (0 to 400 kbps), fast-mode plus (0 to 1
Mbps), and high-speed mode (0 to 3.4 Mbps).
The I2C bus operates in bidirectional, half-duplex mode, using open collector outputs to allow for multiple
devices to share the bus. When a specific device is ready to communicate on the bus, it can take control pulling
the lines low accordingly in order to transmit data. A standard digital isolator or optocoupler is designed to
transfer data in a single direction. In order to support an I2C bus, external circuitry is required to separate the
bidirectional bus into two unidirectional signal paths. The ISO164x devices internally handle the separation and
partitioning of the transmit and receive signals, integrating the external circuitry needed and provide the opencollector signals. They provide high electromagnetic immunity and low emissions at low power consumption.
Each isolation channel has a logic input and output buffer separated by TI's double capacitive silicon dioxide
(SiO2) insulation barrier. When used in conjunction with isolated power supplies, these devices block high
voltages, isolate grounds, and prevent noise currents from entering the local ground and interfering with or
damaging sensitive circuitry.
8.2 Functional Block Diagrams
VCC1
VCC2
SDA2
VREF
Isolation Capacitor
SDA1
SCL1
SCL2
GND1
GND2
VREF
Figure 8-1. ISO1640 Block Diagram
30
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VCC2
SDA1
SDA2
VREF
Isolation Capacitor
VCC1
SCL1
SCL2
GND1
GND2
Figure 8-2. ISO1641 Block Diagram
8.3 Isolation Technology Overview
The ISO164x family of devices has an ON-OFF keying (OOK) modulation scheme to transmit the digital data
across a silicon dioxide based isolation barrier. The transmitter sends a high frequency carrier across the barrier
to represent one digital state and sends no signal to represent the other digital state. The receiver demodulates
the signal after advanced signal conditioning and produces the output through a buffer stage. These devices
also incorporate advanced circuit techniques to maximize the CMTI performance and minimize the radiated
emissions due the high frequency carrier and switching.
8.4 Feature Description
The device enables a complete isolated I2C interface to be implemented within a small form factor having the
features listed in Table 8-1.
Table 8-1. Features List
(1)
PART NUMBER
CHANNEL DIRECTION
RATED ISOLATION(1)
ISO1640
Bidirectional SCL
Bidirectional SDA
5000 VRMS (16DW) 7071
VPK (16DW) 3000 VRMS
(8D) 4242 VPK (8D)
ISO1641
Unidirectional (SCL)
Bidirectional (SDA)
5000 VRMS (16DW) 7071
VPK (16DW) 3000 VRMS
(8D) 4242 VPK (8D)
ISO1642
ISO1643
ISO1644
Bidirectional SCL
Bidirectional SDA
5000 VRMS (16DW) 7071
VPK (16DW)
I2C MAXIMUM
FREQUENCY
GPIO MAXIMUM
FREQUENCY
1.7 MHz
NA
1.7 MHz
50 Mbps
See for detailed Isolation specifications.
8.4.1 Hot Swap
The ISO164x includes Hot Swap circuitry on Side 2 of the isolator to prevent loading on the I2C bus lines while
VCC2 is either unpowered or in the process of being powered on. While VCC2 is below the UVLO threshold,
the ISO164x bus lines will not load the bus to avoid disrupting or corrupting an active I2C bus. If the isolator
is plugged into a live backplane using a staggered connector, where VCC2 and GND2 make connection first
followed by the bus lines, the SDA and SCL lines are pre-charged to VCC2 / 2 to minimize the current required
to charge the parasitic capacitance of the device. Once the device is fully powered on, the device bus pins
become active providing bidirectional, isolated, SCL and SDA lines.
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8.4.2 Protection Features
Features are integrated in the ISO164x to help protect the device from high current events. Enhanced ESD
protection cells are designed on the I2C bus pins to support 10 kV HBM ESD on side 1 and 14 kV HBM ESD on
side 2. The I2C bus pins on side 2 are designed to withstand an unpowered IEC-ESD strike of 8 kV, improving
robustness and system reliability in hot swap applications. In addition to the improved ESD performance, a short
circuit protection circuit is included on side 2 to protect the bus pins (SDA2 and SCL2) against strong short
circuits of 5 ohms or less to VCC2.
Thermal shutdown is integrated in the ISO164x to protect the device from high current events. If the junction
temperature of the device exceeds the thermal shutdown threshold of 190°C (typical), the device turns
off, disabling the I2C circuits and releasing the bus. The shutdown condition is cleared when the junction
temperature drops at least the thermal shutdown hysteresis temperature of 10°C (typical) below the thermal
shutdown temperature of the device.
8.4.3 GPIO Channels
The ISO1642, ISO1643 and ISO1644 intregrate unidirectional isolation channels, in addition to the bidirectional
isolated I2C lines, to support system signals. The ISO1642 includes two channels in opposing directions (1/1
configuration) and the ISO1643 include two channels in the same direction (2/0 configuration). The ISO1644
includes three GPIO channels, two in one direction and one in the opposite direction (2/1 configuration) making
it possible to use with a Serial Peripheral Interface (SPI). The conceptual block diagram of a unidirectional digital
capacitive isolator channel is shown in Figure 8-3.
Receiver
Transmitter
TX IN
OOK
Modulation
TX Signal
Conditioning
Oscillator
SiO2 based
Capacitive
Isolation
Barrier
RX Signal
Conditioning
Envelope
Detection
RX OUT
Emissions
Reduction
Techniques
Figure 8-3. Conceptual Block Diagram of the GPIO Channels
8.5 Isolator Functional Principle
To isolate a bidirectional signal path (SDA or SCL), the ISO1640 internally splits a bidirectional line into two
unidirectional signal lines, each of which is isolated through a single-channel digital isolator. Each channel output
is made open-drain to comply with the open-drain technology of I2C. Side 1 of the ISO1640 connects to a
low-capacitance I2C node (up to 80 pF), while side 2 is designed for connecting to a fully loaded I2C bus with up
to 400 pF of capacitance.
32
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VCC1
VCC2
A
RPU1
SDA1
VC-out
RPU2
B
SDA2
ISO164x
40 mV
Cnode
50 mV
Cbus
C
VSDA1
D
VILT1
VIHT1
VOL1
GND1
GND2
VREF
Figure 8-4. SDA Channel Design and Voltage Levels at SDA1
At first sight, the arrangement of the internal buffers suggests a closed signal loop that is prone to latch-up.
However, this loop is broken by implementing an output buffer (B) whose output low-level is raised by a diode
drop to approximately 0.65 V, and the input buffer (C) that consists of a comparator with defined hysteresis.
The comparator’s upper and lower input thresholds then distinguish between the proper low-potential of 0.4 V
(maximum) driven directly by SDA1 and the buffered output low-level of B.
Figure 8-5 demonstrate the switching behavior of the I2C isolator, ISO164x, between a master node at SDA1
and a heavy loaded bus at SDA2.
VCC2
VOL1
SDA1
50%
SDA2
VIHT1
30%
Receive
Delay
VCC1
SDA1
VCC1
VCC1
VCC2
Receive
Delay
Receive
Delay
Transmit
Delay
VCC1
SDA2
50%
VCC2
VCC2
Transmit
Delay
VIHT2
30%
VOL1
Figure 8-5. SDA Channel Timing in Receive and Transmit Directions
8.5.1 Receive Direction (Left Diagram of Figure 8-5)
When the I2C bus drives SDA2 low, SDA1 follows after a certain delay in the receive path. The output low is the
buffered output of VOL1 = 0.65 V, which is sufficiently low to be detected by Schmitt-trigger inputs with a minimum
input-low voltage of VIL = 0.9 V at 3 V supply levels.
When SDA2 is released, its voltage potential increases towards VCC2 following the time-constant formed
by RPU2 and Cbus. After the receive delay, SDA1 is released and also rises towards VCC1, following the
time-constant RPU1 × Cnode. Because of the significant lower time-constant, SDA1 may reach VCC1 before
SDA2 reaches VCC2 potential.
8.5.2 Transmit Direction (Right Diagram of Figure 8-5)
When a master drives SDA1 low, SDA2 follows after a certain delay in the transmit direction. When SDA2 turns
low it also causes the output of buffer B to turn low but at a higher 0.65 V level. This level cannot be observed
immediately as it is overwritten by the lower low-level of the master.
However, when the master releases SDA1, the voltage potential increases and first must pass the upper input
threshold of the comparator, VIHT1, to release SDA2. SDA1 then increases further until it reaches the buffered
output level of VOL1 = 0.65 V, maintained by the receive path. When comparator C turns high, SDA2 is released
after the delay in transmit direction. It takes another receive delay until B’s output turns high and fully releases
SDA1 to move toward VCC1 potential.
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8.6 Device Functional Modes
Table 8-2 lists the ISO164x functional modes.
Table 8-2. I2C Function Table(1)
POWER STATE
I2C INPUT
I2C OUTPUT
VCC1 < 2.3 V or VCC2 < 1.7 V
X
Z
VCC1 > 2.9 V and VCC2 > 2.25 V
L
L
VCC1 > 2.9 V and VCC2 > 2.25 V
H
Z
VCC1 > 2.9 V and VCC2 > 2.25 V
Z(2)
Undetermined
(1)
(2)
H = High Level; L = Low Level; Z = High Impedance or Float; X = Irrelevant
Invalid input condition as an I2C system requires that a pullup resistor to VCC is connected.
Table 8-3. GPIO Function Table (ISO1642, ISO1643 and ISO1644 only)(1)
VCCI
PU
(1)
(2)
34
VCCO
PU
GPIO INPUT
(INx)
GPIO OUTPUT
(OUTx)
H
H
L
L
Open
L
Default mode: When INx is open, the corresponding channel output goes to
the default low logic state.
Default mode: When VCCI is unpowered, a channel output assumes the low
default logic state.
When VCCI transitions from unpowered to powered-up, a channel output
assumes the logic state of the input.
When VCCI transitions from powered-up to unpowered, channel output
assumes the low default state.
PD
PU
X
L
X
PD
X
Undetermined(2)
COMMENTS
Normal Operation:
A channel output assumes the logic state of the input.
When VCCO is unpowered, a channel output is undetermined.
When VCCO transitions from unpowered to powered-up, a channel output
assumes the logic state of the input
VCCI = Input-side VCC; VCCO = Output-side VCC; PU = Powered up (VCC1 ≥ 2.9 V or VCC2 ≥ 2.25 V); PD = Powered down (VCC1 ≤ 2.3 V
or VCC2 ≤ 1.7 V); X = Irrelevant; H = High level; L = Low level
A strongly driven input signal can weakly power the floating VCC via an internal protection diode and cause undetermined output.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
9.1.1 I2C Bus Overview
The inter-integrated circuit (I2C) bus is a single-ended, multi-master, 2-wire bus for efficient inter-IC
communication in half-duplex mode.
I2C uses open-drain technology, requiring two lines, serial data (SDA) and serial clock (SCL), to be connected
to VDD by resistors (see Figure 9-1). Pulling the line to ground is considered a logic zero while letting the line
float is a logic one. This logic is used as a channel access method. Transitions of logic states must occur while
the SCL pin is low. Transitions while the SCL pin is high indicate START and STOP conditions. Typical supply
voltages are 3.3 V and 5 V, although systems with higher or lower voltages are allowed.
VDD
RPU
RPU
RPU
RPU
RPU
RPU
RPU
RPU
SDA
SCL
SDA
SCL
SDA
GND
SCL
GND
C
Master
ADC
Slave
SDA
SCL
GND
DAC
Slave
SDA
SCL
GND
C
Slave
Figure 9-1. Example I2C Bus
I2C communication uses a 7-bit address space with 16 reserved addresses, so a theoretical maximum of 112
nodes can communicate on the same bus. In practice, however, the number of nodes is limited by the specified,
total bus capacitance of 400 pF, which also restricts communication distances to a few meters.
The specified signaling rates for the ISO164x devices are 100 kbps (standard mode), 400 kbps (fast mode), 1.7
Mbps (fast mode plus).
The bus has two roles for nodes: master and slave. A master node issues the clock and slave addresses,
and also initiates and ends data transactions. A slave node receives the clock and addresses and responds to
requests from the master. Figure 9-2 shows a typical data transfer between master and slave.
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7-bit
ADDRESS
SDA
SCL
1 -7
R/W
ACK
8
9
8-bit
DATA
8-bit
DATA
ACK
1 -8
9
ACK /
NACK
1 -8
9
S
P
START
Condition
STOP
condition
Figure 9-2. Timing Diagram of a Complete Data Transfer
The master initiates a transaction by creating a START condition, following by the 7-bit address of the slave
it wishes to communicate with. This is followed by a single read and write (R/W) bit, representing whether the
master wishes to write to (0), or to read from (1) the slave. The master then releases the SDA line to allow the
slave to acknowledge the receipt of data.
The slave responds with an acknowledge bit (ACK) by pulling the SDA pin low during the entire high time of the
9th clock pulse on the SCL signal, after which the master continues in either transmit or receive mode (according
to the R/W bit sent), while the slave continues in the complementary mode (receive or transmit, respectively).
The address and the 8-bit data bytes are sent most significant bit (MSB) first. The START bit is indicated by
a high-to-low transition of SDA while SCL is high. The STOP condition is created by a low-to-high transition of
SDA while SCL is high.
If the master writes to a slave, it repeatedly sends a byte with the slave sending an ACK bit. In this case, the
master is in master-transmit mode and the slave is in slave-receive mode.
If the master reads from a slave, it repeatedly receives a byte from the slave, while acknowledging (ACK) the
receipt of every byte but the last one (see Figure 9-3). In this situation, the master is in master-receive mode and
the slave is in slave-transmit mode.
The master ends the transmission with a STOP bit, or may send another START bit to maintain bus control for
further transfers.
S Slave Address W A
From Master to Slave
DATA
A
DATA
A P
A = acknowledge
A = not acknowledge
Master Transmitter writing to Slave Receiver
S = Start
From Slave to Master
P = Stop
S Slave Address R A
DATA
A
DATA
A P
Master Receiver reading from Slave Transmitter
R = Read
W = Write
Figure 9-3. Transmit or Receive Mode Changes During a Data Transfer
When writing to a slave, a master mainly operates in transmit-mode and only changes to receive-mode when
receiving acknowledgment from the slave.
When reading from a slave, the master starts in transmit-mode and then changes to receive-mode after sending
a READ request (R/W bit = 1) to the slave. The slave continues in the complementary mode until the end of a
transaction.
Note
The master ends a reading sequence by not acknowledging (NACK) the last byte received. This
procedure resets the slave state machine and allows the master to send the STOP command.
9.2 Typical Application
In Figure 9-4, the ultra low-power microcontroller, MSP430G2132, controls the I2C data traffic of configuration
data and conversion results for the analog inputs and outputs. In Figure 9-5, the TMS320F28035 controls both
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the I2C interface, for communication to a DAC for analog outputs, and a SPI interface, for communication to an
ADC for analog inputs.
Low-power data converters build the analog interface to sensors and actuators. The ISO164x device provides
the required isolation between different ground potentials of the system controller, remote sensor, and actuator
circuitry to prevent ground loop currents that otherwise may falsify the acquired data.
The entire circuit operates from a single 3.3-V supply. A low-power push-pull converter, SN6501, drives a
center-tapped transformer with an output that is rectified and linearly regulated to provide a stable 5-V supply for
the data converters.
VS
3.3V
0.1 μF
2
Vcc
D2
1:2.2
3
MBR0520L
1
SN6501
GND D1
10 μF 0.1 μF
OUT
5
ON
GND
5VISO
0.1 μF
8
10 μF
LP2981-50
3
1
4,5
IN
9
2
10
1Ω
10 μF
1
MBR0520L
VDD
SDA
AIN0
4
4 Analog
Inputs
SCL ADS 1115
ADDR
AIN3
GND RDY
3
7
2
SCL
5VISO
SDA
5VISO
ISO- BARRIER
5VISO
0.1 μF
6
22 μF
VOUT
VIN 2
1 μF
REF5040
4
GND
0.1 μF
0.1 μF
1.5 kΩ
1.5 kΩ
2
5
6
1
VCC1
DVcc
XOUT
XIN
MSP430
SDA
G2132
SCL
9
8
DVss
2
8
VCC2
7
SDA2
ISO164x
3
6
SCL1
SCL2
SDA1
GND1
4
4
0.1 μF
1.5 kΩ
GND2
5
1.5 kΩ
3
15 4 12
A2 VDD IOVDD VREFH
1
SDA
VOUTA
10
SCL
DAC8574
9
LDAC
14
VOUTD
A1
8
A0 A3 GND VREFL
11
13 16
6
4 Analog
Outputs
5
Figure 9-4. Isolated I2C Data Acquisition System
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VS
0.1 F
3.3 V
Vcc
1:2.2
MBR0520L
5V IS O
D2
IN
OUT
TPS76750
SN6501
10 F
0.1 F
10 F
EN
GND
D1
10 F
GND
GND
MBR05 20L
ISO Barrier
5V IS O
5V IS O
VOUT
VIN
22 F
1.5 k
REF5040
1.5 k
0.1 F
1.5 k
0.1 F
1
VDD
SDA
SCL
X2
3
5V IS O
1 F
GND
0.1 F
8
VCC1
VCC2
SDA1
SDA2
SCL1
SCL2
2
X1
1.5 k
7
6
TMS32 0F2803 5
A2 IOVDD VDD VREFH
SDA
VOUT A
SCL
4 Analo g
Outputs
DAC8574
LDAC
SCLK
INA
ISO1644 OUTA
DOUT
INB
OUTB
DIN
OUTC
INC
GND1
GND2
VSS
VOUT D
A1
A0 A3 GND VREFL
5V IS O
0.1 F
DVDD
AVDD
AIN0
SCLK
DIN
4 Analo g
Inputs
ADS1220
DOUT
AIN4
/CS
DGND AVSS
Figure 9-5. Isolated I2C and SPI Data Acquisition System
9.2.1 Design Requirements
The recommended power supply voltages must be from 3 V to 5.5 V for VCC1 and 2.25 V to 5.5 V for VCC2. A
recommended decoupling capacitor with a value of 0.1 µF is required between both the VCC1 and GND1 pins,
and the VCC2 and GND2 pins to support of power supply voltage transients and to ensure reliable operation at
all data rates.
9.2.2 Detailed Design Procedure
Although the ISO1640 features bidirectional data channels, the device performs optimally when side 1 (SDA1
and SCL1) is connected to a single controller or node of an I2C network while side 2 (SDA2 and SCL2) is
connected to the I2C bus. The maximum load permissible on the input lines, SDA1 and SCL1, is ≤ 80 pF and
on the output lines, SDA2 and SCL2, is ≤ 400 pF. In addition to the bidirectional data and clock channels for the
I2C network, the ISO1644 includes 3 GPIOs which can be used for static I/O lines or for a 3 wire SPI interface.
These lines are designed to support up to 50 Mbps data transfer rate.
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The power-supply capacitor with a value of 0.1-µF must be placed as close to the power supply pins as possible.
The recommended placement of the capacitors must be 2-mm maximum from input and output power supply
pins (VCC1 and VCC2).
The minimum pullup resistors on the input lines, SDA1 and SCL1 to VCC1 must be selected in such a way that
input current drawn is ≤ 3.5 mA. The minimum pullup resistors on the input lines, SDA2 and SCL2, to VCC2
must be selected in such a way that output current drawn is ≤ 50 mA. The maximum pullup resistors on the
bus lines (SDA1 and SCL1) to VCC1 and on bus lines (SDA2 and SCL2) to VCC2, depends on the load and
rise time requirements on the respective lines to comply with I2C protocols. For more information, see I2C Bus
Pullup Resistor Calculation.
The output waveforms for SDA1 and SCL1 are captured on the oscilloscope focusing on the low VOL1 voltage
offset offered with the ISO164x. This voltage offset is due to the output low level on side 1 designed to prevent a
latch-up state mentioned in Section 8.5.
ISO164 0
2 mm
maximu m
2 mm
maximu m
VCC1
VCC2
8
1
3.3 k
0.01 …F
0.01 …F
Isol atio n Capa citor
3.3 k
SDA1
2
SCL1
3
3.3 k
SDA2
7
SCL2
6
GND1
4
GND2
5
Side 1
3.3 k
Side 2
Figure 9-6. Typical ISO1640 Circuit Hookup
ISO164 1
2 mm
maximu m
2 mm
maximu m
VCC1
VCC2
8
1
3.3 k
0.01 …F
0.01 …F
Isol atio n Capa citor
3.3 k
SDA1
2
SCL1
3
3.3 k
SDA2
7
SCL2
6
GND1
4
5
Side 1
3.3 k
GND2
Side 2
Figure 9-7. Typical ISO1641 Circuit Hookup
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9.2.3 Application Curve
VOL1 = 650 mV
GND
Figure 9-8. Side 1 ISO1640: Low-to-High Transition
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Figure 9-9. Side 1 ISO1644: Low-to-High Transition With Toggling GPIO lines
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9.3 Insulation Lifetime
Insulation lifetime projection data is collected by using the industry-standard Time Dependent Dielectric
Breakdown (TDDB) test method. In this test, all pins on each side of the barrier are tied together creating a
two-terminal device and high voltage is applied between the two sides; see Figure 9-10 for TDDB test setup. The
insulation breakdown data is collected at various high voltages switching at 60 Hz over temperature. For basic
insulation, VDE standard requires the use of a TDDB projection line with failure rate of less than 1000 part per
million (ppm). For reinforced insulation, VDE standard requires the use of a TDDB projection line with failure rate
of less than 1 part per million (ppm).
Even though the expected minimum insulation lifetime is 20 years, at the specified working isolation voltage,
VDE basic and reinforced certifications require additional safety margin of 20% for working voltage. For basic
certification, device lifetime requires a safety margin of 30% translating to a minimum required insulation lifetime
of 26 years at a working voltage that is 20% higher than the specified value. For reinforced insulation, device
lifetime requires a safety margin of 87.5% translating to a minimum required insulation lifetime of 37.5 years at a
working voltage that is 20% higher than the specified value.
Insulation Lifetime Projection Data for ISO164x in 8-D Package and Insulation Lifetime Projection Data for
ISO164x in 16-DW Package show the intrinsic capability of the isolation barrier to withstand high voltage stress
over its lifetime. Based on the TDDB data, the intrinsic capability of the insulation is 450 VRMS with a lifetime
in excess of 100 years in the 8-D package and 1500 VRMS with a lifetime in excess of 135 years in the 16-DW
package. Other factors, such as package size, pollution degree, material group, etc. can further limit the working
voltage of the component. At the lower working voltages, the corresponding insulation lifetime is much longer
than 100 years in the 8-D package and 135 years in the 16-DW package.
A
Vcc 1
Vcc 2
Time Counter
> 1 mA
DUT
GND 1
GND 2
VS
Oven at 150 °C
Figure 9-10. Test Setup for Insulation Lifetime Measurement
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1.E+11
>>100Yrs
1.E+10
1.E+09
Operating Zone
1.E+08
Time to Fail (sec)
TDDB Line (< 1000 ppm Fail Rate)
1.E+07
1.E+06
1.E+05
VDE Safety Margin Zone
1.E+04
1.E+03
20%
1.E+02
1.E+01
0
1000
2000
3000
4000
5000
6000
7000
8000
Applied Voltage (VRMS)
TA upto 150 oC
Operating Life Time = >>100 Years
Stress Voltage Frequency = 60 Hz
Isolation Working Voltage = 450 VRMS
Figure 9-11. Insulation Lifetime Projection Data for ISO164x in 8-D Package
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Figure 9-12. Insulation Lifetime Projection Data for ISO164x in 16-DW Package
10 Power Supply Recommendations
To help ensure reliable operation at data rates and supply voltages, TI recommends connecting a 0.1-µF bypass
capacitor at the input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the
supply pins as possible. If only a single, primary-side power supply is available in an application, isolated power
can be generated for the secondary-side with the help of a transformer driver such as TI's SN6501 device. For
such applications, detailed power supply design and transformer selection recommendations are available in
SN6501 Transformer Driver for Isolated Power Supplies. (SLLSEA0).
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11 Layout
11.1 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 11-1). Layer stacking
should be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and lowfrequency signal layer.
•
•
•
•
Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/in2.
Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system
to the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping.
Also the power and ground plane of each power system can be placed closer together, thus increasing the
high-frequency bypass capacitance significantly.
For detailed layout recommendations, see the Digital Isolator Design Guide (SLLA284)
11.1.1 PCB Material
For digital circuit boards operating at less than 150 Mbps, (or rise and fall times greater than 1 ns), and trace
lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper
alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater strength
and stiffness, and the self-extinguishing flammability-characteristics.
11.2 Layout Example
High-speed traces
10 mils
Ground plane
40 mils
Keep this
space free
from planes,
traces, pads,
and vias
FR-4
0r ~ 4.5
Power plane
10 mils
Low-speed traces
Figure 11-1. Recommended Layer Stack
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, How Do Isolated I2C Buffers with Hot-Swap Capability and IEC ESD Improve Isolated
I2C?
• Texas Instruments, Digital Isolator Design Guide
• Texas Instruments, How to use isolation to improve ESD, EFT and Surge immunity in industrial systems
application report
• Texas Instruments, Isolation Glossary
• Texas Instruments, What is EMC? 4 questions about EMI, radiated emissions, ESD and EFT in isolated
systems
• Texas Instruments, SN6501 Transformer Driver for Isolated Power Supplies data sheet
• Texas Instruments, SN6505x Transformer Driver for Isolated Power Supplies data sheet
• Texas Instruments, I2C Bus Pullup Resistor Calculation
• Texas Instruments, ISO1640DEVM Evaluation Module Users Guide
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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20-Jan-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
ISO1640BDR
ACTIVE
SOIC
D
8
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
1640B
ISO1640DWR
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO1640
ISO1641BDR
ACTIVE
SOIC
D
8
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
1641B
ISO1641DWR
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO1641
ISO1642DWR
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO1642
ISO1643DWR
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO1643
ISO1644DWR
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO1644
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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