ISO6740-Q1, ISO6741-Q1, ISO6742-Q1
ISO6740-Q1,
ISO6741-Q1,
ISO6742-Q1
SLLSFG4B
– AUGUST 2020
– REVISED FEBRUARY
2021
SLLSFG4B – AUGUST 2020 – REVISED FEBRUARY 2021
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ISO674x-Q1 General-Purpose Reinforced Quad-Channel Automotive Digital Isolators
with Robust EMC
1 Features
3 Description
•
The ISO674x-Q1 devices are high-performance,
quad-channel digital isolators ideal for cost-sensitive
applications requiring up to 5000 VRMS isolation
ratings per UL 1577. These devices are also certified
by VDE, TUV, CSA, and CQC.
•
•
•
•
•
•
•
•
•
•
•
AEC-Q100 qualified with the following results:
– Device temperature Grade 1: –40°C to +125°C
ambient operating temperature range
Meets VDA320 isolation requirements
50 Mbps data rate
Robust isolation barrier:
– High lifetime at 1060 VRMS working voltage
– Up to 5000 VRMS isolation rating
– Up to 10 kV surge capability
– ±75 kV/μs typical CMTI
Wide supply range: 1.71 V to 1.89 V and 2.25 V to
5.5 V
1.71 V to 5.5 V level translation
Default output high (ISO674x-Q1) and low
(ISO674xF-Q1) options
1.6 mA per channel typical at 1 Mbps
Low propagation delay: 11 ns typical
Robust electromagnetic compatibility (EMC)
– System-level ESD, EFT, and surge immunity
– ±8 kV IEC 61000-4-2 contact discharge
protection across isolation barrier
– Low emissions
Wide-SOIC (DW-16) Package
Safety-Related Certifications (pending):
– DIN V VDE 0884-11:2017-01
– UL 1577 component recognition program
– IEC 60950-1, IEC 62368-1, IEC 61010-1,
IEC60601-1 and GB 4943.1-2011 certifications
2 Applications
•
Hybrid, electric and power train system (EV/HEV)
– Battery management system (BMS)
– On-board charger
– DC/DC converter
– Inverter and motor control
The
ISO674x-Q1
devices
provide
high
electromagnetic immunity and low emissions at low
power consumption, while isolating CMOS or
LVCMOS digital I/Os. Each isolation channel has a
logic input and output buffer separated by TI's double
capacitive silicon dioxide (SiO2) insulation barrier.
These devices come with enable pins which can be
used to put the respective outputs in high impedance
for multi-master driving applications. The ISO6740-Q1
device has all four channels in the same direction, the
ISO6741-Q1 device has three forward and one
reverse-direction channels, and the ISO6742-Q1
device has two forward and two reverse-direction
channels. In the event of input power or signal loss,
the default output is high for devices without suffix F
and low for devices with suffix F. See Device
Functional Modes section for further details.
Used in conjunction with isolated power supplies,
these devices help prevent noise currents on data
buses, such as CAN and LIN from damaging sensitive
circuitry. Through innovative chip design and layout
techniques, the electromagnetic compatibility of the
ISO674x-Q1 devices has been significantly enhanced
to ease system-level ESD, EFT, surge, and emissions
compliance. The ISO674x-Q1 family of devices is
available in a 16-pin SOIC wide-body (DW) package
and is a pin-to-pin upgrade to the older generations.
Device Information
PART NUMBER(1)
PACKAGE
ISO6740-Q1, ISO6740F-Q1
ISO6741-Q1, ISO6741F-Q1
ISO6742-Q1, ISO6742F-Q1
(1)
SOIC (DW)
BODY SIZE (NOM)
10.30 mm × 7.50 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
VCCO
VCCI
Series Isolation
Capacitors
INx
OUTx
ENx
GNDI
GNDO
Copyright © 2016, Texas Instruments Incorporated
VCCI=Input supply, VCCO=Output supply
GNDI=Input ground, GNDO=Output ground
Simplified Schematic
An©IMPORTANT
NOTICEIncorporated
at the end of this data sheet addresses availability, warranty, changes, use in
safety-critical
applications,
Copyright
2021 Texas Instruments
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intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings ....................................... 5
6.2 ESD Ratings .............................................................. 5
6.3 Recommended Operating Conditions ........................6
6.4 Thermal Information ...................................................7
6.5 Power Ratings ............................................................7
6.6 Insulation Specifications ............................................ 8
6.7 Safety-Related Certifications ..................................... 9
6.8 Safety Limiting Values ................................................9
6.9 Electrical Characteristics—5-V Supply .................... 10
6.10 Supply Current Characteristics—5-V Supply ......... 11
6.11 Electrical Characteristics—3.3-V Supply ................12
6.12 Supply Current Characteristics—3.3-V Supply ...... 13
6.13 Electrical Characteristics—2.5-V Supply .............. 14
6.14 Supply Current Characteristics—2.5-V Supply ...... 15
6.15 Electrical Characteristics—1.8-V Supply ............... 16
6.16 Supply Current Characteristics—1.8-V Supply ...... 17
6.17 Switching Characteristics—5-V Supply ..................18
6.18 Switching Characteristics—3.3-V Supply ...............19
6.19 Switching Characteristics—2.5-V Supply ...............20
6.20 Switching Characteristics—1.8-V Supply ...............21
6.21 Insulation Characteristics Curves........................... 22
6.22 Typical Characteristics............................................ 23
7 Parameter Measurement Information.......................... 24
8 Detailed Description......................................................26
8.1 Overview................................................................... 26
8.2 Functional Block Diagram......................................... 26
8.3 Feature Description...................................................27
8.4 Device Functional Modes..........................................28
9 Application and Implementation.................................. 29
9.1 Application Information............................................. 29
9.2 Typical Application.................................................... 29
10 Power Supply Recommendations..............................33
11 Layout........................................................................... 34
11.1 Layout Guidelines................................................... 34
11.2 Layout Example...................................................... 35
12 Device and Documentation Support..........................36
12.1 Documentation Support.......................................... 36
12.2 Receiving Notification of Documentation Updates..36
12.3 Support Resources................................................. 36
12.4 Trademarks............................................................. 36
12.5 Electrostatic Discharge Caution..............................36
12.6 Glossary..................................................................36
13 Mechanical, Packaging, and Orderable
Information.................................................................... 36
13.1 Package Option Addendum.................................... 37
13.2 Tape and Reel Information......................................38
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (January 2021) to Revision B (February 2021)
Page
• Updated device status to Production Data......................................................................................................... 1
Changes from Revision * (August 2020) to Revision A (January 2021)
Page
• Added ISO674x-Q1 to APL data sheet. .............................................................................................................1
2
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5 Pin Configuration and Functions
1
16
VCC2
GND1
2
15
GND2
INA
3
14
OUTA
INB
4
13
OUTB
INC
5
12
OUTC
IND
6
11
OUTD
NC
7
10
EN2
GND1
8
9
ISOLATION
VCC1
GND2
Not to scale
Figure 5-1. ISO6740-Q1 DW Package 16-Pin SOIC-WB Top View
1
16
VCC2
GND1
2
15
GND2
INA
3
14
OUTA
INB
4
13
OUTB
INC
5
12
OUTC
OUTD
6
11
IND
EN1
7
10
EN2
GND1
8
9
ISOLATION
VCC1
GND2
Not to scale
Figure 5-2. ISO6741-Q1 DW Package 16-Pin SOIC-WB Top View
1
16
VCC2
GND1
2
15
GND2
INA
3
14
OUTA
INB
4
13
OUTB
OUTC
5
12
INC
OUTD
6
11
IND
EN1
7
10
EN2
GND1
8
9
ISOLATION
VCC1
GND2
Not to scale
Figure 5-3. ISO6742-Q1 DW Package 16-Pin SOIC-WB Top View
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Pin Functions
PIN
NAME
4
I/O
DESCRIPTION
7
I
Output enable 1. Output pins on side 1 are enabled when EN1
is high or open and in high-impedance state when EN1 is low.
For ISO6740, this pin needs to be floating.
10
I
Output enable 2. Output pins on side 2 are enabled when EN2
is high or open and in high-impedance state when EN2 is low.
ISO6740-Q1
ISO6741-Q1
ISO6742-Q1
EN1
-
7
EN2
10
10
GND1
2, 8
2,8
2,8
—
Ground connection for VCC1
GND2
9, 15
9,15
9,15
—
Ground connection for VCC2
INA
3
3
3
I
Input, channel A
INB
4
4
4
I
Input, channel B
INC
5
5
12
I
Input, channel C
IND
6
11
11
I
Input, channel D
NC
7
-
-
OUTA
14
14
14
OUTB
13
13
13
O
Output, channel B
OUTC
12
12
5
O
Output, channel C
OUTD
11
6
6
O
Output, channel D
VCC1
1
1
1
—
Power supply, side 1
VCC2
16
16
16
—
Power supply, side 2
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Not connected
O
Output, channel A
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6 Specifications
6.1 Absolute Maximum Ratings
See(1)
Supply voltage
(2)
MIN
MAX
UNIT
VCC1, VCC2
-0.5
6
V
Voltage at INx,
OUTx, ENx
V
-0.5
VCCX + 0.5 (3)
V
Output current
Io
-15
15
mA
150
°C
-65
150
°C
Temperature
(1)
(2)
(3)
Operating junction temperature, TJ
Storage temperature, Tstg
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak
voltage values
Maximum voltage must not exceed 6 V.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
(3)
(4)
Electrostatic discharge
Human body model (HBM), per ANSI/
ESDA/JEDEC JS-001, all pins(1)
±6000
Charged device model (CDM), per
JEDEC specification JESD22-C101, all
pins(2)
±1500
Contact discharge per IEC 61000-4-2;
Isolation barrier withstand test(3) (4)
±8000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
IEC ESD strike is applied across the barrier with all pins on each side tied together creating a two-terminal device.
Testing is carried out in air or oil to determine the intrinsic contact discharge capability of the device.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
1.89
V
2.25
5.5
V
1.71
1.89
V
2.25
5.5
V
1.71
V
VCC1 (1)
Supply Voltage Side 1
VCC = 1.8 V
1.71
(1)
Supply Voltage Side 1
VCC = 2.5 V to 5 V
VCC2 (1)
Supply Voltage Side 2
VCC = 1.8 V
(1)
Supply Voltage Side 2
VCC = 2.5 V to 5 V
VCC1
VCC2
NOM
Vcc (UVLO
UVLO threshold when supply voltage is rising
+)
Vcc
(UVLO-)
UVLO threshold when supply voltage is falling
Vhys
(UVLO)
Supply voltage UVLO hysteresis
VIH
High level Input voltage
VIL
Low level Input voltage
IOH
High level output current
IOL
Low level output current
DR
Data Rate
TA
Ambient temperature
1.53
1.1
1.41
V
0.08
0.13
V
0.7 x VCCI
(2)
VCCI
0
0.3 x VCCI
6
V
VCCO = 5 V (2)
-4
mA
VCCO = 3.3 V
-2
mA
VCCO = 2.5 V
-1
mA
VCCO = 1.8 V
-1
mA
VCCO = 5 V
4
mA
VCCO = 3.3 V
2
mA
VCCO = 2.5 V
1
mA
VCCO = 1.8 V
(1)
(2)
V
0
-40
25
1
mA
50
Mbps
125
°C
VCC1 and VCC2 can be set independent of one another
VCCI = Input-side VCC; VCCO = Output-side VCC
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6.4 Thermal Information
ISO674x
THERMAL
METRIC(1)
UNIT
DW (SOIC)
16 PINS
RθJA
Junction-to-ambient thermal resistance
73
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
36.1
°C/W
RθJB
Junction-to-board thermal resistance
40.4
°C/W
ψJT
Junction-to-top characterization parameter
17
°C/W
ψJB
Junction-to-board characterization parameter
39.9
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Power Ratings
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
130.9
mW
ISO6740
PD
Maximum power dissipation (both sides)
PD1
Maximum power dissipation (side-1)
PD2
Maximum power dissipation (side-2)
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15
pF, Input a 25-MHz 50% duty cycle
square wave
33
mW
97.9
mW
134.9
mW
ISO6741
PD
Maximum power dissipation (both sides)
PD1
Maximum power dissipation (side-1)
PD2
Maximum power dissipation (side-2)
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15
pF, Input a 25-MHz 50% duty cycle
square wave
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50.8
mW
84.1
mW
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6.6 Insulation Specifications
PARAMETER
VALUE
TEST CONDITIONS
DW-16
UNIT
CLR
External clearance(1)
Shortest terminal-to-terminal distance through air
>8
mm
CPG
External creepage(1)
Shortest terminal-to-terminal distance across the
package surface
>8
mm
DTI
Distance through the insulation
Minimum internal gap (internal clearance)
>17
um
Comparative tracking index
DIN EN 60112 (VDE 0303-11); IEC 60112
>600
V
Material group
According to IEC 60664-1
I
CTI
Overvoltage category per IEC 60664-1
Rated mains voltage ≤ 600 VRMS
I-IV
Rated mains voltage ≤ 1000 VRMS
I-III
DIN VDE V 0884-11:2017-01 (2)
VIORM
Maximum repetitive peak isolation voltage
AC voltage (bipolar)
1500
VPK
VIOWM
Maximum working isolation voltage
AC voltage; Time dependent dielectric breakdown
(TDDB) Test; See Figure 9-8
1060
VRMS
DC voltage
1500
VDC
7071
VPK
VPK
VIOTM
Maximum transient isolation voltage
VTEST = VIOTM,
t = 60 s (qualification);
VTEST = 1.2 x VIOTM,
t= 1 s (100% production)
VIOSM
Maximum surge isolation voltage(3)
Test method per IEC 62368-1, 1.2/50 µs waveform,
VTEST = 1.6 x VIOSM (qualification)
6250
Method a, After Input-output safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.2 x VIORM, tm = 10 s
≤5
Method a, After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.6 x VIORM, tm = 10 s
≤5
Method b; At routine test (100% production) and
preconditioning (type test)
Vini = 1.2 x VIOTM, tini = 1 s;
Vpd(m) = 1.875 x VIORM, tm = 1 s
≤5
VIO = 0.4 x sin (2πft), f = 1 MHz
~1
VIO = 500 V, TA = 25°C
>1012
VIO = 500 V, 100°C ≤ TA ≤ 125°C
>1011
VIO = 500 V at TS = 150°C
>109
qpd
Apparent
charge(4)
Barrier capacitance, input to output(5)
CIO
Isolation resistance(5)
RIO
Pollution degree
2
Climatic category
40/125/21
pC
pF
Ω
UL 1577
VISO
(1)
(2)
(3)
(4)
(5)
8
Maximum withstanding isolation voltage
VTEST = VISO , t = 60 s (qualification),
VTEST = 1.2 x VISO , t = 1 s (100% production)
5000
VRMS
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application.
Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the
isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in
certain cases. Techniques such as inserting grooves and/or ribs on a printed-circuit board are used to help increase these
specifications.
This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured
by means of suitable protective circuits.
Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
Apparent charge is electrical discharge caused by a partial discharge (pd).
All pins on each side of the barrier tied together creating a two-terminal device.
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6.7 Safety-Related Certifications
VDE
CSA
UL
CQC
TUV
Plan to certify according to
Plan to certify according to Plan to certify according to Plan to certify according to
EN 61010-1:2010/
Plan to certify according to
DIN VDE V 0884-11:2017- IEC 60950-1 and IEC
UL 1577 Component
A1:2019, EN
GB4943.1-2011
60950-1:2006/A2:2013
01
62368-1
Recognition Program
and EN 62368-1:2014
Maximum transient
isolation voltage,
7071 VPK;
Maximum repetitive peak
isolation voltage, 1500
VPK;
Maximum surge isolation
voltage,
6250 VPK
Certificate planned
5000 VRMS insulation per
CSA 60950-1-07+A1+A2,
IEC 60950-1 2nd
Ed.+A1+A2, CSA
62368-1- 14 and IEC
Single protection,
62368-1:2014 800 VRMS
5000 VRMS
(DW-16) maximum
working voltage (pollution
degree 2, material group I)
5000 VRMS insulation per
EN 61010-1:2010 (3rd Ed)
Reinforced insulation,
up to working voltage of
Altitude ≤ 5000 m, Tropical
600 VRMS
Climate,
5000 VRMS insulation per
700 VRMS maximum
EN 60950- 1:2006/
working voltage
A2:2013 up to working
voltage of 800 VRMS
Certificate planned
Certificate planned
File number: E181974
Certificate planned
6.8 Safety Limiting Values
Safety limiting(1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RθJA =73°C/W, VI = 5.5 V, TJ = 150°C, TA
= 25°C
311.4
mA
RθJA = 73°C/W, VI = 3.6 V, TJ = 150°C, TA
= 25°C
475.7
DW-16 PACKAGE
IS
Safety input, output, or supply current
PS
Safety input, output, or total power
TS
Maximum safety temperature
(1)
mA
RθJA = 73°C/W, VI = 2.75 V, TJ = 150°C,
TA = 25°C
622
RθJA = 73°C/W, VI = 1.89 V, TJ = 150°C,
TA = 25°C
905.1
mA
1712.4
mW
RθJA = 73°C/W, TJ = 150°C, TA = 25°C
150
°C
The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS
and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be
exceeded. These limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the table is that of a device installed on a high-K test board for leaded surface-mount
packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum allowed junction temperature.
PS = IS × VI, where VI is the maximum input voltage.
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6.9 Electrical Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
VCCO - 0.4 (1)
UNIT
VOH
High-level output voltage
IOH = -4 mA; See Figure 7-1
VOL
Low-level output voltage
IOL = 4 mA; See Figure 7-1
VIT+(IN)
Rising input switching threshold
VIT-(IN)
Falling input switching threshold
0.3 x VCCI
V
VI(HYS)
Input threshold voltage hysteresis
0.1 x VCCI
V
(1)
IIH
High-level input current
VIH = VCCI
IIL
Low-level input current
VIL = 0 V at INx
(1)
at INx
IIH
High-level input current
VIH = VCCI
IIL
Low-level input current
VIL = 0 V at ENx
CMTI
Common mode transient immunity
VI = VCC or 0 V, VCM = 1200 V;
See Figure 7-4
Ci
Input Capacitance (2)
VI = VCC/ 2 + 0.4×sin(2πft), f = 2
MHz, VCC = 5 V
(1)
(2)
10
V
0.4
V
0.7 x VCCI (1)
V
10
-10
µA
at ENx
28
-28
50
µA
uA
uA
75
kV/us
2.8
pF
VCCI = Input-side VCC; VCCO = Output-side VCC
Measured from input pin to same side ground.
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6.10 Supply Current Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
SUPPLY
CURRENT
MIN
TYP
MAX
ICC1
1.6
2.2
ICC2
2.1
3.4
ICC1
5.8
8
UNIT
ISO6740
Supply current - DC signal
VI = VCC1 (1)(ISO6740); VI = 0 V (ISO6740 with F
suffix)
(2)
VI = 0 V (ISO6740); VI = VCC1 (ISO6740 with F suffix)
1 Mbps
Supply current - AC signal
(3)
All channels switching with square
wave clock input; CL = 15 pF
10 Mbps
50 Mbps
ICC2
2.3
3.7
ICC1
3.7
5.1
ICC2
2.4
3.8
ICC1
3.8
5.3
ICC2
4.8
6.4
ICC1
4.4
6
ICC2
15
17.8
mA
ISO6741
Supply current - DC signal
VI = VCCI (1)(ISO6741); VI = 0 V (ISO6741 with F suffix)
(2)
VI = 0 V (ISO6741); VI = VCCI (ISO6741 with F suffix)
1 Mbps
Supply current - AC signal
(3)
All channels switching with square
wave clock input; CL = 15 pF
10 Mbps
50 Mbps
(1)
(2)
(3)
ICC1
1.9
2.8
ICC2
2.2
3.5
ICC1
5.1
7.2
ICC2
3.4
5.1
ICC1
3.6
5.1
ICC2
3
4.5
ICC1
4.2
5.8
ICC2
4.8
6.5
ICC1
7.3
9.3
ICC2
12.6
15.3
mA
VCCI = Input-side VCC
Supply current valid for ENx = VCCx and ENx = 0V
Supply current valid for ENx = VCCx
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6.11 Electrical Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
TEST CONDITIONS
MIN
VOH
High-level output voltage
PARAMETER
IOH = -2mA; See Figure 7-1
VCCO - 0.2 (1)
VOL
Low-level output voltage
IOL = 2mA; See Figure 7-1
VIT+(IN)
Rising input switching threshold
VIT-(IN)
Falling input switching threshold
0.3 x VCCI
V
VI(HYS)
Input threshold voltage
hysteresis
0.1 x VCCI
V
IIH
High-level input current
Low-level input current
VIL = 0 V at INx
IIH
High-level input current
VIH = VCCI (1) at ENx
IIL
Low-level input current
VIL = 0 V at ENx
CMTI
Common mode transient
immunity
VI = VCC or 0 V, VCM = 1200
V; See Figure 7-4
Ci
Input Capacitance (2)
VI = VCC/ 2 + 0.4×sin(2πft), f = 2
MHz, VCC = 3.3 V
12
MAX UNIT
V
VIH = VCCI (1) at INx
IIL
(1)
(2)
TYP
0.2
V
0.7 x VCCI (1)
V
10
-10
µA
µA
30
-30
uA
uA
50
75
kV/us
2.8
pF
VCCI = Input-side VCC; VCCO = Output-side VCC
Measured from input pin to same side ground.
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6.12 Supply Current Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
SUPPLY
CURRENT
MIN
TYP
MAX
1.6
2.2
ICC2
2.1
3.3
ICC1
5.7
8
ICC2
2.3
3.6
ICC1
3.7
5.1
ICC2
2.4
3.7
ICC1
3.8
5.2
UNIT
ISO6740
EN2 = VCC2; VI = VCC1 (ISO6740); VI = 0 V (ISO6740
with F suffix)
Supply current - DC signal
EN2 = VCC2; VI = 0 V (ISO6740); VI = VCC1 (ISO6740
with F suffix)
1 Mbps
Supply current - AC signal
All channels switching with square
wave clock input; CL = 15 pF
10 Mbps
ICC1
10 Mbps
ICC2
4
5.6
50 Mbps
ICC1
4.2
5.7
50 Mbps
ICC2
11.2
13.8
ICC1
1.9
2.7
ICC2
2.2
3.4
ICC1
5
7.1
ICC2
3.4
5.1
ICC1
3.5
5
ICC2
2.9
4.4
ICC1
4
5.5
ICC2
4.2
5.8
ICC1
6.1
8
ICC2
9.7
12.1
mA
ISO6741
Supply current - DC signal
VI = VCCI
suffix)
(1)(ISO6741);
VI = 0 V (ISO6741 with F
(2)
VI = 0 V (ISO6741); VI = VCCI (ISO6741 with F suffix)
1 Mbps
Supply current - AC signal
(3)
All channels switching with square
wave clock input; CL = 15 pF
10 Mbps
50 Mbps
(1)
(2)
(3)
mA
VCCI = Input-side VCC
Supply current valid for ENx = VCCx and ENx = 0V
Supply current valid for ENx = VCCx
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6.13 Electrical Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)
TEST CONDITIONS
MIN
VOH
High-level output voltage
PARAMETER
IOH = -1mA; See Figure 7-1
VCCO - 0.1 (1)
VOL
Low-level output voltage
IOL = 1mA; See Figure 7-1
VIT+(IN)
Rising input switching threshold
VIT-(IN)
Falling input switching threshold
0.3 x VCCI
V
VI(HYS)
Input threshold voltage
hysteresis
0.1 x VCCI
V
IIH
High-level input current
Low-level input current
VIL = 0 V at INx
IIH
High-level input current
VIH = VCCI (1) at ENx
IIL
Low-level input current
VIL = 0 V at ENx
CMTI
Common mode transient
immunity
VI = VCC or 0 V, VCM = 1200
V; See Figure 7-4
Ci
Input Capacitance (2)
VI = VCC/ 2 + 0.4×sin(2πft), f = 2
MHz, VCC = 2.5 V
14
MAX UNIT
V
VIH = VCCI (1) at INx
IIL
(1)
(2)
TYP
0.1
V
0.7 x VCCI (1)
V
10
-10
µA
µA
30
-30
uA
uA
50
75
kV/us
2.8
pF
VCCI = Input-side VCC; VCCO = Output-side VCC
Measured from input pin to same side ground.
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6.14 Supply Current Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
SUPPLY
CURRENT
MIN
TYP
MAX
1.6
2.2
UNIT
ISO6740
EN2 = VCC2; VI = VCC1 (ISO6740); VI = 0 V (ISO6740
with F suffix)
Supply current - DC signal
EN2 = VCC2; VI = 0 V (ISO6740); VI = VCC1 (ISO6740
with F suffix)
All channels switching with square
wave clock input; CL = 15 pF
ICC2
2.1
3.3
ICC1
5.7
7.9
ICC2
2.3
3.6
ICC1
3.7
5.1
ICC2
2.3
3.6
10 Mbps
ICC1
3.7
5.1
10 Mbps
ICC2
3.5
5.1
50 Mbps
ICC1
4.1
5.6
50 Mbps
ICC2
9
11.2
ICC1
1.9
2.7
ICC2
2.2
3.4
ICC1
5
7.1
ICC2
3.4
5.1
ICC1
3.5
5
ICC2
2.9
4.4
ICC1
3.9
5.4
ICC2
3.8
5.4
ICC1
5.5
7.2
ICC2
8.1
10.2
1 Mbps
Supply current - AC signal
ICC1
mA
ISO6741
Supply current - DC signal
VI = VCCI (1)(ISO6741); VI = 0 V (ISO6741 with F suffix)
(2)
VI = 0 V (ISO6741); VI = VCCI (ISO6741 with F suffix)
1 Mbps
Supply current - AC signal
(3)
All channels switching with square
wave clock input; CL = 15 pF
10 Mbps
50 Mbps
(1)
(2)
(3)
mA
VCCI = Input-side VCC
Supply current valid for ENx = VCCx and ENx = 0V
Supply current valid for ENx = VCCx
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6.15 Electrical Characteristics—1.8-V Supply
VCC1 = VCC2 = 1.8 V ±5% (over recommended operating conditions unless otherwise noted)
TEST CONDITIONS
MIN
VOH
High-level output voltage
PARAMETER
IOH = -1mA; See Figure 7-1
VCCO - 0.1 (1)
VOL
Low-level output voltage
IOL = 1mA; See Figure 7-1
VIT+(IN)
Rising input switching threshold
VIT-(IN)
Falling input switching threshold
0.3 x VCCI
V
VI(HYS)
Input threshold voltage hysteresis
0.1 x VCCI
V
(1)
IIH
High-level input current
VIH = VCCI
IIL
Low-level input current
VIL = 0 V at INx
(1)
High-level input current
VIH = VCCI
IIL
Low-level input current
VIL = 0 V at ENx
CMTI
Common mode transient immunity
VI = VCC or 0 V, VCM = 1200 V;
See Figure 7-4
Ci
Input Capacitance (2)
VI = VCC/ 2 + 0.4×sin(2πft), f = 2
MHz, VCC = 1.8 V
16
MAX
0.1
V
0.7 x VCCI (1)
V
10
-10
µA
µA
at ENx
30
-30
50
UNIT
V
at INx
IIH
(1)
(2)
TYP
µA
µA
75
kV/us
2.8
pF
VCCI = Input-side VCC; VCCO = Output-side VCC
Measured from input pin to same side ground.
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6.16 Supply Current Characteristics—1.8-V Supply
VCC1 = VCC2 = 1.8 V ±5% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
SUPPLY
CURRENT
MIN
TYP
MAX
1.2
1.8
UNIT
ISO6740
EN2 = VCC2; VI = VCC1 (ISO6740); VI = 0 V (ISO6740
with F suffix)
ICC1
ICC2
2
3.4
EN2 = VCC2; VI = 0 V (ISO6740); VI = VCC1 (ISO6740
with F suffix)
ICC1
5.1
7.6
Supply current - DC signal
1 Mbps
Supply current - AC signal
All channels switching with square
wave clock input; CL = 15 pF
10 Mbps
ICC2
2.2
3.7
ICC1
3.1
4.7
ICC2
2.2
3.7
ICC1
3.2
4.8
10 Mbps
ICC2
3.1
4.6
50 Mbps
ICC1
3.4
5.1
50 Mbps
ICC2
7
8.9
ICC1
1.5
2.4
ICC2
2
3.4
ICC1
4.5
6.9
ICC2
3.2
5
ICC1
3.1
4.7
ICC2
2.7
4.3
mA
ISO6741
Supply current - DC signal
VI = VCCI (1)(ISO6741); VI = 0 V (ISO6741 with F suffix)
(2)
VI = 0 V (ISO6741); VI = VCCI (ISO6741 with F suffix)
1 Mbps
Supply current - AC signal
(3)
All channels switching with square
wave clock input; CL = 15 pF
10 Mbps
50 Mbps
(1)
(2)
(3)
ICC1
3.3
5
ICC2
3.4
5
ICC1
4.5
6.3
ICC2
6.4
8.3
mA
VCCI = Input-side VCC
Supply current valid for ENx = VCCx and ENx = 0V
Supply current valid for ENx = VCCx
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6.17 Switching Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
tPLH, tPHL
Propagation delay time
distortion(1)
PWD
Pulse width
tsk(o)
Channel-to-channel output skew time(2)
|tPHL – tPLH|
TEST CONDITIONS
MIN
@100kbps
See Figure 7-1
Part-to-part skew
tr
Output signal rise time
tf
Output signal fall time
tPHZ
Disable propagation delay, high-to-high impedance
output
tPLZ
Disable propagation delay, low-to-high impedance
output
tPZH
Enable propagation delay, high impedance-to-high
output for ISO674x
tPZL
Enable propagation delay, high impedance-to-low
output for ISO674x
tPU
Time from UVLO to valid output data
tDO
Default output delay time from input power loss
tie
Time interval error
216 – 1 PRBS data at 50 Mbps
18
ns
0.2
7
ns
6
ns
6
ns
2.6
4.5
ns
2.6
4.5
ns
18.6
25.8
ns
18.6
25.8
ns
14.2
21.1
ns
14.2
21.1
ns
300
us
0.3
us
See Figure 7-2
Measured from the time VCC goes
below 1.2V. See Figure 7-3
(3)
18
Same-direction channels
See Figure 7-1
MAX UNIT
11
time(3)
tsk(pp)
(1)
(2)
TYP
0.1
1
ns
Also known as pulse skew.
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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6.18 Switching Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
tPLH, tPHL
Propagation delay time
distortion(1)
PWD
Pulse width
tsk(o)
Channel-to-channel output skew time(2)
|tPHL – tPLH|
TEST CONDITIONS
@100kbps
See Figure 7-1
Part-to-part skew
tr
Output signal rise time
Output signal fall time
tPHZ
Disable propagation delay, high-to-high impedance
output
tPLZ
Disable propagation delay, low-to-high impedance
output
tPZH
Enable propagation delay, high impedance-to-high
output for ISO674x
tPZL
Enable propagation delay, high impedance-to-low
output for ISO674x
tPU
Time from UVLO to valid output data
MAX UNIT
11
18
ns
0.5
7
ns
6
ns
Same-direction channels
See Figure 7-1
tf
7
ns
1.6
3.2
ns
1.6
3.2
ns
23.2
34.4
ns
23.2
34.4
ns
16.6
23
ns
16.6
23
ns
300
us
0.3
us
See Figure 7-2
tDO
Default output delay time from input power loss
Measured from the time VCC goes
below 1.2V. See Figure 7-3
tie
Time interval error
216 – 1 PRBS data at 50 Mbps
(3)
TYP
time(3)
tsk(pp)
(1)
(2)
MIN
0.1
1
ns
Also known as pulse skew.
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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6.19 Switching Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
tPLH, tPHL
Propagation delay time
distortion(1)
PWD
Pulse width
tsk(o)
Channel-to-channel output skew time(2)
|tPHL – tPLH|
TEST CONDITIONS
MIN
@100kbps
See Figure 7-1
Part-to-part skew
tr
Output signal rise time
tf
Output signal fall time
tPHZ
Disable propagation delay, high-to-high impedance
output
tPLZ
Disable propagation delay, low-to-high impedance
output
tPZH
Enable propagation delay, high impedance-to-high
output for ISO674x
tPZL
Enable propagation delay, high impedance-to-low
output for ISO674x
tPU
Time from UVLO to valid output data
tDO
Default output delay time from input power loss
tie
Time interval error
216 – 1 PRBS data at 50 Mbps
20
ns
0.6
7.1
ns
6
ns
7
ns
2
4
ns
2
4
ns
28.1
43
ns
28.1
43
ns
20.4
36.3
ns
20.4
36.3
ns
300
us
0.3
us
See Figure 7-2
Measured from the time VCC goes
below 1.2V. See Figure 7-3
(3)
20.5
Same-direction channels
See Figure 7-1
MAX UNIT
12
time(3)
tsk(pp)
(1)
(2)
TYP
0.1
1
ns
Also known as pulse skew.
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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6.20 Switching Characteristics—1.8-V Supply
VCC1 = VCC2 = 1.8 V ±5% (over recommended operating conditions unless otherwise noted)
PARAMETER
tPLH, tPHL
Propagation delay time
distortion(1)
PWD
Pulse width
tsk(o)
Channel-to-channel output skew time(2)
|tPHL – tPLH|
TEST CONDITIONS
@100kbps
See Figure 7-1
Part-to-part skew
tr
Output signal rise time
Output signal fall time
tPHZ
Disable propagation delay, high-to-high impedance
output
tPLZ
Disable propagation delay, low-to-high impedance
output
tPZH
Enable propagation delay, high impedance-to-high
output for ISO674x
tPZL
Enable propagation delay, high impedance-to-low
output for ISO674x
tPU
Time from UVLO to valid output data
MAX UNIT
15
24
ns
0.7
8.2
ns
6
ns
Same-direction channels
See Figure 7-1
tf
8.8
ns
2.7
5.3
ns
2.7
5.3
ns
40.3
63
ns
40.3
63
ns
30
51.4
ns
30
51.4
ns
300
us
0.3
us
See Figure 7-2
tDO
Default output delay time from input power loss
Measured from the time VCC goes
below 1.2V. See Figure 7-3
tie
Time interval error
216 – 1 PRBS data at 50 Mbps
(3)
TYP
time(3)
tsk(pp)
(1)
(2)
MIN
0.1
1
ns
Also known as pulse skew.
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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6.21 Insulation Characteristics Curves
1800
Vcc = 5.5 V
Vcc = 3.6 V
Vcc = 2.75 V
Vcc = 1.89 V
800
600
400
200
1600
Safety Limiting Power (mW)
Safety Limiting Current (mA)
1000
1400
1200
1000
800
600
400
200
0
0
0
20
40
60
80
100
120
Ambient Temperature ( C)
140
160
Figure 6-1. Thermal Derating Curve for Safety
Limiting Current for DW-16 Package
22
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0
20
40
60
80
100
120
Ambient Temperature ( C)
140
160
Figure 6-2. Thermal Derating Curve for Safety
Limiting Power for DW-16 Package
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6.22 Typical Characteristics
10.5
ICC1 at 1.8 V
ICC2 at 1.8 V
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
Supply Current (mA)
9
7.5
6
4.5
3
1.5
0
TA = 25°C
CL = 15 pF
TA = 25°C
Figure 6-3. ISO6741-Q1 Supply Current vs Data
Rate (With 15-pF Load)
40
50
CL = No Load
0.8
VCC1 at 1.8 V
VCC2 at 2.5 V
VCC1 at 3.3 V
VCC2 at 5 V
VCC1 at 1.8 V
VCC2 at 2.5 V
VCC1 at 3.3 V
VCC2 at 5 V
0.7
Low-Level Output Voltage (V)
High-Level Output Voltage (V)
6
20
30
Data Rate (Mbps)
Figure 6-4. ISO6741-Q1 Supply Current vs Data
Rate (With No Load)
8
7
10
5
4
3
2
1
0.6
0.5
0.4
0.3
0.2
0.1
0
-15
0
-10
-5
High-Level Output Current (mA)
0
TA = 25°C
0
5
10
Low-Level Output Current (mA)
15
TA = 25°C
1.625
1.6
1.575
1.55
1.525
1.5
1.475
1.45
1.425
1.4
1.375
1.35
1.325
1.3
1.275
-55
17
16
Propagation Delay Time (ns)
Power Supply UVLO Threshold (V)
Figure 6-5. High-Level Output Voltage vs High-level Figure 6-6. Low-Level Output Voltage vs Low-Level
Output Current
Output Current
VCC1 +
VCC1 VCC2 +
VCC2 -
15
14
13
12
11
10
9
8
-5
45
Free-Air Temperature ( C)
95
125
Figure 6-7. Power Supply Undervoltage Threshold
vs Free-Air Temperature
7
-55
tPHL at 1.8 V
tPLH at 1.8 V
tPHL at 2.5 V
tPLH at 2.5 V
tPHL at 3.3 V
tPLH at 3.3 V
-5
45
Free-Air Temperature ( C)
tPHL at 5 V
tPLH at 5 V
95
125
Figure 6-8. Propagation Delay Time vs Free-Air
Temperature
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7 Parameter Measurement Information
Isolation Barrier
IN
Input
Generator
(See Note A)
VI
VCCI
VI
OUT
50%
50%
0V
tPLH
CL
See Note B
VO
50
tPHL
VO
VOH
90%
50%
50%
10%
VOL
tf
tr
Copyright © 2016, Texas Instruments Incorporated
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3ns, ZO = 50
Ω. At the input, 50 Ω resistor is required to terminate Input Generator signal. It is not needed in actual application.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 7-1. Switching Characteristics Test Circuit and Voltage Waveforms
VCCO
VCC
Isolation Barrier
0V
IN
VO
VI
tPZL
0V
tPLZ
VOH
EN
0.5 V
VO
50%
VOL
50
OUT
VCC
VO
VCC / 2
VCC / 2
VI
0V
EN
CL
See Note B
VI
VCC / 2
VCC / 2
VI
CL
See Note B
IN
Input
Generator
(See Note A)
±1%
OUT
Isolation Barrier
Input
Generator
(See Note A)
3V
RL = 1 k
tPZH
RL = 1 k
±1%
VOH
50%
VO
0.5 V
tPHZ
50
0V
Copyright © 2016, Texas Instruments Incorporated
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 10 kHz, 50% duty cycle,
tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 7-2. Enable/Disable Propagation Delay Time Test Circuit and Waveform
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VI See Note B
VCC
VCC
Isolation Barrier
IN = 0 V (Devices without suffix F)
IN = VCC (Devices with suffix F)
VI
IN
1.4 V
0V
OUT
VO
tDO
CL
See Note A
default high
VOH
50%
VO
VOL
default low
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
B. Power Supply Ramp Rate = 10 mV/ns
Figure 7-3. Default Output Delay Time Test Circuit and Voltage Waveforms
VCCI
VCCO
C = 0.1 µF ±1%
Isolation Barrier
C = 0.1 µF ±1%
IN
S1
Pass-fail criteria:
The output must
remain stable.
OUT
+
CL
See Note A
VOH or VOL
±
GNDI
+
VCM ±
GNDO
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 7-4. Common-Mode Transient Immunity Test Circuit
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8 Detailed Description
8.1 Overview
The ISO674x-Q1 family of devices have an ON-OFF keying (OOK) modulation scheme to transmit the digital
data across a silicon dioxide based isolation barrier. The transmitter sends a high frequency carrier across the
barrier to represent one digital state and sends no signal to represent the other digital state. The receiver
demodulates the signal after advanced signal conditioning and produces the output through a buffer stage. If the
ENx pin is low then the output goes to high impedance. The ISO674x-Q1 devices also incorporate advanced
circuit techniques to maximize the CMTI performance and minimize the radiated emissions due to the high
frequency carrier and IO buffer switching. The conceptual block diagram of a digital capacitive isolator, Figure
8-1, shows a functional block diagram of a typical channel.
8.2 Functional Block Diagram
Transmitter
Receiver
EN
TX IN
OOK
Modulation
TX Signal
Conditioning
SiO2 based
Capacitive
Isolation
Barrier
RX Signal
Conditioning
Envelope
Detection
RX OUT
Emissions
Reduction
Techniques
Oscillator
Copyright © 2016, Texas Instruments Incorporated
Figure 8-1. Conceptual Block Diagram of a Digital Capacitive Isolator
Figure 8-2 shows a conceptual detail of how the ON-OFF keying scheme works.
TX IN
Carrier signal through
isolation barrier
RX OUT
Figure 8-2. On-Off Keying (OOK) Based Modulation Scheme
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8.3 Feature Description
Table 8-1 provides an overview of the device features.
Table 8-1. Device Features
(1)
PART NUMBER
CHANNEL DIRECTION
MAXIMUM DATA
RATE
DEFAULT
OUTPUT
PACKAGE
RATED ISOLATION(1)
ISO6740-Q1
4 Forward,
0 Reverse
50 Mbps
High
DW-16
5000 VRMS / 8000 VPK
ISO6740F-Q1
4 Forward,
0 Reverse
50 Mbps
Low
DW-16
5000 VRMS / 8000 VPK
ISO6741-Q1
3 Forward,
1 Reverse
50 Mbps
High
DW-16
5000 VRMS / 8000 VPK
ISO6741F-Q1
3 Forward,
1 Reverse
50 Mbps
Low
DW-16
5000 VRMS / 8000 VPK
ISO6742-Q1
2 Forward,
2 Reverse
50 Mbps
High
DW-16
5000 VRMS / 8000 VPK
ISO6742F-Q1
2 Forward,
2 Reverse
50 Mbps
Low
DW-16
5000 VRMS / 8000 VPK
See for detailed isolation ratings.
8.3.1 Electromagnetic Compatibility (EMC) Considerations
Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge
(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances
are regulated by international standards such as IEC 61000-4-x and CISPR 25. Although system-level
performance and reliability depends, to a large extent, on the application board design and layout, the ISO674xQ1 family of devices incorporates many chip-level design improvements for overall system robustness. Some of
these improvements include:
• Robust ESD protection cells for input and output signal pins and inter-chip bond pads.
• Low-resistance connectivity of ESD cells to supply and ground pins.
• Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.
• Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance
path.
• PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic
SCRs.
• Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.
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8.4 Device Functional Modes
Table 8-2 lists the functional modes for the ISO674x-Q1 devices.
Table 8-2. Function Table
VCCI (1)
VCCO
PU
(2)
(3)
OUTPUT
(OUTx)
H
H or open
H
L
H or open
L
Open
H or open
Default
X
L
Z
PU
X
(1)
INPUT
(INx) (3)
OUTPUT
ENABLE
(ENx)
PU
COMMENTS
Normal Operation: A channel output assumes the logic state of its
input.
Default mode: When INx is open, the corresponding channel output
goes to its default logic state. Default is High for ISO674x-Q1 and
Low for ISO674x-Q1 with F suffix.
A low value of output enable causes the outputs to be highimpedance.
PD
PU
X
H or open
Default
Default mode: When VCCI is unpowered, a channel output assumes
the logic state based on the selected default option. Default is High
for ISO674x-Q1 and Low for ISO674x-Q1 with F suffix. When VCCI
transitions from unpowered to powered-up, a channel output assumes
the logic state of the input. When VCCI transitions from powered-up to
unpowered, channel output assumes the selected default state.
X
PD
X
X
Undetermined
When VCCO is unpowered, a channel output is undetermined(2). When
VCCO transitions from unpowered to powered-up, a channel output
assumes the logic state of the input.
VCCI = Input-side VCC; VCCO = Output-side VCC; PU = Powered up (VCC ≥ 1.71 V); PD = Powered down (VCC ≤ 1.05 V); X = Irrelevant;
H = High level; L = Low level ; Z = High Impedance
The outputs are in undetermined state when 1.7 V < VCCI, VCCO < 2.25 V and 1.05 V < VCCI, VCCO < 1.71 V
A strongly driven input signal can weakly power the floating VCC through an internal protection diode and cause undetermined output
8.4.1 Device I/O Schematics
Input (Devices with F suffix)
Input (Devices without F suffix)
VCCI
VCCI
VCCI
VCCI
VCCI
VCCI
VCCI
1.5 M
985
985
INx
INx
1.5 M
Output
Enable
VCCO
VCCI
VCCI
VCCI
VCCI
550 k
~20
20 k
985
OUTx
INx
Figure 8-3. Device I/O Schematics
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The ISO674x-Q1 devices are high-performance, quad-channel digital isolators. These devices come with enable
pins on each side which can be used to put the respective outputs in high impedance for multi master driving
applications. The ISO674x-Q1 devices use single-ended CMOS-logic switching technology. The supply voltage
range is from 1.71 V to 5.5 V for both supplies, VCC1 and VCC2. Since an isolation barrier separates the two
sides, each side can be sourced independently with any voltage within recommended operating conditions. As
an example, it is possible to supply ISO674x-Q1 VCC1 with 3.3 V (which is within 1.71 V to 5.5 V) and VCC2 with
5V (which is also within 1.71 V to 5.5 V). You can use the digital isolator as a logic-level translator in addition to
providing isolation. When designing with digital isolators, keep in mind that because of the single-ended design
structure, digital isolators do not conform to any specific interface standard and are only intended for isolating
single-ended CMOS or TTL digital signal lines. The isolator is typically placed between the data controller (that
is, μC or UART), and a data converter or a line transceiver, regardless of the interface type or standard.
9.2 Typical Application
Figure 9-1 shows ISO6741-Q1 in a belt starter generator application.
48 V Side
12 V Side
MCU
TMS570
ISO6741-Q1
nSTB
EN
TCAN1043
TXD
RXD
WAKE
CANH
CANL
Figure 9-1. Belt Starter Generator Application
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9.2.1 Design Requirements
To design with these devices, use the parameters listed in Table 9-1.
Table 9-1. Design Parameters
PARAMETER
VALUE
Supply voltage, VCC1 and VCC2
1.71 V to 1.89 V and 2.25 V to 5.5 V
Decoupling capacitor between VCC1 and GND1
0.1 µF
Decoupling capacitor from VCC2 and GND2
0.1 µF
9.2.2 Detailed Design Procedure
Unlike optocouplers, which require external components to improve performance, provide bias, or limit current,
the ISO674x-Q1 family of devices only require two external bypass capacitors to operate.
2 mm maximum
from VCC2
2 mm maximum
from VCC1
0.1 µF
0.1 µF
VCC2
VCC1
1
16
2
15
INA
3
14
OUTA
INB
4
13
OUTB
INC
5
12
OUTC
OUTD
6
11
IND
7
10
8
9
GND1
GND2
EN2
EN1
GND2
GND1
Figure 9-2. Typical ISO674x-Q1 Circuit Hook-up
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9.2.3 Application Curve
1 V/ div
0.75 V/ div
The following typical eye diagrams of the ISO674x-Q1 family of devices indicates low jitter and wide open eye at
the maximum data rate of 50 Mbps.
Time = 5 ns / div
Time = 5 ns / div
– 1,
Figure 9-4. Eye Diagram at 50 Mbps PRBS 216 – 1,
3.3 V and 25°C
0.5 V/ div
0.5 V/ div
Figure 9-3. Eye Diagram at 50 Mbps PRBS
5 V and 25°C
216
Time = 5 ns / div
Time = 5 ns / div
Figure 9-5. Eye Diagram at 50 Mbps PRBS
2.5 V and 25°C
216
– 1,
Figure 9-6. Eye Diagram at 50 Mbps PRBS 216 – 1,
1.8 V and 25°C
9.2.3.1 Insulation Lifetime
Insulation lifetime projection data is collected by using industry-standard Time Dependent Dielectric Breakdown
(TDDB) test method. In this test, all pins on each side of the barrier are tied together creating a two-terminal
device and high voltage applied between the two sides; See Figure 9-7 for TDDB test setup. The insulation
breakdown data is collected at various high voltages switching at 60 Hz over temperature. For reinforced
insulation, VDE standard requires the use of TDDB projection line with failure rate of less than 1 part per million
(ppm). Even though the expected minimum insulation lifetime is 20 years at the specified working isolation
voltage, VDE reinforced certification requires additional safety margin of 20% for working voltage and 87.5% for
lifetime which translates into minimum required insulation lifetime of 37.5 years at a working voltage that's 20%
higher than the specified value.
Figure 9-8 shows the intrinsic capability of the isolation barrier to withstand high voltage stress over its lifetime.
Based on the TDDB data, the intrinsic capability of the insulation is 1060 VRMS with a lifetime of 220 years. Other
factors, such as package size, pollution degree, material group, etc. can further limit the working voltage of the
component. The working voltage of DW-16 package is specified upto 1060 VRMS. At the lower working voltages,
the corresponding insulation lifetime is much longer than 220 years.
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A
Vcc 1
Vcc 2
Time Counter
> 1 mA
DUT
GND 1
GND 2
VS
Oven at 150 °C
Figure 9-7. Test Setup for Insulation Lifetime Measurement
Figure 9-8. Insulation Lifetime Projection Data
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10 Power Supply Recommendations
To help ensure reliable operation at data rates and supply voltages, a 0.1-μF bypass capacitor is recommended
at the input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins
as possible. If only a single primary-side power supply is available in an application, isolated power can be
generated for the secondary-side with the help of a transformer driver. For automotive applications, please use
SN6501-Q1 or SN6505A-Q1. For such applications, detailed power supply design and transformer selection
recommendations are available in SN6501-Q1 Transformer Driver for Isolated Power Supplies or SN6505A-Q1
Low-Noise 1-A Transformer Drivers for Isolated Power Supplies.
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11 Layout
11.1 Layout Guidelines
A minimum of two layers is required to accomplish a cost optimized and low EMI PCB design. To further improve
EMI, a four layer board can be used (see Figure 11-2). Layer stacking for a four layer board should be in the
following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency signal
layer.
•
•
•
•
Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/inch2.
Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to
the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also
the power and ground plane of each power system can be placed closer together, thus increasing the highfrequency bypass capacitance significantly.
For detailed layout recommendations, refer to the Digital Isolator Design Guide.
11.1.1 PCB Material
For digital circuit boards operating below 150 Mbps, (or rise and fall times higher than 1 ns), and trace lengths of
up to 10 inches, use standard FR-4 UL94V-0 printed circuit boards. This PCB is preferred over cheaper
alternatives due to its lower dielectric losses at high frequencies, less moisture absorption, greater strength and
stiffness, and self-extinguishing flammability-characteristics.
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11.2 Layout Example
Solid supply islands reduce
inductance because large peak
currents flow into the VCC pin
2 mm
maximum
from VCC1
2 mm
maximum
from VCC2
VCC1
VCC2
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
GND2
0.1 …F GND1
EN1
0.1 …F
EN2
GND2
GND1
Solid ground islands help
dissipate heat through PCB
Figure 11-1. Layout Example
High-speed traces
10 mils
Ground plane
40 mils
Keep this
space free
from planes,
traces, pads,
and vias
FR-4
0r ~ 4.5
Power plane
10 mils
Low-speed traces
Figure 11-2. Layout Example Schematic
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, Digital Isolator Design Guide
• Texas Instruments, Digital Isolator Design Guide
• Texas Instruments, Isolation Glossary
• Texas Instruments, How to use isolation to improve ESD, EFT, and Surge immunity in industrial systems
application report
• Texas Instruments, SN6505x-Q1 Low-Noise 1-A Transformer Drivers for Isolated Power Supplies
• Texas Instruments, TCAN1044-Q1 Automotive Fault-Protected CAN FD Transceiver
• Texas Instruments, TPS763xx-Q1 Low-Power, 150-mA, Low-Dropout Linear Regulators data sheet
• Texas Instruments, TMS320F2803x Piccolo™ Microcontrollers data sheet
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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13.1 Package Option Addendum
Packaging Information
Package Type
Package
Drawing
Pins
Package Qty
Eco Plan(2)
ISO6740QDWR ACTIVE
Q1
SOIC
DW
16
2000
Green (RoHS & NIPDAU
no Sb/Br)
Level-2-260C-1 --40 to 125
YEAR
ISO6740
ISO6740FQDW ACTIVE
RQ1
SOIC
DW
16
2000
Green (RoHS & NIPDAU
no Sb/Br)
Level-2-260C-1 --40 to 125
YEAR
ISO6740F
ISO6741QDWR ACTIVE
Q1
SOIC
DW
16
2000
Green (RoHS & NIPDAU
no Sb/Br)
Level-2-260C-1 --40 to 125
YEAR
ISO6741
ISO6741FQDW ACTIVE
RQ1
SOIC
DW
16
2000
Green (RoHS & NIPDAU
no Sb/Br)
Level-2-260C-1 --40 to 125
YEAR
ISO6741F
ISO6742QDWR ACTIVE
Q1
SOIC
DW
16
2000
Green (RoHS & NIPDAU
no Sb/Br)
Level-2-260C-1 --40 to 125
YEAR
ISO6742
ISO6742FQDW ACTIVE
RQ1
SOIC
DW
16
2000
Green (RoHS & NIPDAU
no Sb/Br)
Level-2-260C-1 --40 to 125
YEAR
ISO6742F
Orderable
Device
Status(1)
Lead/Ball
Finish(6)
MSL Peak
Temp(3)
Op Temp (°C)
Device
Marking(4) (5)
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13.2 Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
B0 W
Reel
Diameter
Cavity
A0
B0
K0
W
P1
A0
Dimension designed to accommodate the component width
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1
Q2
Q1
Q2
Q3
Q4
Q3
Q4
User Direction of Feed
Pocket Quadrants
38
Device
Package
Type
Package
Drawing
Pins
SPQ
Reel
Diameter
(mm)
Reel
Width W1
(mm)
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
ISO6740QDWRQ1
SOIC
DW
16
2000
330.0
24.4
10.9
10.7
2.7
12.0
24.0
Q1
ISO6740FQDWRQ1
SOIC
DW
16
2000
330.0
24.4
10.9
10.7
2.7
12.0
24.0
Q1
ISO6741QDWRQ1
SOIC
DW
16
2000
330.0
24.4
10.9
10.7
2.7
12.0
24.0
Q1
ISO6741FQDWRQ1
SOIC
DW
16
2000
330.0
24.4
10.9
10.7
2.7
12.0
24.0
Q1
ISO6742QDWRQ1
SOIC
DW
16
2000
330.0
24.4
10.9
10.7
2.7
12.0
24.0
Q1
ISO6742FQDWRQ1
SOIC
DW
16
2000
330.0
24.4
10.9
10.7
2.7
12.0
24.0
Q1
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: ISO6740-Q1 ISO6741-Q1 ISO6742-Q1
ISO6740-Q1, ISO6741-Q1, ISO6742-Q1
www.ti.com
SLLSFG4B – AUGUST 2020 – REVISED FEBRUARY 2021
TAPE AND REEL BOX DIMENSIONS
Width (mm)
W
L
H
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ISO6740QDWRQ1
SOIC
DW
16
2000
367.0
367.0
45.0
ISO6740FQDWRQ1
SOIC
DW
16
2000
367.0
367.0
45.0
ISO6741QDWRQ1
SOIC
DW
16
2000
367.0
367.0
45.0
ISO6741FQDWRQ1
SOIC
DW
16
2000
367.0
367.0
45.0
ISO6742QDWRQ1
SOIC
DW
16
2000
367.0
367.0
45.0
ISO6742FQDWRQ1
SOIC
DW
16
2000
367.0
367.0
45.0
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: ISO6740-Q1 ISO6741-Q1 ISO6742-Q1
Submit Document Feedback
39
PACKAGE OPTION ADDENDUM
www.ti.com
27-Feb-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
ISO6740FQDWRQ1
PREVIEW
SOIC
DW
16
2000
RoHS (In work)
& Non-Green
Call TI
Call TI
-40 to 125
ISO6740QDWRQ1
PREVIEW
SOIC
DW
16
2000
RoHS (In work)
& Non-Green
Call TI
Call TI
-40 to 125
ISO6741FQDWRQ1
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO6741F
ISO6741QDWRQ1
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO6741
ISO6742FQDWRQ1
PREVIEW
SOIC
DW
16
2000
RoHS (In work)
& Non-Green
Call TI
Call TI
-40 to 125
ISO6742QDWRQ1
PREVIEW
SOIC
DW
16
2000
RoHS (In work)
& Non-Green
Call TI
Call TI
-40 to 125
XISO6740FQDWRQ1
ACTIVE
SOIC
DW
16
2000
RoHS (In work)
& Non-Green
Call TI
Call TI
-40 to 125
XISO6740QDWRQ1
ACTIVE
SOIC
DW
16
2000
RoHS (In work)
& Non-Green
Call TI
Call TI
-40 to 125
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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