ISO6760-Q1, ISO6761-Q1, ISO6762-Q1, ISO6763-Q1
ZHCSLW8B – AUGUST 2021 – REVISED MAY 2022
EMC 性能优异的 ISO676x-Q1 通用六通道自动增强型数字隔离器
1 特性
3 说明
• 具有符合 AEC-Q100 标准的下列特性：
– 器件温度等级 1：–40°C 至 +125°C 环境工作
温度范围
• 满足 VDA320 隔离要求
• 50Mbps 数据速率
• 稳健可靠的隔离栅：
– 在 1500 VRMS 工作电压下具有超长的寿命
– 隔离等级高达 5000 VRMS
– 浪涌能力高达 10kV
– CMTI 典型值为 ±150 kV/μs
• 宽电源电压范围：1.71V 到 1.89V 和 2.25V 到 5.5V
• 1.71V 至 5.5V 电平转换
• 默认输出高电平 (ISO676x-Q1) 和低电平
(ISO676xF-Q1) 选项
• 1Mbps 时的每通道电流典型值为 1.6mA
• 低传播延迟：11ns（典型值）
• 优异的电磁兼容性 (EMC)
– 系统级 ESD、EFT 和浪涌抗扰性
– 低辐射
• 宽体 SOIC (DW-16) 封装
• 安全相关认证（待审核）：
– DIN VDE V 0884-11:2017-01
– UL 1577 组件认证计划
– IEC 62368-1、IEC 61010-1、IEC 60601-1 和
GB 4943.1-2011 认证
ISO676x-Q1 器件是高性能六通道数字隔离器，可提供
符合 UL 1577 的 5000 VRMS 隔离额定值，非常适合具
有此类需求的成本敏感型应用。这些器件还通过了
VDE、TUV、CSA 和 CQC 认证。
2 应用
• 混合动力、电动和动力总成系统 (EV/HEV)
– 电池管理系统 (BMS)
– 车载充电器
– 直流/直流转换器
– 逆变器和电机控制
在 隔 离 CMOS 或 者 LVCMOS 数 字 I/O 的 同 时 ，
ISO676x-Q1 器件可提供高电磁抗扰度和低辐射，同时
具备低功耗特性。每条隔离通道的逻辑输入和输出缓冲
器均由 TI 的双电容二氧化硅 (SiO2) 绝缘栅相隔离。
ISO676x 系列器件采用所有可能的引脚配置，因此所
有六个通道都可以处于同一方向，或者一个、两个或三
个通道处于反向，而其余通道处于正向。如果输入功率
或信号出现损失，不带后缀 F 的器件默认输出 高电
平 ，带后缀 F 的器件默认输出 低电平 。更多详细信
息，请参见器件功能模式部分。
这些器件与隔离式电源结合使用，有助于防止 CAN 和
LIN 等数据总线上的噪声电流损坏敏感电路。凭借创新
型芯片设计和布线技术，ISO676x-Q1 器件的电磁兼容
性得到了显著增强，可缓解系统级 ESD、EFT 和浪涌
问题并符合辐射标准。ISO676x-Q1 系列器件采用 16
引脚 SOIC 宽体 (DW) 封装，是对前几代器件的引脚到
引脚的升级。
器件描述
器件型号 (1)
封装
封装尺寸
ISO6760-Q1、ISO6760FQ1、ISO6761-Q1、
ISO6761F-Q1、ISO6762Q1、ISO6762F-Q1、
ISO6763-Q1、ISO6763FQ1
SOIC (DW)
10.30mm x
7.50mm
(1)
如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
VCCO
VCCI
Series Isolation
Capacitors
INx
OUTx
GNDI
GNDO
Copyright © 2016, Texas Instruments Incorporated
VCCI = 输入电源，VCCO = 输出电源
GNDI = 输入接地，GNDO = 输出接地
简化版原理图
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLLSFK2
ISO6760-Q1, ISO6761-Q1, ISO6762-Q1, ISO6763-Q1
www.ti.com.cn
ZHCSLW8B – AUGUST 2021 – REVISED MAY 2022
Table of Contents
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................6
6.4 Thermal Information....................................................7
6.5 Power Ratings.............................................................7
6.6 Insulation Specifications............................................. 8
6.7 Safety-Related Certifications...................................... 9
6.8 Safety Limiting Values.................................................9
Electrical Characteristics—5-V Supply........................... 10
6.9 Supply Current Characteristics—5-V Supply............ 10
6.10 Electrical Characteristics—3.3-V Supply................ 12
6.11 Supply Current Characteristics—3.3-V Supply....... 12
6.12 Electrical Characteristics—2.5-V Supply ............... 14
6.13 Supply Current Characteristics—2.5-V Supply....... 14
Electrical Characteristics—1.8-V Supply........................ 16
6.14 Supply Current Characteristics—1.8-V Supply....... 16
6.15 Switching Characteristics—5-V Supply...................18
6.16 Switching Characteristics—3.3-V Supply................19
6.17 Switching Characteristics—2.5-V Supply................20
6.18 Switching Characteristics—1.8-V Supply................21
6.19 Insulation Characteristics Curves........................... 22
6.20 Typical Characteristics............................................ 23
7 Parameter Measurement Information.......................... 25
8 Detailed Description......................................................26
8.1 Overview................................................................... 26
8.2 Functional Block Diagram......................................... 26
8.3 Feature Description...................................................27
8.4 Device Functional Modes..........................................28
9 Application and Implementation.................................. 29
9.1 Application Information............................................. 29
9.2 Typical Application.................................................... 30
10 Power Supply Recommendations..............................33
11 Layout........................................................................... 34
11.1 Layout Guidelines................................................... 34
11.2 Layout Example...................................................... 35
12 Device and Documentation Support..........................36
12.1 Documentation Support.......................................... 36
12.2 Receiving Notification of Documentation Updates..36
12.3 支持资源..................................................................36
12.4 Trademarks............................................................. 36
12.5 Electrostatic Discharge Caution..............................36
12.6 术语表..................................................................... 36
13 Mechanical, Packaging, and Orderable
Information.................................................................... 36
13.1 Package Option Addendum.................................... 40
13.2 Tape and Reel Information......................................41
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision A (November 2021) to Revision B (May 2022)
Page
• Updated CMTI spec for 5-V, 3.3-V and 2.5-V supply conditions.........................................................................5
Changes from Revision * (August 2021) to Revision A (November 2021)
Page
• 将器件状态更新为“量产数据”......................................................................................................................... 1
2
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: ISO6760-Q1 ISO6761-Q1 ISO6762-Q1 ISO6763-Q1
ISO6760-Q1, ISO6761-Q1, ISO6762-Q1, ISO6763-Q1
www.ti.com.cn
ZHCSLW8B – AUGUST 2021 – REVISED MAY 2022
5 Pin Configuration and Functions
1
16
VCC2
INA
2
15
OUTA
INB
3
14
OUTB
INC
4
13
OUTC
IND
5
12
OUTD
INE
6
11
OUTE
INF
7
10
OUTF
GND1
8
9
GND2
ISOLATION
VCC1
Not to scale
图 5-1. ISO6760-Q1 DW Package 16-Pin SOIC-WB Top View
1
16
VCC2
INA
2
15
OUTA
INB
3
14
OUTB
INC
4
13
OUTC
IND
5
12
OUTD
INE
6
11
OUTE
OUTF
7
10
INF
GND1
8
9
ISOLATION
VCC1
GND2
Not to scale
图 5-2. ISO6761-Q1 DW Package 16-Pin SOIC-WB Top View
1
16
VCC2
INA
2
15
OUTA
INB
3
14
OUTB
INC
4
13
OUTC
IND
5
12
OUTD
OUTE
6
11
INE
OUTF
7
10
INF
GND1
8
9
ISOLATION
VCC1
GND2
Not to scale
图 5-3. ISO6762-Q1 DW Package 16-Pin SOIC-WB Top View
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: ISO6760-Q1 ISO6761-Q1 ISO6762-Q1 ISO6763-Q1
3
ISO6760-Q1, ISO6761-Q1, ISO6762-Q1, ISO6763-Q1
www.ti.com.cn
ZHCSLW8B – AUGUST 2021 – REVISED MAY 2022
1
16
VCC2
INA
2
15
OUTA
INB
3
14
OUTB
INC
4
13
OUTC
OUTD
5
12
IND
OUTE
6
11
INE
OUTF
7
10
INF
GND1
8
9
ISOLATION
VCC1
GND2
Not to scale
图 5-4. ISO6763-Q1 DW Package 16-Pin SOIC-WB Top View
表 5-1. Pin Functions
PIN
NAME
4
NO.
I/O
DESCRIPTION
ISO6760-Q1
ISO6761-Q1
ISO6762-Q1
ISO6763-Q1
GND1
8
8
8
8
—
Ground connection for VCC1
GND2
9
9
9
9
—
Ground connection for VCC2
INA
2
2
2
2
I
Input, channel A
INB
3
3
3
3
I
Input, channel B
INC
4
4
4
4
I
Input, channel C
IND
5
5
5
12
I
Input, channel D
INE
6
6
11
11
I
Input, channel E
INF
7
10
10
10
I
Input, channel F
OUTA
15
15
15
15
O
Output, channel A
OUTB
14
14
14
14
O
Output, channel B
OUTC
13
13
13
13
O
Output, channel C
OUTD
12
12
12
5
O
Output, channel D
OUTE
11
11
6
6
O
Output, channel E
OUTF
10
7
7
7
O
Output, channel F
VCC1
1
1
1
1
—
Power supply, side 1
VCC2
16
16
16
16
—
Power supply, side 2
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: ISO6760-Q1 ISO6761-Q1 ISO6762-Q1 ISO6763-Q1
ISO6760-Q1, ISO6761-Q1, ISO6762-Q1, ISO6763-Q1
www.ti.com.cn
ZHCSLW8B – AUGUST 2021 – REVISED MAY 2022
6 Specifications
6.1 Absolute Maximum Ratings
See(1)
MIN
MAX
VCC1 to GND1
-0.5
6
VCC2 to GND2
-0.5
6
Input/Output
Voltage
INx to GNDx
-0.5
VCCX + 0.5 (3)
OUTx to GNDx
-0.5
VCCX + 0.5 (3)
Output Current
Io
-15
Supply Voltage (2)
Temperature
(1)
(2)
(3)
Operating junction temperature, TJ
Storage temperature, Tstg
-65
UNIT
V
V
15
mA
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak
voltage values
Maximum voltage must not exceed 6 V.
6.2 ESD Ratings
(1) (2)
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/
ESDA/JEDEC JS-001, all pins(1)
±2000
Charged device model (CDM), per
JEDEC specification JESD22-C101, all
pins(2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: ISO6760-Q1 ISO6761-Q1 ISO6762-Q1 ISO6763-Q1
5
ISO6760-Q1, ISO6761-Q1, ISO6762-Q1, ISO6763-Q1
www.ti.com.cn
ZHCSLW8B – AUGUST 2021 – REVISED MAY 2022
6.3 Recommended Operating Conditions
MIN
MAX
UNIT
1.71
1.89
V
2.25
5.5
V
(3)
1.71
1.89
V
VCC2 (1)
Supply Voltage Side 2 (3)
2.25
5.5
V
Vcc
(UVLO+)
UVLO threshold when supply voltage is rising
1.71
V
Vcc
(UVLO-)
UVLO threshold when supply voltage is falling
Vhys
(UVLO)
Supply voltage UVLO hysteresis
VIH
High level Input voltage
VIL
Low level Input voltage
(3)
VCC1 (1)
Supply Voltage Side 1 (3)
(1)
VCC1
VCC2
(1)
Supply Voltage Side 1
Supply Voltage Side 2
IOL
Low level output current
DR
Data Rate
TA
Ambient temperature
(1)
(2)
(3)
6
High level output current
1.53
1.1
1.41
V
0.08
0.13
V
0.7 x VCCI
VCCO
IOH
NOM
(2)
=5V
(2)
VCCI
V
0
0.3 x VCCI
V
-4
mA
VCCO = 3.3 V
-2
mA
VCCO = 2.5 V
-1
mA
VCCO = 1.8 V
-1
mA
VCCO = 5 V
4
mA
VCCO = 3.3 V
2
mA
VCCO = 2.5 V
1
mA
VCCO = 1.8 V
1
mA
50
Mbps
125
°C
0
-40
25
VCC1 and VCC2 can be set independent of one another
VCCI = Input-side VCC; VCCO = Output-side VCC
The channel outputs are in undetermined state when 1.89 V < VCC1, VCC2 < 2.25 V and 1.05 V < VCC1, VCC2 < 1.71 V
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: ISO6760-Q1 ISO6761-Q1 ISO6762-Q1 ISO6763-Q1
ISO6760-Q1, ISO6761-Q1, ISO6762-Q1, ISO6763-Q1
www.ti.com.cn
ZHCSLW8B – AUGUST 2021 – REVISED MAY 2022
6.4 Thermal Information
ISO676x
THERMAL METRIC
(1)
DW (SOIC)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
68.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
31.8
°C/W
RθJB
Junction-to-board thermal resistance
32.7
°C/W
ψJT
Junction-to-top characterization parameter
13.5
°C/W
ψJB
Junction-to-board characterization parameter
32.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
°C/W
6.5 Power Ratings
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
192
mW
45
mW
147
mW
197
mW
63
mW
134
mW
197
mW
ISO6760
PD
Maximum power dissipation (both sides)
PD1
Maximum power dissipation (side-1)
PD2
Maximum power dissipation (side-2)
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15
pF, Input a 25-MHz 50% duty cycle
square wave
ISO6761
PD
Maximum power dissipation (both sides)
PD1
Maximum power dissipation (side-1)
PD2
Maximum power dissipation (side-2)
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15
pF, Input a 25-MHz 50% duty cycle
square wave
ISO6762
PD
Maximum power dissipation (both sides)
PD1
Maximum power dissipation (side-1)
PD2
Maximum power dissipation (side-2)
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15
pF, Input a 25-MHz 50% duty cycle
square wave
81
mW
116
mW
196
mW
98
mW
98
mW
ISO6763
PD
Maximum power dissipation (both sides)
PD1
Maximum power dissipation (side-1)
PD2
Maximum power dissipation (side-2)
Copyright © 2022 Texas Instruments Incorporated
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15
pF, Input a 25-MHz 50% duty cycle
square wave
Submit Document Feedback
Product Folder Links: ISO6760-Q1 ISO6761-Q1 ISO6762-Q1 ISO6763-Q1
7
ISO6760-Q1, ISO6761-Q1, ISO6762-Q1, ISO6763-Q1
www.ti.com.cn
ZHCSLW8B – AUGUST 2021 – REVISED MAY 2022
6.6 Insulation Specifications
PARAMETER
VALUE
TEST CONDITIONS
DW-16
UNIT
CLR
External clearance(1)
Shortest terminal-to-terminal distance through air
>8
mm
CPG
External creepage(1)
Shortest terminal-to-terminal distance across the
package surface
>8
mm
DTI
Distance through the insulation
Minimum internal gap (internal clearance)
>17
um
CTI
Comparative tracking index
DIN EN 60112 (VDE 0303-11); IEC 60112
>600
V
Material group
According to IEC 60664-1
I
Rated mains voltage ≤ 600 VRMS
I-IV
Rated mains voltage ≤ 1000 VRMS
I-III
Maximum repetitive peak isolation voltage
AC voltage (bipolar)
2121
VPK
Maximum working isolation voltage
AC voltage; Time dependent dielectric breakdown
(TDDB) Test; See 图 9-8
1500
VRMS
DC voltage
2121
VDC
Overvoltage category per IEC 60664-1
DIN VDE V 0884-11:2017-01(2)
VIORM
VIOWM
VIOTM
Maximum transient isolation voltage
VTEST = VIOTM,
t = 60 s (qualification);
VTEST = 1.2 x VIOTM,
t= 1 s (100% production)
7071
VPK
VIOSM
Maximum surge isolation voltage(3)
Test method per IEC 62368-1, 1.2/50 µs waveform,
VTEST = 1.6 x VIOSM = 10,000 VPK (qualification)
6250
VPK
Method a, After Input-output safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.2 x VIORM, tm = 10 s
≤5
Method a, After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.6 x VIORM, tm = 10 s
≤5
Method b1; At routine test (100% production) and
preconditioning (type test)
Vini = 1.2 x VIOTM, tini = 1 s;
Vpd(m) = 1.875 x VIORM, tm = 1 s
≤5
VIO = 0.4 x sin (2πft), f = 1 MHz
~1
VIO = 500 V, TA = 25°C
>1012
VIO = 500 V, 100°C ≤ TA ≤ 125°C
>1011
VIO = 500 V at TS = 150°C
>109
Apparent charge(4)
qpd
Barrier capacitance, input to output(5)
CIO
Isolation resistance(5)
RIO
Pollution degree
2
Climatic category
40/125/21
pC
pF
Ω
UL 1577
VISO
(1)
(2)
(3)
(4)
(5)
8
Maximum withstanding isolation voltage
VTEST = VISO , t = 60 s (qualification),
VTEST = 1.2 x VISO , t = 1 s (100% production)
5000
VRMS
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application.
Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the
isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in
certain cases. Techniques such as inserting grooves and/or ribs on a printed-circuit board are used to help increase these
specifications.
This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured
by means of suitable protective circuits.
Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
Apparent charge is electrical discharge caused by a partial discharge (pd).
All pins on each side of the barrier tied together creating a two-terminal device.
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: ISO6760-Q1 ISO6761-Q1 ISO6762-Q1 ISO6763-Q1
ISO6760-Q1, ISO6761-Q1, ISO6762-Q1, ISO6763-Q1
www.ti.com.cn
ZHCSLW8B – AUGUST 2021 – REVISED MAY 2022
6.7 Safety-Related Certifications
VDE
CSA
UL
CQC
TUV
Plan to certify according to
Plan to certify according to Plan to certify according to Plan to certify according to
Plan to certify according to EN 61010-1:2010/
DIN VDE V 0884-11:2017- IEC 62368-1, IEC 61010-1 UL 1577 Component
GB4943.1-2011
A1:2019 and EN
01
and IEC 60601-1
Recognition Program
62368-1:2014
Maximum transient
isolation
voltage, 7071 VPK;
Maximum repetitive peak
isolation
voltage, 2121 VPK;
Maximum surge isolation
voltage, 6250 VPK
Certificate planned
600 VRMS reinforced
insulation per CSA
62368-1:19 and IEC
62368-1:2018; 600 VRMS
reinforced insulation
per CSA 61010-1-12+A1
and IEC 61010-1 3rd Ed
Single protection,
(pollution degree 2,
5000 VRMS
material group I);
2 MOPP (Means of Patient
Protection) per CSA
60601-1-14 and IEC
60601-1 Ed.3+A1, 250
VRMS max working voltage
Certificate planned
Certificate planned
Reinforced insulation,
Altitude ≤ 5000 m,
Tropical Climate,
700 VRMS
maximum working voltage
5000 VRMS reinforced
insulation per EN
61010-1:2010/A1:2019
and EN 62368-1:2014 up
to working voltage of 600
VRMS
Certificate planned
Certificate planned
6.8 Safety Limiting Values
Safety limiting(1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RθJA =68.8°C/W, VI = 5.5 V, TJ = 150°C,
TA = 25°C
330
mA
RθJA = 68.8°C/W, VI = 3.6 V, TJ = 150°C,
TA = 25°C
504
mA
RθJA = 68.8°C/W, VI = 2.75 V, TJ =
150°C, TA = 25°C
660
mA
RθJA = 68.8°C/W, VI = 1.89 V, TJ =
150°C, TA = 25°C
956
mA
1820
mW
150
°C
DW-16 PACKAGE
IS
PS
TS
(1)
Safety input, output, or supply current
Safety input, output, or total power (1)
Maximum safety temperature
(1)
RθJA = 68.8°C/W, TJ = 150°C, TA = 25°C
(1)
The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS
and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be
exceeded. These limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the table is that of a device installed on a high-K test board for leaded surface-mount
packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum allowed junction temperature.
PS = IS × VI, where VI is the maximum input voltage.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: ISO6760-Q1 ISO6761-Q1 ISO6762-Q1 ISO6763-Q1
9
ISO6760-Q1, ISO6761-Q1, ISO6762-Q1, ISO6763-Q1
www.ti.com.cn
ZHCSLW8B – AUGUST 2021 – REVISED MAY 2022
Electrical Characteristics—5-V Supply
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
IOH = -4 mA; See 图 7-1
VOL
Low-level output voltage
IOL = 4 mA; See 图 7-1
MIN
MAX
VCCO - 0.4
VIT+(IN)
Rising input switching threshold
VIT-(IN)
Falling input switching threshold
VI(HYS)
Input threshold voltage hysteresis
IIH
High-level input current
VIH = VCCI (1) at INx
IIL
Low-level input current
VIL = 0 V at INx
-10
CMTI
Common mode transient immunity
VI = VCC or 0 V, VCM = 1200
V; See 图 7-3
100
Ci
Input Capacitance (2)
VI = VCC/ 2 + 0.4×sin(2πft), f =
2 MHz, VCC = 5 V
(1)
(2)
TYP
UNIT
V
0.4
V
(1)
V
0.7 x VCCI
0.3 x VCCI
V
0.1 x VCCI
V
10
µA
µA
150
kV/us
2.8
pF
VCCI = Input-side VCC; VCCO = Output-side VCC
Measured from input pin to same side ground.
6.9 Supply Current Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted).
PARAMETER
TEST CONDITIONS
SUPPLY
CURRENT
MIN
TYP
MAX
ICC1
2.2
2.8
ICC2
3.1
5.2
ICC1
8.3
11.1
ICC2
3.4
5.7
ICC1
5.3
7.0
ICC2
3.7
5.9
ICC1
5.4
7.2
ICC2
7.0
9.7
ICC1
6.3
8.1
ICC2
21.9
26.6
ICC1
2.4
3.5
ICC2
3.6
5.8
ICC1
7.6
10.4
ICC2
5.0
7.6
ICC1
5.1
7.0
ICC2
4.6
7.0
ICC1
5.8
7.8
ICC2
7.4
10.2
UNIT
ISO6760
VI = VCC1 (ISO6760); VI = 0 V (ISO6760 with F suffix)
Supply current - DC signal
VI = 0 V (ISO6760); VI = VCC1 (ISO6760 with F suffix)
1 Mbps
Supply current - AC signal
All channels switching with square
wave clock input; CL = 15 pF
10 Mbps
50 Mbps
mA
ISO6761
VI = VCC1 (ISO6761); VI = 0 V (ISO6761 with F suffix)
Supply current - DC signal
VI = 0 V (ISO6761); VI = VCC1 (ISO6761 with F suffix)
1 Mbps
Supply current - AC signal
All channels switching with square
wave clock input; CL = 15 pF
10 Mbps
50 Mbps
ICC1
8.9
11.4
ICC2
20.0
24.4
mA
ISO6762
10
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: ISO6760-Q1 ISO6761-Q1 ISO6762-Q1 ISO6763-Q1
ISO6760-Q1, ISO6761-Q1, ISO6762-Q1, ISO6763-Q1
www.ti.com.cn
ZHCSLW8B – AUGUST 2021 – REVISED MAY 2022
VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted).
PARAMETER
TEST CONDITIONS
VI = VCC1 (ISO6762); VI = 0 V (ISO6762 with F suffix)
Supply current - DC signal
VI = 0 V (ISO6762); VI = VCC1 (ISO6762 with F suffix)
1 Mbps
Supply current - AC signal
All channels switching with square
wave clock input; CL = 15 pF
10 Mbps
50 Mbps
SUPPLY
CURRENT
MIN
TYP
MAX
ICC1
2.7
4.1
ICC2
3.3
5.2
ICC1
6.9
9.7
ICC2
5.6
8.3
ICC1
5
7
ICC2
4.7
7
ICC1
6.2
8.4
ICC2
7
9.6
ICC1
11.7
14.6
ICC2
17.2
21.1
UNIT
mA
ISO6763
Supply current - DC signal
Supply current - AC signal
VI = VCCI (ISO6763); VI = 0 V (ISO6763 with F suffix)
ICC1, ICC2
3
4.7
VI = 0 V (ISO6763); VI = VCCI (ISO6763 with F suffix)
ICC1, ICC2
6.3
9
1 Mbps
ICC1, ICC2
4.8
7
10 Mbps
ICC1, ICC2
6.6
9
50 Mbps
ICC1, ICC2
14.4
17.8
All channels switching with square
wave clock input; CL = 15 pF
Copyright © 2022 Texas Instruments Incorporated
mA
Submit Document Feedback
Product Folder Links: ISO6760-Q1 ISO6761-Q1 ISO6762-Q1 ISO6763-Q1
11
ISO6760-Q1, ISO6761-Q1, ISO6762-Q1, ISO6763-Q1
www.ti.com.cn
ZHCSLW8B – AUGUST 2021 – REVISED MAY 2022
6.10 Electrical Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted).
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
IOH = -2mA ; See 图 7-1
VOL
Low-level output voltage
IOL = 2mA ; See 图 7-1
MIN
TYP
MAX UNIT
VCCO - 0.2
V
0.2
V
(1)
V
VIT+(IN)
Rising input switching threshold
VIT-(IN)
Falling input switching threshold
0.3 x VCCI
V
VI(HYS)
Input threshold voltage
hysteresis
0.1 x VCCI
V
IIH
High-level input current
VIH = VCCI (1) at INx
IIL
Low-level input current
VIL = 0 V at INx
-10
CMTI
Common mode transient
immunity
VI = VCC or 0 V, VCM = 1200
V; See 图 7-3
100
Ci
Input Capacitance(2)
VI = VCC/ 2 + 0.4×sin(2πft), f =
2 MHz, VCC = 3.3 V
(1)
(2)
0.7 x VCCI
10
µA
µA
150
kV/us
2.8
pF
VCCI = Input-side VCC; VCCO = Output-side VCC
Measured from input pin to same side ground.
6.11 Supply Current Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted).
PARAMETER
TEST CONDITIONS
SUPPLY
CURRENT
MIN
TYP
MAX
ICC1
2.2
2.8
ICC2
3.1
5.1
ICC1
8.3
10.9
ICC2
3.4
5.6
ICC1
5.3
6.9
ICC2
3.5
5.7
ICC1
5.3
7
ICC2
5.9
8.5
UNIT
ISO6760
VI = VCC1 (ISO6760); VI = 0 V (ISO6760 with F suffix)
Supply current - DC signal
VI = 0 V (ISO6760); VI = VCC1 (ISO6760 with F suffix)
1 Mbps
Supply current - AC signal
All channels switching with square
wave clock input; CL = 15 pF
10 Mbps
50 Mbps
ICC1
5.9
7.6
ICC2
16.6
20.9
ICC1
2.4
3.5
ICC2
3.6
5.8
ICC1
7.5
10.3
ICC2
4.9
7.5
ICC1
5
7
ICC2
4.5
6.9
ICC1
5.5
7.5
ICC2
6.5
9.2
mA
ISO6761
VI = VCC1 (ISO6761); VI = 0 V (ISO6761 with F suffix)
Supply current - DC signal
VI = 0 V (ISO6761); VI = VCC1 (ISO6761 with F suffix)
1 Mbps
Supply current - AC signal
All channels switching with square
wave clock input; CL = 15 pF
10 Mbps
50 Mbps
ICC1
7.7
10
ICC2
15.5
19.6
mA
ISO6762
12
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: ISO6760-Q1 ISO6761-Q1 ISO6762-Q1 ISO6763-Q1
ISO6760-Q1, ISO6761-Q1, ISO6762-Q1, ISO6763-Q1
www.ti.com.cn
ZHCSLW8B – AUGUST 2021 – REVISED MAY 2022
VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted).
PARAMETER
TEST CONDITIONS
VI = VCC1 (ISO6762); VI = 0 V (ISO6762 with F suffix)
Supply current - DC signal
VI = 0 V (ISO6762); VI = VCC1 (ISO6762 with F suffix)
1 Mbps
Supply current - AC signal
All channels switching with square
wave clock input; CL = 15 pF
10 Mbps
50 Mbps
SUPPLY
CURRENT
MIN
TYP
MAX
ICC1
2.7
4.1
ICC2
3.3
5.2
ICC1
6.9
9.6
ICC2
5.6
8.2
ICC1
4.9
6.9
ICC2
4.6
6.9
ICC1
5.7
7.9
ICC2
6.2
8.8
ICC1
9.6
12.4
ICC2
13.5
17.1
UNIT
mA
ISO6763
Supply current - DC signal
Supply current - AC signal
VI = VCCI (ISO6763); VI = 0 V (ISO6763 with F suffix)
ICC1, ICC2
3
4.6
VI = 0 V (ISO6763); VI = VCCI (ISO6763 with F suffix)
ICC1, ICC2
6.2
8.9
1 Mbps
ICC1, ICC2
4.8
6.9
10 Mbps
ICC1, ICC2
6
8.4
50 Mbps
ICC1, ICC2
11.6
14.7
All channels switching with square
wave clock input; CL = 15 pF
Copyright © 2022 Texas Instruments Incorporated
mA
Submit Document Feedback
Product Folder Links: ISO6760-Q1 ISO6761-Q1 ISO6762-Q1 ISO6763-Q1
13
ISO6760-Q1, ISO6761-Q1, ISO6762-Q1, ISO6763-Q1
www.ti.com.cn
ZHCSLW8B – AUGUST 2021 – REVISED MAY 2022
6.12 Electrical Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted).
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
IOH = -1mA ; See 图 7-1
VOL
Low-level output voltage
IOL = 1mA ; See 图 7-1
MIN
TYP
MAX UNIT
VCCO - 0.1
V
0.1
V
(1)
V
VIT+(IN)
Rising input switching threshold
VIT-(IN)
Falling input switching threshold
0.3 x VCCI
V
VI(HYS)
Input threshold voltage
hysteresis
0.1 x VCCI
V
IIH
High-level input current
VIH = VCCI (1) at INx
IIL
Low-level input current
VIL = 0 V at INx
-10
CMTI
Common mode transient
immunity
VI = VCC or 0 V, VCM = 1200
V; See 图 7-3
100
Ci
Input Capacitance(2)
VI = VCC/ 2 + 0.4×sin(2πft), f =
2 MHz, VCC = 2.5 V
(1)
(2)
0.7 x VCCI
10
µA
µA
150
kV/us
2.8
pF
VCCI = Input-side VCC; VCCO = Output-side VCC
Measured from input pin to same side ground.
6.13 Supply Current Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted).
PARAMETER
TEST CONDITIONS
SUPPLY
CURRENT
MIN
TYP
MAX
ICC1
2.2
2.8
ICC2
3.1
5.1
ICC1
8.3
10.8
ICC2
3.4
5.6
ICC1
5.2
6.8
ICC2
3.5
5.6
ICC1
5.3
6.9
ICC2
5.3
7.7
UNIT
ISO6760
VI = VCC1 (ISO6760); VI = 0 V (ISO6760 with F suffix)
Supply current - DC signal
VI = 0 V (ISO6760); VI = VCC1 (ISO6760 with F suffix)
1 Mbps
Supply current - AC signal
All channels switching with square
wave clock input; CL = 15 pF
10 Mbps
50 Mbps
ICC1
5.7
7.5
ICC2
13.2
16.9
ICC1
2.4
3.5
ICC2
3.6
5.7
ICC1
7.5
10.3
ICC2
4.9
7.5
ICC1
5
6.9
ICC2
4.4
6.8
ICC1
5.3
7.3
ICC2
5.9
8.5
mA
ISO6761
VI = VCC1 (ISO6761); VI = 0 V (ISO6761 with F suffix)
Supply current - DC signal
VI = 0 V (ISO6761); VI = VCC1 (ISO6761 with F suffix)
1 Mbps
Supply current - AC signal
All channels switching with square
wave clock input; CL = 15 pF
10 Mbps
50 Mbps
ICC1
7
9.3
ICC2
12.7
16.3
mA
ISO6762
14
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: ISO6760-Q1 ISO6761-Q1 ISO6762-Q1 ISO6763-Q1
ISO6760-Q1, ISO6761-Q1, ISO6762-Q1, ISO6763-Q1
www.ti.com.cn
ZHCSLW8B – AUGUST 2021 – REVISED MAY 2022
VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted).
PARAMETER
TEST CONDITIONS
VI = VCC1 (ISO6762); VI = 0 V (ISO6762 with F suffix)
Supply current - DC signal
VI = 0 V (ISO6762); VI = VCC1 (ISO6762 with F suffix)
1 Mbps
Supply current - AC signal
All channels switching with square
wave clock input; CL = 15 pF
10 Mbps
50 Mbps
SUPPLY
CURRENT
MIN
TYP
MAX
ICC1
2.7
4
ICC2
3.3
5.2
ICC1
6.9
9.6
ICC2
5.6
8.2
ICC1
4.9
6.9
ICC2
4.6
6.8
ICC1
5.5
7.6
ICC2
5.8
8.2
ICC1
8.4
11
ICC2
11.2
14.5
UNIT
mA
ISO6763
Supply current - DC signal
Supply current - AC signal
VI = VCCI (ISO6763); VI = 0 V (ISO6763 with F suffix)
ICC1, ICC2
3
4.6
VI = 0 V (ISO6763); VI = VCCI (ISO6763 with F suffix)
ICC1, ICC2
6.2
8.9
1 Mbps
ICC1, ICC2
4.7
6.9
10 Mbps
ICC1, ICC2
5.6
7.9
50 Mbps
ICC1, ICC2
9.8
12.7
All channels switching with square
wave clock input; CL = 15 pF
Copyright © 2022 Texas Instruments Incorporated
mA
Submit Document Feedback
Product Folder Links: ISO6760-Q1 ISO6761-Q1 ISO6762-Q1 ISO6763-Q1
15
ISO6760-Q1, ISO6761-Q1, ISO6762-Q1, ISO6763-Q1
www.ti.com.cn
ZHCSLW8B – AUGUST 2021 – REVISED MAY 2022
Electrical Characteristics—1.8-V Supply
VCC1 = VCC2 = 1.8 V ±10% (over recommended operating conditions unless otherwise noted).
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
IOH = -1mA ; See 图 7-1
VOL
Low-level output voltage
IOL = 1mA ; See 图 7-1
VIT+(IN)
Rising input switching threshold
VIT-(IN)
Falling input switching threshold
VI(HYS)
Input threshold voltage hysteresis
IIH
High-level input current
VIH = VCCI (1) at INx
IIL
Low-level input current
VIL = 0 V at INx
CMTI
Common mode transient immunity
VI = VCC or 0 V, VCM = 1200
V; See 图 7-3
Ci
Input Capacitance(2)
VI = VCC/ 2 + 0.4×sin(2πft), f =
2 MHz, VCC = 1.8 V
(1)
(2)
MIN
TYP
MAX
VCCO - 0.1
UNIT
V
0.1
V
(1)
V
0.7 x VCCI
0.3 x VCCI
V
0.1 x VCCI
V
10
-10
µA
µA
50
75
kV/us
2.8
pF
VCCI = Input-side VCC; VCCO = Output-side VCC
Measured from input pin to same side ground.
6.14 Supply Current Characteristics—1.8-V Supply
VCC1 = VCC2 = 1.8 V ±10% (over recommended operating conditions unless otherwise noted).
PARAMETER
TEST CONDITIONS
SUPPLY
CURRENT
MIN
TYP
MAX
1.5
2.1
UNIT
ISO6760
VI = VCC1 (ISO6760); VI = 0 V (ISO6760 with F suffix)
Supply current - DC signal
VI = 0 V (ISO6760); VI = VCC1 (ISO6760 with F suffix)
1 Mbps
Supply current - AC signal
All channels switching with square
wave clock input; CL = 15 pF
10 Mbps
50 Mbps
ICC1
ICC2
3
5.1
ICC1
7.3
10.3
ICC2
3.3
5.6
ICC1
4.4
6.2
ICC2
3.3
5.5
ICC1
4.5
6.3
ICC2
4.6
7
ICC1
4.8
6.7
ICC2
10.1
13
ICC1
1.8
2.9
ICC2
3.4
5.7
ICC1
6.7
9.8
ICC2
4.6
7.4
ICC1
4.3
6.4
ICC2
4.1
6.7
ICC1
4.6
6.7
ICC2
5.2
7.9
ICC1
5.8
8.1
ICC2
9.9
13
mA
ISO6761
VI = VCC1 (ISO6761); VI = 0 V (ISO6761 with F suffix)
Supply current - DC signal
VI = 0 V (ISO6761); VI = VCC1 (ISO6761 with F suffix)
1 Mbps
Supply current - AC signal
All channels switching with square
wave clock input; CL = 15 pF
10 Mbps
50 Mbps
mA
ISO6762
16
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: ISO6760-Q1 ISO6761-Q1 ISO6762-Q1 ISO6763-Q1
ISO6760-Q1, ISO6761-Q1, ISO6762-Q1, ISO6763-Q1
www.ti.com.cn
ZHCSLW8B – AUGUST 2021 – REVISED MAY 2022
VCC1 = VCC2 = 1.8 V ±10% (over recommended operating conditions unless otherwise noted).
PARAMETER
TEST CONDITIONS
VI = VCC1 (ISO6762); VI = 0 V (ISO6762 with F suffix)
MIN
ICC1
TYP
MAX
2.2
3.6
ICC2
3
5
ICC1
6.2
9.2
ICC2
5.1
8
ICC1
4.3
6.5
ICC2
4.2
6.6
ICC1
4.7
7
ICC2
5
7.6
ICC1
6.8
9.3
ICC2
8.9
11.8
VI = VCCI (ISO6763); VI = 0 V (ISO6763 with F suffix)
ICC1, ICC2
2.6
4.3
VI = 0 V (ISO6763); VI = VCCI (ISO6763 with F suffix)
ICC1, ICC2
5.7
8.6
1 Mbps
ICC1, ICC2
4.2
6.5
10 Mbps
ICC1, ICC2
4.9
7.3
50 Mbps
ICC1, ICC2
7.9
10.5
Supply current - DC signal
VI = 0 V (ISO6762); VI = VCC1 (ISO6762 with F suffix)
1 Mbps
Supply current - AC signal
SUPPLY
CURRENT
All channels switching with square
wave clock input; CL = 15 pF
10 Mbps
50 Mbps
UNIT
mA
ISO6763
Supply current - DC signal
Supply current - AC signal
All channels switching with square
wave clock input; CL = 15 pF
Copyright © 2022 Texas Instruments Incorporated
mA
Submit Document Feedback
Product Folder Links: ISO6760-Q1 ISO6761-Q1 ISO6762-Q1 ISO6763-Q1
17
ISO6760-Q1, ISO6761-Q1, ISO6762-Q1, ISO6763-Q1
www.ti.com.cn
ZHCSLW8B – AUGUST 2021 – REVISED MAY 2022
6.15 Switching Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
11
18
ns
7
ns
6
ns
6
ns
4.5
ns
4.5
ns
300
us
0.3
us
ISO676x
tPLH, tPHL
Propagation delay time
Propagation delay
time
PWD
Pulse width distortion(1) |tPHL – tPLH|
See 图 7-1
Pulse width
distortion(1) |tPHL –
tPLH|
tsk(o)
Channel-toChannel-to-channel output skew time(2) channel output
skew time(2)
tsk(pp)
Part-to-part skew time(3)
Part-to-part skew
time(3)
tr
Output signal rise time
Output signal rise
time
Same-direction channels
See 图 7-1
tf
Output signal fall time
Output signal fall
time
tPU
Time from UVLO to valid output data
Time from UVLO to
valid output data
tDO
Default output delay time from input
power loss
Default output
delay time from
input power loss
Measured from the time VCC goes
below 1.2V. See 图 7-2
tie
Time interval error
Time interval error
216 – 1 PRBS data at 50 Mbps
(1)
(2)
(3)
18
0.1
1
ns
Also known as pulse skew.
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: ISO6760-Q1 ISO6761-Q1 ISO6762-Q1 ISO6763-Q1
ISO6760-Q1, ISO6761-Q1, ISO6762-Q1, ISO6763-Q1
www.ti.com.cn
ZHCSLW8B – AUGUST 2021 – REVISED MAY 2022
6.16 Switching Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
11
18
ns
7
ns
6
ns
7
ns
3.2
ns
3.2
ns
300
us
0.3
us
ISO676x
tPLH, tPHL
Propagation delay time
Propagation delay
time
PWD
Pulse width distortion(1) |tPHL – tPLH|
See 图 7-1
Pulse width
distortion(1) |tPHL –
tPLH|
tsk(o)
Channel-toChannel-to-channel output skew time(2) channel output
skew time(2)
tsk(pp)
Part-to-part skew time(3)
Part-to-part skew
time(3)
tr
Output signal rise time
Output signal rise
time
Same-direction channels
See 图 7-1
tf
Output signal fall time
Output signal fall
time
tPU
Time from UVLO to valid output data
Time from UVLO to
valid output data
tDO
Default output delay time from input
power loss
Default output
delay time from
input power loss
Measured from the time VCC goes
below 1.2V. See 图 7-2
tie
Time interval error
Time interval error
216 – 1 PRBS data at 50 Mbps
(1)
(2)
(3)
0.1
1
ns
Also known as pulse skew.
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: ISO6760-Q1 ISO6761-Q1 ISO6762-Q1 ISO6763-Q1
19
ISO6760-Q1, ISO6761-Q1, ISO6762-Q1, ISO6763-Q1
www.ti.com.cn
ZHCSLW8B – AUGUST 2021 – REVISED MAY 2022
6.17 Switching Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
12
20.5
ns
7.1
ns
6
ns
7
ns
4
ns
4
ns
300
us
0.3
us
ISO676x
tPLH, tPHL
Propagation delay time
Propagation delay
time
PWD
Pulse width distortion(1) |tPHL – tPLH|
See 图 7-1
Pulse width
distortion(1) |tPHL –
tPLH|
tsk(o)
Channel-toChannel-to-channel output skew time(2) channel output
skew time(2)
tsk(pp)
Part-to-part skew time(3)
Part-to-part skew
time(3)
tr
Output signal rise time
Output signal rise
time
Same-direction channels
See 图 7-1
tf
Output signal fall time
Output signal fall
time
tPU
Time from UVLO to valid output data
Time from UVLO to
valid output data
tDO
Default output delay time from input
power loss
Default output
delay time from
input power loss
Measured from the time VCC goes
below 1.2V. See 图 7-2
tie
Time interval error
Time interval error
216 – 1 PRBS data at 50 Mbps
(1)
(2)
(3)
20
0.1
1
ns
Also known as pulse skew.
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: ISO6760-Q1 ISO6761-Q1 ISO6762-Q1 ISO6763-Q1
ISO6760-Q1, ISO6761-Q1, ISO6762-Q1, ISO6763-Q1
www.ti.com.cn
ZHCSLW8B – AUGUST 2021 – REVISED MAY 2022
6.18 Switching Characteristics—1.8-V Supply
VCC1 = VCC2 = 1.8 V ±5% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
15
24
ns
8.2
ns
6
ns
8.8
ns
4.7
ns
4.7
ns
300
us
0.3
us
ISO676x
tPLH, tPHL
Propagation delay time
Propagation delay
time
PWD
Pulse width distortion |tPHL – tPLH|
Pulse width
distortion |tPHL –
tPLH|
tsk(o)
Channel-toChannel-to-channel output skew time(1) channel output
skew time(1)
tsk(pp)
Part-to-part skew time(2)
Part-to-part skew
time(2)
tr
Output signal rise time
Output signal rise
time
See 图 7-1
Same-direction channels
See 图 7-1
tf
Output signal fall time
Output signal fall
time
tPU
Time from UVLO to valid output data
Time from UVLO to
valid output data
tDO
Default output delay time from input
power loss
Default output
delay time from
input power loss
Measured from the time VCC goes
below 1.2V. See 图 7-2
tie
Time interval error
Time interval error
216 – 1 PRBS data at 50 Mbps
(1)
(2)
0.1
1
ns
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: ISO6760-Q1 ISO6761-Q1 ISO6762-Q1 ISO6763-Q1
21
ISO6760-Q1, ISO6761-Q1, ISO6762-Q1, ISO6763-Q1
www.ti.com.cn
ZHCSLW8B – AUGUST 2021 – REVISED MAY 2022
6.19 Insulation Characteristics Curves
2000
Vcc = 5.5V
Vcc = 3.6V
Vcc = 2.75V
Vcc = 1.89V
800
600
400
200
1800
Safety Limiting Power (mW)
Safety Limiting Current (mA)
1000
1600
1400
1200
1000
800
600
400
200
0
0
0
20
40
60
80
100
120
Ambient Temperature ( C)
140
160
图 6-1. Thermal Derating Curve for Safety Limiting
Current for DW-16 Package
22
Submit Document Feedback
0
20
40
60
80
100
120
Ambient Temperature ( C)
140
160
图 6-2. Thermal Derating Curve for Safety Limiting
Power for DW-16 Package
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: ISO6760-Q1 ISO6761-Q1 ISO6762-Q1 ISO6763-Q1
ISO6760-Q1, ISO6761-Q1, ISO6762-Q1, ISO6763-Q1
www.ti.com.cn
ZHCSLW8B – AUGUST 2021 – REVISED MAY 2022
6.20 Typical Characteristics
16
14
Supply Current (mA)
14
12
10
at
at
at
at
at
at
at
at
1.8 V
1.8 V
2.5 V
2.5 V
3.3 V
3.3 V
5V
5V
8
6
2
8
1.8 V
1.8 V
2.5 V
2.5 V
3.3 V
3.3 V
5V
5V
6
2
0
10
20
30
Data Rate (Mbps)
TA = 25°C
40
50
0
CL = 15 pF
10
20
30
Data Rate (Mbps)
TA = 25°C
图 6-3. ISO6760-Q1 Supply Current vs Data Rate
(With 15-pF Load)
40
50
CL = No Load
图 6-4. ISO6760-Q1 Supply Current vs Data Rate
(With No Load)
18
14
14
12
10
at
at
at
at
at
at
at
at
1.8 V
1.8 V
2.5 V
2.5 V
3.3 V
3.3 V
5V
5V
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
12
Supply Current (mA)
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
16
Supply Current (mA)
10
at
at
at
at
at
at
at
at
4
4
8
6
10
8
at
at
at
at
at
at
at
at
1.8 V
1.8 V
2.5 V
2.5 V
3.3 V
3.3 V
5V
5V
6
4
4
2
2
0
10
20
30
Data Rate (Mbps)
TA = 25°C
40
50
0
CL = 15 pF
10
20
30
Data Rate (Mbps)
TA = 25°C
图 6-5. ISO6761-Q1 Supply Current vs Data Rate
(With 15-pF Load)
40
50
CL = No Load
图 6-6. ISO6761-Q1 Supply Current vs Data Rate
(With No Load)
16
12
12
10
at
at
at
at
at
at
at
at
1.8 V
1.8 V
2.5 V
2.5 V
3.3 V
3.3 V
5V
5V
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
10
Supply Current (mA)
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
14
Supply Current (mA)
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
12
Supply Current (mA)
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
8
6
8
at
at
at
at
at
at
at
at
1.8 V
1.8 V
2.5 V
2.5 V
3.3 V
3.3 V
5V
5V
6
4
4
2
2
0
10
TA = 25°C
20
30
Data Rate (Mbps)
40
50
CL = 15 pF
图 6-7. ISO6762-Q1 Supply Current vs Data Rate
(With 15-pF Load)
Copyright © 2022 Texas Instruments Incorporated
0
10
TA = 25°C
20
30
Data Rate (Mbps)
40
50
CL = No Load
图 6-8. ISO6762-Q1 Supply Current vs Data Rate
(With No Load)
Submit Document Feedback
Product Folder Links: ISO6760-Q1 ISO6761-Q1 ISO6762-Q1 ISO6763-Q1
23
ISO6760-Q1, ISO6761-Q1, ISO6762-Q1, ISO6763-Q1
www.ti.com.cn
ZHCSLW8B – AUGUST 2021 – REVISED MAY 2022
14
9
ICC1 at 1.8 V
ICC2 at 1.8 V
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
10
8
Supply Current (mA)
Supply Current (mA)
12
8
6
10
20
30
Data Rate (Mbps)
TA = 25°C
40
50
0
CL = 15 pF
4
3
2
1
-10
-5
High-Level Output Current (mA)
14
13
12
11
10
tPHL at 1.8 V
tPLH at 1.8 V
tPHL at 2.5 V
8
-55
0
TA = 25°C
图 6-11. High-Level Output Voltage vs High-level
Output Current
1.6
0.7
Low-Level Output Voltage (V)
0.8
1.55
1.5
1.45
1.4
1.35
VCC1 +
VCC1 VCC2 +
VCC2 -
-35
-15
tPLH at 2.5 V
tPHL at 3.3 V
tPLH at 3.3 V
5
25
45
65
Free-Air Temperature ( C)
tPHL at 5 V
tPLH at 5V
85
105
125
图 6-12. Propagation Delay Time vs Free-Air
Temperature
1.65
1.2
-55
CL = No Load
15
9
0
-15
1.25
50
16
5
1.3
40
17
VCC1 at 1.8 V
VCC2 at 2.5 V
VCC1 at 3.3 V
VCC2 at 5 V
Propagation Delay Time (ns)
6
20
30
Data Rate (Mbps)
图 6-10. ISO6763-Q1 Supply Current vs Data Rate
(With No Load)
8
7
10
TA = 25°C
图 6-9. ISO6763-Q1 Supply Current vs Data Rate
(With 15-pF Load)
High-Level Output Voltage (V)
6
4
0
Power Supply UVLO Threshold (V)
7
5
4
VCC1 at 1.8 V
VCC2 at 2.5 V
VCC1 at 3.3 V
VCC2 at 5 V
0.6
0.5
0.4
0.3
0.2
0.1
0
-5
45
Free-Air Temperature ( C)
95
125
图 6-13. Power Supply Undervoltage Threshold vs
Free-Air Temperature
24
ICC1 at 1.8 V
ICC2 at 1.8 V
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
Submit Document Feedback
0
5
10
Low-Level Output Current (mA)
15
TA = 25°C
图 6-14. Low-Level Output Voltage vs Low-Level
Output Current
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: ISO6760-Q1 ISO6761-Q1 ISO6762-Q1 ISO6763-Q1
ISO6760-Q1, ISO6761-Q1, ISO6762-Q1, ISO6763-Q1
www.ti.com.cn
ZHCSLW8B – AUGUST 2021 – REVISED MAY 2022
7 Parameter Measurement Information
Isolation Barrier
IN
Input
Generator
(See Note A)
VI
VCCI
VI
OUT
50%
50%
0V
tPLH
CL
See Note B
VO
50
tPHL
VOH
90%
50%
VO
50%
10%
VOL
tf
tr
Copyright © 2016, Texas Instruments Incorporated
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3ns, ZO
B.
= 50 Ω. At the input, 50 Ω resistor is required to terminate Input Generator signal. It is not needed in actual application.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
图 7-1. Switching Characteristics Test Circuit and Voltage Waveforms
VI See Note B
VCC
VCC
Isolation Barrier
IN = 0 V (Devices without suffix F)
IN = VCC (Devices with suffix F)
VI
IN
1.4 V
0V
OUT
VO
tDO
CL
See Note A
default high
VOH
50%
VO
VOL
default low
A.
B.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Power Supply Ramp Rate = 10 mV/ns
图 7-2. Default Output Delay Time Test Circuit and Voltage Waveforms
VCCO
Isolation Barrier
VCCI
IN
S1
Pass-fail criteria:
The output must
remain stable.
OUT
+
CL
See Note A
VOH or VOL
±
GNDI
+
VCM ±
GNDO
A.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
B.
For optimized CMTI performance, a 0.1 μF + 1 μF decoupling capacitor should be placed close to VCC1 and VCC2. Please see 节 11.2
for capacitor placement details. A recommended 0.1μF capacitor is LLL185R71A104MA11L (CAP CER 0.1UF 10V X7R 0306 - LW
Reversed Low ESL Chip Ceramic Capacitors) or equivalent.
图 7-3. Common-Mode Transient Immunity Test Circuit
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: ISO6760-Q1 ISO6761-Q1 ISO6762-Q1 ISO6763-Q1
25
ISO6760-Q1, ISO6761-Q1, ISO6762-Q1, ISO6763-Q1
www.ti.com.cn
ZHCSLW8B – AUGUST 2021 – REVISED MAY 2022
8 Detailed Description
8.1 Overview
The ISO676x-Q1 family of devices have an ON-OFF keying (OOK) modulation scheme to transmit the digital
data across a silicon dioxide based isolation barrier. The transmitter sends a high frequency carrier across the
barrier to represent one digital state and sends no signal to represent the other digital state. The receiver
demodulates the signal after advanced signal conditioning and produces the output through a buffer stage. If the
ENx pin is low then the output goes to high impedance. The ISO676x-Q1 devices also incorporate advanced
circuit techniques to maximize the CMTI performance and minimize the radiated emissions due to the high
frequency carrier and IO buffer switching. The conceptual block diagram of a digital capacitive isolator, 图 8-1,
shows a functional block diagram of a typical channel.
8.2 Functional Block Diagram
Transmitter
Receiver
EN
TX IN
OOK
Modulation
TX Signal
Conditioning
SiO2 based
Capacitive
Isolation
Barrier
RX Signal
Conditioning
Envelope
Detection
RX OUT
Emissions
Reduction
Techniques
Oscillator
Copyright © 2016, Texas Instruments Incorporated
图 8-1. Conceptual Block Diagram of a Digital Capacitive Isolator
图 8-2 shows a conceptual detail of how the ON-OFF keying scheme works.
TX IN
Carrier signal through
isolation barrier
RX OUT
图 8-2. On-Off Keying (OOK) Based Modulation Scheme
26
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: ISO6760-Q1 ISO6761-Q1 ISO6762-Q1 ISO6763-Q1
ISO6760-Q1, ISO6761-Q1, ISO6762-Q1, ISO6763-Q1
www.ti.com.cn
ZHCSLW8B – AUGUST 2021 – REVISED MAY 2022
8.3 Feature Description
表 8-1 provides an overview of the device features.
表 8-1. Device Features
(1)
PART NUMBER
CHANNEL DIRECTION
MAXIMUM DATA
RATE
DEFAULT
OUTPUT
PACKAGE
RATED ISOLATION(1)
ISO6760-Q1
6 Forward, 0 Reverse
50 Mbps
High
DW-16
5000 VRMS / 7071 VPK
ISO6760F-Q1
6 Forward, 0 Reverse
50 Mbps
Low
DW-16
5000 VRMS / 7071 VPK
ISO6761-Q1
5 Forward, 1 Reverse
50 Mbps
High
DW-16
5000 VRMS / 7071 VPK
ISO6761F-Q1
5 Forward, 1 Reverse
50 Mbps
Low
DW-16
5000 VRMS / 7071 VPK
ISO6762-Q1
4 Forward, 2 Reverse
50 Mbps
High
DW-16
5000 VRMS / 7071 VPK
ISO6762F-Q1
4 Forward, 2 Reverse
50 Mbps
Low
DW-16
5000 VRMS / 7071 VPK
ISO6763-Q1
3 Forward, 3 Reverse
50 Mbps
High
DW-16
5000 VRMS / 7071 VPK
ISO6763F-Q1
3 Forward, 3 Reverse
50 Mbps
Low
DW-16
5000 VRMS / 7071 VPK
See for detailed isolation ratings.
8.3.1 Electromagnetic Compatibility (EMC) Considerations
Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge
(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances
are regulated by international standards such as IEC 61000-4-x and CISPR 25. Although system-level
performance and reliability depends, to a large extent, on the application board design and layout, the ISO676xQ1 family of devices incorporates many chip-level design improvements for overall system robustness. Some of
these improvements include:
• Robust ESD protection cells for input and output signal pins and inter-chip bond pads.
• Low-resistance connectivity of ESD cells to supply and ground pins.
• Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.
• Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance
path.
• PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic
SCRs.
• Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: ISO6760-Q1 ISO6761-Q1 ISO6762-Q1 ISO6763-Q1
27
ISO6760-Q1, ISO6761-Q1, ISO6762-Q1, ISO6763-Q1
www.ti.com.cn
ZHCSLW8B – AUGUST 2021 – REVISED MAY 2022
8.4 Device Functional Modes
表 8-2 lists the functional modes for the ISO676x-Q1 devices.
表 8-2. Function Table
VCCI (1)
VCCO
PU
(1)
(2)
(3)
INPUT
(INx) (3)
OUTPUT
(OUTx)
H
H
L
L
Open
Default
Default mode: When INx is open, the corresponding channel output goes to its
default logic state. Default is High for ISO676x-Q1 and Low for ISO676x-Q1
with F suffix.
Default mode: When VCCI is unpowered, a channel output assumes the logic
state based on the selected default option. Default is High for ISO676x-Q1 and
Low for ISO676x-Q1 with F suffix. When VCCI transitions from unpowered to
powered-up, a channel output assumes the logic state of the input. When VCCI
transitions from powered-up to unpowered, channel output assumes the
selected default state.
COMMENTS
Normal Operation: A channel output assumes the logic state of its input.
PU
PD
PU
X
Default
X
PD
X
Undetermined
When VCCO is unpowered, a channel output is undetermined(2). When VCCO
transitions from unpowered to powered-up, a channel output assumes the
logic state of the input.
VCCI = Input-side VCC; VCCO = Output-side VCC; PU = Powered up (VCC ≥ 1.71 V); PD = Powered down (VCC ≤ 1.05 V); X =
Irrelevant; H = High level; L = Low level ; Z = High Impedance
The outputs are in undetermined state when 1.05 V < VCCI, VCCO < 1.71 V and 1.89 V < VCCI, VCCO < 2.25 V
A strongly driven input signal can weakly power the floating VCC through an internal protection diode and cause undetermined output
8.4.1 Device I/O Schematics
Input (Devices with F suffix)
Input (Devices without F suffix)
VCCI
VCCI
VCCI
VCCI
VCCI
VCCI
VCCI
1.5 M
985
985
INx
INx
1.5 M
Output
VCCO
~20
OUTx
图 8-3. Device I/O Schematics
28
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: ISO6760-Q1 ISO6761-Q1 ISO6762-Q1 ISO6763-Q1
ISO6760-Q1, ISO6761-Q1, ISO6762-Q1, ISO6763-Q1
www.ti.com.cn
ZHCSLW8B – AUGUST 2021 – REVISED MAY 2022
9 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The ISO676x-Q1 devices are high-performance, six-channel digital isolators. The ISO676x-Q1 devices use
single-ended CMOS-logic switching technology. The supply voltage range is from 1.71 V to 5.5 V for both
supplies, VCC1 and VCC2. Since an isolation barrier separates the two sides, each side can be sourced
independently with any voltage within recommended operating conditions. As an example, it is possible to
supply ISO676x-Q1 VCC1 with 3.3 V (which is within 1.71 V to 5.5 V) and VCC2 with 5V (which is also within 1.71
V to 5.5 V). You can use the digital isolator as a logic-level translator in addition to providing isolation. When
designing with digital isolators, keep in mind that because of the single-ended design structure, digital isolators
do not conform to any specific interface standard and are only intended for isolating single-ended CMOS or TTL
digital signal lines. The isolator is typically placed between the data controller (that is, MCU or FPGA), and a
data converter or a line transceiver, regardless of the interface type or standard.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: ISO6760-Q1 ISO6761-Q1 ISO6762-Q1 ISO6763-Q1
29
ISO6760-Q1, ISO6761-Q1, ISO6762-Q1, ISO6763-Q1
www.ti.com.cn
ZHCSLW8B – AUGUST 2021 – REVISED MAY 2022
9.2 Typical Application
图 9-1 shows the isolated serial-peripheral interface (SPI) and controller-area network (CAN) interface
implementation.
VS
10 F
3.3 V
2
Vcc
MBR0520L
1:1.33
3
D2
1
SN6501-Q1
10 F 0.1 F
1
D1
GND
4
IN
OUT
5
ISO 3.3V
TPS76333-Q1 10 F
3
2
EN
GND
2
1 µF
4
MBR0520L
GND
6
22 µF
GND
0.1 µF
0.1 F
0.1 F
2
SPISTEA
44
SPICLKA
SPISIMOA
SPISOMIA
TMS320F28035Q
CANRXA
CANTXA
VSS
6, 28
3
33
4
36
6
34
INA
25
OUTA
OUTB
INB
INC
OUTE
OUTF
5
31
32
7
26
8
16
VCC2
1
VCC1
0.1 F
VDDIO
VOUT
5
ISO Barrier
29, 57
VIN
REF5025A-Q1
ISO6762-Q1
15
33
14
34
36
OUTC
INE
INF
5
4
CS
CH0
SCLK
28
16 Analog
Inputs
ADS7953-Q1
SDI
SDO
CH15
BDGND
27
13
AGND
11
REFM
30
1, 22
11
0.1 F
10
IND
OUTD 12
GND1
GND2
8
7
AINP MXO +VBD +VA REFP
3
4
9
1
VCC
R
RS 8
10
CANH
SN65HVD231Q-Q1
D
CANL
GND
(optional)
CAN Bus
7
6 10
(optional)
Vref 5
2
SM712
4.7 nF /
2 kV
图 9-1. Isolated SPI and CAN Interface
30
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: ISO6760-Q1 ISO6761-Q1 ISO6762-Q1 ISO6763-Q1
ISO6760-Q1, ISO6761-Q1, ISO6762-Q1, ISO6763-Q1
www.ti.com.cn
ZHCSLW8B – AUGUST 2021 – REVISED MAY 2022
9.2.1 Design Requirements
To design with these devices, use the parameters listed in 表 9-1.
表 9-1. Design Parameters
PARAMETER
VALUE
Supply voltage, VCC1 and VCC2
1.71 V to 1.89 V and 2.25 V to 5.5 V
Decoupling capacitor between VCC1 and GND1
0.1 µF
Decoupling capacitor from VCC2 and GND2
0.1 µF
9.2.2 Detailed Design Procedure
Unlike optocouplers, which require external components to improve performance, provide bias, or limit current,
the ISO676x-Q1 family of devices only require two external bypass capacitors to operate.
0.1 µF
0.1 µF
VCC1
1
16
VCC2
INA
2
15
OUTA
INB
3
14
OUTB
INC
4
13
OUTC
OUTD
5
12
IND
OUTE
6
11
INE
OUTF
7
10
INF
8
9
GND2
GND1
图 9-2. Typical ISO676x-Q1 Circuit Hook-up
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: ISO6760-Q1 ISO6761-Q1 ISO6762-Q1 ISO6763-Q1
31
ISO6760-Q1, ISO6761-Q1, ISO6762-Q1, ISO6763-Q1
www.ti.com.cn
ZHCSLW8B – AUGUST 2021 – REVISED MAY 2022
9.2.3 Application Curve
1 V/ div
0.75 V/ div
The following typical eye diagrams of the ISO676x-Q1 family of devices indicates low jitter and wide open eye at
the maximum data rate of 50 Mbps.
Time = 5 ns / div
图 9-3. Eye Diagram at 50 Mbps PRBS 216 – 1, 5 V
and 25°C
图 9-4. Eye Diagram at 50 Mbps PRBS 216 – 1, 3.3
V and 25°C
0.5 V/ div
0.5 V/ div
Time = 5 ns / div
Time = 5 ns / div
Time = 5 ns / div
图 9-5. Eye Diagram at 50 Mbps PRBS
V and 25°C
216
– 1, 2.5
图 9-6. Eye Diagram at 50 Mbps PRBS 216 – 1, 1.8
V and 25°C
9.2.3.1 Insulation Lifetime
Insulation lifetime projection data is collected by using industry-standard Time Dependent Dielectric Breakdown
(TDDB) test method. In this test, all pins on each side of the barrier are tied together creating a two-terminal
device and high voltage applied between the two sides; See 图 9-7 for TDDB test setup. The insulation
breakdown data is collected at various high voltages switching at 60 Hz over temperature. For reinforced
insulation, VDE standard requires the use of TDDB projection line with failure rate of less than 1 part per million
(ppm). Even though the expected minimum insulation lifetime is 20 years at the specified working isolation
voltage, VDE reinforced certification requires additional safety margin of 20% for working voltage and 87.5% for
lifetime which translates into minimum required insulation lifetime of 37.5 years at a working voltage that's 20%
higher than the specified value.
图 9-8 shows the intrinsic capability of the isolation barrier to withstand high voltage stress over its lifetime.
Based on the TDDB data, the intrinsic capability of the insulation is 1500 VRMS with a lifetime of 220 years. Other
factors, such as package size, pollution degree, material group, etc. can further limit the working voltage of the
component. The working voltage of DW-16 package is specified upto 1500 VRMS. At the lower working voltages,
the corresponding insulation lifetime is much longer than 220 years.
32
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: ISO6760-Q1 ISO6761-Q1 ISO6762-Q1 ISO6763-Q1
ISO6760-Q1, ISO6761-Q1, ISO6762-Q1, ISO6763-Q1
www.ti.com.cn
ZHCSLW8B – AUGUST 2021 – REVISED MAY 2022
A
Vcc 1
Vcc 2
Time Counter
> 1 mA
DUT
GND 1
GND 2
VS
Oven at 150 °C
图 9-7. Test Setup for Insulation Lifetime Measurement
图 9-8. Insulation Lifetime Projection Data
10 Power Supply Recommendations
To help ensure reliable operation at data rates and supply voltages, a 0.1-μF bypass capacitor is recommended
at the input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins
as possible. If only a single primary-side power supply is available in an application, isolated power can be
generated for the secondary-side with the help of a transformer driver. For automotive applications, please use
SN6501-Q1 or SN6505B-Q1. For such applications, detailed power supply design and transformer selection
recommendations are available in SN6501-Q1 Transformer Driver for Isolated Power Supplies or SN6505B-Q1
Automotive, low-noise, 1-A, 420-kHz transformer driver with soft start for isolated power supplies.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: ISO6760-Q1 ISO6761-Q1 ISO6762-Q1 ISO6763-Q1
33
ISO6760-Q1, ISO6761-Q1, ISO6762-Q1, ISO6763-Q1
www.ti.com.cn
ZHCSLW8B – AUGUST 2021 – REVISED MAY 2022
11 Layout
11.1 Layout Guidelines
A minimum of two layers is required to accomplish a low EMI PCB design. To further improve EMI, a four layer
board can be used (see 图 11-2). Layer stacking for a four layer board should be in the following order (top-tobottom): high-speed signal layer, ground plane, power plane and low-frequency signal layer.
• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/inch2.
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to
the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also
the power and ground plane of each power system can be placed closer together, thus increasing the highfrequency bypass capacitance significantly.
For detailed layout recommendations, refer to the Digital Isolator Design Guide.
11.1.1 PCB Material
For digital circuit boards operating below 150 Mbps, (or rise and fall times higher than 1 ns), and trace lengths of
up to 10 inches, use standard FR-4 UL94V-0 printed circuit boards. This PCB is preferred over cheaper
alternatives due to its lower dielectric losses at high frequencies, less moisture absorption, greater strength and
stiffness, and self-extinguishing flammability-characteristics.
34
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: ISO6760-Q1 ISO6761-Q1 ISO6762-Q1 ISO6763-Q1
ISO6760-Q1, ISO6761-Q1, ISO6762-Q1, ISO6763-Q1
www.ti.com.cn
ZHCSLW8B – AUGUST 2021 – REVISED MAY 2022
11.2 Layout Example
Solid supply islands reduce
inductance because large peak
currents flow into the VCC pin
0.5 mm
maximum
from VCC1
0.5 mm
maximum
from VCC2
VCC1
VCC2
1
16
0.1 …F
0.1 …F
I/O pins
routed
through
alternate
layer with
vias
2
15
3
14
4
13
5
12
6
11
7
10
8
9
GND2
GND1
Solid ground islands help
dissipate heat through PCB
图 11-1. Layout Example
High-speed traces
10 mils
Ground plane
40 mils
Keep this
space free
from planes,
traces, pads,
and vias
FR-4
0r ~ 4.5
Power plane
10 mils
Low-speed traces
图 11-2. Four Layer Board Layout Example
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: ISO6760-Q1 ISO6761-Q1 ISO6762-Q1 ISO6763-Q1
35
ISO6760-Q1, ISO6761-Q1, ISO6762-Q1, ISO6763-Q1
www.ti.com.cn
ZHCSLW8B – AUGUST 2021 – REVISED MAY 2022
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, Digital Isolator Design Guide
• Texas Instruments, Digital Isolator Design Guide
• Texas Instruments, Isolation Glossary
• Texas Instruments, How to use isolation to improve ESD, EFT, and Surge immunity in industrial systems
application report
• Texas Instruments, SN6505x-Q1 Low-Noise 1-A Transformer Drivers for Isolated Power Supplies
• Texas Instruments, TCAN1044-Q1 Automotive Fault-Protected CAN FD Transceiver
• Texas Instruments, TPS763xx-Q1 Low-Power, 150-mA, Low-Dropout Linear Regulators data sheet
• Texas Instruments, TMS320F2803x Piccolo™ Microcontrollers data sheet
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
36
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: ISO6760-Q1 ISO6761-Q1 ISO6762-Q1 ISO6763-Q1
ISO6760-Q1, ISO6761-Q1, ISO6762-Q1, ISO6763-Q1
www.ti.com.cn
ZHCSLW8B – AUGUST 2021 – REVISED MAY 2022
PACKAGE OUTLINE
DW0016A
SOIC - 2.65 mm max height
SCALE 1.500
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
14X 1.27
16
1
2X
8.89
10.5
10.1
NOTE 3
8
9
0.51
0.31
0.25
C A B
16X
7.6
7.4
NOTE 4
B
2.65 MAX
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 -8
1.27
0.40
DETAIL A
(1.4)
TYPICAL
4220721/A 07/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
www.ti.com
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: ISO6760-Q1 ISO6761-Q1 ISO6762-Q1 ISO6763-Q1
37
ISO6760-Q1, ISO6761-Q1, ISO6762-Q1, ISO6763-Q1
www.ti.com.cn
ZHCSLW8B – AUGUST 2021 – REVISED MAY 2022
EXAMPLE BOARD LAYOUT
DW0016A
SOIC - 2.65 mm max height
SOIC
16X (2)
SEE
DETAILS
SYMM
16
1
16X (0.6)
SYMM
14X (1.27)
9
8
R0.05 TYP
(9.3)
LAND PATTERN EXAMPLE
SCALE:7X
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
0.07 MAX
ALL AROUND
METAL
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220721/A 07/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
38
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: ISO6760-Q1 ISO6761-Q1 ISO6762-Q1 ISO6763-Q1
ISO6760-Q1, ISO6761-Q1, ISO6762-Q1, ISO6763-Q1
www.ti.com.cn
ZHCSLW8B – AUGUST 2021 – REVISED MAY 2022
EXAMPLE STENCIL DESIGN
DW0016A
SOIC - 2.65 mm max height
SOIC
16X (2)
SYMM
1
16
16X (0.6)
SYMM
14X (1.27)
9
8
R0.05 TYP
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:7X
4220721/A 07/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: ISO6760-Q1 ISO6761-Q1 ISO6762-Q1 ISO6763-Q1
39
ISO6760-Q1, ISO6761-Q1, ISO6762-Q1, ISO6763-Q1
www.ti.com.cn
ZHCSLW8B – AUGUST 2021 – REVISED MAY 2022
13.1 Package Option Addendum
Packaging Information
Package Type
Package
Drawing
Pins
Package Qty
Eco Plan(2)
ISO6760QDWR ACTIVE
Q1
SOIC
DW
16
2000
Green (RoHS & NIPDAU
no Sb/Br)
Level-2-260C-1 -40 to 125
YEAR
ISO6760
ISO6760FQDW ACTIVE
RQ1
SOIC
DW
16
2000
Green (RoHS & NIPDAU
no Sb/Br)
Level-2-260C-1 -40 to 125
YEAR
ISO6760
F
ISO6761QDWR ACTIVE
Q1
SOIC
DW
16
2000
Green (RoHS & NIPDAU
no Sb/Br)
Level-2-260C-1 -40 to 125
YEAR
ISO6761
ISO6761FQDW ACTIVE
RQ1
SOIC
DW
16
2000
Green (RoHS & NIPDAU
no Sb/Br)
Level-2-260C-1 -40 to 125
YEAR
ISO6761
F
ISO6762QDWR ACTIVE
Q1
SOIC
DW
16
2000
Green (RoHS & NIPDAU
no Sb/Br)
Level-2-260C-1 -40 to 125
YEAR
ISO6762
ISO6762FQDW ACTIVE
RQ1
SOIC
DW
16
2000
Green (RoHS & NIPDAU
no Sb/Br)
Level-2-260C-1 -40 to 125
YEAR
ISO6762
F
ISO6763QDWR ACTIVE
Q1
SOIC
DW
16
2000
Green (RoHS & NIPDAU
no Sb/Br)
Level-2-260C-1 -40 to 125
YEAR
ISO6763
ISO6763FQDW ACTIVE
RQ1
SOIC
DW
16
2000
Green (RoHS & NIPDAU
no Sb/Br)
Level-2-260C-1 -40 to 125
YEAR
ISO6763
F
Orderable
Device
40
Status(1)
Lead/Ball
Finish(6)
Submit Document Feedback
MSL Peak
Temp(3)
Op Temp (°C)
Device
Marking(4) (5)
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: ISO6760-Q1 ISO6761-Q1 ISO6762-Q1 ISO6763-Q1
ISO6760-Q1, ISO6761-Q1, ISO6762-Q1, ISO6763-Q1
www.ti.com.cn
ZHCSLW8B – AUGUST 2021 – REVISED MAY 2022
13.2 Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
B0 W
Reel
Diameter
Cavity
A0
B0
K0
W
P1
A0
Dimension designed to accommodate the component width
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1
Q2
Q1
Q2
Q3
Q4
Q3
Q4
User Direction of Feed
Pocket Quadrants
Device
Package
Type
Package
Drawing
Pins
SPQ
Reel
Diameter
(mm)
Reel
Width W1
(mm)
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
ISO6760QDWRQ1
SOIC
DW
16
2000
330.0
24.4
10.9
10.7
2.7
12.0
24.0
Q1
ISO6760FQDWRQ1
SOIC
DW
16
2000
330.0
24.4
10.9
10.7
2.7
12.0
24.0
Q1
ISO6761FQDWRQ1
SOIC
DW
16
2000
330.0
24.4
10.9
10.7
2.7
12.0
24.0
Q1
ISO6761QDWRQ1
SOIC
DW
16
2000
330.0
24.4
10.9
10.7
2.7
12.0
24.0
Q1
ISO6762FQDWRQ1
SOIC
DW
16
2000
330.0
24.4
10.9
10.7
2.7
12.0
24.0
Q1
ISO6762QDWRQ1
SOIC
DW
16
2000
330.0
24.4
10.9
10.7
2.7
12.0
24.0
Q1
ISO6763FQDWRQ1
SOIC
DW
16
2000
330.0
24.4
10.9
10.7
2.7
12.0
24.0
Q1
ISO6763QDWRQ1
SOIC
DW
16
2000
330.0
24.4
10.9
10.7
2.7
12.0
24.0
Q1
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: ISO6760-Q1 ISO6761-Q1 ISO6762-Q1 ISO6763-Q1
41
ISO6760-Q1, ISO6761-Q1, ISO6762-Q1, ISO6763-Q1
www.ti.com.cn
ZHCSLW8B – AUGUST 2021 – REVISED MAY 2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
L
W
42
H
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ISO6760QDWRQ1
SOIC
DW
16
2000
367.0
367.0
45.0
ISO6760FQDWRQ1
SOIC
DW
16
2000
367.0
367.0
45.0
ISO6761FQDWRQ1
SOIC
DW
16
2000
367.0
367.0
45.0
ISO6761QDWRQ1
SOIC
DW
16
2000
367.0
367.0
45.0
ISO6762FQDWRQ1
SOIC
DW
16
2000
367.0
367.0
45.0
ISO6762QDWRQ1
SOIC
DW
16
2000
367.0
367.0
45.0
ISO6763FQDWRQ1
SOIC
DW
16
2000
367.0
367.0
45.0
ISO6763QDWRQ1
SOIC
DW
16
2000
367.0
367.0
45.0
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: ISO6760-Q1 ISO6761-Q1 ISO6762-Q1 ISO6763-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
29-Apr-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
ISO6760FQDWRQ1
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO6760F
ISO6760QDWRQ1
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO6760
ISO6761FQDWRQ1
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO6761F
ISO6761QDWRQ1
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO6761
ISO6762FQDWRQ1
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO6762F
ISO6762QDWRQ1
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO6762
ISO6763FQDWRQ1
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO6763F
ISO6763QDWRQ1
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO6763
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
