ISO6760L
SLLSFO3A – DECEMBER 2021 – REVISED FEBRUARY 2023
ISO6760L Six-Channel Reinforced Digital Isolators with Integrated Interlock and
Robust EMC
1 Features
3 Description
•
The ISO6760L and ISO6760LN devices are highperformance, six-channel digital isolators with
integrated interlock function for applications requiring
up to 5000 VRMS isolation ratings per UL 1577. These
devices are also certified by VDE, TUV, CSA, and
CQC.
•
•
•
•
•
•
•
•
•
2 Applications
•
•
•
•
Motor drives
Appliances
Grid
Building Automation
The ISO6760L family of devices integrate a series of
logic gates to provide hardware interlock functionality
for adjacent channels. The interlock feature ensures
that each channel, in a channel pairing, will not be
enabled at the same time. If both channels in the
pairing share the same input logic, the output logic will
always be low. The ISO6760L family of devices have
all six channels in the same direction and provide
high electromagnetic immunity and low emissions at
low power consumption, while isolating CMOS or
LVCMOS digital I/Os. Each isolation channel has a
logic input and output buffer separated by TI's double
capacitive silicon dioxide (SiO2) insulation barrier.
Used in conjunction with intelligent power modules
(IPMs), the interlock feature in these devices help
prevent shoot through current between the high
side and low side gate driver during turn on
and turn off events. Six channels, including three
pairings of interlock circuitry, are integrated in a
16-pin SOIC wide-body (DW) package with space
savings greater than 50% compared to optocoupler
solutions. Through innovative chip design and layout
techniques, the electromagnetic compatibility of the
ISO6760L devices has been significantly enhanced to
ease system-level ESD, EFT, surge, and emissions
compliance.
Device Description
Part Number
ISO6760L,
ISO6760LN
Package
Body Size
SOIC (DW)
10.30 mm × 7.50
mm
ISO6760L
IPM
C2000
MCU
VCC1
1
INA_H
2
INA_L
3
INB_H
4
INB_L
5
INC_H
6
INC_L
7
GND1
8
I
N
T
E
R
L
O
C
K
ISOLATION
•
ISO6760 with integrated Interlock function
– Designed to support opposite polarity of
adjacent channels
– Three sets of paired interlock channels
Robust isolation barrier:
– High lifetime at 1500 VRMS working voltage
– Up to 5000 VRMS isolation rating
– Up to 10 kV surge capability
– ±130 kV/μs typical CMTI
Wide supply range: 1.71 V to 1.89 V and 2.25 V to
5.5 V
Channel output non-inverting (ISO6760L) and
inverting (ISO6760LN) options
50 Mbps data rate
1.71 V to 5.5 V level translation
Wide temperature range: –40°C to 125°C
1.4 mA per channel typical at 1 Mbps
Robust electromagnetic compatibility (EMC)
– System-level ESD, EFT, and surge immunity
– Low emissions
Wide-SOIC (DW-16) Package
Safety-Related Certifications:
– DIN EN IEC 60747-17 (VDE 0884-17)
– UL 1577 component recognition program
– IEC 62368-1, IEC 61010-1, IEC 60601-1 and
GB 4943.1 certifications
I
N
T
E
R
L
O
C
K
I
N
T
E
R
L
O
C
K
16
VCC2
15
OUTA_H
14
OUTA_L
13
OUTB_H
12
OUTB_L
11
OUTC_H
10
OUTC_L
High side
gate driver
Level
shift
High side
gate driver
High side
gate driver
3 phase
IGBT
inverter
Low side
gate driver
9 GND2
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
M
ISO6760L
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SLLSFO3A – DECEMBER 2021 – REVISED FEBRUARY 2023
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................6
6.5 Power Ratings.............................................................6
6.6 Insulation Specifications............................................. 7
6.7 Safety-Related Certifications...................................... 9
6.8 Safety Limiting Values.................................................9
6.9 Electrical Characteristics—5-V Supply..................... 10
6.10 Supply Current Characteristics—5-V Supply.......... 10
6.11 Electrical Characteristics—3.3-V Supply................. 11
6.12 Supply Current Characteristics—3.3-V Supply....... 11
6.13 Electrical Characteristics—2.5-V Supply ............... 12
6.14 Supply Current Characteristics—2.5-V Supply....... 12
6.15 Electrical Characteristics—1.8-V Supply................ 13
6.16 Supply Current Characteristics—1.8-V Supply....... 13
6.17 Switching Characteristics—5-V Supply...................14
6.18 Switching Characteristics—3.3-V Supply................15
6.19 Switching Characteristics—2.5-V Supply................16
6.20 Switching Characteristics—1.8-V Supply................17
6.21 Insulation Characteristics Curves........................... 18
6.22 Typical Characteristics............................................ 19
7 Parameter Measurement Information.......................... 20
8 Detailed Description......................................................21
8.1 Overview................................................................... 21
8.2 Functional Block Diagram......................................... 21
8.3 Feature Description...................................................22
8.4 Device Functional Modes..........................................24
9 Application and Implementation.................................. 25
9.1 Application Information............................................. 25
9.2 Typical Application.................................................... 26
10 Insulation Lifetime ......................................................29
11 Power Supply Recommendations..............................30
12 Layout...........................................................................31
12.1 Layout Guidelines................................................... 31
12.2 Layout Example...................................................... 32
13 Device and Documentation Support..........................33
13.1 Documentation Support.......................................... 33
13.2 Receiving Notification of Documentation Updates..33
13.3 Support Resources................................................. 33
13.4 Trademarks............................................................. 33
13.5 Electrostatic Discharge Caution..............................33
13.6 Glossary..................................................................33
14 Mechanical, Packaging, and Orderable
Information.................................................................... 33
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (December 2021) to Revision A (February 2023)
Page
• Changed standard name From: "DIN V VDE V 0884-11:2017-01" To: "DIN EN IEC 60747-17 (VDE 0884-17)"
throughout the document ...................................................................................................................................1
• Removed references to standard IEC/EN/CSA 60950-1 throughout the document...........................................1
• Updated standards marked as "planned" to include certificate numbers thoughout the document....................1
• Removed standard revision and year references from all standard names thoughout the document................1
• Added Maximum impulse voltage (VIMP) specification per DIN EN IEC 60747-17 (VDE 0884-17)....................7
• Changed test conditions and values of Maximum surge isolation voltage (VIOSM) specification per DIN EN IEC
60747-17 (VDE 0884-17)....................................................................................................................................7
• Clarified method b test conditions of Apparent charge (qPD)..............................................................................7
• Changed Maximum surge isolation voltage (VIOSM) from 6250 VPK to 10000 VPK ............................................ 9
• Changed working voltage lifetime margin From: 87.5% To: 50%, minimum required insulation lifetime From:
37.5 years To: 30 years and insulation lifetime per TDDB From: 220 years To: 36 years per DIN EN IEC
60747-17 (VDE 0884-17)..................................................................................................................................29
• Changed Figure 10-2 as per DIN EN IEC 60747-17 (VDE 0884-17)............................................................... 29
• Updated to DW0016B mechanical drawing...................................................................................................... 33
2
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5 Pin Configuration and Functions
1
16
VCC2
INA_H
2
15
OUTA_H
INA_L
3
14
OUTA_L
INB_H
4
13
OUTB_H
INB_L
5
12
OUTB_L
INC_H
6
11
OUTC_H
INC_L
7
10
OUTC_L
GND1
8
9
ISOLATION
VCC1
GND2
Not to scale
Figure 5-1. ISO6760L DW Package 16-Pin SOIC-WB Top View
Table 5-1. Pin Functions
PIN
NAME
ISO6760L
I/O
DESCRIPTION
GND1
8
—
Ground connection for VCC1
GND2
9
—
Ground connection for VCC2
INA_H
2
I
Input, channel A_H (Interlock paired with channel A_L)
INA_L
3
I
Input, channel A_L (Interlock paired with channel A_H)
INB_H
4
I
Input, channel B_H (Interlock paired with channel B_L)
INB_L
5
I
Input, channel B_L (Interlock paired with channel B_H)
INC_H
6
I
Input, channel C_H (Interlock paired with channel C_L)
INC_L
7
I
Input, channel C_L (Interlock paired with channel C_H)
OUTA_H
15
O
Output, channel A_H (Interlock paired with channel A_L)
OUTA_L
14
O
Output, channel A_L (Interlock paired with channel A_H)
OUTB_H
13
O
Output, channel B_H (Interlock paired with channel B_L)
OUTB_L
12
O
Output, channel B_L (Interlock paired with channel B_H)
OUTC_H
11
O
Output, channel C_H (Interlock paired with channel C_L)
OUTC_L
10
O
Output, channel C_L (Interlock paired with channel C_H)
VCC1
1
—
Power supply, side 1
VCC2
16
—
Power supply, side 2
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6 Specifications
6.1 Absolute Maximum Ratings
See(1)
MIN
MAX
VCC1 to GND1
-0.5
6
VCC2 to GND2
-0.5
6
Input/Output
Voltage
INx to GNDx
-0.5
VCCX + 0.5 (3)
OUTx to GNDx
-0.5
VCCX + 0.5 (3)
Output Current
Io
-15
Supply Voltage (2)
Temperature
(1)
(2)
(3)
Operating junction temperature, TJ
Storage temperature, Tstg
-65
UNIT
V
V
15
mA
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak
voltage values
Maximum voltage must not exceed 6 V.
6.2 ESD Ratings
(1) (2)
VALUE
Electrostatic discharge
Human body model (HBM), per ANSI/
ESDA/JEDEC JS-001, all pins(1)
±2000
Electrostatic discharge
Charged device model (CDM), per
JEDEC specification JESD22-C101, all
pins(2)
±1500
V(ESD)
(1)
(2)
4
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
MIN
MAX
UNIT
1.71
1.89
V
2.25
5.5
V
2(3)
1.71
1.89
V
VCC2 (1)
Supply Voltage Side 2(3)
2.25
5.5
V
Vcc
(UVLO+)
UVLO threshold when supply voltage is rising
1.71
V
Vcc
(UVLO-)
UVLO threshold when supply voltage is falling
Vhys
(UVLO)
Supply voltage UVLO hysteresis
VIH
High level Input voltage
VIL
Low level Input voltage
1(3)
VCC1 (1)
Supply Voltage Side 1(3)
(1)
VCC1
VCC2
(1)
Supply Voltage Side
Supply Voltage Side
IOL
High level output current
Low level output current
DR
Data Rate
TA
Ambient temperature
(1)
(2)
(3)
1.53
1.1
1.41
V
0.08
0.13
V
0.7 x VCCI
VCCO
IOH
NOM
(2)
=5V
(2)
VCCI
V
0
0.3 x VCCI
V
-4
mA
VCCO = 3.3 V
-2
mA
VCCO = 2.5 V
-1
mA
VCCO = 1.8 V
-1
mA
VCCO = 5 V
4
mA
VCCO = 3.3 V
2
mA
VCCO = 2.5 V
1
mA
VCCO = 1.8 V
1
mA
VCC = 2.25 V to 5.5 V
0
50
Mbps
VCC = 1.71 V to 1.89 V
0
25
Mbps
125
°C
-40
25
VCC1 and VCC2 can be set independent of one another
VCCI = Input-side VCC; VCCO = Output-side VCC
The channel outputs are in undetermined state when 1.89 V < VCC1, VCC2 < 2.25 V and 1.05 V < VCC1, VCC2 < 1.71 V
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6.4 Thermal Information
ISO6760L
THERMAL METRIC
(1)
UNIT
DW (SOIC)
16 PINS
RθJA
Junction-to-ambient thermal resistance
68.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
31.8
°C/W
RθJB
Junction-to-board thermal resistance
32.7
°C/W
ψJT
Junction-to-top characterization parameter
13.5
°C/W
ψJB
Junction-to-board characterization parameter
32.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
°C/W
6.5 Power Ratings
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
200
mW
45
mW
155
mW
ISO6760L
6
PD
Maximum power dissipation (both sides)
PD1
Maximum power dissipation (side-1)
PD2
Maximum power dissipation (side-2)
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL =
15 pF, Input a 25-MHz 50% duty cycle
square wave
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6.6 Insulation Specifications
PARAMETER
VALUE
TEST CONDITIONS
DW-16
UNIT
CLR
External clearance(1)
Shortest terminal-to-terminal distance through air
>8
mm
CPG
External creepage(1)
Shortest terminal-to-terminal distance across the
package surface
>8
mm
DTI
Distance through the insulation
Minimum internal gap (internal clearance)
>17
um
CTI
Comparative tracking index
DIN EN 60112 (VDE 0303-11); IEC 60112
>600
V
Material group
According to IEC 60664-1
I
Rated mains voltage ≤ 600 VRMS
I-IV
Rated mains voltage ≤ 1000 VRMS
I-III
Maximum repetitive peak isolation voltage
AC voltage (bipolar)
2121
VPK
Maximum working isolation voltage
AC voltage; Time dependent dielectric breakdown
(TDDB) Test;
See Insulation Lifetime Projection Data
1500
VRMS
DC voltage
2121
VDC
Overvoltage category per IEC 60664-1
DIN EN IEC 60747-17 (VDE 0884-17)
VIORM
VIOWM
(2)
VIOTM
Maximum transient isolation voltage
VTEST = VIOTM,
t = 60 s (qualification);
VTEST = 1.2 x VIOTM,
t= 1 s (100% production)
7071
VPK
VIMP
Maximum impulse voltage(3)
Tested in air, 1.2/50-us waveform per IEC 62368-1
7692
VPK
VIOSM
Maximum surge isolation voltage(4)
VIOSM ≥ 1.3 x VIMP; Tested in oil (qualification test),
1.2/50-μs waveform per IEC 62368-1
10000
VPK
Method a, After Input-output safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.2 x VIORM, tm = 10 s
≤5
Method a, After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.6 x VIORM, tm = 10 s
≤5
Method b: At routine test (100% production) and
preconditioning (type test);
Vini = 1.2 x VIOTM, tini = 1 s;
Vpd(m) = 1.875 x VIORM, tm = 1 s (method b1) or
Vpd(m) = Vini, tm = tini (method b2)
≤5
VIO = 0.4 x sin (2πft), f = 1 MHz
~1
VIO = 500 V, TA = 25°C
>1012
VIO = 500 V, 100°C ≤ TA ≤ 125°C
>1011
VIO = 500 V at TS = 150°C
>109
Apparent charge(5)
qpd
Barrier capacitance, input to output(6)
CIO
Isolation resistance(6)
RIO
pC
Pollution degree
2
Climatic category
40/125/21
pF
Ω
UL 1577
VISO
(1)
(2)
(3)
(4)
(5)
Maximum withstanding isolation voltage
VTEST = VISO , t = 60 s (qualification),
VTEST = 1.2 x VISO , t = 1 s (100% production)
5000
VRMS
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application.
Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of
the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become
equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed-circuit board are used to help increase these
specifications.
This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured
by means of suitable protective circuits.
Testing is carried out in air to determine the surge immunity of the package.
Testing is carried out in oil to determine the intrinsic surge immunity of the isolation barrier.
Apparent charge is electrical discharge caused by a partial discharge (pd).
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(6)
8
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All pins on each side of the barrier tied together creating a two-terminal device.
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6.7 Safety-Related Certifications
VDE
CSA
Certified according to DIN
EN IEC 60747-17 (VDE
0884-17)
Maximum transient
isolation voltage, 7071
VPK;
Maximum repetitive peak
isolation voltage, 2121
VPK;
Maximum surge isolation
voltage,
10000 VPK
Certificate number:
40040142
UL
Certified according to IEC Certified according to
62368-1, IEC 61010-1 and UL 1577 Component
IEC 60601
Recognition Program
600 VRMS reinforced
insulation per CSA
62368-1 and IEC 62368-1;
600 VRMS reinforced
insulation per CSA
61010-1and IEC 61010-1
(pollution degree 2,
Single protection,
material group I);
5000 VRMS
2 MOPP (Means of
Patient Protection) per
CSA 60601-1 and IEC
60601-1, 250 VRMS max
working voltage
Master contract number:
220991
File number: E181974
CQC
TUV
Certified according to GB
4943.1
Certified according to EN
61010-1 and EN 62368-1
Reinforced insulation,
Altitude ≤ 5000 m, Tropical
Climate,
700 VRMS maximum
working voltage
5000 VRMS reinforced
insulation per EN 61010-1
and EN 62368-1 up to
working voltage of 600
VRMS
Certificate number:
CQC21001304083
Client ID number: 077311
6.8 Safety Limiting Values
Safety limiting(1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RθJA =68.8°C/W, VI = 5.5 V, TJ = 150°C,
TA = 25°C
330
mA
RθJA = 68.8°C/W, VI = 3.6 V, TJ = 150°C,
TA = 25°C
504
mA
RθJA = 68.8°C/W, VI = 2.75 V, TJ = 150°C,
TA = 25°C
660
mA
RθJA = 68.8°C/W, VI = 1.89 V, TJ = 150°C,
TA = 25°C
956
mA
1820
mW
150
°C
DW-16 PACKAGE
IS
Safety input, output, or supply current (1)
PS
Safety input, output, or total power (1)
TS
Maximum safety temperature (1)
(1)
RθJA = 68.8°C/W, TJ = 150°C, TA = 25°C
The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The
IS and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be
exceeded. These limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the table is that of a device installed on a high-K test board for leaded surface-mount
packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum allowed junction temperature.
PS = IS × VI, where VI is the maximum input voltage.
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6.9 Electrical Characteristics—5-V Supply
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VOH
High-level output voltage
IOH = -4 mA; See Switching
Characteristics Test Circuit and
Voltage Waveforms
VOL
Low-level output voltage
IOL = 4 mA; See Switching
Characteristics Test Circuit and
Voltage Waveforms
VIT+(IN)
Rising input switching threshold
VIT-(IN)
Falling input switching threshold
VI(HYS)
Input threshold voltage hysteresis
IIH
High-level input current
VIH = VCCI (1) at INx
IIL
Low-level input current
VIL = 0 V at INx
CMTI
Common mode transient immunity
VI = VCC or 0 V, VCM = 1200
V; see Common-Mode Transient
Immunity Test Circuit
Ci
Input Capacitance (2)
VI = VCC/ 2 + 0.4×sin(2πft), f = 2
MHz, VCC = 5 V
(1)
(2)
TYP
MAX
VCCO - 0.4
UNIT
V
0.4
V
0.7 x VCCI (1)
V
0.3 x VCCI
V
0.1 x VCCI
V
10
-10
µA
µA
50
130
kV/us
2.8
pF
VCCI = Input-side VCC; VCCO = Output-side VCC
Measured from input pin to same side ground.
6.10 Supply Current Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted).
PARAMETER
SUPPLY
CURRENT
TEST CONDITIONS
MIN
TYP
MAX
ICC1
5.11
6.97
ICC2
3.3
5.38
ICC1
5.13
6.99
ICC2
3.7
5.83
ICC1
5.29
7.19
ICC2
7.27
9.9
UNIT
ISO6760L
Supply current - DC signal
Output A: GND for ISO6760L and Vcc for ISO6760LN
Output B: Vcc for ISO6760L and GND for ISO6760LN
1 Mbps
Supply current - AC signal
All channels switching with square
wave clock input; CL = 15 pF
10 Mbps
50 Mbps
10
ICC1
6.12
8.16
ICC2
23.62
27.74
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6.11 Electrical Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VOH
High-level output voltage
IOH = -2 mA; See Switching
Characteristics Test Circuit and
Voltage Waveforms
VOL
Low-level output voltage
IOL = 2 mA; See Switching
Characteristics Test Circuit and
Voltage Waveforms
VIT+(IN)
Rising input switching threshold
VIT-(IN)
Falling input switching threshold
0.3 x VCCI
V
VI(HYS)
Input threshold voltage
hysteresis
0.1 x VCCI
V
IIH
High-level input current
VIH = VCCI (1) at INx
IIL
Low-level input current
VIL = 0 V at INx
CMTI
Common mode transient
immunity
VI = VCC or 0 V, VCM = 1200
V; see Common-Mode Transient
Immunity Test Circuit
Ci
Input Capacitance(2)
VI = VCC/ 2 + 0.4×sin(2πft), f = 2
MHz, VCC = 3.3 V
(1)
(2)
VCCO - 0.2
V
0.2
V
0.7 x VCCI (1)
V
10
-10
µA
µA
50
130
kV/us
2.8
pF
VCCI = Input-side VCC; VCCO = Output-side VCC
Measured from input pin to same side ground.
6.12 Supply Current Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted).
PARAMETER
SUPPLY
CURRENT
TEST CONDITIONS
MIN
TYP
MAX
ICC1
5.08
6.89
ICC2
3.28
5.36
ICC1
5.1
6.9
ICC2
3.57
5.68
ICC1
5.18
7.04
ICC2
6.07
8.62
ICC1
5.74
7.68
ICC2
17.54
21.5
UNIT
ISO6760L
Supply current - DC signal
Output A: GND for ISO6760L and Vcc for ISO6760LN
Output B: Vcc for ISO6760L and GND for ISO6760LN
1 Mbps
Supply current - AC signal
All channels switching with square
wave clock input; CL = 15 pF
10 Mbps
50 Mbps
mA
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6.13 Electrical Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VOH
High-level output voltage
IOH = -1 mA; See Switching
Characteristics Test Circuit and
Voltage Waveforms
VOL
Low-level output voltage
IOL = 1 mA; See Switching
Characteristics Test Circuit and
Voltage Waveforms
VIT+(IN)
Rising input switching threshold
VIT-(IN)
Falling input switching threshold
0.3 x VCCI
V
VI(HYS)
Input threshold voltage
hysteresis
0.1 x VCCI
V
IIH
High-level input current
VIH = VCCI (1) at INx
IIL
Low-level input current
VIL = 0 V at INx
CMTI
Common mode transient
immunity
VI = VCC or 0 V, VCM = 1200
V; see Common-Mode Transient
Immunity Test Circuit
Ci
Input Capacitance(2)
VI = VCC/ 2 + 0.4×sin(2πft), f = 2
MHz, VCC = 2.5 V
(1)
(2)
VCCO - 0.1
V
0.1
V
0.7 x VCCI (1)
V
10
-10
µA
µA
50
130
kV/us
2.8
pF
VCCI = Input-side VCC; VCCO = Output-side VCC
Measured from input pin to same side ground.
6.14 Supply Current Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted).
PARAMETER
SUPPLY
CURRENT
TEST CONDITIONS
MIN
TYP
MAX
ICC1
5.07
6.85
ICC2
3.28
5.35
ICC1
5.08
6.87
ICC2
3.49
5.59
ICC1
5.14
6.97
ICC2
5.34
7.8
ICC1
5.59
7.49
ICC2
13.83
17.47
UNIT
ISO6760L
Supply current - DC signal
Output A: GND for ISO6760L and Vcc for ISO6760LN
Output B: Vcc for ISO6760L and GND for ISO6760LN
1 Mbps
Supply current - AC signal
All channels switching with square
wave clock input; CL = 15 pF
10 Mbps
25 Mbps
12
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6.15 Electrical Characteristics—1.8-V Supply
VCC1 = VCC2 = 1.8 V ±10% (over recommended operating conditions unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
VOH
High-level output voltage
IOH = -1 mA; See Switching
Characteristics Test Circuit and
Voltage Waveforms
VOL
Low-level output voltage
IOL = 1 mA; See Switching
Characteristics Test Circuit and
Voltage Waveforms
VIT+(IN)
Rising input switching threshold
VIT-(IN)
Falling input switching threshold
VI(HYS)
Input threshold voltage hysteresis
IIH
High-level input current
VIH = VCCI (1) at INx
IIL
Low-level input current
VIL = 0 V at INx
CMTI
Common mode transient immunity
VI = VCC or 0 V, VCM = 1200
V; see Common-Mode Transient
Immunity Test Circuit
Ci
Input Capacitance(2)
VI = VCC/ 2 + 0.4×sin(2πft), f = 2
MHz, VCC = 1.8 V
(1)
(2)
TYP
MAX
VCCO - 0.1
UNIT
V
0.1
V
0.7 x VCCI (1)
V
0.3 x VCCI
V
0.1 x VCCI
V
10
-10
µA
µA
50
75
kV/us
2.8
pF
VCCI = Input-side VCC; VCCO = Output-side VCC
Measured from input pin to same side ground.
6.16 Supply Current Characteristics—1.8-V Supply
VCC1 = VCC2 = 1.8 V ±10% (over recommended operating conditions unless otherwise noted).
PARAMETER
SUPPLY
CURRENT
TEST CONDITIONS
MIN
TYP
MAX
ICC1
4.27
6.24
ICC2
3.15
5.39
ICC1
4.28
6.25
ICC2
3.3
5.55
ICC1
4.37
6.37
ICC2
4.6
7.04
ICC1
4.5
6.5
ICC2
6.84
9.47
UNIT
ISO6760L
Supply current - DC signal
Output A: GND for ISO6760L and Vcc for ISO6760LN
Output B: Vcc for ISO6760L and GND for ISO6760LN
1 Mbps
Supply current - AC signal
All channels switching with square
wave clock input; CL = 15 pF
10 Mbps
50 Mbps
(25Mbps)
mA
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6.17 Switching Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
13
20.5
ns
1
7
ns
6
ns
6
ns
2.6
4.5
ns
2.6
4.5
ns
300
us
0.3
us
ISO6760L
tPLH, tPHL
Propagation delay time
PWD
Pulse width distortion(1) |tPHL – tPLH|
tsk(o)
Channel-to-channel output skew time(2)
tsk(pp)
Part-to-part skew time(3)
tr
Output signal rise time
tf
Output signal fall time
One input in static state and other input
is toggled at 100kbps. See Switching
Characteristics Test Circuit and Voltage
Waveforms
Same-direction channels
See Switching Characteristics Test
Circuit and Voltage Waveforms
Time from UVLO to
valid output data
tPU
Time from UVLO to valid output data
tDO
Default output delay time from input power loss
Measured from the time VCC goes
below 1.2V. See Default Output
Delay Time Test Circuit and Voltage
Waveforms
tie
Time interval error
216 – 1 PRBS data at 50 Mbps
(1)
(2)
(3)
14
0.1
1
ns
Also known as pulse skew.
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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6.18 Switching Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
13
21
ns
1
7
ns
6
ns
7
ns
1.6
2.8
ns
1.6
2.8
ns
300
us
0.3
us
ISO6760L
tPLH, tPHL
Propagation delay time
PWD
Pulse width distortion(1) |tPHL – tPLH|
tsk(o)
Channel-to-channel output skew time(2)
tsk(pp)
Part-to-part skew time(3)
tr
Output signal rise time
tf
Output signal fall time
One input in static state and other input
is toggled at 100kbps. See Switching
Characteristics Test Circuit and Voltage
Waveforms
Same-direction channels
See Switching Characteristics Test
Circuit and Voltage Waveforms
Time from UVLO to
valid output data
tPU
Time from UVLO to valid output data
tDO
Default output delay time from input power loss
Measured from the time VCC goes
below 1.2V. See Default Output
Delay Time Test Circuit and Voltage
Waveforms
tie
Time interval error
216 – 1 PRBS data at 50 Mbps
(1)
(2)
(3)
0.1
1
ns
Also known as pulse skew.
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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6.19 Switching Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
14.5
23.5
ns
1
7.1
ns
ISO6760L
tPLH, tPHL
Propagation delay time
PWD
Pulse width distortion(1) |tPHL – tPLH|
tsk(o)
Channel-to-channel output skew time(2)
tsk(pp)
Part-to-part skew time(3)
tr
Output signal rise time
tf
Output signal fall time
One input in static state and other input
is toggled at 100kbps. See Switching
Characteristics Test Circuit and Voltage
Waveforms
Same-direction channels
See Switching Characteristics Test
Circuit and Voltage Waveforms
Time from UVLO to valid output data
tDO
Default output delay time from input power loss
Measured from the time VCC goes
below 1.2V. See Default Output
Delay Time Test Circuit and Voltage
Waveforms
tie
Time interval error
216 – 1 PRBS data at 50 Mbps
(3)
16
ns
ns
2
4
ns
2
4
ns
300
us
0.3
us
Time from UVLO to
valid output data
tPU
(1)
(2)
6
7.9
0.1
1
ns
Also known as pulse skew.
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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6.20 Switching Characteristics—1.8-V Supply
VCC1 = VCC2 = 1.8 V ±5% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
18
31
ns
1
8.2
ns
ISO6760L
tPLH, tPHL
Propagation delay time
PWD
Pulse width distortion |tPHL – tPLH|
tsk(o)
Channel-to-channel output skew time(1)
tsk(pp)
Part-to-part skew time(2)
tr
Output signal rise time
tf
Output signal fall time
One input in static state and other input
is toggled at 100kbps. See Switching
Characteristics Test Circuit and Voltage
Waveforms
Same-direction channels
See Switching Characteristics Test
Circuit and Voltage Waveforms
Time from UVLO to valid output data
tDO
Default output delay time from input power loss
Measured from the time VCC goes
below 1.2V. See Default Output
Delay Time Test Circuit and Voltage
Waveforms
tie
Time interval error
216 – 1 PRBS data at 50 Mbps
(2)
ns
ns
2.7
5.3
ns
2.7
5.3
ns
300
us
0.3
us
Time from UVLO to
valid output data
tPU
(1)
6
11.7
0.1
1
ns
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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6.21 Insulation Characteristics Curves
2000
Vcc = 5.5V
Vcc = 3.6V
Vcc = 2.75V
Vcc = 1.89V
800
600
400
200
1800
Safety Limiting Power (mW)
Safety Limiting Current (mA)
1000
1600
1400
1200
1000
800
600
400
200
0
0
0
20
40
60
80
100
120
Ambient Temperature ( C)
140
160
Figure 6-1. Thermal Derating Curve for Safety
Limiting Current for DW-16 Package
18
0
20
40
60
80
100
120
Ambient Temperature ( C)
140
160
Figure 6-2. Thermal Derating Curve for Safety
Limiting Power for DW-16 Package
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6.22 Typical Characteristics
18
Supply Current (mA)
16
14
12
10
at
at
at
at
at
at
at
at
1.8 V
1.8 V
2.5 V
2.5 V
3.3 V
3.3 V
5V
5V
Supply Current (mA)
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
8
6
4
2
0
5
10
15
20
25
30
Data Rate (Mbps)
TA = 25°C
35
40
45
50
9.5
9
8.5
8
7.5
7
6.5
6
5.5
5
4.5
4
3.5
3
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
0
5
1.8 V
1.8 V
2.5 V
2.5 V
3.3 V
3.3 V
5V
5V
15
20
25
30
Data Rate (Mbps)
TA = 25°C
CL = 15 pF
Figure 6-3. ISO6760L Supply Current vs Data Rate
(With 15-pF Load)
35
40
45
50
CL = No Load
Figure 6-4. ISO6763 Supply Current vs Data Rate
(With No Load)
0.8
8
VCC1 at 1.8 V
VCC2 at 2.5 V
VCC1 at 3.3 V
VCC2 at 5 V
6
VCC1 at 1.8 V
VCC2 at 2.5 V
VCC1 at 3.3 V
VCC2 at 5 V
0.7
Low-Level Output Voltage (V)
7
High-Level Output Voltage (V)
10
at
at
at
at
at
at
at
at
5
4
3
2
1
0.6
0.5
0.4
0.3
0.2
0.1
0
0
-15
-10
-5
High-Level Output Current (mA)
0
0
TA = 25°C
5
10
Low-Level Output Current (mA)
15
TA = 25°C
Figure 6-5. High-Level Output Voltage vs High-level Figure 6-6. Low-Level Output Voltage vs Low-Level
Output Current
Output Current
22
Power Supply UVLO Threshold (V)
1.65
Propagation Delay Time (ns)
20
18
16
14
12
10
tPHL at 1.8 V
tPLH at 1.8 V
tPHL at 2.5 V
8
6
-40
-25
-10
5
tPLH at 2.5 V
tPHL at 3.3 V
tPLH at 3.3 V
20
35
50
65
Temperature (C)
95
110 125
1.5
1.45
1.4
1.35
1.3
1.25
VCC1 +
VCC1 VCC2 +
VCC2 -
1.2
-55
tPHL at 5 V
tPLH at 5 V
80
1.6
1.55
-5
45
Free-Air Temperature ( C)
95
125
TA = 25°C
Figure 6-8. Power Supply Undervoltage Threshold
vs Free-Air Temperature
Figure 6-7. Propagation Delay Time vs Free-Air
Temperature
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7 Parameter Measurement Information
Isolation Barrier
IN
Input
Generator
(See Note A)
VI
VCCI
VI
OUT
50%
50%
0V
tPLH
CL
See Note B
VO
50
tPHL
VOH
90%
50%
VO
50%
10%
VOL
tf
tr
Copyright © 2016, Texas Instruments Incorporated
A.
B.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3ns, ZO =
50 Ω. At the input, 50 Ω resistor is required to terminate Input Generator signal. It is not needed in actual application.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 7-1. Switching Characteristics Test Circuit and Voltage Waveforms
VI See Note B
VCC
VCC
Isolation Barrier
IN = 0 V (Devices without suffix F)
IN = VCC (Devices with suffix F)
VI
IN
1.4 V
0V
OUT
VO
tDO
CL
See Note A
default high
VOH
50%
VO
VOL
default low
A.
B.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Power Supply Ramp Rate = 10 mV/ns
Figure 7-2. Default Output Delay Time Test Circuit and Voltage Waveforms
S1
VCCO
Isolation Barrier
VCCI
IN
Pass-fail criteria:
The output must
remain stable.
OUT
+
CL
See Note A
VOH or VOL
±
GNDI
A.
B.
+
VCM ±
GNDO
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
For optimized CMTI performance, a 0.1 μF + 1 μF decoupling capacitor should be placed close to VCC1 and VCC2. Please see Section
12.2 for capacitor placement details. A recommended 0.1μF capacitor is LLL185R71A104MA11L (CAP CER 0.1UF 10V X7R 0306 - LW
Reversed Low ESL Chip Ceramic Capacitors) or equivalent.
Figure 7-3. Common-Mode Transient Immunity Test Circuit
20
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8 Detailed Description
8.1 Overview
The ISO6760L family of devices have an ON-OFF keying (OOK) modulation scheme to transmit the digital data
across a silicon dioxide based isolation barrier. The transmitter sends a high frequency carrier across the barrier
to represent one digital state and sends no signal to represent the other digital state. The receiver demodulates
the signal after advanced signal conditioning and produces the output which goes through an interlock stage
before an output buffer. The ISO6760L family offers two options, a standard non-inverting channel, ISO6760L,
and a channel inverting ISO6760LN. The two offerings make the ISO6760L family compatable with historical
optocoupler based solutions. The ISO6760L devices also incorporate advanced circuit techniques to maximize
the CMTI performance and minimize the radiated emissions due to the high frequency carrier and IO buffer
switching. The conceptual block diagram of a digital capacitive isolator, Figure 8-1, shows a functional block
diagram of a typical channel.
8.2 Functional Block Diagram
Transmitter
Receiver
EN
TX IN
OOK
Modulation
TX Signal
Conditioning
Oscillator
SiO2 based
Capacitive
Isolation
Barrier
RX Signal
Conditioning
Envelope
Detection
RX OUT
Emissions
Reduction
Techniques
Copyright © 2016, Texas Instruments Incorporated
Figure 8-1. Conceptual Block Diagram of a Digital Capacitive Isolator
Figure 8-2 shows a conceptual detail of how the ON-OFF keying scheme works.
TX IN
Carrier signal through
isolation barrier
RX OUT
Figure 8-2. On-Off Keying (OOK) Based Modulation Scheme
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8.3 Feature Description
Table 8-1 provides an overview of the device features.
Table 8-1. Device Features
(1)
PART NUMBER
CHANNEL DIRECTION
MAXIMUM DATA
RATE
OUTPUT
PACKAGE
RATED ISOLATION(1)
ISO6760L
6 Forward,
3 Interlock Pairs
50 Mbps
Non-Inverted
DW-16
5000 VRMS / 7000 VPK
ISO6760LN
6 Forward,
3 Interlock Pairs
50 Mbps
Inverted
DW-16
5000 VRMS / 7000 VPK
See for detailed isolation ratings.
8.3.1 Electromagnetic Compatibility (EMC) Considerations
Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge
(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances
are regulated by international standards such as IEC 61000-4-x and CISPR 32. Although system-level
performance and reliability depends, to a large extent, on the application board design and layout, the ISO676x
family of devices incorporates many chip-level design improvements for overall system robustness. Some of
these improvements include:
• Robust ESD protection cells for input and output signal pins and inter-chip bond pads.
• Low-resistance connectivity of ESD cells to supply and ground pins.
• Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.
• Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance
path.
• PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic
SCRs.
• Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.
8.3.2 Interlock Capability
ISOLATION
The ISO6760L family incorporates a series of logic gates to protect adjacent channel pairings from both
registering high simultaneously. When paired with an IPM, this interlock circuitry provides protection proventing
shoot through current to both the high-side and low-side switch of the module. This design, shown in ISO6760L
Channel Pairing Block Diagram of Interlock, is used to make sure that when one of the channel pairings is logic
high, the other channel will output logic low. ISO6760L Device Truth Table provides the logic output state to the
corresponding input state for ISO6760L and ISO6760LN (Inverted) Device Truth Table provides the logic output
state to the corresponding input state for ISO6760LN (inverted output version).
INx_H
INx_L
I
N
T
E
R
L
O
C
K
OUTx_H
OUTx_L
Figure 8-3. ISO6760L Channel Pairing Block Diagram of Interlock
ISO6760L Device Truth Table
INx_H
22
INx_L
OUTx_H
High
Low
High
Low
Low
High
Low
High
High
High
Low
Low
Low
Low
Low
Low
Floating
Floating
Low
Low
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Table 8-2. ISO6760LN (Inverted) Device Truth Table
INx_H
INx_L
OUTx_H
OUTx_L
High
Low
Low
High
Low
High
High
Low
High
High
Low
Low
Low
Low
Low
Low
Floating
Floating
Low
Low
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8.4 Device Functional Modes
Function Table lists the functional modes for the ISO6760L devices.
Function Table
VCCI (1)
VCCO
PU
PU
INPUT
(INx_H and
INx_L) (3)
OUTPUT
(OUTx_H and
OUTx_L)
COMMENTS
Normal
Normal Operation: A channel output assumes the logic state of its input
noted in ISO6760L Device Truth Table and ISO6760LN (Inverted) Device Truth
Table .
H
L
Open
Output Low: When VCCI is unpowered and VCCO is powered up, the output
interlock circuit will set the output to logic low.
When VCCI transitions from unpowered to powered-up, a channel output
PD
PU
X
assumes the logic state in ISO6760L Device Truth Table and ISO6760LN
Low
(Inverted) Device Truth Table .
When VCCI transitions from powered-up to unpowered, channel output will be
the output low state.
X
PD
X
Undetermined
When VCCO is unpowered, a channel output is undetermined(2).
When VCCO transitions from unpowered to powered-up, a channel output
assumes the logic state of its input noted in ISO6760L Device Truth Table
and ISO6760LN (Inverted) Device Truth Table .
(1)
(2)
(3)
VCCI = Input-side VCC; VCCO = Output-side VCC; PU = Powered up (VCC ≥ 1.71 V); PD = Powered down (VCC ≤ 1.05 V); X = Irrelevant;
H = High level; L = Low level ; Z = High Impedance
The outputs are in undetermined state when 1.7 V < VCCI, VCCO < 2.25 V and 1.05 V < VCCI, VCCO < 1.71 V
A strongly driven input signal can weakly power the floating VCC through an internal protection diode and cause undetermined output
8.4.1 Device I/O Schematics
Input (Devices with F suffix)
Input (Devices without F suffix)
VCCI
VCCI
VCCI
VCCI
VCCI
VCCI
VCCI
1.5 M
985
985
INx
INx
1.5 M
Output
VCCO
~20
OUTx
Figure 8-4. Device I/O Schematics
24
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The ISO6760L devices are high-performance, six-channel digital isolators. The ISO6760L devices use singleended CMOS-logic switching technology with built in hardware interlock logic. The supply voltage range is from
1.71 V to 5.5 V for both supplies, VCC1 and VCC2. Since an isolation barrier separates the two sides, each side
can be sourced independently with any voltage within recommended operating conditions. As an example, it
is possible to supply ISO6760L VCC1 with 3.3 V (which is within 1.71 V to 5.5 V) and VCC2 with 5V (which is
also within 1.71 V to 5.5 V). You can use the digital isolator as a logic-level translator in addition to providing
isolation. When designing with digital isolators, keep in mind that because of the single-ended design structure,
digital isolators do not conform to any specific interface standard and are only intended for isolating single-ended
CMOS or TTL digital signal lines. The isolator is typically placed between the data controller (that is, MCU or
FPGA), and a data converter or a line transceiver, regardless of the interface type or standard.
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9.2 Typical Application
Figure 9-1 shows the isolated connections between a processor and Intelligent Power Module (IPM) interface
implementation.
5.0V
DC-DC
24V
10 μF
Vcc
D2
IN
OUT
10 μF
LDO
SN6505
15V_ISO
10 μF
EN
GND
D1
Reinforced ISO Barrier
GND
5.0V
5V_ISO
OUT
IN
1 µF
LDO
GND
EN
HV DC+
15V_ISO
0.1 μF
0.1 μF
0.1 μF
VCC1
VDDIO
UH
VH
CONTROLLER
WH
UL
VL
WL
2
4
6
3
UHIN
INA_H
OUTA_H
OUTB_H
INB_H
15
VHIN
13
WHIN
INC_H
OUTC_H
ISO6760L
Signal
Level shift
+
Bias
Supply
Bootstrap
High side
gate driver
High side
gate driver
OUTA_L
INB_L
OUTB_L 12
INC_L
OUTC_L 10
GND1
GND2
14
U
High side
gate driver
3 phase
IGBT
inverter
11
INA_L
5
7
IPM with SIGNAL LEVEL-SHIFT and
BOOTSTRAP for GATE DRIVER BIAS SUPPLY
16
VCC2
1
ULIN
VLIN
V
M
W
Low side
gate driver
VSS
8
WLIN
9
HV DCHV DC-
Figure 9-1. Isolation for Intelligent Power Module (IPM) Interface
26
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9.2.1 Design Requirements
To design with these devices, use the parameters listed in Table 9-1.
Table 9-1. Design Parameters
PARAMETER
VALUE
Supply voltage, VCC1 and VCC2
1.71 V to 1.89 V and 2.25 V to 5.5 V
Decoupling capacitor between VCC1 and GND1
0.1 µF
Decoupling capacitor from VCC2 and GND2
0.1 µF
9.2.2 Detailed Design Procedure
Unlike optocouplers, which require external components to improve performance, provide bias, or limit current,
the ISO6760L family of devices only require two external bypass capacitors to operate.
1
INA_H
2
INA_L
3
INB_H
4
INB_L
5
INC_H
6
INC_L
7
8
GND1
I
N
T
E
R
L
O
C
K
ISOLATION
VCC1
I
N
T
E
R
L
O
C
K
I
N
T
E
R
L
O
C
K
16
VCC2
15
OUTA_H
14
OUTB_H
13
OUTC_H
12
OUTA_L
11
OUTB_L
10
OUTC_L
9
GND2
Figure 9-2. Typical ISO6760L Circuit Hook-up
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9.2.3 Application Curve
The following diagrams of the ISO6760L family of devices show how the hardware interlock circuitry protects
against shoot through current. Within a channel pairing, both outputs cannot be high simultaneously. ISO6760L
Interlock Diagram shows the ISO6760L demonstrating the hardware interlock on a 200 Hz input signal out of
phase between two adjacent channels. ISO6760L Interlock Diagram shows the the normal ISO6760 (device
offered without interlock circuitry) with a 200 Hz input signal out of phase between two adjacent channels for
comparison.
Figure 9-3. ISO6760L Interlock Diagram
28
Figure 9-4. ISO6760 (Device without Interlock)
Diagram
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10 Insulation Lifetime
Insulation lifetime projection data is collected by using industry-standard Time Dependent Dielectric Breakdown
(TDDB) test method. In this test, all pins on each side of the barrier are tied together creating a two-terminal
device and high voltage applied between the two sides; See Figure 10-1 for TDDB test setup. The insulation
breakdown data is collected at various high voltages switching at 60 Hz over temperature. For reinforced
insulation, VDE standard requires the use of TDDB projection line with failure rate of less than 1 part per million
(ppm). Even though the expected minimum insulation lifetime is 20 years at the specified working isolation
voltage, VDE reinforced certification requires additional safety margin of 20% for working voltage and 50% for
lifetime which translates into minimum required insulation lifetime of 30 years at a working voltage that's 20%
higher than the specified value.
Figure 10-2 shows the intrinsic capability of the isolation barrier to withstand high voltage stress over its lifetime.
Based on the TDDB data, the intrinsic capability of the insulation is 1500 VRMS with a lifetime of 36 years. Other
factors, such as package size, pollution degree, material group, etc. can further limit the working voltage of the
component. The working voltage of DW-16 package is specified upto 1500 VRMS. At the lower working voltages,
the corresponding insulation lifetime is much longer than 36 years.
A
Vcc 1
Vcc 2
Time Counter
> 1 mA
DUT
GND 1
GND 2
VS
Oven at 150 °C
Figure 10-1. Test Setup for Insulation Lifetime Measurement
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1.E+12
1.E+11
50 %
1.E+10
54 Yrs
1.E+09
36 Yrs
Time to Fail (sec)
1.E+08
TDDB Line (
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