ISO7021FD

ISO7021 ISO7021 SLLSFA0B – JULY 2019 – REVISED AUGUST 2020 SLLSFA0B – JULY 2019 – REVISED AUGUST 2020 www.ti.com ISO7021 Ultra-Low Power Two-Channel Digital Isolator • 1 Features • • • • • • • • • Ultra-low power consumption – 4.8 μA per channel quiescent current (3.3 V) – 15 μA per channel at 100 kbps (3.3 V) – 120 μA per channel at 1 Mbps (3.3 V) Robust isolation barrier – >100-year projected lifetime – 3000 VRMS isolation rating – ±100 kV/μs typical CMTI Wide supply range: 1.71 V to 1.89 V and 2.25 V to 5.5 V Wide temperature range: –55°C to +125°C Small 8-SOIC package (8-D) Signaling rate: Up to 4 Mbps Default output High (ISO7021) and Low (ISO7021F) options Robust electromagnetic compatibility (EMC) – System-level ESD, EFT, and surge immunity – ±8 kV IEC 61000-4-2 contact discharge protection across isolation barrier – Very low emissions Safety-related certifications (planned): – DIN V VDE 0884-11:2017-01 – UL 1577 Component Recognition Program – IEC 60950-1, IEC 62368-1, IEC 61010-1, IEC60601-1 and GB 4943.1-2011 certifications – IECEx (IEC 60079-0 & IEC 60079-11) and ATEX (EN IEC60079-0 & EN 60079-11) 2 Applications • • 4-mA to 20-mA loop powered field transmitters Factory automation and process automation Low-power GPIO, UART isolation 3 Description The ISO7021 device is an ultra-low power, multichannel digital isolator that can be used to isolate CMOS or LVCMOS digital I/Os. Each isolation channel has a logic input and output buffer separated by a double capacitive silicon dioxide (SiO2) insulation barrier. Innovative edge based architecture combined with an ON-OFF keying modulation scheme allows these isolators to consume very-low power while meeting 3000-VRMS isolation rating per UL1577. The per channel dynamic current consumption of the device is under 120 μA/Mbps and the per channel static current consumption is 4.8 μA at 3.3 V, allowing for use of the ISO7021 in both power and thermal constrained system designs. The device can operate as low as 1.71 V, as high as 5.5 V , and is fully functional with different supply voltages on each side of isolation barrier. The twochannel isolator comes in a narrow body 8-SOIC package with one forward and one reverse-direction channel in a 8-SOIC package. The device has default output high and low options. If the input power or signal is lost, default output is high for the ISO7021 device without the suffix F and low for the ISO7021F device with the F suffix. See the Device Functional Modes section for more information. Device Information PART NUMBER(1) ISO7021 (1) PACKAGE SOIC (8-D) BODY SIZE (NOM) 4.90 mm × 3.91 mm For all available packages, see the orderable addendum at the end of the data sheet. 400 VCC1 VCC2 VCC2 Current per Channel (PA) VCC1 VDD ISO7021 MCU ADC DGND GND1 Digital Ground GND2 Galvanic Isolation Barrier ISO Ground 100 10 Simplified Application Schematic 2 1 10 100 Data Rate (kbps) 1000 4000 SLLS Data Rate vs Power Consumption at 3.3 V An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated intellectual property matters and other important disclaimers. PRODUCTION DATA. Product Folder Links: ISO7021 1 ISO7021 www.ti.com SLLSFA0B – JULY 2019 – REVISED AUGUST 2020 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................3 Pin Functions.................................................................... 3 6 Specifications.................................................................. 4 6.1 Absolute Maximum Ratings ....................................... 4 6.2 ESD Ratings .............................................................. 4 6.3 Recommended Operating Conditions ........................5 6.4 Thermal Information ...................................................6 6.5 Power Ratings ............................................................6 6.6 Insulation Specifications ............................................ 7 6.7 Safety-Related Certifications ..................................... 8 6.8 Safety Limiting Values ................................................8 6.9 Electrical Characteristics 5V Supply .......................... 9 6.10 Supply Current Characteristics 5V Supply ...............9 6.11 Electrical Characteristics 3.3V Supply ................... 10 6.12 Supply Current Characteristics 3.3V Supply ..........10 6.13 Electrical Characteristics 2.5V Supply ................... 11 6.14 Supply Current Characteristics 2.5V Supply .......... 11 6.15 Electrical Characteristics 1.8V Supply ................... 12 6.16 Supply Current Characteristics 1.8V Supply ..........12 6.17 Switching Characteristics .......................................13 7 Parameter Measurement Information.......................... 14 8 Detailed Description......................................................15 8.1 Overview................................................................... 15 8.2 Functional Block Diagram......................................... 15 8.3 Feature Description...................................................16 8.4 Device Functional Modes..........................................17 9 Application and Implementation.................................. 18 9.1 Application Information............................................. 18 9.2 Typical Application.................................................... 20 10 Power Supply Recommendations..............................23 11 Layout........................................................................... 24 11.1 Layout Guidelines................................................... 24 11.2 Layout Example...................................................... 24 12 Device and Documentation Support..........................25 12.1 Documentation Support.......................................... 25 12.2 Receiving Notification of Documentation Updates..25 12.3 Support Resources................................................. 25 12.4 Trademarks............................................................. 25 12.5 Electrostatic Discharge Caution..............................25 12.6 Glossary..................................................................25 13 Mechanical, Packaging, and Orderable Information.................................................................... 25 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision * (July 2019) to Revision A (October 2019) Page • RTM release....................................................................................................................................................... 1 Changes from Revision A (October 2019) to Revision B (August 2020) Page • Updated front page by renaming the certifications, adding (planned) and including the completed ATEX certification..........................................................................................................................................................1 • Added IECEx and ATEX to Safety-Related Certifications...................................................................................8 • Added Section 9.1.2 section............................................................................................................................. 20 • Updated pin numbers to reflect 8D package ................................................................................................... 21 2 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ISO7021 ISO7021 www.ti.com SLLSFA0B – JULY 2019 – REVISED AUGUST 2020 Device Comparison Table Table 5-1. Device Features PART NUMBER CHANNEL DIRECTION MAXIMUM DATA RATE DEFAULT OUTPUT PACKAGE RATED ISOLATION ISO7021 1 Forward, 1 Reverse 4 Mbps High SOIC-8 3000 VRMS / 4242 VPK ISO7021 with F suffix 1 Forward, 1 Reverse 4 Mbps Low SOIC-8 3000 VRMS / 4242 VPK 5 Pin Configuration and Functions VCC1 1 OUTA 2 INB 3 GND1 4 ISOLATION Pin Functions 8 VCC2 7 INA 6 OUTB 5 GND2 Not to scale Figure 5-1. D Package 8-Pin SOIC Top View PIN I/O DESCRIPTION NAME NO. GND1 4 — Ground connection for VCC1 GND2 5 — Ground connection for VCC2 INA 7 I INB 3 I Input, channel B OUTA 2 O Output, channel A Input, channel A OUTB 6 O Output, channel B VCC1 1 — Power supply, side 1 VCC2 8 — Power supply, side 2 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ISO7021 3 ISO7021 www.ti.com SLLSFA0B – JULY 2019 – REVISED AUGUST 2020 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) (2) (3) Supply Voltage MIN MAX VCC1 to GND1 -0.5 6 VCC2 to GND2 -0.5 6 Input/Output Voltage INx to GNDx -0.5 VCCX + 0.5 OUTx to GNDx -0.5 VCCX + 0.5 Output Current Io -15 Temperature (1) (2) (3) Operating junction temperature, TJ Storage temperature, Tstg -65 UNIT V V 15 mA 150 °C 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak voltage values Maximum voltage must not exceed 6 V. 6.2 ESD Ratings (1) (2) VALUE V(ESD) (1) (2) (3) (4) 4 Electrostatic discharge Human body model (HBM), per ANSI/ ESDA/JEDEC JS-001, all pins(1) ±6000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±1500 Contact discharge per IEC 61000-4-2; Isolation barrier withstand test(3) (4) ±8000 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. IEC ESD strike is applied across the barrier with all pins on each side tied together creating a two-terminal device. Testing is carried out in air or oil to determine the intrinsic contact discharge capability of the device. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ISO7021 ISO7021 www.ti.com SLLSFA0B – JULY 2019 – REVISED AUGUST 2020 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT 1.89 V 2.25 5.5 V 1.71 1.89 V VCC1 (1) Supply Voltage Side 1 VCCO (2)= 1.8 V 1.71 (1) Supply Voltage Side 1 VCCO = 2.5 V to 5 V VCC2 (1) Supply Voltage Side 2 VCCO = 1.8 V Supply Voltage Side 2 VCCO = 2.5 V to 5 V VCC1 VCC2 (1) VIH High level Input voltage VIL Low level Input voltage IOH High level output current IOL Low level output current DR Data Rate TA Ambient temperature 2.25 5.5 V 0.7 x VCCI VCCI V 0 0.3 x VCCI V VCCO = 5 V -4 mA VCCO = 3.3 V -2 mA VCCO = 2.5 V -1 mA VCCO = 1.8 V -1 mA VCCO = 5 V 4 mA VCCO = 3.3 V 2 mA VCCO = 2.5 V 1 mA VCCO = 1.8 V (1) (2) NOM 1 mA 0 4 Mbps -55 125 °C VCC1 and VCC2 can be set independent of one another VCCI = Input-side VCC; VCCO = Output-side VCC Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ISO7021 5 ISO7021 www.ti.com SLLSFA0B – JULY 2019 – REVISED AUGUST 2020 6.4 Thermal Information ISO7021 THERMAL METRIC(1) UNIT D (SOIC) 8 PINS RθJA Junction-to-ambient thermal resistance 94.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 28.6 °C/W RθJB Junction-to-board thermal resistance 43.6 °C/W ψJT Junction-to-top characterization parameter 2.3 °C/W ψJB Junction-to-board characterization parameter 42.9 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance — °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 6.5 Power Ratings PARAMETER 6 PD Maximum power dissipation (both sides) PD1 Maximum power dissipation (side-1) PD2 Maximum power dissipation (side-2) TEST CONDITIONS VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF, Input a 2-MHz 50% duty cycle square wave Submit Document Feedback MIN TYP MAX UNIT 8.4 mW 4.2 mW 4.2 mW Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ISO7021 ISO7021 www.ti.com SLLSFA0B – JULY 2019 – REVISED AUGUST 2020 6.6 Insulation Specifications PARAMETER SPECIFIC ATIONS TEST CONDITIONS UNIT 8-D IEC 60664-1 CLR External clearance(1) Side 1 to side 2 distance through air 4 mm CPG External creepage(1) Side 1 to side 2 distance across package surface 4 mm DTI Distance through the insulation Minimum internal gap (internal clearance) >17 µm CTI Comparative tracking index IEC 60112; UL 746A >600 V Material Group According to IEC 60664-1 I Rated mains voltage ≤ 150 VRMS I-IV Rated mains voltage ≤ 300 VRMS I-III Maximum repetitive peak isolation voltage AC voltage (bipolar) 566 Maximum isolation working voltage AC voltage (sine wave); time-dependent dielectric 400 breakdown (TDDB) test; VRMS DC voltage 566 VDC 4242 VPK VPK Overvoltage category DIN V VDE V 0884-11:2017-01 VIORM VIOWM VIOTM Maximum transient isolation voltage VTEST = VIOTM , t = 60 s (qualification); VTEST = 1.2 × VIOTM, t = 1 s (100% production) VIOSM Maximum surge isolation voltage(2) Test method per IEC 62368-1, 1.2/50 µs waveform, VTEST = 1.6 × VIOSM = TBD VPK (qualification) 4000 Method a: After I/O safety test subgroup 2/3, Vini = VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM , tm = 10 s ≤5 Method a: After environmental tests subgroup 1, Vini = VIOTM, tini = 60 s; Vpd(m) = 1.6 × VIORM , tm = 10 s ≤5 Apparent charge(3) qpd VPK pC Method b1: At routine test (100% production) and preconditioning (type test), Vini = VIOTM, tini = 1 s; ≤ 5 Vpd(m) = 1.875 × VIORM , tm = 1 s Barrier capacitance, input to output(4) CIO Insulation resistance, input to output(4) RIO VIO = 0.4 × sin (2 πft), f = 1 MHz 1 pF 1012 VIO = 500 V, TA = 25°C > VIO = 500 V, 100°C ≤ TA ≤ 150°C > 1011 VIO = 500 V at TS = 150°C > Ω 109 Pollution degree 2 Climatic category 55/125/ 21 UL 1577 VISO (1) (2) (3) (4) Withstand isolation voltage VTEST = VISO , t = 60 s (qualification); VTEST = 1.2 × VISO , t = 1 s (100% production) 3000 VRMS Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications. Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier. Apparent charge is electrical discharge caused by a partial discharge (pd). All pins on each side of the barrier tied together creating a two-pin device. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ISO7021 7 ISO7021 www.ti.com SLLSFA0B – JULY 2019 – REVISED AUGUST 2020 6.7 Safety-Related Certifications VDE CSA Plan to certify Certified according to according to DIN V IEC 60950-1 and IEC VDE V 0884-11:201762368-1 01 Maximum transient isolation voltage, 4242 VPK; Maximum repetitive peak isolation voltage, 566 VPK; Maximum surge isolation voltage, 4000 VPK Certificate planned 3000 VRMS insulation per CSA 60950-1-07+A1+A2, IEC 60950-1 2nd Ed.+A1+A2, CSA 62368-1- 14 and IEC 62368-1:2014 370 VRMS (DBQ-16) maximum working voltage (pollution degree 2, material group I) Certificate planned UL CQC Plan to certify Plan to certify according to UL 1577 according to Component GB4943.1-2011 Recognition Program Basic insulation, Altitude ≤ 5000 m, Tropical Climate, 250 VRMS maximum working voltage Single protection, 3000 VRMS Certificate planned Certificate planned TUV IECEx / ATEX Plan to certify according to EN 61010-1:2010 (3rd Ed) and EN 609501:2006/A2:2013 Certified for use in intrinsic safety (IS) to IS applications under ATEX and IECEx. 3000 VRMS insulation per EN 61010-1:2010 (3rd Ed) up to working voltage of 300 VRMS 3000 VRMS insulation per EN 609501:2006/A2:2013 up to working voltage of 370 VRMS ATEX: EN IEC60079-0:2018 and EN 60079-11:2012 IECEx:IEC 60079-0:2017 (7th Ed) and IEC60079-11:2011 (6th Ed) Markings: II 1G Ex ia IIC Ga See the Section 9.1.2 Certificate planned IECEx certificate: IECEx CSA 20.012U ATEX certificate: CSANe 20ATEX2090U 6.8 Safety Limiting Values Safety limiting(1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RθJA = 94.3°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C 241 mA RθJA = 94.3°C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C 368 RθJA = 94.3°C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C 482 RθJA = 94.3°C/W, VI = 1.89 V, TJ = 150°C, TA = 25°C 701 mA 1325 mW 150 °C D-8 PACKAGE IS PS Safety input, output, or total power TS Maximum safety temperature (1) 8 Safety input, output, or supply current RθJA = 94.3°C/W, TJ = 150°C, TA = 25°C mA The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be exceeded. These limits vary with the ambient temperature, TA. The junction-to-air thermal resistance, RθJA, in the table is that of a device installed on a high-K test board for leaded surface-mount packages. Use these equations to calculate the value for each parameter: TJ = TA + RθJA × P, where P is the power dissipated in the device. TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum allowed junction temperature. PS = IS × VI, where VI is the maximum input voltage. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ISO7021 ISO7021 www.ti.com SLLSFA0B – JULY 2019 – REVISED AUGUST 2020 6.9 Electrical Characteristics 5V Supply over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VIT+(IN) Rising input switching threshold MIN VIT-(IN) Falling input switching threshold High-level output voltage IOH = -4 mA VOL Low-level output voltage IOL = 4 mA VI(HYS) Input threshold voltage hysteresis IIH High-level input current VIH = VCCI (1) at INx IIL Low-level input current VIL = 0 V at INx -1 CMTI Common mode transient immunity VI = VCC or 0 V, VCM = 1200 V 50 Input Capacitance (2) VI = VCC/ 2 + 0.4×sin(2πft), f = 2 MHz, VCC = 5 V (1) (2) MAX UNIT 0.7 x VCCI (1) VOH Ci TYP V 0.3 x VCCI V VCCO - 0.4 V 0.4 V 0.1 x VCCI V 1 µA µA 100 kV/us 2 pF VCCI = Input-side VCC; VCCO = Output-side VCC Measured from input pin to same side ground. 6.10 Supply Current Characteristics 5V Supply over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS SUPPLY CURRENT MIN TYP MAX UNIT ISO7021 Supply current - DC signal VI = VCC1 (ISO7021); VI = 0 V (ISO7021 with F suffix) ICC1 5.9 11.8 µA ICC2 5.9 11.8 µA VI = 0 V (ISO7021); VI = VCC1 (ISO7021 with F suffix) ICC1 6.5 11.9 µA ICC2 6.5 11.9 µA ICC1 7.2 12.2 µA ICC2 7.2 12.2 µA ICC1 15.9 27.7 µA ICC2 15.9 27.7 µA ICC1 129.0 175.0 µA ICC2 129.0 175.0 µA ICC1(ch) + ICC2(ch) 5.9 11.4 µA ICC1(ch) + ICC2(ch) 6.5 11.8 µA ICC1(ch) + ICC2(ch) 7.2 12.2 µA 10 kbps, No Load Supply current - AC signal 100 kbps, No Load 1 Mbps, No Load VI = VCC1 (ISO7021); VI = 0 V (ISO7021 with F suffix) VI = 0 V (ISO7021); VI = VCC1 (ISO7021 Total Supply Current with F suffix) Per Channel 10 kbps, No Load 100 kbps, No Load ICC1(ch) + ICC2(ch) 15.9 27.8 µA 1 Mbps, No Load ICC1(ch) + ICC2(ch) 129.0 175.0 µA Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ISO7021 9 ISO7021 www.ti.com SLLSFA0B – JULY 2019 – REVISED AUGUST 2020 6.11 Electrical Characteristics 3.3V Supply over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN Rising input switching threshold VIT-(IN) Falling input switching threshold VOH High-level output voltage IOH = -2mA VOL Low-level output voltage IOL = 2mA VI(HYS) Input threshold voltage hysteresis IIH High-level input current VIH = VCCI (1) at INx IIL Low-level input current VIL = 0 V at INx -1 CMTI Common mode transient immunity VI = VCC or 0 V, VCM = 1200 V 50 Ci Input Capacitance(2) VI = VCC/ 2 + 0.4×sin(2πft), f = 2 MHz, VCC = 3.3 V (1) (2) TYP MAX UNIT 0.7 x VCCI (1) VIT+(IN) V 0.3 x VCCI V VCCO - 0.3 V 0.3 V 0.1 x VCCI V 1 µA µA 100 kV/us 2 pF VCCI = Input-side VCC; VCCO = Output-side VCC Measured from input pin to same side ground. 6.12 Supply Current Characteristics 3.3V Supply over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS SUPPLY CURRENT MIN TYP MAX UNIT ISO7021 Supply current - DC signal VI = VCC1 (ISO7021); VI = 0 V (ISO7021 with F suffix) ICC1 4.8 7.8 µA ICC2 4.8 7.8 µA VI = 0 V (ISO7021); VI = VCC1 (ISO7021 with F suffix) ICC1 5.2 8.4 µA ICC2 5.2 8.4 µA ICC1 5.7 8.8 µA 10 kbps, No Load Supply current - AC signal 100 kbps, No Load 1 Mbps, No Load VI = VCC1 (ISO7021); VI = 0 V (ISO7021 with F suffix) VI = 0 V (ISO7021); VI = VCC1 (ISO7021 Total Supply Current with F suffix) Per Channel 10 kbps, No Load 10 ICC2 5.7 8.8 µA ICC1 15.0 23.0 µA ICC2 15.0 23.0 µA ICC1 120.0 153.0 µA ICC2 120.0 155.0 µA ICC1(ch) + ICC2(ch) 4.8 7.8 µA ICC1(ch) + ICC2(ch) 5.2 8.4 µA ICC1(ch) + ICC2(ch) 5.7 8.8 µA 100 kbps, No Load ICC1(ch) + ICC2(ch) 15.0 23.0 µA 1 Mbps, No Load ICC1(ch) + ICC2(ch) 120.0 153.0 µA Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ISO7021 ISO7021 www.ti.com SLLSFA0B – JULY 2019 – REVISED AUGUST 2020 6.13 Electrical Characteristics 2.5V Supply over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN Rising input switching threshold VIT-(IN) Falling input switching threshold VOH High-level output voltage IOH = -1mA VOL Low-level output voltage IOL = 1mA VI(HYS) Input threshold voltage hysteresis IIH High-level input current VIH = VCCI (1) at INx IIL Low-level input current VIL = 0 V at INx -1 CMTI Common mode transient immunity VI = VCC or 0 V, VCM = 1200 V 50 Ci Input Capacitance(2) VI = VCC/ 2 + 0.4×sin(2πft), f = 2 MHz, VCC = 2.5 V (1) (2) TYP MAX UNIT 0.7 x VCCI (1) VIT+(IN) V 0.3 x VCCI V VCCO - 0.2 V 0.2 V 0.1 x VCCI V 1 µA µA 100 kV/us 2 pF VCCI = Input-side VCC; VCCO = Output-side VCC Measured from input pin to same side ground. 6.14 Supply Current Characteristics 2.5V Supply over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS SUPPLY CURRENT MIN TYP MAX UNIT ISO7021 Supply current - DC signal VI = VCC1 (ISO7021); VI = 0 V (ISO7021 with F suffix) ICC1 4.4 6.9 µA ICC2 4.3 6.9 µA VI = 0 V (ISO7021); VI = VCC1 (ISO7021 with F suffix) ICC1 4.8 7.4 µA ICC2 4.8 7.4 µA ICC1 5.0 7.8 µA 10 kbps, No Load Supply current - AC signal 100 kbps, No Load 1 Mbps, No Load VI = VCC1 (ISO7021); VI = 0 V (ISO7021 with F suffix) VI = 0 V (ISO7021); VI = VCC1 (ISO7021 Total Supply Current with F suffix) Per Channel 10 kbps, No Load ICC2 5.0 7.8 µA ICC1 12.4 21.2 µA ICC2 12.4 21.2 µA ICC1 112.0 144.0 µA ICC2 113.0 144.0 µA ICC1(ch) + ICC2(ch) 4.4 6.9 µA ICC1(ch) + ICC2(ch) 4.8 7.4 µA ICC1(ch) + ICC2(ch) 5.0 7.8 µA 100 kbps, No Load ICC1(ch) + ICC2(ch) 12.4 21.2 µA 1 Mbps, No Load ICC1(ch) + ICC2(ch) 113.0 144.0 µA Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ISO7021 11 ISO7021 www.ti.com SLLSFA0B – JULY 2019 – REVISED AUGUST 2020 6.15 Electrical Characteristics 1.8V Supply over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VIT+(IN) Rising input switching threshold MIN VIT-(IN) Falling input switching threshold High-level output voltage IOH = -1mA VOL Low-level output voltage IOL = 1mA VI(HYS) Input threshold voltage hysteresis IIH High-level input current VIH = VCCI (1) at INx IIL Low-level input current VIL = 0 V at INx -1 CMTI Common mode transient immunity VI = VCC or 0 V, VCM = 1200 V 50 Input Capacitance(2) VI = VCC/ 2 + 0.4×sin(2πft), f = 2 MHz, VCC = 1.8 V (1) (2) MAX UNIT 0.7 x VCCI (1) VOH Ci TYP V 0.3 x VCCI V VCCO - 0.2 V 0.2 V 0.1 x VCCI V 1 µA µA 100 kV/us 2 pF VCCI = Input-side VCC; VCCO = Output-side VCC Measured from input pin to same side ground. 6.16 Supply Current Characteristics 1.8V Supply over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS SUPPLY CURRENT MIN TYP MAX UNIT ISO7021 Supply current - DC signal VI = VCC1 (ISO7021); VI = 0 V (ISO7021 with F suffix) ICC1 3.4 5.7 µA ICC2 3.4 5.7 µA VI = 0 V (ISO7021); VI = VCC1 (ISO7021 with F suffix) ICC1 3.8 6.2 µA ICC2 3.8 6.2 µA ICC1 4.1 6.7 µA ICC2 4.1 6.7 µA ICC1 9.9 19.3 µA ICC2 9.9 19.3 µA ICC1 90.0 134.0 µA ICC2 90.0 134.0 µA ICC1(ch) + ICC2(ch) 3.4 5.7 µA ICC1(ch) + ICC2(ch) 3.8 6.2 µA ICC1(ch) + ICC2(ch) 3.9 6.7 µA 10 kbps, No Load Supply current - AC signal 100 kbps, No Load 1 Mbps, No Load VI = VCC1 (ISO7021); VI = 0 V (ISO7021 with F suffix) VI = 0 V (ISO7021); VI = VCC1 (ISO7021 Total Supply Current with F suffix) Per Channel 10 kbps, No Load 12 100 kbps, No Load ICC1(ch) + ICC2(ch) 9.9 19.3 µA 1 Mbps, No Load ICC1(ch) + ICC2(ch) 90.0 134.0 µA Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ISO7021 ISO7021 www.ti.com SLLSFA0B – JULY 2019 – REVISED AUGUST 2020 6.17 Switching Characteristics VCC1, VCC2 = 1.71 V to 1.89 V or 2.25 V to 5.5 V (over recommended operating conditions unless otherwise noted) PARAMETER tPLH, tPHL Propagation delay time tP(dft) Propagation delay drift tUI Minimum pulse width TEST CONDITIONS MIN See Figure 7-1 TYP MAX UNIT 140 165 ns 15 See Figure 7-1 ps/℃ 250 ns PWD Pulse width distortion 10 ns tsk(o) Channel to channel output skew time 10 ns tsk(p-p) Part to part skew time tr Output signal rise time 70 ns VCC = 1.71 V to 1.9 V, See Figure 7-1 8 ns VCC = 2.25 V to 5.5 V, See Figure 7-1 5 ns VCC = 1.71 V to 1.9 V, See Figure 7-1 8 ns VCC = 2.25 V to 5.5 V, See Figure 7-1 5 ns 750 us 5 ms tf Output signal fall time tDO Default output delay time from input power loss tPU Time from UVLO to valid output data 1 FR Refresh rate 5 See Figure 7-2 400 10 kbps Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ISO7021 13 ISO7021 www.ti.com SLLSFA0B – JULY 2019 – REVISED AUGUST 2020 7 Parameter Measurement Information Isolation Barrier IN Input Generator (See Note A) VCCI VI VI OUT 50% 50% 0V tPLH tPHL CL See Note B VO VOH 90% 50% VO 50% 10% VOL tf tr A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3ns, ZO = 50 Ω. At the input, 50 Ω resistor is required to terminate Input Generator signal. It is not needed in actual application. B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 7-1. Switching Characteristics Test Circuit and Voltage Waveforms VI VCC VCC Isolation Barrier IN = 0 V (Devices without suffix F) IN = VCC (Devices with suffix F) VI IN 1.7 V 0V OUT VO tDO CL See Note A VO default high VOH 50% VOL default low A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. B. Power Supply Ramp Rate = 10 mV/ns Figure 7-2. Default Output Delay Time Test Circuit and Voltage Waveforms VCCI VCCO C = 0.1 µF ±1% Pass-fail criteria: The output must remain stable. Isolation Barrier S1 C = 0.1 µF ±1% IN OUT + VOH or VOL CL See Note A GNDI + VCM ± ± GNDO A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 7-3. Common-Mode Transient Immunity Test Circuit 14 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ISO7021 ISO7021 www.ti.com SLLSFA0B – JULY 2019 – REVISED AUGUST 2020 8 Detailed Description 8.1 Overview The ISO7021 device uses edge encoding of data with an ON-OFF keying (OOK) modulation scheme to transmit the digital data across a silicon dioxide isolation barrier. The transmitter uses a high frequency carrier signal to pass data across the barrier representing a signal edge transition. Using this method achieves very low power consumption and high immunity. The receiver demodulates the carrier signal after advanced signal conditioning and produces the output through a buffer stage. For low data rates, a refresh logic option is available to make sure the output state matches the input state. Advanced circuit techniques are used to maximize the CMTI performance and minimize the radiated emissions due to the high frequency carrier and IO buffer switching. The conceptual block diagram of a digital capacitive isolator, Figure 8-2, shows a functional block diagram of a typical channel. 8.2 Functional Block Diagram Transmitter Receiver OOK Modulation TX IN Edge Encoding TX Signal Conditioning Refresh Logic Oscillator SiO2 based Capacitive Isolation Barrier RX Signal Conditioning Envelope Detection RX OUT Watch Dog Timer Figure 8-1. Conceptual Block Diagram of a Digital Capacitive Isolator Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ISO7021 15 ISO7021 www.ti.com SLLSFA0B – JULY 2019 – REVISED AUGUST 2020 Transmitter Receiver OOK Modulation TX IN Edge Encoding TX Signal Conditioning Refresh Logic Oscillator SiO2 based Capacitive Isolation Barrier RX Signal Conditioning Envelope Detection RX OUT Watch Dog Timer Figure 8-2. Conceptual Block Diagram of a Digital Capacitive Isolator 8.3 Feature Description 8.3.1 Refresh The ISO7021 uses an edge based encoding scheme to transfer an input signal change across the isolation barrier versus sending across the DC state. The built in refresh function consistently validates that the DC output state of each isolator channel matches the DC input state. An internal watchdog timer monitors for activity on the individual inputs and transmits the logic state when there is no input signal transition for more than 100 µs. This ensures that the input and output state of the isolator always match. 8.3.2 Electromagnetic Compatibility (EMC) Considerations Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge (ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level performance and reliability depends, to a large extent, on the application board design and layout, the ISO70xx family of devices incorporates many chip-level design improvements for overall system robustness. Some of these improvements include: • Robust ESD protection cells for input and output signal pins and inter-chip bond pads. • Low-resistance connectivity of ESD cells to supply and ground pins. • Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events. • Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance path. • PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic SCRs. • Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation. The device has no issue being able to meet either CISPR 22 Class A and CISPR22 Class B standards in an unshielded environment. 16 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ISO7021 ISO7021 www.ti.com SLLSFA0B – JULY 2019 – REVISED AUGUST 2020 8.4 Device Functional Modes Table 8-1 shows the functional modes for the device. Table 8-1. Function Table VCCI 1 VCCO PU PU INPUT (INx) 3 OUTPUT (OUTx) H H L L X Default The channel output assumes the selected default option. When VCCI is unpowered, a channel output assumes the logic state based on the selected default option. Default is High for the device without the F suffix and Low for device with the F suffix. When VCCI transitions from unpowered to powered-up, a channel output assumes the logic state of the input. When VCCI transitions from powered-up to unpowered, channel output assumes the selected default state. PD PU X Default X PD X Undetermined COMMENTS Normal Operation: A channel output assumes the logic state of its input. When VCCO is unpowered, a channel output is undetermined and tri state2. When VCCO transitions from unpowered to powered-up, a channel output assumes the selected default option. 1. VCCI = Input-side VCC; VCCO = Output-side VCC; PU = Powered up (VCC ≥ 1.54 V); PD = Powered down (VCC ≤ 1.54); X = Irrelevant; H = High level; L = Low level ; Z = High Impedance. 2. The outputs are in undetermined state when 1.54 V < VCCI, VCCO < 1.54 V. 3. A strongly driven input signal can weakly power the floating VCC through an internal protection diode and cause undetermined output. 8.4.1 Device I/O Schematics Output Input VCCO VCCI VCCI VCCI ~20 985 OUTx INx Figure 8-3. Device I/O Schematics Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ISO7021 17 ISO7021 www.ti.com SLLSFA0B – JULY 2019 – REVISED AUGUST 2020 9 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The ISO7021 device is an ultra-low power digital isolator. The device uses single-ended CMOS-logic switching technology. The voltage range is from 1.71 V to 1.89 V and 2.25 V to 5.5 V for both supplies, VCC1 and VCC2, and can be set irrespective of one another. When designing with digital isolators, keep in mind that because of the single-ended design structure, digital isolators do not conform to any specific interface standard and are only intended for isolating single-ended CMOS or TTL digital signal lines. The isolator is typically placed between the data controller (that is, μC or UART), and a data converter or a line transceiver, regardless of the interface type or standard. See Isolated power and data interface for low-power applications reference design TI Design for detailed information on designing the ISO70xx in low-power applications. 9.1.1 Insulation Lifetime Insulation lifetime projection data is collected by using industry-standard Time Dependent Dielectric Breakdown (TDDB) test method. In this test, all pins on each side of the barrier are tied together creating a two-terminal device and high voltage applied between the two sides; see Figure 9-1 for TDDB test setup. The insulation breakdown data is collected at various high voltages switching at 60 Hz over temperature. For reinforced insulation, VDE standard requires the use of TDDB projection line with failure rate of less than 1 part per million (ppm) and a minimum insulation lifetime of 20 years. VDE standard also requires additional safety margin of 20% for working voltage and 87.5% for insulation lifetime which translates into minimum required life time of 37.5 years. Figure 9-2 shows the intrinsic capability of the isolation barrier to withstand high voltage stress over its lifetime. Based on the TDDB data, the intrinsic capability of these devices is 400 VRMS with a lifetime of >100 years. Other factors, such as package size, pollution degree, material group, and so forth can further limit the working voltage of the component. The working voltage of the DBQ-16 package specified up to 400 VRMS. At the lower working voltages, the corresponding insulation barrier life time is much longer. A Vcc 1 Vcc 2 Time Counter > 1 mA DUT GND 1 GND 2 VS Oven at 150 °C Figure 9-1. Test Setup for Insulation Lifetime Measurement 18 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ISO7021 ISO7021 www.ti.com SLLSFA0B – JULY 2019 – REVISED AUGUST 2020 Figure 9-2. Insulation Lifetime Projection Data Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ISO7021 19 ISO7021 www.ti.com SLLSFA0B – JULY 2019 – REVISED AUGUST 2020 9.1.2 Intrinsic Safety The ISO7021 supports Intrinsically Safe (IS) to IS applications and carry IECEx and ATEX certifications. These devices do not currently support IS to non-IS galvanic isolation applications due to the minimum insulation thickness requirements of IEC 60079-11. 9.1.2.1 Schedule of Limitations These components are certified to comply with IEC 60079-0, Edition 7, IEC 60079-11, Edition 6, EN IEC60079-0:2018 and EN 60070-11:2012. When one of these components is used in an equipment, the component is to be soldered on a PCB inside a suitable enclosure and re-evaluated as an equipment. The operating temperature range of these components is -55°C to +85°C. The creepage and clearance distances across the isolating component have been evaluated, but the distance to other circuitry remain the responsibility of the user of the final equipment. This assembly is an isolating component between separate intrinsically safe circuits. The assembly must be connected to suitably certified intrinsically safe circuits considering the entity parameters and temperature ratings in the application scenario shown in Table 9-1 Table 9-1. Entity Parameters and Temperature Ratings ENTITY PARAMETERS SIDE 1 APPLICATION IS to IS: Case 1 ENTITY PARAMETERS SIDE 2 Ui = 50 V Ui = 50 V Ii = 300 mA Ii = 300 mA Pi = 1.3 W Pi = 1.3 W Li = 0 H Li = 0 H Ci = 4 pF Ci = 4 pF AMBIENT TEMPERATURE RANGE MAXIMUM COMPONENT TEMPERATURE -55°C to +85°C 183°C 9.2 Typical Application Figure 9-3 shows the isolated UART. Isolation Barrier VCC1 VCC2 0.1 …F 0.1 …F 0.1 F 0.1 F 0.1 F 0.1 F 1 0Ÿ AVCC VCC1 DVCC OUTA UCA0RXD INA DVDD INB UCA0TXD OUTB 10 nF AIN0 1 NŸ 100 nF AIN1 ADS122U04 Rx 10 nF AIN2 AIN3 DGND DVSS GND1 AVDD Tx ISO7021 MSP430FR2355 AVSS VCC2 AVSS 1 NŸ Thermocouple 1 0Ÿ GND2 Figure 9-3. Isolated UART for a Temperature Field Transmitter 20 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ISO7021 ISO7021 www.ti.com SLLSFA0B – JULY 2019 – REVISED AUGUST 2020 9.2.1 Design Requirements To design with these devices, use the parameters listed in Table 9-2. Table 9-2. Design Parameters PARAMETER VALUE Supply voltage, VCC1 and VCC2 1.71 V to 1.89 V or 2.25 V to 5.5 V Decoupling capacitor between VCC1 and GND1 0.1 µF Decoupling capacitor from VCC2 and GND2 0.1 µF 9.2.2 Detailed Design Procedure Unlike optocouplers, which require external components to improve performance, provide bias, or limit current, the device only require two external bypass capacitors to operate. 2 mm maximum from VCC2 2 mm maximum from VCC1 VCC2 VCC1 GND1 1 GND2 8 0.1 µF 0.1 µF OUTA 2 7 INA INB 3 6 OUTB 4 5 GND2 GND1 Figure 9-4. Typical ISO7021 Circuit Hook-up Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ISO7021 21 ISO7021 www.ti.com SLLSFA0B – JULY 2019 – REVISED AUGUST 2020 9.2.3 Application Curves The following typical eye diagrams of the device indicates wide open eye at the maximum data rate of 4 Mbps. Figure 9-5. Eye Diagram at 4 Mbps PRBS 216 – 1, 1.8 V and 25°C 22 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ISO7021 ISO7021 www.ti.com SLLSFA0B – JULY 2019 – REVISED AUGUST 2020 Figure 9-6. Eye Diagram at 4 Mbps PRBS 216 – 1, 5 V and 25°C 10 Power Supply Recommendations Put a 0.1-μF bypass capacitor at the input and output supply pins (VCC1 and VCC2) to make sure that operation is reliable at data rates and supply voltage. Put the capacitors as near to the supply pins as possible. If only one primary-side power supply is available in an application, use a transformer driver to help generate the isolated power for the secondary-side. Texas Instruments recommends the SN6501 device or SN6505A device. Refer to the SN6501 Transformer Driver for Isolated Power Supplies data sheet or SN6505 Low-Noise 1-A Transformer Drivers for Isolated Power Supplies data sheet for detailed power supply design and transformer selection recommendations. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ISO7021 23 ISO7021 www.ti.com SLLSFA0B – JULY 2019 – REVISED AUGUST 2020 11 Layout 11.1 Layout Guidelines A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 1-1). Layer stacking should be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and lowfrequency signal layer. • • • • Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits of the data link. Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for transmission line interconnects and provides an excellent low-inductance path for the return current flow. Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of approximately 100 pF/in2. Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links usually have margin to tolerate discontinuities such as vias. If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the power and ground plane of each power system can be placed closer together, thus increasing the highfrequency bypass capacitance significantly. Refer to the Digital Isolator Design Guide for detailed layout recommendations,. 11.1.1 PCB Material For digital circuit boards operating at less than 150 Mbps, (or rise and fall times greater than 1 ns), and trace lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and the self-extinguishing flammability-characteristics. 11.2 Layout Example High-speed traces 10 mils Ground plane 40 mils Keep this space free from planes, traces, pads, and vias FR-4 0r ~ 4.5 Power plane 10 mils Low-speed traces Figure 11-1. Recommended Layer Stack 24 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ISO7021 ISO7021 www.ti.com SLLSFA0B – JULY 2019 – REVISED AUGUST 2020 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation For related documentation see the following: • Texas Instruments, Digital Isolator Design Guide • Texas Instruments, Isolation Glossary • Texas Instruments, ADS1220 4-Channel, 2-kSPS, Low-Power, 24-Bit ADC with Integrated PGA and Reference data sheet • Texas Instruments, ADS122U04 24-Bit, 4-Channel, 2-kSPS, Delta-Sigma ADC With UART Interface data sheet • Texas Instruments, ADS124S0x Low-Power, Low-Noise, Highly Integrated, 6- and 12-Channel, 4-kSPS, 24Bit, Delta-Sigma ADC with PGA and Voltage Reference data sheet • Texas Instruments, Uniquely Efficient Isolated DC/DC Converter for Ultra-Low Power and Low-Power Applications TI Design • Texas Instruments, SN6501 Transformer Driver for Isolated Power Supplies data sheet • Texas Instruments, SN6505A Low-Noise 1-A Transformer Drivers for Isolated Power Supplies data sheet • Texas Instruments, Isolated power and data interface for low-power applications reference design TI Design 12.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.3 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 12.4 Trademarks TI E2E™ is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.6 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ISO7021 25 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) ISO7021D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -55 to 125 7021 ISO7021DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -55 to 125 7021 ISO7021FD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -55 to 125 7021F ISO7021FDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -55 to 125 7021F (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of