ISO7041-Q1
SLLSFN3 – JUNE 2022
ISO7041-Q1 Automotive, Ultra-Low Power Four-Channel Digital Isolator
1 Features
3 Description
•
The ISO7041-Q1 device is an ultra-low power,
multichannel digital isolator that can be used to
isolate CMOS or LVCMOS digital I/Os. Each isolation
channel has a logic input and output buffer separated
by a double capacitive silicon dioxide (SiO2) insulation
barrier. Innovative edge based architecture combined
with an ON-OFF keying modulation scheme allows
these isolators to consume very-low power while
meeting 3000-VRMS isolation rating per UL1577. The
per channel dynamic current consumption of the
device is under 120 μA/Mbps and the per channel
static current consumption is 3.5 μA at 3.3 V, allowing
for use of the ISO7041-Q1 in both power and thermal
constrained system designs.
•
•
•
•
•
•
•
•
•
•
•
AEC-Q100 qualified with the following results:
– Device temperature Grade 1: –40°C to +125°C
ambient operating temperature range
Functional Safety-Capable
– Documentation available to aid functional safety
system design: ISO7041-Q1
Meets VDA320 isolation requirements
Ultra-low power consumption
– 3.5 μA per channel quiescent current (3.3 V)
– 15 μA per channel at 100 kbps (3.3 V)
– 116 μA per channel at 1 Mbps (3.3 V)
Robust isolation barrier
– >100-year projected lifetime
– 3000 VRMS isolation rating
– ±100 kV/μs typical CMTI
Wide supply range: 3.0 V to 5.5 V
Wide temperature range: –40°C to +125°C
Small 16-QSOP package (16-DBQ)
Signaling rate: Up to 4 Mbps
Default output High (ISO7041-Q1) and Low
(ISO7041F-Q1) options
Robust electromagnetic compatibility (EMC)
– System-level ESD, EFT, and surge immunity
– ±8 kV IEC 61000-4-2 contact discharge
protection across isolation barrier
– Very low emissions
Safety-related certifications (planned):
– DIN V VDE 0884-11:2017-01
– UL 1577 Component Recognition Program
– IEC 60950-1, IEC 62368-1, IEC 61010-1,
IEC60601-1 and GB 4943.1-2011 certifications
The device can operate as low as 3.0 V, as high
as 5.5 V, and is fully functional with different supply
voltages on each side of isolation barrier. The four
channel isolator comes in a 16-QSOP package with
three forward-direction channels and one reversedirection channel. The device has default output high
and low options. If the input power or signal is lost,
default output is high for the ISO7041-Q1 device
without the suffix F and low for the ISO7041F-Q1
device with the F suffix. See the Device Functional
Modes section for more information.
Device Information
PART
NUMBER(1)
(1)
FUSE
BODY SIZE (NOM)
4.90 mm × 3.90 mm
Relay
IN
Fuse/relay sense
BAT
CVDD
12 V
PMIC
VCC1
VCC2
OUT
BQ75614-Q1
ISO7041-Q1
VCC
MCU
UART
Current sense
Load
GPIOx
Battery
...
Hybrid, electric and powertrain system (EV/HEV)
– Battery management system (BMS)
– On-board charger
– Traction inverter
– DC/DC converter
– Inverter and motor control
QSOP (16)
For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
PACKAGE
ISO7041-Q1
GND1
GND2
Rs
Simplified Application Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ISO7041-Q1
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................6
6.5 Power Ratings.............................................................6
Insulation Specifications................................................... 7
6.6 Safety-Related Certifications...................................... 8
6.7 Safety Limiting Values.................................................8
6.8 Electrical Characteristics 5V Supply........................... 9
6.9 Supply Current Characteristics 5V Supply..................9
6.10 Electrical Characteristics 3.3V Supply.................... 11
6.11 Supply Current Characteristics 3.3V Supply........... 11
6.12 Switching Characteristics........................................12
6.13 Insulation Characteristics Curves........................... 12
6.14 Typical Characteristics............................................ 13
7 Parameter Measurement Information.......................... 14
8 Detailed Description......................................................15
8.1 Overview................................................................... 15
8.2 Functional Block Diagram......................................... 15
8.3 Feature Description...................................................15
8.4 Device Functional Modes..........................................17
9 Application and Implementation.................................. 19
9.1 Application Information............................................. 19
9.2 Typical Application.................................................... 20
10 Power Supply Recommendations..............................24
11 Layout........................................................................... 25
11.1 Layout Guidelines................................................... 25
11.2 Layout Example...................................................... 25
12 Device and Documentation Support..........................26
12.1 Documentation Support.......................................... 26
12.2 Receiving Notification of Documentation Updates..26
12.3 Support Resources................................................. 26
12.4 Trademarks............................................................. 26
12.5 Electrostatic Discharge Caution..............................26
12.6 Glossary..................................................................26
13 Mechanical, Packaging, and Orderable
Information.................................................................... 26
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
June 2022
*
Initial Release
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Device Comparison Table
Table 5-1. Device Features
PART NUMBER
CHANNEL DIRECTION
MAXIMUM DATA
RATE
DEFAULT
OUTPUT
PACKAGE
RATED ISOLATION
ISO7041-Q1
3 Forward,
1 Reverse
4 Mbps
High
DBQ-16
3000 VRMS / 4242 VPK
ISO7041-Q1 with F
suffix
3 Forward,
1 Reverse
4 Mbps
Low
DBQ-16
3000 VRMS / 4242 VPK
5 Pin Configuration and Functions
1
VCC1
VCC2
16
GND1
GND2
15
3
INA
OUTA
14
4
INB
OUTB
13
5
INC
OUTC
12
6
OUTD
IND
11
7
GND1
GND2
10
8
GND1
GND2
9
ISOLATION
2
Not to scale
Figure 5-1. ISO7041-Q1 DBQ Package 16-Pin QSOP Top View
Table 5-1. Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
2
GND1
7
—
Ground connection for VCC1
—
Ground connection for VCC2
8
9
GND2
10
15
INA
3
I
Input, channel A. 300-Ω series resistor recommended
INB
4
I
Input, channel B. 300-Ω series resistor recommended
INC
5
I
Input, channel C. 300-Ω series resistor recommended
IND
11
I
Input, channel D. 300-Ω series resistor recommended
OUTA
14
O
Output, channel A. 300-Ω series resistor recommended
OUTB
13
O
Output, channel B. 300-Ω series resistor recommended
OUTC
12
O
Output, channel C. 300-Ω series resistor recommended
OUTD
6
O
Output, channel D. 300-Ω series resistor recommended
VCC1
1
—
Power supply, side 1
VCC2
16
—
Power supply, side 2
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2) (3)
Supply Voltage
Input/Output
Voltage
MIN
MAX
VCC1 to GND1
-0.5
6
VCC2 to GND2
-0.5
6
INx to GNDx
-0.5
VCCX + 0.5
OUTx to GNDx
-0.5
VCCX + 0.5
UNIT
V
V
ENx to GNDx
-0.5
VCCX + 0.5
Input Current
Input Channels, Ii
-15
15
mA
Output Current
Io
-15
Temperature
(1)
(2)
(3)
Operating junction temperature, TJ
Storage temperature, Tstg
-65
15
mA
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak
voltage values
Maximum voltage must not exceed 6 V.
6.2 ESD Ratings
(1) (2)
VALUE
V(ESD)
(1)
(2)
(3)
(4)
4
Electrostatic discharge
Human body model (HBM), per ANSI/
ESDA/JEDEC JS-001, all pins(1)
±5000
Charged device model (CDM), per
JEDEC specification JESD22-C101, all
pins(2)
±1500
Contact discharge per IEC 61000-4-2;
Isolation barrier withstand test(3) (4)
±8000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
IEC ESD strike is applied across the barrier with all pins on each side tied together creating a two-terminal device.
Testing is carried out in air or oil to determine the intrinsic contact discharge capability of the device.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VCC1 (1)
Supply Voltage Side 1
(1)
Supply Voltage Side 2
VCC2
VIH
High level Input voltage
VIL
Low level Input voltage
IOH
High level output current
IOL
Low level output current
DR
Data Rate
TA
Ambient temperature
(1)
(2)
3.0
NOM
MAX
UNIT
5.5
V
3.0
5.5
V
0.7 x VCCI
VCCI
V
0
0.3 x VCCI
VCCO (2) = 5 V
-4
VCCO = 3.3 V
-2
VCCO = 5 V
mA
4
VCCO = 3.3 V
V
mA
mA
2
mA
0
4
Mbps
-40
125
°C
VCC1 and VCC2 can be set independent of one another
VCCI = Input-side VCC; VCCO = Output-side VCC
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6.4 Thermal Information
ISO7041-Q1
THERMAL
METRIC(1)
UNIT
DBQ (SOIC)
16 PINS
RθJA
Junction-to-ambient thermal resistance
87.0
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
33.3
°C/W
RθJB
Junction-to-board thermal resistance
49.1
°C/W
ψJT
Junction-to-top characterization parameter
8.4
°C/W
ψJB
Junction-to-board characterization parameter
48.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Power Ratings
PARAMETER
6
PD
Maximum power dissipation (both sides)
PD1
Maximum power dissipation (side-1)
PD2
Maximum power dissipation (side-2)
TEST CONDITIONS
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15
pF, Input a 1-MHz 50% duty cycle square
wave
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MIN
TYP
MAX
UNIT
7.82
mW
4.46
mW
3.36
mW
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Insulation Specifications
PARAMETER
SPECIFICATIONS
TEST CONDITIONS
QSOP-16
UNIT
IEC 60664-1
External clearance(1)
Side 1 to side 2 distance through air
>3.7
mm
CPG
External Creepage(1)
Side 1 to side 2 distance across package
surface
>3.7
mm
DTI
Distance through the insulation
Minimum internal gap (internal clearance)
17
µm
CTI
Comparative tracking index
IEC 60112; UL 746A
>600
Material Group
According to IEC 60664-1
I
Overvoltage category per IEC 60664-1
Rated mains voltage ≤ 300 VRMS
I-III
CLR
DIN V VDE V
V
0884-11:2017-01(2)
VIORM
Maximum repetitive peak isolation voltage
AC voltage (bipolar)
566
VPK
VIOWM
Maximum isolation working voltage
AC voltage (sine wave); time-dependent
dielectric breakdown (TDDB) test; See TBD
400
VRMS
DC voltage
566
VDC
4242
VPK
VPK
VIOTM
Maximum transient isolation voltage
VTEST = VIOTM , t = 60 s (qualification); VTEST
= 1.2 × VIOTM, t = 1 s (100% production)
VIOSM
Maximum surge isolation voltage(3)
Test method per IEC 62368-1, 1.2/50 µs
waveform, VTEST = 1.6 × VIOSM = 6400 VPK
(qualification)
4000
Method a: After I/O safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM ,
tm = 10 s
≤5
Apparent charge(4)
qpd
Method a: After environmental tests subgroup
1, Vini = VIOTM, tini = 60 s;
≤5
Vpd(m) = 1.6 × VIORM , tm = 10 s
pC
Method b1: At routine test (100% production)
and preconditioning (type test), Vini = VIOTM,
≤5
tini = 1 s;
Vpd(m) = 1.875 × VIORM , tm = 1 s
Barrier capacitance, input to output(5)
CIO
Insulation resistance, input to output(5)
RIO
VIO = 0.4 × sin (2 πft), f = 1 MHz
~1.5
VIO = 500 V, TA = 25°C
> 1012
VIO = 500 V, 100°C ≤ TA ≤ 150°C
> 1011
VIO = 500 V at TS = 150°C
> 109
Pollution degree
2
Climatic category
55/125/21
pF
Ω
UL 1577
VISO
(1)
(2)
(3)
(4)
(5)
Withstand isolation voltage
VTEST = VISO , t = 60 s (qualification); VTEST =
3000
1.2 × VISO , t = 1 s (100% production)
VRMS
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application.
Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the
isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal
in certain cases. Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these
specifications.
This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured
by means of suitable protective circuits.
Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
Apparent charge is electrical discharge caused by a partial discharge (pd).
All pins on each side of the barrier tied together creating a two-pin device.
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6.6 Safety-Related Certifications
VDE
CSA
Certified according to DIN
VDE V 0884-11:2017- 01
UL
Certified according to
Certified according to IEC
UL 1577 Component
60950-1 and IEC 62368-1
Recognition Program
Maximum transient
isolation voltage,
4242 VPK;
Maximum repetitive peak
isolation voltage, 566 VPK;
Maximum surge isolation
voltage,
4000 VPK
3000 VRMS insulation per
CSA 60950-1-07+A1+A2,
IEC 60950-1 2nd
Ed.+A1+A2, CSA
62368-1- 14 and IEC
Single protection,
62368-1:2014 370 VRMS
3000 VRMS
(DBQ-16) maximum
working voltage (pollution
degree 2, material group I)
Certification Planned
Certification Planned
Certification Planned
CQC
TUV
Certified according to
GB4943.1-2011
Certified according
to EN 61010-1:2010/
A1:2019, EN 609501:2006/A2:2013 and EN
62368-1:2014
EN 61010- 1:2010/
A1:2019, 300 VRMS basic
Basic insulation, Altitude ≤
isolation
5000 m, Tropical Climate,
EN 60950- 1:2006/
400 VRMS maximum
A2:2013 and EN
working voltage
62368-1:2014, 400 VRMS
basic isolation
Certification Planned
Certification Planned
6.7 Safety Limiting Values
Safety limiting(1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RθJA = 87°C/W, VI = 5.5 V, TJ = 150°C, TA
= 25°C
261
mA
RθJA = 87°C/W, VI = 3.6 V, TJ = 150°C, TA
= 25°C
399
mA
1435
mW
150
°C
16-QSOP PACKAGE
IS
PS
Safety input, output, or total power
TS
Maximum safety temperature
(1)
8
Safety input, output, or supply current
RθJA = 87°C/W, TJ = 150°C, TA = 25°C
The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The
IS and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be
exceeded. These limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the table is that of a device installed on a high-K test board for leaded surface-mount
packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum allowed junction temperature.
PS = IS × VI, where VI is the maximum input voltage.
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6.8 Electrical Characteristics 5V Supply
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
Rising input switching threshold
VIT-(IN)
Falling input switching threshold
VOH
High-level output voltage
IOH = -4 mA
VOL
Low-level output voltage
IOL = 4 mA
VI(HYS)
Input threshold voltage
hysteresis
IIH
High-level input current
VIH = VCCI (1) at INx
IIL
Low-level input current
VIL = 0 V at INx
-1
CMTI
Common mode transient
immunity
VI = VCC or 0 V, VCM = 1200 V
50
Ci
Input Capacitance (2)
VI = VCC/ 2 + 0.4×sin(2πft), f = 1
MHz, VCC = 5 V
(1)
(2)
TYP
MAX UNIT
0.7 x VCCI (1)
VIT+(IN)
V
0.3 x VCCI
V
VCCO - 0.4
V
0.4
V
0.1 x VCCI
V
1
µA
µA
100
kV/us
2
pF
VCCI = Input-side VCC; VCCO = Output-side VCC
Measured from input pin to same side ground.
6.9 Supply Current Characteristics 5V Supply
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SUPPLY CURRENT
MIN
TYP
MAX
UNIT
ICC1
6.2
14.3
µA
ICC2
10.1
18.5
µA
Refresh enable
VI = VCCI (1) (ISO7041-Q1);
VI = 0 V (ISO7041-Q1 with F suffix)
ICC1
8.2
16.7
µA
ICC2
10.8
18.5
µA
Refresh enable
VI = 0 V (ISO7041-Q1);
VI = VCCI (ISO7041-Q1 with F suffix)
ICC1
9.5
19.9
µA
ICC2
11.3
19.5
µA
Refresh disable
10 kbps, No Load
ICC1
6.7
19.7
µA
ICC2
11.8
20.6
µA
Refresh disable
100 kbps, No Load
ICC1
37.1
57.4
µA
ICC2
25.8
37.7
µA
Refresh disable
1 Mbps, No Load
ICC1
340.5
436.1
µA
ICC2
167.0
211.1
µA
Refresh enable
10 kbps, No Load
ICC1
10.6
20.8
µA
ICC2
11.9
20.4
µA
Refresh enable
100 kbps, No Load
ICC1
37.1
57.4
µA
ICC2
25.8
37.7
µA
Refresh enable
1 Mbps, No Load
ICC1
338.3
436.1
µA
ICC2
166.0
211.1
µA
DC Signal
ICC1(ch) + ICC2(ch)
4.1
7.4
µA
ICC1(ch) + ICC2(ch)
5.9
10.7
µA
ICC1(ch) + ICC2(ch)
17.4
23.4
µA
ICC1(ch) + ICC2(ch)
137.0
164.5
µA
ISO7041-Q1
Refresh disable
Supply current - DC
signal
Supply current - AC
signal
Total Supply Current 10 kbps, No Load
Per Channel,
100 kbps, No Load
Refresh Disabled
1 Mbps, No Load
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over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VI = VCCI (ISO7041-Q1);
VI = 0 V (ISO7041-Q1 with F suffix)
VI = 0 V (ISO7041-Q1);
Total Supply Current
VI = VCCI (ISO7041-Q1 with F suffix)
Per Channel,
Refresh Enabled
10 kbps, No Load
(1)
10
SUPPLY CURRENT
MIN
TYP
MAX
UNIT
ICC1(ch) + ICC2(ch)
4.8
8.5
µA
ICC1(ch) + ICC2(ch)
5.3
9.6
µA
ICC1(ch) + ICC2(ch)
5.7
10.4
µA
100 kbps, No Load
ICC1(ch) + ICC2(ch)
16.4
22.3
µA
1 Mbps, No Load
ICC1(ch) + ICC2(ch)
125.9
154.0
µA
VCCI = Input-side VCC
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6.10 Electrical Characteristics 3.3V Supply
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
Rising input switching threshold
VIT-(IN)
Falling input switching threshold
VOH
High-level output voltage
IOH = -2mA
VOL
Low-level output voltage
IOL = 2mA
VI(HYS)
Input threshold voltage
hysteresis
IIH
High-level input current
VIH = VCCI (1) at INx
IIL
Low-level input current
VIL = 0 V at INx
-1
CMTI
Common mode transient
immunity
VI = VCC or 0 V, VCM = 1200 V
50
Ci
Input Capacitance(2)
VI = VCC/ 2 + 0.4×sin(2πft), f = 1
MHz, VCC = 3.6 V
(1)
(2)
TYP
MAX UNIT
0.7 x VCCI (1)
VIT+(IN)
V
0.3 x VCCI
V
VCCO - 0.3
V
0.3
V
0.1 x VCCI
V
1
µA
µA
100
kV/us
2
pF
VCCI = Input-side VCC; VCCO = Output-side VCC
Measured from input pin to same side ground.
6.11 Supply Current Characteristics 3.3V Supply
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SUPPLY CURRENT
MIN
TYP
MAX
UNIT
ISO7041-Q1
ICC1
5.1
8.8
µA
ICC2
8.9
14.0
µA
Refresh enable
VI = VCCI (1) (ISO7041-Q1);
VI = 0 V (ISO7041-Q1 with F suffix)
ICC1
6.8
12.2
µA
ICC2
9.6
14.0
µA
Refresh enable
VI = 0 V (ISO7041-Q1);
VI = VCCI (ISO7041-Q1 with F suffix)
ICC1
8.1
14.8
µA
ICC2
10.0
15.6
µA
Refresh disable
10 kbps, No Load
ICC1
7.9
13.7
µA
ICC2
10.4
15.9
µA
Refresh disable
100 kbps, No Load
ICC1
35.9
48.3
µA
ICC2
22.7
31.4
µA
Refresh disable
1 Mbps, No Load
ICC1
316.4
395.7
µA
ICC2
147.2
188.2
µA
Refresh enable
10 kbps, No Load
ICC1
9.8
16.4
µA
ICC2
10.5
16.2
µA
Refresh enable
100 kbps, No Load
ICC1
35.9
48.3
µA
ICC2
22.7
31.4
µA
Refresh enable
1 Mbps, No Load
ICC1
315.3
395.7
µA
ICC2
146.2
188.2
µA
DC Signal
ICC1(ch) + ICC2(ch)
3.5
5.7
µA
Refresh disable
Supply current - DC
signal
Supply current - AC
signal
Total Supply Current 10 kbps, No Load
Per Channel,
100 kbps, No Load
Refresh Disabled
1 Mbps, No Load
ICC1(ch) + ICC2(ch)
5.2
8.2
µA
ICC1(ch) + ICC2(ch)
14.8
19.2
µA
ICC1(ch) + ICC2(ch)
115.7
138.7
µA
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over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SUPPLY CURRENT
VI = VCCI (ISO7041-Q1);
VI = 0 V (ISO7041-Q1 with F suffix)
VI = 0 V (ISO7041-Q1);
Total Supply Current
VI = VCCI (ISO7041-Q1 with F suffix)
Per Channel,
Refresh Enabled
10 kbps, No Load
(1)
MIN
TYP
MAX
UNIT
ICC1(ch) + ICC2(ch)
4.2
6.8
µA
ICC1(ch) + ICC2(ch)
4.6
7.7
µA
ICC1(ch) + ICC2(ch)
5.2
8.2
µA
100 kbps, No Load
ICC1(ch) + ICC2(ch)
14.8
19.2
µA
1 Mbps, No Load
ICC1(ch) + ICC2(ch)
115.7
138.7
µA
VCCI = Input-side VCC
6.12 Switching Characteristics
VCC1, VCC2 = 3.0 V to 5.5 V (over recommended operating conditions unless otherwise noted)
PARAMETER
tPLH, tPHL
Propagation delay time
tP(dft)
Propagation delay drift
tUI
Minimum pulse width
PWD
Pulse width distortion
TEST CONDITIONS
MIN
See Figure 7-1
TYP
MAX
UNIT
148
165
ns
15
See Figure 7-1
ps/℃
250
ns
10
ns
Same-direction channels
10
ns
Opposite-direction channels
10
ns
70
ns
tsk(o)
Channel to channel output skew time
tsk(p-p)
Part to part skew time
tr
Output signal rise time
See Figure 7-1
16
ns
tf
Output signal fall time
See Figure 7-1
16
ns
tDO
Default output delay time from input
power loss
See Figure 7-2
750
us
tPU
Time from UVLO to valid output data
1
FR
Refresh rate
5
400
5
10
ms
kbps
6.13 Insulation Characteristics Curves
500
1600
400
Safety Limiting Power (mW)
Safety Limiting Current (mA)
VCC = 3.6 V
VCC = 5.5 V
300
200
100
800
400
0
0
0
20
40
60
80
100
120
Ambient Temperature (C)
140
160
Figure 6-1. Thermal Derating Curve for Limiting
Current per VDE
12
1200
0
40
80
120
Ambient Temperature (qC)
160
200
SLLS
Figure 6-2. Thermal Derating Curve for Limiting
Power per VDE
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6.14 Typical Characteristics
500
Current per Channel (A)
Current per Channel (A)
500
100
10
2
1
10
TA = 25°C
100
Data Rate (kbps)
1000
CL = 0 pF
1
TA = 25°C
10
100
Data Rate (kbps)
1000
4000
CL = 15 pF
Figure 6-4. ISO7041-Q1 Supply Current vs Data
Rate at 3.3 V
(With 15-pF Load)
500
Current per Channel (A)
500
Current per Channel (A)
10
2
0.2
4000
Figure 6-3. ISO7041-Q1 Supply Current vs Data
Rate at 3.3 V
(With No Load)
100
10
2
0.2
100
1
TA = 25°C
10
100
Data Rate (kbps)
1000
4000
CL = 0 pF
100
10
2
0.2
1
TA = 25°C
Figure 6-5. ISO7041-Q1 Supply Current vs Data
Rate at 5 V
(With No Load)
10
100
Data Rate (kbps)
1000
4000
CL = 15 pF
Figure 6-6. ISO7041-Q1 Supply Current vs Data
Rate at 5 V
(With 15-pF Load)
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7 Parameter Measurement Information
Isolation Barrier
IN
Input
Generator
(See Note A)
VCCI
VI
VI
OUT
50%
50%
0V
tPLH
tPHL
CL
See Note B
VO
VOH
90%
50%
VO
50%
10%
VOL
tf
tr
A.
B.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3ns, ZO =
50 Ω. At the input, 50 Ω resistor is required to terminate Input Generator signal. It is not needed in actual application.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 7-1. Switching Characteristics Test Circuit and Voltage Waveforms
VI
VCC
VCC
Isolation Barrier
IN = 0 V (Devices without suffix F)
IN = VCC (Devices with suffix F)
VI
IN
1.7 V
0V
OUT
VO
tDO
CL
See Note A
VO
default high
VOH
50%
VOL
default low
A.
B.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Power Supply Ramp Rate = 10 mV/ns
Figure 7-2. Default Output Delay Time Test Circuit and Voltage Waveforms
VCCI
VCCO
C = 0.1 µF ±1%
Pass-fail criteria:
The output must
remain stable.
Isolation Barrier
S1
C = 0.1 µF ±1%
IN
OUT
+
VOH or VOL
CL
See Note A
GNDI
A.
+
VCM ±
±
GNDO
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 7-3. Common-Mode Transient Immunity Test Circuit
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8 Detailed Description
8.1 Overview
The ISO7041-Q1 device uses edge encoding of data with an ON-OFF keying (OOK) modulation scheme to
transmit the digital data across a silicon dioxide isolation barrier. The transmitter uses a high frequency carrier
signal to pass data across the barrier representing a signal edge transition. Using this method achieves very
low power consumption and high immunity. The receiver demodulates the carrier signal after advanced signal
conditioning and produces the output through a buffer stage. For low data rates, a refresh logic option is
available to make sure the output state matches the input state. Advanced circuit techniques are used to
maximize the CMTI performance and minimize the radiated emissions due to the high frequency carrier and IO
buffer switching. The conceptual block diagram of a digital capacitive isolator, Conceptual Block Diagram of a
Digital Capacitive Isolator, shows a functional block diagram of a typical channel.
8.2 Functional Block Diagram
Transmitter
Receiver
OOK
Modulation
TX IN
Edge
Encoding
TX Signal
Conditioning
Refresh
Logic
Oscillator
SiO2 based
Capacitive
Isolation
Barrier
RX Signal
Conditioning
Envelope
Detection
RX OUT
Watch Dog
Timer
Figure 8-1. Conceptual Block Diagram of a Digital Capacitive Isolator
8.3 Feature Description
8.3.1 Refresh
The ISO7041 uses an edge based encoding scheme to transfer an input signal change across the isolation
barrier versus sending across the DC state. The built in refresh function consistently validates that the DC output
state of each isolator channel matches the DC input state. An internal watchdog timer monitors for activity on the
individual inputs and transmits the logic state when there is no input signal transition for more than 100 µs. This
ensures that the input and output state of the isolator always match.
8.3.2 Electromagnetic Compatibility (EMC) Considerations
Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge
(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances
are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level
performance and reliability depends, to a large extent, on the application board design and layout, the ISO70xx
family of devices incorporates many chip-level design improvements for overall system robustness. Some of
these improvements include:
• Robust ESD protection cells for input and output signal pins and inter-chip bond pads.
• Low-resistance connectivity of ESD cells to supply and ground pins.
• Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.
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•
•
•
Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance
path.
PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic
SCRs.
Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.
The device has no issue being able to meet either CISPR 22 Class A and CISPR22 Class B standards in an
unshielded environment.
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8.4 Device Functional Modes
Table 8-1 shows the functional modes for the device.
Table 8-1. Function Table
VCCI (1)
PU
PD
X
X
(1)
(2)
VCCO
INPUT
(INx)
REFRESH
ENABLE
(ENx)
OUTPUT
(OUTx)
H
L
H
L
L
L
X
H
Undetermined
PU
PU
PD
X
Normal Operation:
A channel output assumes the logic state of its input.
The device needs an input signal transition to validate the output
tracks the input state. Without a signal edge transition, the output will
be in an undetermined state.
When VCCI is unpowered, a channel output assumes the logic state
based on the selected default option. Default is High for the device
without the F suffix and Low for device with the F suffix.
When VCCI transitions from unpowered to powered-up, a channel
output assumes the logic state of the input.
When VCCI transitions from powered-up to unpowered, channel
output assumes the selected default state.
L
Default
H
Undetermined
When VCCI is unpowered, a channel output assumes the logic state
based on the previous state of the output before VCCI powered down.
L
Undetermined
When VCCO is unpowered, a channel output is undetermined.(2)
When VCCO transitions from unpowered to powered-up, a channel
output assumes the logic state of the input.
H
Undetermined
When VCCO is unpowered, a channel output is undetermined.(2)
When VCCO transitions from unpowered to powered-up, a channel
output assumes the selected default option.
Open
Undetermined
When ENx is unconnected or open, the device output will be in an
undetermined and unknown state. ENx must be connected high or
low for the device to behave correctly.
X
X
X
COMMENTS
VCCI = Input-side VCC; VCCO = Output-side VCC; PU = Powered up (VCC ≥ 1.54 V); PD = Powered down (VCC ≤ 1.54); X = Irrelevant; H
= High level; L = Low level ; Z = High Impedance.
A strongly driven input signal can weakly power the floating VCC through an internal protection diode and cause undetermined output.
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8.4.1 Device I/O Schematics
Refresh Enable
Input
VCCI
VCCI
VCCI
VCCI
985
VCCI
VCCI
1970
INx
ENx
Output
VCCO
~20
OUTx
Figure 8-2. Device I/O Schematics
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The ISO7041-Q1 device is an ultra-low power digital isolator. The device uses single-ended CMOS-logic
switching technology. The voltage range is from 3.0 V to 5.5 V for both supplies, VCC1 and VCC2, and can
be set irrespective of one another. When designing with digital isolators, keep in mind that because of the
single-ended design structure, digital isolators do not conform to any specific interface standard and are only
intended for isolating single-ended CMOS or TTL digital signal lines. The isolator is typically placed between the
data controller (that is, μC or UART), and a data converter or a line transceiver, regardless of the interface type
or standard. See Isolated power and data interface for low-power applications reference design TI Design for
detailed information on designing the ISO70xx in low-power applications.
9.1.1 Insulation Lifetime
Insulation lifetime projection data is collected by using industry-standard Time Dependent Dielectric Breakdown
(TDDB) test method. In this test, all pins on each side of the barrier are tied together creating a two-terminal
device and high voltage applied between the two sides; see Figure 9-1 for TDDB test setup. The insulation
breakdown data is collected at various high voltages switching at 60 Hz over temperature. For reinforced
insulation, VDE standard requires the use of TDDB projection line with failure rate of less than 1 part per million
(ppm) and a minimum insulation lifetime of 20 years. VDE standard also requires additional safety margin of
20% for working voltage and 87.5% for insulation lifetime which translates into minimum required life time of 37.5
years.
Figure 9-2 shows the intrinsic capability of the isolation barrier to withstand high voltage stress over its lifetime.
Based on the TDDB data, the intrinsic capability of these devices is 400 VRMS with a lifetime of >100 years.
Other factors, such as package size, pollution degree, material group, and so forth can further limit the working
voltage of the component. The working voltage of the DBQ-16 package specified up to 400 VRMS. At the lower
working voltages, the corresponding insulation barrier life time is much longer.
A
Vcc 1
Vcc 2
Time Counter
> 1 mA
DUT
GND 1
GND 2
VS
Oven at 150 °C
Figure 9-1. Test Setup for Insulation Lifetime Measurement
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Figure 9-2. Insulation Lifetime Projection Data
9.2 Typical Application
Isolated UART for an Automotive Battery Management System shows the isolated UART and GPIO (NFAULT)
interface.
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CVDD
N
N
CVSS
1
DVDD
N
N
10 k
TSREF
DVSS
GPIO1
1
10 k
REFHP
N
N
REFHM
1
GPIO2
GPIO3
AVDD
N
GPIO4
GPIO5
NEG5V
N
N
GPIO6
AVS S
GPIO7
LDOIN
GPIO8
NPNB
To CVDD
MCU
ISO7041-Q1
BQ75614-Q1
VCC1
BAT
VCC2
VCC
100 k
100 k
10 nF
INA
OUTA
NFA UL T
INB
OUTB
INT
TX
INC
OUTC
RX
RX
OUTD
IND
TX
GND1
GND2
VC14
0.47 uF
CELL 14
+
100 k
VC13
0.47 uF
CELL 13
+
GND
VC1
0.47 uF
VC0
+
0.47 uF
CELL 1
CB14
CELL 14
0.47 uF
CB13
CELL 13
SRP
CB1
CELL 1
0.47 uF
Rse nse
CB0
CELL 0
SRN
0.47 uF
Figure 9-3. Isolated UART for an Automotive Battery Management System
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9.2.1 Design Requirements
To design with these devices, use the parameters listed in Table 9-1.
Table 9-1. Design Parameters
PARAMETER
VALUE
Supply voltage, VCC1 and VCC2
3.0 V to 5.5 V
Decoupling capacitor between VCC1 and GND1
0.1 µF
Decoupling capacitor from VCC2 and GND2
0.1 µF
9.2.2 Detailed Design Procedure
Unlike optocouplers, which require external components to improve performance, provide bias, or limit current,
the device only require two external bypass capacitors to operate.
2 mm maximu m
from V CC 2
2 mm maximu m
from V CC 1
VCC 2
VCC 1
1
0.1 µF
16
GND1
GND2
0.1 µF
2
15
INA
3
14
OUTA
INB
4
13
OUTB
INC
5
12
OUTC
OUTD
6
11
IND
7
10
8
9
GND2
GND1
GND2
GND1
Figure 9-4. Typical ISO7041-Q1 Circuit Hook-up
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9.2.3 Application Curves
The following typical eye diagrams of the device indicates wide open eye at the maximum data rate of 4 Mbps.
Figure 9-5. Eye Diagram at 4 Mbps PRBS 216 – 1, 3.3 V and 25°C
Figure 9-6. Eye Diagram at 4 Mbps PRBS 216 – 1, 5 V and 25°C
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10 Power Supply Recommendations
Put a 0.1-μF bypass capacitor at the input and output supply pins (VCC1 and VCC2) to make sure that operation
is reliable at data rates and supply voltage. Put the capacitors as near to the supply pins as possible. If only one
primary-side power supply is available in an application, use a transformer driver to help generate the isolated
power for the secondary-side. Texas Instruments recommends the SN6501 device or SN6505A device. Refer to
the SN6501 Transformer Driver for Isolated Power Supplies data sheet or SN6505 Low-Noise 1-A Transformer
Drivers for Isolated Power Supplies data sheet for detailed power supply design and transformer selection
recommendations.
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11 Layout
11.1 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 11-1). Layer stacking
should be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and lowfrequency signal layer.
•
•
•
•
Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/in2.
Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system
to the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping.
Also the power and ground plane of each power system can be placed closer together, thus increasing the
high-frequency bypass capacitance significantly.
Refer to the Digital Isolator Design Guide for detailed layout recommendations,.
11.1.1 PCB Material
For digital circuit boards operating at less than 150 Mbps, (or rise and fall times greater than 1 ns), and trace
lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper
alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater strength
and stiffness, and the self-extinguishing flammability-characteristics.
11.2 Layout Example
High-speed traces
10 mils
Ground plane
40 mils
Keep this space
free from planes,
traces, pads, and
vias
FR-4
0r ~ 4.5
Power plane
10 mils
Low-speed traces
Figure 11-1. Recommended Layer Stack
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Digital Isolator Design Guide
• Texas Instruments, Isolation Glossary
• Texas Instruments,BQ75614-Q1, 14-S automotive precision battery monitor, balancer and integrated
protector with ASIL-D compliance
• Texas Instruments, Uniquely Efficient Isolated DC/DC Converter for Ultra-Low Power and Low-Power
Applications TI Design
• Texas Instruments, SN6501 Transformer Driver for Isolated Power Supplies data sheet
• Texas Instruments, SN6505A Low-Noise 1-A Transformer Drivers for Isolated Power Supplies data sheet
• Texas Instruments, Isolated power and data interface for low-power applications reference design TI Design
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
ISO7041FQDBQRQ1
ACTIVE
SSOP
DBQ
16
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7041F
Samples
ISO7041QDBQRQ1
ACTIVE
SSOP
DBQ
16
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7041
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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