Product
Folder
Sample &
Buy
Technical
Documents
Tools &
Software
Support &
Community
ISO7131CC, ISO7140CC, ISO7140FCC, ISO7141CC, ISO7141FCC
ZHCS221F – APRIL 2013 – REVISED JANUARY 2015
ISO71xxCC 4242VPK 小封装低功耗三通道和四通道数字隔离器
1 特性
•
•
•
•
1
•
•
•
•
•
•
•
最大信号传输速率： 50Mbps（5V 电源）
具有集成噪声滤波器的稳健耐用设计
缺省输出低选项（后缀 F）
低功耗，每通道 ICC 典型值（3.3V 电源）：
– ISO7131：1Mbps 时为 1.5mA，
25Mbps 时为 2.6mA
– ISO7140：1Mbps 时为 1mA，
25Mbps 时为 2.3mA
– ISO7141：1Mbps 时为 1.3mA，
25Mbps 时为 2.6mA
低传播延迟：典型值 23ns
（3.3V 电源）
宽温度范围：-40℃ 至 125°C
50kV/µs 瞬态抗扰度，典型值
采用 SiO2 隔离格栅，使用寿命长
可由 2.7V、3.3V 和 5V 电源及逻辑电平供电
小型四分之一尺寸小外形封装 (QSOP)-16 封装
安全及管理批准
– 符合 UL 1577 的长达 1 分钟的 2500VRMS 隔离
– 符合 DIN V VDE V 0884-10 (VDE V 088410):2006-12 的 4242VPK 隔离，566VPK 工作电
压
– CSA 组件接受通知 5A，IEC 60950-1 和 IEC
61010-1 终端设备标准
– 符合 GB 4943.1-2011 的 CQC 认证
2 应用范围
•
通用隔离
– 工业现场总线 (Fieldbus)
– Profibus 现场总线
– Modbus™
– DeviceNet 数据总线
– RS-232，RS-485
– 串行外设接口
3 说明
ISO7131、ISO7140 和 ISO7141 器件提供符合 UL
标准的长达 1 分钟的 2500 VRMS 电流隔离，以及符合
VDE 标准的 4242 VPK。 ISO7131 有三个通道，其中
两个为正向通道，一个为反向通道。 ISO7140 和
ISO7141 均为四通道隔离器；ISO7140 有四个正向通
道，而 ISO7141 有三个正向通道和一个反向通道。 这
些器件在由 5V 电源和 3.3V/2.7V 电源供电时，分别可
提供 50Mbps 和 40Mbps 的最大数据传输速率，并且
输入上带有集成滤波器，适用于易受噪声干扰的应用。
后缀 F 表示缺省输出状态为低电平；否则，缺省输出
状态为高电平（请见表 3）。
每个隔离通道的逻辑输入和输出缓冲器均由二氧化硅
(SiO2) 绝缘隔栅分离开来。 与隔离式电源一起使用
时，这些器件可防止数据总线或者其它电路上的噪声电
流进入本地接地并且干扰或损坏敏感电路。 这些器件
具有晶体管晶体管逻辑电路 (TTL) 输入阈值，并且可
由 2.7V、3.3V 和 5V 电压供电运行。 通过 2.7V 或
3.3V 电源供电时，所有输入均可耐受 5V 电压。
器件信息(1)
器件型号
封装
封装尺寸（标称值）
ISO7131CC
ISO7140CC
ISO7140FCC
SSOP (16)
4.90mm × 3.90mm
ISO7141CC
ISO7141FCC
(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。
简化电路原理图
VCCI
VCCO
Isolation
Capacitor
INx
OUTx
ENx
GND1
GND2
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SLLSE83
ISO7131CC, ISO7140CC, ISO7140FCC, ISO7141CC, ISO7141FCC
ZHCS221F – APRIL 2013 – REVISED JANUARY 2015
www.ti.com.cn
目录
1
2
3
4
5
6
特性 ..........................................................................
应用范围...................................................................
说明 ..........................................................................
修订历史记录 ...........................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
5
6.1
6.2
6.3
6.4
6.5
6.6
Absolute Maximum Ratings ..................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 6
Power Dissipation Ratings ........................................ 6
Electrical Characteristics: VCC1 and VCC2 at 5 V
±10% .......................................................................... 6
6.7 Electrical Characteristics: VCC1 and VCC2 at 3.3 V
±10% .......................................................................... 6
6.8 Electrical Characteristics: VCC1 and VCC2 at 2.7 V ... 7
6.9 Switching Characteristics: VCC1 and VCC2 at 5 V
±10% .......................................................................... 7
6.10 Switching Characteristics: VCC1 and VCC2 at 3.3 V
±10% .......................................................................... 8
6.11 Switching Characteristics: VCC1 and VCC2 at 2.7 V. 8
6.12 Supply Current: VCC1 and VCC2 at 5 V ±10% ......... 9
6.13 Supply Current: VCC1 and VCC2 at 3.3 V ±10% .... 10
6.14 Supply Current: VCC1 and VCC2 at 2.7 V............... 11
6.15 Typical Characteristics .......................................... 12
7
8
Parameter Measurement Information ................ 14
Detailed Description ............................................ 16
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
16
16
17
19
Application and Implementation ........................ 21
9.1 Application Information............................................ 21
9.2 Typical Applications ................................................ 21
10 Power Supply Recommendations ..................... 25
11 Layout................................................................... 25
11.1 Layout Guidelines ................................................. 25
11.2 Layout Example .................................................... 25
12 器件和文档支持 ..................................................... 26
12.1
12.2
12.3
12.4
12.5
文档支持................................................................
相关链接................................................................
商标 .......................................................................
静电放电警告.........................................................
术语表 ...................................................................
26
26
26
26
26
13 机械封装和可订购信息 .......................................... 26
4 修订历史记录
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (September 2013) to Revision F
Page
•
已添加 引脚配置和功能部分，ESD 额定表，特性描述部分，器件功能模式，应用和实施部分，电源相关建议部分，布
局部分，器件和文档支持部分以及机械、封装和可订购信息部分部分 .................................................................................... 1
•
VDE 标准更改为 DIN V VDE V 0884-10 (VDE V 0884-10):2006-12...................................................................................... 1
Changes from Revision D (August 2013) to Revision E
Page
•
将符合 UL 1577 的长达 1 分钟的 2500VRMS 隔离从（审批正在审理中）更改为（已通过审批） .......................................... 1
•
Added note1 to the AVAILABLE OPTIONS table................................................................................................................. 17
•
Changed 图 15 ..................................................................................................................................................................... 18
•
Changed From: Basic Insulation To: Basic Insulation, Altitude ≤ 5000m, Tropical Climate, 250 VRMS maximum
working voltage in the Regulatory Information table ............................................................................................................ 19
•
Changed File number: E181974 (approval pending) To: File number: E181974 in the Regulatory Information table ........ 19
•
Changed the title of 图 21, 图 22, and 图 23 to include "PRBS 216 - 1" ............................................................................... 23
Changes from Revision C (July 2013) to Revision D
Page
•
添加了安全列表项“GB 4943.1-2011 和 GB 8898:2011 CQC 认证（审批正在审理中）” ....................................................... 1
•
Added 图 2............................................................................................................................................................................ 12
•
Deleted "Product Preview" From the AVAILABLE OPTIONS table ..................................................................................... 17
•
Changed the REGULATORY INFORMATION, added column for CQC .............................................................................. 19
2
版权 © 2013–2015, Texas Instruments Incorporated
ISO7131CC, ISO7140CC, ISO7140FCC, ISO7141CC, ISO7141FCC
www.ti.com.cn
Changes from Revision B (June 2013) to Revision C
ZHCS221F – APRIL 2013 – REVISED JANUARY 2015
Page
•
将特性从：ISO7140：1Mbps 时待定 (TBD)，25Mbps 时 TBD 改为：ISO7140：1Mbps 时为 1mA，25Mbps 时为 2.3mA 1
•
在说明中添加了文本：“当由一个 2.7V 或者 3.3V 电源供电时，所有输入均可耐受 5V 电压。” ............................................. 1
•
删除了产品状态表 ................................................................................................................................................................... 1
•
更改了安全和管理批准............................................................................................................................................................ 1
•
Changed the ABSOLUTE MAXIMUM RATINGS table .......................................................................................................... 5
•
Changed the SWITCHING CHARACTERISTICS table, Input glitch rejection time. .............................................................. 7
•
Changed the SWITCHING CHARACTERISTICS table, Input glitch rejection time. ............................................................. 8
•
Changed the SWITCHING CHARACTERISTICS table, Input glitch rejection time. ............................................................. 8
•
Changed ISO7140 in the SUPPLY CURRENT table From: TBD To: values......................................................................... 9
•
Changed ISO7140 in the SUPPLY CURRENT table From: TBD To: values....................................................................... 10
•
Changed ISO7140 in the SUPPLY CURRENT table From: TBD To: values....................................................................... 11
•
Changed 图 1 X-axis scale ................................................................................................................................................... 12
•
Changed the AVAILABLE OPTIONS table........................................................................................................................... 17
Changes from Revision A (June 2013) to Revision B
•
Page
将器件 ISO7141CC 从：产品预览改为：在产品状态表中发布............................................................................................... 1
Changes from Original (April 2013) to Revision A
Page
•
更改了简化电路原理图，添加了接地符号 ............................................................................................................................... 1
•
Changed the SWITCHING CHARACTERISTICS table, Input glitch rejection time. Values by device. ................................. 7
•
Changed the SWITCHING CHARACTERISTICS table, Input glitch rejection time. Values by device. ................................. 8
•
Changed the SWITCHING CHARACTERISTICS table, Input glitch rejection time. Values by device. ................................. 8
•
Added 图 3............................................................................................................................................................................ 12
Copyright © 2013–2015, Texas Instruments Incorporated
3
ISO7131CC, ISO7140CC, ISO7140FCC, ISO7141CC, ISO7141FCC
ZHCS221F – APRIL 2013 – REVISED JANUARY 2015
www.ti.com.cn
5 Pin Configuration and Functions
16-Pin
SSOP Package
Top View
ISO7131
ISO7140
ISO7141
VCC1
1
16
VCC2
VCC1
1
16
VCC2
VCC1
1
16
GND1
2
15
GND2
GND1
2
15
GND2
GND1
2
15
GND2
INA
INB
3
14
OUTA
3
14
OUTA
14
OUTA
13
OUTB
4
13
OUTB
INA
INB
3
4
INA
INB
4
13
OUTB
OUTC
5
12
INC
INC
5
12
OUTC
INC
5
12
OUTC
NC
6
11
NC
IND
6
11
OUTD
OUTD
6
11
IND
EN1
7
10
EN2
NC
7
10
EN
EN1
7
10
EN2
GND1
8
9
GND1
8
9
GND1
8
9
GND2
GND2
VCC2
GND2
Pin Functions
PIN
NAME
I/O
DESCRIPTION
—
I
Output enable. All output pins are enabled when EN is high or disconnected and
disabled when EN is low.
—
7
I
Output enable 1. Output pins on side-1 are enabled when EN1 is high or
disconnected and disabled when EN1 is low.
—
10
I
Output enable 2. Output pins on side-2 are enabled when EN2 is high or
disconnected and disabled when EN2 is low.
ISO7131
ISO7140
ISO7141
EN
—
10
EN1
7
EN2
10
GND1
2,8
2,8
2,8
—
Ground connection for VCC1
GND2
9,15
9,15
9,15
—
Ground connection for VCC2
INA
3
3
3
I
Input, channel A
INB
4
4
4
I
Input, channel B
INC
12
5
5
I
Input, channel C
IND
—
6
11
I
Input, channel D
NC
6,11
7
—
—
No Connect pins are floating with no internal connection
OUTA
14
14
14
O
Output, channel A
OUTB
13
13
13
O
Output, channel B
OUTC
5
12
12
O
Output, channel C
OUTD
—
11
6
O
Output, channel D
VCC1
1
1
1
—
Power supply, VCC1
VCC2
16
16
16
—
Power supply, VCC2
4
Copyright © 2013–2015, Texas Instruments Incorporated
ISO7131CC, ISO7140CC, ISO7140FCC, ISO7141CC, ISO7141FCC
www.ti.com.cn
ZHCS221F – APRIL 2013 – REVISED JANUARY 2015
6 Specifications
6.1 Absolute Maximum Ratings (1)
VCC1, VCC2
Supply voltage (2)
MIN
MAX
–0.5
6
INx, ENx,
OUTx
Voltage
–0.5
IO
Output current
–15
TJ
Maximum junction temperature
Tstg
Storage temperature
(1)
(2)
(3)
UNIT
V
VCC+ 0.5
–65
(3)
V
15
mA
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak
voltage values.
Maximum voltage must not exceed 6 V
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±4000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
VCC1, VCC2
IOH
Supply voltage
2.7
High-level output current (VCC ≥ 3.0 V)
–4
High-level output current (VCC < 3.0 V)
–2
NOM
MAX
5.5
V
mA
IOL
Low-level output current
VIH
High-level input voltage
VIL
Low-level input voltage
tui
Input pulse duration (VCC ≥ 4.5V)
20
tui
Input pulse duration (VCC < 4.5V)
25
1 / tui
Signaling rate (VCC ≥ 4.5V)
0
50
1 / tui
Signaling rate (VCC < 4.5V)
0
40
TA
Ambient temperature
–40
TJ
Junction temperature
–40
Copyright © 2013–2015, Texas Instruments Incorporated
UNIT
4
2
5.5
0
0.8
mA
V
ns
25
125
Mbps
°C
136
5
ISO7131CC, ISO7140CC, ISO7140FCC, ISO7141CC, ISO7141FCC
ZHCS221F – APRIL 2013 – REVISED JANUARY 2015
www.ti.com.cn
6.4 Thermal Information
ISO7131, ISO714x
THERMAL METRIC (1)
DBQ
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
104.5
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
57.8
°C/W
RθJB
Junction-to-board thermal resistance
46.8
°C/W
ψJT
Junction-to-top characterization parameter
18.3
°C/W
ψJB
Junction-to-board characterization parameter
46.4
°C/W
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.5 Power Dissipation Ratings
TEST CONDITIONS
PD
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF
Input a 25-MHz, 50% duty cycle square wave
Device power dissipation
VALUE
UNIT
150
mW
6.6 Electrical Characteristics: VCC1 and VCC2 at 5 V ±10%
VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted.)
PARAMETER
MIN
TYP
IOH = –4 mA; see 图 10
TEST CONDITIONS
VCCO
(1)
– 0.5
4.8
IOH = –20 μA; see 图 10
VCCO
(1)
– 0.1
5
VOH
High-level output voltage
VOL
Low-level output voltage
VI(HYS)
Input threshold voltage
hysteresis
IIH
High-level input current
VIH = VCC at INx or ENx
IIL
Low-level input current
VIL = 0 V at INx or ENx
CMTI
Common-mode transient
immunity
VI = VCC or 0 V; see 图 13
(1)
MAX
UNIT
V
IOL = 4 mA; see 图 10
0.2
0.4
IOL = 20 μA; see 图 10
0
0.1
450
V
mV
10
μA
μA
–10
25
75
kV/μs
VCCO is the supply voltage, VCC1 or VCC2, for the output channel that is being measured.
6.7 Electrical Characteristics: VCC1 and VCC2 at 3.3 V ±10%
VCC1 and VCC2 at 3.3 V ±10% (over recommended operating conditions unless otherwise noted.)
PARAMETER
MIN
TYP
IOH = –4 mA; see 图 10
TEST CONDITIONS
VCCO
(1)
– 0.5
3
IOH = –20 μA; see 图 10
VCCO
(1)
– 0.1
3.3
VOH
High-level output voltage
VOL
Low-level output voltage
VI(HYS)
Input threshold voltage hysteresis
IIH
High-level input current
VIH = VCC at INx or ENx
IIL
Low-level input current
VIL = 0 V at INx or ENx
CMTI
Common-mode transient
immunity
VI = VCC or 0 V; see 图 13
(1)
6
MAX
V
IOL = 4 mA; see 图 10
0.2
0.4
IOL = 20 μA; see 图 10
0
0.1
425
V
mV
10
μA
μA
–10
25
UNIT
50
kV/μs
VCCO is the supply voltage, VCC1 or VCC2, for the output channel that is being measured.
版权 © 2013–2015, Texas Instruments Incorporated
ISO7131CC, ISO7140CC, ISO7140FCC, ISO7141CC, ISO7141FCC
www.ti.com.cn
ZHCS221F – APRIL 2013 – REVISED JANUARY 2015
6.8 Electrical Characteristics: VCC1 and VCC2 at 2.7 V
VCC1 and VCC2 at 2.7 V (over recommended operating conditions unless otherwise noted.)
PARAMETER
TEST CONDITIONS
IOH = –2 mA; see 图 10
VCCO
(1)
IOH = –20 μA; see 图 10
VCCO
(1)
VOH
High-level output voltage
VOL
Low-level output voltage
VI(HYS)
Input threshold voltage hysteresis
IIH
High-level input current
VIH = VCC at INx or ENx
IIL
Low-level input current
VIL = 0 V at INx or ENx
CMTI
Common-mode transient immunity
VI = VCC or 0 V; see 图 13
(1)
MIN
TYP
– 0.3
2.5
– 0.1
2.7
MAX
UNIT
V
IOL = 4 mA; see 图 10
0.2
0.4
IOL = 20 μA; see 图 10
0
0.1
V
350
mV
μA
10
μA
–10
25
50
kV/μs
VCCO is the supply voltage, VCC1 or VCC2, for the output channel that is being measured.
6.9 Switching Characteristics: VCC1 and VCC2 at 5 V ±10%
VCC1 and VCC2 at 5 V ±10% (over recommended operating conditions unless otherwise noted.)
PARAMETER
tPLH, tPHL
Propagation delay time
PWD (1)
Pulse width distortion |tPHL – tPLH|
tsk(o)
(2)
tsk(pp)
(3)
Channel-to-channel output skew time
Output signal rise time
tf
Output signal fall time
tPHZ, tPLZ
Disable propagation delay, high/low-to-high impedance output
tPZH, tPZL
Enable propagation delay, high impedance-to-high/low output
tfs
Fail-safe output delay time from input data or power loss
tGR
Input glitch rejection time
(3)
See 图 10
MIN
TYP
12
19
MAX UNIT
35
3
Same-direction
channels
2
Opposite-direction
channels
4
12
See 图 10
See 图 11
See 图 12
ns
ns
Part-to-part skew time
tr
(1)
(2)
TEST CONDITIONS
2
ns
ns
2
ns
6
10
5
10
ns
ns
9.5
μs
11
ns
Also known as pulse skew
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals, and loads.
版权 © 2013–2015, Texas Instruments Incorporated
7
ISO7131CC, ISO7140CC, ISO7140FCC, ISO7141CC, ISO7141FCC
ZHCS221F – APRIL 2013 – REVISED JANUARY 2015
www.ti.com.cn
6.10 Switching Characteristics: VCC1 and VCC2 at 3.3 V ±10%
VCC1 and VCC2 at 3.3 V ±10% (over recommended operating conditions unless otherwise noted.)
PARAMETER
tPLH, tPHL
Propagation delay time
PWD (1)
Pulse width distortion |tPHL – tPLH|
tsk(o)
(2)
tsk(pp)
(3)
Channel-to-channel output skew time
Output signal rise time
tf
Output signal fall time
tPHZ, tPLZ
Disable propagation delay, from high/low to
high-impedance output
tPZH, tPZL
Enable propagation delay, from highimpedance to high/low output
tfs
Fail-safe output delay time from input data or
power loss
tGR
Input glitch rejection time
(3)
MIN
TYP
MAX
15
23
45
See 图 10
UNIT
ns
3
Same-direction Channels
2
Opposite-direction
Channels
4
Part-to-part skew time
tr
(1)
(2)
TEST CONDITIONS
ns
19
See 图 10
ns
2.5
ns
2.5
ns
6.5
15
ns
6.5
15
ns
See 图 11
See 图 12
8
μs
12.5
ns
Also known as pulse skew
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
6.11 Switching Characteristics: VCC1 and VCC2 at 2.7 V
VCC1 and VCC2 at 2.7 V (over recommended operating conditions unless otherwise noted.)
PARAMETER
tPLH, tPHL
Propagation delay time
PWD (1)
Pulse width distortion |tPHL – tPLH|
tsk(o)
(2)
tsk(pp)
(3)
Channel-to-channel output skew time
Output signal rise time
tf
Output signal fall time
tPHZ, tPLZ
Disable propagation delay, from high/low to highimpedance output
tPZH, tPZL
Enable propagation delay, from high-impedance to
high/low output
tfs
Fail-safe output delay time from input data or power loss
tGR
Input glitch rejection time
(3)
8
See 图 10
MIN
TYP
MAX
15
27
50
3
Same-direction Channels
2
Opposite-direction
Channels
4
Part-to-part skew time
tr
(1)
(2)
TEST CONDITIONS
22
See 图 10
UNIT
ns
ns
ns
3
ns
3
ns
9
15
ns
9
15
ns
See 图 11
See 图 12
8.5
μs
14
ns
Also known as pulse skew
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals, and loads.
版权 © 2013–2015, Texas Instruments Incorporated
ISO7131CC, ISO7140CC, ISO7140FCC, ISO7141CC, ISO7141FCC
www.ti.com.cn
ZHCS221F – APRIL 2013 – REVISED JANUARY 2015
6.12 Supply Current: VCC1 and VCC2 at 5 V ±10%
VCC1 and VCC2 at 5 V ±10% (over recommended operating conditions unless otherwise noted.)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
2.2
3.7
3.7
5
2.2
3.7
UNIT
ISO7131
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
Disable
EN1 = EN2 = 0 V
DC to 1 Mbps
10 Mbps
25 Mbps
DC signal: VI = VCC or 0 V
AC signal: All channels switching with square-wave
clock input; CL = 15 pF
50 Mbps
3.7
5
3.4
4.8
4.9
6.6
4.9
6.6
6.8
9
7.1
10
10.5
13
0.6
1.2
4.6
7
0.6
1.3
mA
mA
ISO7140
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
Disable
EN = 0 V
DC to 1 Mbps
10 Mbps
25 Mbps
DC Signal: VI = VCC or 0 V,
AC Signal: All channels switching with square wave
clock input; CL = 15 pF
50 Mbps
4.8
7
1.4
2.2
6.9
9.2
2.7
3.9
10.3
13.5
4.7
6.5
15.6
21
2.5
4.2
4.2
7
2.5
4.2
4.2
7
3.8
5.3
6.2
9.6
5.6
7.5
mA
mA
ISO7141
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
Disable
EN1 = EN2 = 0V
DC to 1 Mbps
10 Mbps
25 Mbps
DC signal: VI = VCC or 0 V,
AC signal: All channels switching with square wave
clock input; CL = 15 pF
50 Mbps
版权 © 2013–2015, Texas Instruments Incorporated
9.2
13
8.4
11.2
14
18.5
mA
mA
9
ISO7131CC, ISO7140CC, ISO7140FCC, ISO7141CC, ISO7141FCC
ZHCS221F – APRIL 2013 – REVISED JANUARY 2015
www.ti.com.cn
6.13 Supply Current: VCC1 and VCC2 at 3.3 V ±10%
VCC1 and VCC2 at 3.3 V ±10% (over recommended operating conditions unless otherwise noted.)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
1.9
2.7
2.6
3.8
1.9
2.7
2.6
3.8
2.4
3.5
3.5
4.7
3.2
4.6
4.7
6.2
5
7
7
9
0.3
0.7
3.6
5.2
0.4
0.8
3.7
5.3
0.9
1.4
5.1
6.8
1.7
2.4
7.3
10
2.4
3.7
9.4
13
2
3.1
3.2
4.9
UNIT
ISO7131
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
Disable
EN1 = EN2 = 0 V
DC to 1 Mbps
10 Mbps
25 Mbps
DC signal: VI = VCC or 0 V
AC signal: All channels switching with square-wave
clock input; CL = 15 pF
40 Mbps
mA
mA
ISO7140
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
Disable
EN = 0 V
DC to 1 Mbps
10 Mbps
25 Mbps
DC signal: VI = VCC or 0 V,
AC signal: All channels switching with square-wave
clock input; CL = 15 pF
40 Mbps
mA
mA
ISO7141
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
10
Disable
EN1 = EN2 = 0 V
DC to 1 Mbps
10 Mbps
25 Mbps
40 Mbps
DC signal: VI = VCC or 0 V,
AC signal: All channels switching with square-wave
clock input; CL = 15 pF
2
3.1
3.2
4.9
2.8
3.8
4.5
6.1
4
5.2
6.4
8.3
5
8
8.2
11.6
mA
mA
版权 © 2013–2015, Texas Instruments Incorporated
ISO7131CC, ISO7140CC, ISO7140FCC, ISO7141CC, ISO7141FCC
www.ti.com.cn
ZHCS221F – APRIL 2013 – REVISED JANUARY 2015
6.14 Supply Current: VCC1 and VCC2 at 2.7 V
VCC1 and VCC2 at 2.7 V (over recommended operating conditions unless otherwise noted.)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
1.2
2.4
2.3
3.3
1.2
2.4
2.3
3.3
2.1
3
2.9
4
3
3.8
UNIT
ISO7131
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
Disable
EN1 = EN2 = 0 V
DC to 1 Mbps
10 Mbps
25 Mbps
DC signal: VI = VCC or 0 V
AC signal: All channels switching with square-wave
clock input; CL = 15 pF
40 Mbps
4
5.2
4.2
5.3
5.8
7
0.2
0.4
3.2
4.7
0.2
0.5
3.4
4.8
0.6
1
4.5
6.3
1.2
1.8
6.2
8
1.8
2.6
8
11
1.6
2.6
2.8
4.1
1.6
2.6
2.8
4.1
2.3
3.2
mA
mA
ISO7140
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
Disable
EN = 0 V
DC to 1 Mbps
10 Mbps
25 Mbps
DC signal: VI = VCC or 0 V,
AC signal: All channels switching with square-wave
clock input; CL = 15 pF
40 Mbps
mA
mA
ISO7141
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
Disable
EN1 = EN2 = 0 V
DC to 1 Mbps
10 Mbps
25 Mbps
DC signal: VI = VCC or 0 V,
AC signal: All channels switching with square-wave
clock input; CL = 15 pF
40 Mbps
版权 © 2013–2015, Texas Instruments Incorporated
3.8
5
3.3
4.2
5.4
6.8
4.3
5.8
6.9
9.2
mA
mA
11
ISO7131CC, ISO7140CC, ISO7140FCC, ISO7141CC, ISO7141FCC
ZHCS221F – APRIL 2013 – REVISED JANUARY 2015
www.ti.com.cn
6.15 Typical Characteristics
12.00
ICC2
5VV
ICC2
at 5
ICC2
3.3VV
ICC2
at 3.3
ICC1
at 5
ICC1
5VV
ICC1
at 3.3
ICC1
3.3VV
16
Supply Current (mA)
10.00
Supply Current (mA)
18
ICC1
3.3VV
ICC1 atat3.3
ICC2 atat3.3
ICC2
3.3VV
ICC1 atat5 5VV
ICC1
ICC2 atat5 5VV
ICC2
8.00
6.00
4.00
14
12
10
8
6
4
2.00
2
0.00
0
0
10
20
30
40
50
Data Rate (Mbps)
60
图 1. ISO7131 Supply Current for All Channels vs Data Rate
16
20
30
40
50
60
Data Rate (Mbps)
C001
图 2. ISO7140 Supply Current for All Channels vs Data Rate
5.00
High-Level Output Voltage (V)
Supply Current (mA)
12
10
6.00
ICC2
5VV
ICC2
at 5
ICC2
at 3.3
ICC2
3.3VV
ICC1
at 5
ICC1
5VV
ICC1
at 3.3
ICC1
3.3VV
14
0
C001
10
8
6
4
2
4.00
3.00
2.00
1.00
3.3V V
VVCC
3.3
CC atat
0.00
VVCC
5 5V V
CC atat
0
±1.00
0
10
20
30
40
Data Rate (Mbps)
50
60
±15
图 3. ISO7141 Supply Current for All Channels vs Data Rate
C002
1.75
V
VCC
CC atat55VV
1.50
1.25
1.00
0.75
0.50
0.25
0.00
0
5
10
Low-Level Output Current (mA)
15
C003
图 5. Low-Level Output Voltage vs Low-Level Output
Current
Power Supply Undervoltage Threshold (V)
2.48
VCC
3.3VV
V
CC atat3.3
Low-Level Output Voltage (V)
0
±5
图 4. High-Level Output Voltage vs High-Level Output
Current
2.00
12
±10
High-Level Output Current (mA)
C001
VCC
Rising
V
CC Rising
2.46
V
VCC
Falling
CC Falling
2.44
2.42
2.40
2.38
2.36
2.34
±50
0
50
100
Free-Air Temperature (ƒC)
150
C004
图 6. VCC Undervoltage Threshold vs Free-Air Temperature
版权 © 2013–2015, Texas Instruments Incorporated
ISO7131CC, ISO7140CC, ISO7140FCC, ISO7141CC, ISO7141FCC
www.ti.com.cn
ZHCS221F – APRIL 2013 – REVISED JANUARY 2015
30
1.2
25
1
Pk-Pk Output Jitter (ns)
Propagation Delay Time (ns)
Typical Characteristics (接
接下页)
20
15
10
ttpLH
3.3
3.3VV
pLH atat
ttpHL
3.3
3.3VV
pHL atat
ttpLH
5 5VV
pLH atat
ttpHL
5 5VV
pHL atat
5
0
±50
0
50
100
0.6
0.4
0.2
Output Jitter at 5 V
Output Jitter at 3.3 V
0
150
Free-Air Temperature (C)
0.8
0
20
40
Data Rate (Mbps)
C005
图 7. Propagation Delay Time vs Free-Air Temperature
60
C006
图 8. Output Jitter vs Data Rate
Input Glitch Rejection Time (ns)
18
16
14
12
10
8
6
4
ttGR
2.7VV
GR atat2.7
ttGR
3.3VV
GR atat3.3
ttGR
GR atat55VV
2
0
±50
0
50
100
Free-Air Temperature (C)
150
C007
图 9. Input Glitch Rejection vs Free-Air Temperature
版权 © 2013–2015, Texas Instruments Incorporated
13
ISO7131CC, ISO7140CC, ISO7140FCC, ISO7141CC, ISO7141FCC
ZHCS221F – APRIL 2013 – REVISED JANUARY 2015
www.ti.com.cn
ISOLATION BARRIER
7 Parameter Measurement Information
IN
Input
Generator
NOTE A
50 W
VI
VCC1
VI
VCC/2
OUT
VCC/2
0V
tPHL
tPLH
VO
CL
NOTE
B
VOH
90%
VO
50%
10%
tf
tr
50%
VOL
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50 Ω. At the input, a 50-Ω resistor is required to terminate the input-generator signal. It is not
needed in an actual application.
B.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
图 10. Switching-Characteristics Test Circuit and Voltage Waveforms
VCC
VCC
ISOLATION BARRIER
0V
R L = 1 k W ± 1%
IN
Input
Generator
OUT
EN
VO
0V
tPLZ
tPZL
VO
CL
VCC/2
VCC/2
VI
VCC
0.5 V
50%
VOL
NOTE
B
VI
50 W
ISOLATION BARRIER
NOTE A
IN
3V
Input
Generator
NOTE A
VI
VCC
OUT
VO
VCC/2
VI
VCC/2
0V
EN
50 W
CL
NOTE
B
tPZH
R L = 1 k W ± 1%
VO
VOH
50%
0.5 V
tPHZ
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50 Ω.
B.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
0V
图 11. Enable/Disable Propagation Delay-Time Test Circuit and Waveform
14
版权 © 2013–2015, Texas Instruments Incorporated
ISO7131CC, ISO7140CC, ISO7140FCC, ISO7141CC, ISO7141FCC
www.ti.com.cn
ZHCS221F – APRIL 2013 – REVISED JANUARY 2015
Parameter Measurement Information (接
接下页)
VI
IN = 0 V (Devices without suffix F)
IN = VCC (Devices with suffix F)
A.
IN
VCC
ISOLATION BARRIER
VCC
2.7 V
VI
OUT
0V
t fs
VO
fs high
CL
NOTE A
VO
VOH
50%
fs low V
OL
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
图 12. Failsafe Delay-Time Test Circuit and Voltage Waveforms
VCC1
VCC2
IN
S1
ISOLATION BARRIER
C = 0.1 mF ±1%
GND1
C = 0.1 mF ±1%
OUT
CL
NOTE A
Pass/Fail Criterion –
the output must
remain stable.
VOH or VOL
GND2
VTEST
A.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
图 13. Common-Mode Transient Immunity Test Circuit
版权 © 2013–2015, Texas Instruments Incorporated
15
ISO7131CC, ISO7140CC, ISO7140FCC, ISO7141CC, ISO7141FCC
ZHCS221F – APRIL 2013 – REVISED JANUARY 2015
www.ti.com.cn
8 Detailed Description
8.1 Overview
The isolator in 图 14 is based on a capacitive isolation barrier technique. The I/O channel of the device consists
of two internal data channels, a high-frequency channel (HF) with a bandwidth from 100 kbps up to
150 Mbps, and a low-frequency channel (LF) covering the range from 100 kbps down to DC. In principle, a
single-ended input signal entering the HF-channel is split into a differential signal through the inverter gate at the
input. The following capacitor-resistor networks differentiate the signal into transients, which then are converted
into differential pulses by two comparators. The comparator outputs drive a NOR-gate flip-flop whose output
feeds an output multiplexer. A decision logic (DCL) at the driving output of the flip-flop measures the durations
between signal transients. If the duration between two consecutive transients exceeds a certain time limit, (as in
the case of a low-frequency signal), the DCL forces the output-multiplexer to switch from the high- to the lowfrequency channel.
Because low-frequency input signals require the internal capacitors to assume prohibitively large values, these
signals are pulse-width modulated (PWM) with the carrier frequency of an internal oscillator, thus creating a
sufficiently high frequency signal, capable of passing the capacitive barrier. As the input is modulated, a low-pass
filter (LPF) is needed to remove the high-frequency carrier from the actual data before passing it on to the output
multiplexer.
8.2 Functional Block Diagram
图 14. Conceptual Block Diagram of a Digital Capacitive Isolator
16
版权 © 2013–2015, Texas Instruments Incorporated
ISO7131CC, ISO7140CC, ISO7140FCC, ISO7141CC, ISO7141FCC
www.ti.com.cn
ZHCS221F – APRIL 2013 – REVISED JANUARY 2015
8.3 Feature Description
表 1. Product Features
PRODUCT
RATED
ISOLATION
INPUT
THRESHOLD
DEFAULT
OUTPUT
ISO7131CC
ISO7140CC
ISO7140FCC
(1)
MAX DATA RATE
and
INPUT FILTER
CHANNEL
DIRECTION
2 forward,
1 reverse
High
4242 VPK (1)
1.5-V TTL
(CMOS compatible)
Low
ISO7141CC
High
ISO7141FCC
Low
4 forward,
0 reverse
50 Mbps,
with noise filter integrated
3 forward,
1 reverse
See Regulatory Information for detailed Isolation Ratings.
8.3.1 Insulation and Safety-Related Specifications
MAX
UNIT
VIOTM
Maximum transient overvoltage per
DIN V VDE V 0884-10 (VDE V
0884-10):2006-12
PARAMETER
4242
VPK
VIORM
Maximum working voltage per DIN
V VDE V 0884-10 (VDE V 088410):2006-12
566
VPK
VISO
Isolation Voltage per UL 1577
Input-to-output test voltage per DIN
V VDE V 0884-10 (VDE V 088410):2006-12
VPR
TEST CONDITIONS
MIN
TYP
VTEST = VISO, t = 60 sec (qualification)
2500
VTEST = 1.2 * VISO, t = 1 sec (100% production)
3000
After Input/Output safety test subgroup 2/3,
VPR = VIORM x 1.2, t = 10 s,
Partial discharge < 5 pC
679
Method a, After environmental tests subgroup 1,
VPR = VIORM x 1.6, t = 10 s,
Partial discharge < 5 pC
906
Method b1, 100% production test,
VPR = VIORM x 1.875, t = 1 s,
Partial discharge < 5 pC
VRMS
VPK
1061
L(I01)
Minimum air gap (clearance)
Shortest terminal to terminal distance through air
3.7
mm
L(I02)
Minimum external tracking
(creepage)
Shortest terminal to terminal distance across the
package surface
3.7
mm
Minimum internal gap (internal
clearance)
Distance through the insulation
0.014
mm
Pollution degree
Tracking resistance (comparative
tracking index)
CTI
2
DIN IEC 60112 / VDE 0303 Part 1
o
RIO
(1)
CIO
(1)
CI
(1)
(2)
(2)
Isolation Resistance, Input to Output
≥400
V
12
VIO = 500 V, TA = 25 C
>10
VIO = 500 V, 100oC ≤ TA ≤ TA max
>1011
Ω
Barrier capacitance, input to output
VI = 0.4 sin (2πft), f = 1 MHz
2.3
pF
Input capacitance
VI = VCC/2 + 0.4 sin (2πft), f = 1 MHz, VCC = 5 V
2.8
pF
All pins on each side of the barrier tied together creating a two-terminal device.
Measured from input pin to ground.
版权 © 2013–2015, Texas Instruments Incorporated
17
ISO7131CC, ISO7140CC, ISO7140FCC, ISO7141CC, ISO7141FCC
ZHCS221F – APRIL 2013 – REVISED JANUARY 2015
www.ti.com.cn
spacer
注
Creepage and clearance requirements should be applied according to the specific
equipment isolation standards of an application. Care should be taken to maintain the
creepage and clearance distance of a board design to ensure that the mounting pads of
the isolator on the printed-circuit-board (PCB) do not reduce this distance.
Creepage and clearance on a PCB become equal in certain cases. Techniques such as
inserting grooves and/or ribs on a PCB are used to help increase these specifications.
表 2. IEC 60664-1 Ratings Table
PARAMETER
Basic Isolation Group
TEST CONDITIONS
SPECIFICATION
Material Group
Installation classification
II
Rated mains voltage ≤ 150 VRMS
I–IV
Rated mains voltage ≤ 300 VRMS
I–III
Rated mains voltage ≤ 400 VRMS
I–II
8.3.1.1 Safety Limiting Values
Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry.
A failure of the IO can allow low resistance to ground or the supply and, without current limiting, dissipate
sufficient power to overheat the die and damage the isolation barrier, potentially leading to secondary system
failures.
PARAMETER
IS
Safety input, output, or supply
current
TS
Maximum case temperature
TEST CONDITIONS
DBQ-16
MIN
TYP MAX
RθJA = 104.5°C/W, VI = 5.5V, TJ = 150°C, TA = 25°C
217
RθJA = 104.5°C/W, VI = 3.6V, TJ = 150°C, TA = 25°C
332
RθJA = 104.5°C/W, VI = 2.7V, TJ = 150°C, TA = 25°C
443
150
UNIT
mA
°C
Safety Limiting Current – mA
The safety-limiting constraint is the absolute-maximum junction temperature specified in the Absolute Maximum
Ratings (1) table. The power dissipation and junction-to-air thermal impedance of the device installed in the
application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the
Thermal Information table is that of a device installed on a high-K test board for leaded surface-mount packages.
The power is the recommended maximum input voltage times the current. The junction temperature is then the
ambient temperature plus the power times the junction-to-air thermal resistance.
500
450
400
350
300
250
200
150
100
50
0
VCC1 = VCC2 = 2.7V
VCC1 = VCC2 = 3.6V
VCC1 = VCC2 = 5.5V
0
50
100
150
200
o
Case Temperature – C
图 15. DBQ-16 θJC Thermal Derating Curve
(1)
18
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
版权 © 2013–2015, Texas Instruments Incorporated
ISO7131CC, ISO7140CC, ISO7140FCC, ISO7141CC, ISO7141FCC
www.ti.com.cn
ZHCS221F – APRIL 2013 – REVISED JANUARY 2015
8.3.1.2 Regulatory Information
VDE
UL
CSA
Certified according to DIN V
Recognized under UL 1577
VDE V 0884-10 (VDE V 0884- Component Recognition
10):2006-12 and DIN EN
Program
61010-1
Basic Insulation
Maximum Transient
Overvoltage, 4242 VPK
Maximum Working Voltage,
566 VPK
Certificate number: 40016131
(1)
CQC
Approved under CSA Component
Acceptance Notice 5A, IEC 60950-1, and
IEC 61010-1
Certified according to GB
4943.1-2011
Single protection, 2500 VRMS
(1)
Reinforced Insulation per CSA 60950-1-03
and IEC 60950-1 (2nd Ed.), 185 VRMS
maximum working voltage
Basic Insulation per CSA 60950-1-03 and
IEC 60950-1 (2nd Ed.), 370 VRMS
maximum working voltage
Reinforced Insulation per CSA 61010-1-12
and IEC 61010-1 (3rd Edition), 150 VRMS
maximum working voltage
Basic Insulation per CSA 61010-1-12 and
IEC 61010-1 (3rd Edition), 300 VRMS
maximum working voltage
Basic Insulation, Altitude ≤
5000m, Tropical Climate, 250
VRMS maximum working
voltage
File number: E181974
Master contract number: 220991
Certificate number:
CQC14001109540
Production tested ≥ 3000 Vrms for 1 second in accordance with UL 1577.
8.4 Device Functional Modes
表 3. Function Table (1)
VCCI
PU
(1)
VCCO
PU
OUTPUT (OUTx)
INPUT
(INx)
OUTPUT ENABLE
(ENx)
ISO71xxCC
ISO71xxFCC
H
H or open
H
H
L
H or open
L
L
X
L
Z
Z
Open
H or open
H
L
PD
PU
X
H or open
H
L
PD
PU
X
L
Z
Z
PU
PD
X
X
Undetermined
Undetermined
VCCI = Input-side VCC; VCCO = Output-side VCC; PU = Powered Up (VCC ≥ 2.7 V); PD = Powered Down
(VCC ≤ 2.1 V); X = Irrelevant; H = High Level; L = Low Level; Z = High Impedance
版权 © 2013–2015, Texas Instruments Incorporated
19
ISO7131CC, ISO7140CC, ISO7140FCC, ISO7141CC, ISO7141FCC
ZHCS221F – APRIL 2013 – REVISED JANUARY 2015
www.ti.com.cn
Output
ISO71xxFCC Input
VCCO
VCCI
VCCI
500Ω
8Ω
IN
OUT
13Ω
7.5 uA
Enable
ISO71xxCC Input
VCCI
VCCO
VCCI
VCCI
1 MΩ
7.5 uA
500Ω
500Ω
IN
VCCO
VCCO
IN
图 16. Device I/O Schematics
20
版权 © 2013–2015, Texas Instruments Incorporated
ISO7131CC, ISO7140CC, ISO7140FCC, ISO7141CC, ISO7141FCC
www.ti.com.cn
ZHCS221F – APRIL 2013 – REVISED JANUARY 2015
9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
ISO71xx use single-ended TTL-logic switching technology. Its supply voltage range is from 3 V to 5.5 V for both
supplies, VCC1 and VCC2. When designing with digital isolators, it is important to note that due to the single-ended
design structure, digital isolators do not conform to any specific interface standard and are only intended for
isolating single-ended CMOS or TTL digital signal lines. The isolator is typically placed between the data
controller (that is, μC or UART), and a data converter or a line transceiver, regardless of the interface type or
standard.
9.2 Typical Applications
9.2.1 Isolated Data Acquisition System for Process Control
ISO71xx combined with TI's precision analog-to-digital converter and mixed signal micro-controller can create an
advanced isolated data acquisition system as shown in 图 17.
5 VISO
ISO-BARRIER
5 VISO
5 VISO
0 .1 F
22
AVDD
11
RTD
12
16
1
0.1 F
DVDD
AIN1+
A0
AIN1-
A1
SCLK
Bridge
18
17
AIN2+
DOUT
13
14
16
Current
shunt
15
7
13
27
12
28
11
ADS1234
AIN3+
5VISO
AIN3-
REFGAIN0
GAIN1
AIN4+
AIN4AGND
21
SPEED
PWDN
10
14
8
AIN2REF+
Thermo
couple
3.3 V
3.3 V
0 .1 F
9, 15
5 VISO
V CC2
VCC 1
EN2
EN1
INA
OUTA
OUTB
ISO7141
OUTC
IND
GND2
INB
INC
OUTD
GND1
0 .1 F
1
7
11
4
12
5
14
6
13
0.1 F
0.1 F
16
10
23
14
24
13
25
12
26
11
DGND
9, 15
V CC2
VCC 1
EN
NC
OUTA
OUTB
INA
ISO7140
INB
OUTC
INC
OUTD
IND
GND2
GND1
DVcc
P 3.0
XOUT
3.3 V
CLK
MSP430
F2132
P3.7
SOMI
P 3.4
1
7
XIN
P3.6
15
5
P 3.1
2, 8
20
19
2
0.1 F
3
0.1 F
DVss
P3.5
6
18
17
16
4
3
4
5
6
2, 8
2
图 17. Isolated Data Acquisition System for Process Control
版权 © 2013–2015, Texas Instruments Incorporated
21
ISO7131CC, ISO7140CC, ISO7140FCC, ISO7141CC, ISO7141FCC
ZHCS221F – APRIL 2013 – REVISED JANUARY 2015
www.ti.com.cn
Typical Applications (接
接下页)
9.2.1.1 Design Requirements
Unlike optocouplers, which need external components to improve performance, provide bias, or limit current,
ISO71xx only needs two external bypass capacitors to operate.
9.2.1.2 Detailed Design Procedure
ISO7131
0.1 µF
VCC1
0.1 µF
16
2
15
INA
3
14
OUTA
INB
4
13
OUTB
OUTC
5
12
INC
6
11
7
10
8
9
NC
ISO7140
0.1 µF
VCC2
1
GND1
2 mm max
from VCC2
2 mm max
from VCC1
2 mm max
from VCC2
2 mm max
from VCC1
0.1 µF
VCC2
1
16
2
15
INA
3
14
OUTA
INB
4
13
OUTB
INC
5
12
OUTC
IND
6
11
OUTD
7
10
8
9
VCC1
GND2
GND1
NC
NC
EN2
EN1
GND1
GND2
EN
GND2
GND1
图 18. Typical ISO7131 Circuit Hook-up
图 19. Typical ISO7140 Circuit Hook-up
2 mm max
from VCC2
2 mm max
from VCC1
ISO7141
0.1 µF
VCC1
GND2
0.1 µF
VCC2
1
16
2
15
INA
3
14
OUTA
INB
4
13
OUTB
INC
5
12
OUTD
6
11
7
10
8
9
GND1
GND2
IND
EN2
EN1
GND1
OUTC
GND2
图 20. Typical ISO7141 Circuit Hook-up
22
版权 © 2013–2015, Texas Instruments Incorporated
ISO7131CC, ISO7140CC, ISO7140FCC, ISO7141CC, ISO7141FCC
www.ti.com.cn
ZHCS221F – APRIL 2013 – REVISED JANUARY 2015
Typical Applications (接
接下页)
9.2.1.3 Application Curves
Typical eye diagrams of ISO71xx (see 图 21, 图 22, and 图 23) indicate low jitter and wide open eye at the
maximum data rate.
图 21. Typical Eye Diagram at 40 MBPS, PRBS 216 - 1, 2.7-V
Operation
图 22. Typical Eye Diagram at 40 MBPS, PRBS 216 - 1, 3.3-V
Operation
图 23. Typical Eye Diagram at 50 MBPS, PRBS 216 - 1, 5-V Operation
版权 © 2013–2015, Texas Instruments Incorporated
23
ISO7131CC, ISO7140CC, ISO7140FCC, ISO7141CC, ISO7141FCC
ZHCS221F – APRIL 2013 – REVISED JANUARY 2015
www.ti.com.cn
Typical Applications (接
接下页)
9.2.2 Isolated RS-485 Interface
VIN
3.3V
0.1 F
2
Vcc D2 3
1:2.2 MBR0520L
1
SN6501
GND D1
3
1
10 F
OUT
5
TPS76350
10 F 0.1 F
4,5
IN
EN
GND
2
5VISO
10 F
MBR0520L
ISO-BARRIER
0.1 F
0.1 F
0.1 F
2
6
P3.0
XOUT
XIN
16
1
DVcc
5
0.1 F
11
15
MSP430 UCA0TXD
F2132
UCA0RXD 16
DVss
3
4
5
VCC1
VCC2
INA
OUTA
ISO7131
INB
OUTC
7 EN1
4
GND1
2,8
OUTB
INC
VCC
14
13
12
EN2 10
GND2
2
3
4
1
RE
DE
10
MELF
B
D
SN65HVD
3082E A
R
GND
10
MELF
SM712
9,15
4.7nF/
2kV
图 24. Isolated RS-485 Interface
9.2.2.1 Design Requirements
See previous Design Requirements.
9.2.2.2 Detailed Design Procedure
See previous Detailed Design Procedure.
9.2.2.3 Application Curves
See previous Application Curves.
24
版权 © 2013–2015, Texas Instruments Incorporated
ISO7131CC, ISO7140CC, ISO7140FCC, ISO7141CC, ISO7141FCC
www.ti.com.cn
ZHCS221F – APRIL 2013 – REVISED JANUARY 2015
10 Power Supply Recommendations
To ensure reliable operation at all data rates and supply voltages, a 0.1-µF bypass capacitor is recommended at
input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins as
possible. If only a single primary-side power supply is available in an application, isolated power can be
generated for the secondary-side with the help of a transformer driver such as TI's SN6501. For such
applications, detailed power supply design and transformer selection recommendations are available in SN6501
data sheet (SLLSEA0).
11 Layout
11.1 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see 图 25). Layer stacking should be
in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency
signal layer.
• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100pF/in2.
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power / ground plane system to the
stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the
power and ground plane of each power system can be placed closer together, thus increasing the high-frequency
bypass capacitance significantly.
For detailed layout recommendations, see Application Note SLLA284, Digital Isolator Design Guide.
11.1.1 PCB Material
For digital circuit boards operating below 150 Mbps, (or rise and fall times higher than 1 ns), and trace lengths of
up to 10 inches, use standard FR-4 epoxy-glass as PCB material. FR-4 (Flame Retardant 4) meets the
requirements of Underwriters Laboratories UL94-V0, and is preferred over cheaper alternatives due to its lower
dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and its selfextinguishing flammability-characteristics.
11.2 Layout Example
High-speed traces
10 mils
Ground plane
40 mils
Keep this
space free
from planes,
traces , pads,
and vias
FR-4
0r ~ 4.5
Power plane
10 mils
Low-speed traces
图 25. Recommended Layer Stack
版权 © 2013–2015, Texas Instruments Incorporated
25
ISO7131CC, ISO7140CC, ISO7140FCC, ISO7141CC, ISO7141FCC
ZHCS221F – APRIL 2013 – REVISED JANUARY 2015
www.ti.com.cn
12 器件和文档支持
12.1 文档支持
12.1.1 相关文档
• SLLA284，《数字隔离器设计指南》
• SLLSEA0，《用于隔离电源的变压器驱动器》
12.2 相关链接
以下表格列出了快速访问链接。 范围包括技术文档、支持与社区资源、工具和软件，并且可以快速访问样片或购买
链接。
表 4. 相关链接
器件
产品文件夹
样片与购买
技术文档
工具与软件
支持与社区
ISO7131CC
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
ISO7140CC
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
ISO7140FCC
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
ISO7141CC
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
ISO7141FCC
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
12.3 商标
Modbus is a trademark of Gould Inc.
All other trademarks are the property of their respective owners.
12.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.5 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、首字母缩略词和定义。
SLLA353 - 《隔离相关术语》。
13 机械封装和可订购信息
以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不对
本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
26
版权 © 2013–2015, Texas Instruments Incorporated
重要声明
德州仪器(TI) 及其下属子公司有权根据 JESD46 最新标准, 对所提供的产品和服务进行更正、修改、增强、改进或其它更改， 并有权根据
JESD48 最新标准中止提供任何产品和服务。客户在下订单前应获取最新的相关信息, 并验证这些信息是否完整且是最新的。所有产品的销售
都遵循在订单确认时所提供的TI 销售条款与条件。
TI 保证其所销售的组件的性能符合产品销售时 TI 半导体产品销售条件与条款的适用规范。仅在 TI 保证的范围内，且 TI 认为 有必要时才会使
用测试或其它质量控制技术。除非适用法律做出了硬性规定，否则没有必要对每种组件的所有参数进行测试。
TI 对应用帮助或客户产品设计不承担任何义务。客户应对其使用 TI 组件的产品和应用自行负责。为尽量减小与客户产品和应 用相关的风险，
客户应提供充分的设计与操作安全措施。
TI 不对任何 TI 专利权、版权、屏蔽作品权或其它与使用了 TI 组件或服务的组合设备、机器或流程相关的 TI 知识产权中授予 的直接或隐含权
限作出任何保证或解释。TI 所发布的与第三方产品或服务有关的信息，不能构成从 TI 获得使用这些产品或服 务的许可、授权、或认可。使用
此类信息可能需要获得第三方的专利权或其它知识产权方面的许可，或是 TI 的专利权或其它 知识产权方面的许可。
对于 TI 的产品手册或数据表中 TI 信息的重要部分，仅在没有对内容进行任何篡改且带有相关授权、条件、限制和声明的情况 下才允许进行
复制。TI 对此类篡改过的文件不承担任何责任或义务。复制第三方的信息可能需要服从额外的限制条件。
在转售 TI 组件或服务时，如果对该组件或服务参数的陈述与 TI 标明的参数相比存在差异或虚假成分，则会失去相关 TI 组件 或服务的所有明
示或暗示授权，且这是不正当的、欺诈性商业行为。TI 对任何此类虚假陈述均不承担任何责任或义务。
客户认可并同意，尽管任何应用相关信息或支持仍可能由 TI 提供，但他们将独力负责满足与其产品及在其应用中使用 TI 产品 相关的所有法
律、法规和安全相关要求。客户声明并同意，他们具备制定与实施安全措施所需的全部专业技术和知识，可预见 故障的危险后果、监测故障
及其后果、降低有可能造成人身伤害的故障的发生机率并采取适当的补救措施。客户将全额赔偿因 在此类安全关键应用中使用任何 TI 组件而
对 TI 及其代理造成的任何损失。
在某些场合中，为了推进安全相关应用有可能对 TI 组件进行特别的促销。TI 的目标是利用此类组件帮助客户设计和创立其特 有的可满足适用
的功能安全性标准和要求的终端产品解决方案。尽管如此，此类组件仍然服从这些条款。
TI 组件未获得用于 FDA Class III（或类似的生命攸关医疗设备）的授权许可，除非各方授权官员已经达成了专门管控此类使 用的特别协议。
只有那些 TI 特别注明属于军用等级或“增强型塑料”的 TI 组件才是设计或专门用于军事/航空应用或环境的。购买者认可并同 意，对并非指定面
向军事或航空航天用途的 TI 组件进行军事或航空航天方面的应用，其风险由客户单独承担，并且由客户独 力负责满足与此类使用相关的所有
法律和法规要求。
TI 已明确指定符合 ISO/TS16949 要求的产品，这些产品主要用于汽车。在任何情况下，因使用非指定产品而无法达到 ISO/TS16949 要
求，TI不承担任何责任。
产品
应用
数字音频
www.ti.com.cn/audio
通信与电信
www.ti.com.cn/telecom
放大器和线性器件
www.ti.com.cn/amplifiers
计算机及周边
www.ti.com.cn/computer
数据转换器
www.ti.com.cn/dataconverters
消费电子
www.ti.com/consumer-apps
DLP® 产品
www.dlp.com
能源
www.ti.com/energy
DSP - 数字信号处理器
www.ti.com.cn/dsp
工业应用
www.ti.com.cn/industrial
时钟和计时器
www.ti.com.cn/clockandtimers
医疗电子
www.ti.com.cn/medical
接口
www.ti.com.cn/interface
安防应用
www.ti.com.cn/security
逻辑
www.ti.com.cn/logic
汽车电子
www.ti.com.cn/automotive
电源管理
www.ti.com.cn/power
视频和影像
www.ti.com.cn/video
微控制器 (MCU)
www.ti.com.cn/microcontrollers
RFID 系统
www.ti.com.cn/rfidsys
OMAP应用处理器
www.ti.com/omap
无线连通性
www.ti.com.cn/wirelessconnectivity
德州仪器在线技术支持社区
www.deyisupport.com
IMPORTANT NOTICE
邮寄地址： 上海市浦东新区世纪大道1568 号，中建大厦32 楼邮政编码： 200122
Copyright © 2015, 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
24-Apr-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ISO7131CCDBQ
ACTIVE
SSOP
DBQ
16
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7131CC
ISO7131CCDBQR
ACTIVE
SSOP
DBQ
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7131CC
ISO7140CCDBQ
ACTIVE
SSOP
DBQ
16
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7140CC
ISO7140CCDBQR
ACTIVE
SSOP
DBQ
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7140CC
ISO7140FCCDBQ
ACTIVE
SSOP
DBQ
16
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7140FC
ISO7140FCCDBQR
ACTIVE
SSOP
DBQ
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7140FC
ISO7141CCDBQ
ACTIVE
SSOP
DBQ
16
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7141CC
ISO7141CCDBQR
ACTIVE
SSOP
DBQ
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7141CC
ISO7141FCCDBQ
ACTIVE
SSOP
DBQ
16
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7141FC
ISO7141FCCDBQR
ACTIVE
SSOP
DBQ
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7141FC
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Apr-2015
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Feb-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
ISO7131CCDBQR
SSOP
DBQ
16
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
ISO7140CCDBQR
SSOP
DBQ
16
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
ISO7140FCCDBQR
SSOP
DBQ
16
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
ISO7141CCDBQR
SSOP
DBQ
16
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
ISO7141FCCDBQR
SSOP
DBQ
16
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Feb-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ISO7131CCDBQR
SSOP
DBQ
16
2500
367.0
367.0
38.0
ISO7140CCDBQR
SSOP
DBQ
16
2500
367.0
367.0
38.0
ISO7140FCCDBQR
SSOP
DBQ
16
2500
367.0
367.0
38.0
ISO7141CCDBQR
SSOP
DBQ
16
2500
367.0
367.0
38.0
ISO7141FCCDBQR
SSOP
DBQ
16
2500
367.0
367.0
38.0
Pack Materials-Page 2
重要声明
德州仪器(TI) 及其下属子公司有权根据 JESD46 最新标准, 对所提供的产品和服务进行更正、修改、增强、改进或其它更改， 并有权根据
JESD48 最新标准中止提供任何产品和服务。客户在下订单前应获取最新的相关信息, 并验证这些信息是否完整且是最新的。所有产品的销售
都遵循在订单确认时所提供的TI 销售条款与条件。
TI 保证其所销售的组件的性能符合产品销售时 TI 半导体产品销售条件与条款的适用规范。仅在 TI 保证的范围内，且 TI 认为 有必要时才会使
用测试或其它质量控制技术。除非适用法律做出了硬性规定，否则没有必要对每种组件的所有参数进行测试。
TI 对应用帮助或客户产品设计不承担任何义务。客户应对其使用 TI 组件的产品和应用自行负责。为尽量减小与客户产品和应 用相关的风险，
客户应提供充分的设计与操作安全措施。
TI 不对任何 TI 专利权、版权、屏蔽作品权或其它与使用了 TI 组件或服务的组合设备、机器或流程相关的 TI 知识产权中授予 的直接或隐含权
限作出任何保证或解释。TI 所发布的与第三方产品或服务有关的信息，不能构成从 TI 获得使用这些产品或服 务的许可、授权、或认可。使用
此类信息可能需要获得第三方的专利权或其它知识产权方面的许可，或是 TI 的专利权或其它 知识产权方面的许可。
对于 TI 的产品手册或数据表中 TI 信息的重要部分，仅在没有对内容进行任何篡改且带有相关授权、条件、限制和声明的情况 下才允许进行
复制。TI 对此类篡改过的文件不承担任何责任或义务。复制第三方的信息可能需要服从额外的限制条件。
在转售 TI 组件或服务时，如果对该组件或服务参数的陈述与 TI 标明的参数相比存在差异或虚假成分，则会失去相关 TI 组件 或服务的所有明
示或暗示授权，且这是不正当的、欺诈性商业行为。TI 对任何此类虚假陈述均不承担任何责任或义务。
客户认可并同意，尽管任何应用相关信息或支持仍可能由 TI 提供，但他们将独力负责满足与其产品及在其应用中使用 TI 产品 相关的所有法
律、法规和安全相关要求。客户声明并同意，他们具备制定与实施安全措施所需的全部专业技术和知识，可预见 故障的危险后果、监测故障
及其后果、降低有可能造成人身伤害的故障的发生机率并采取适当的补救措施。客户将全额赔偿因 在此类安全关键应用中使用任何 TI 组件而
对 TI 及其代理造成的任何损失。
在某些场合中，为了推进安全相关应用有可能对 TI 组件进行特别的促销。TI 的目标是利用此类组件帮助客户设计和创立其特 有的可满足适用
的功能安全性标准和要求的终端产品解决方案。尽管如此，此类组件仍然服从这些条款。
TI 组件未获得用于 FDA Class III（或类似的生命攸关医疗设备）的授权许可，除非各方授权官员已经达成了专门管控此类使 用的特别协议。
只有那些 TI 特别注明属于军用等级或“增强型塑料”的 TI 组件才是设计或专门用于军事/航空应用或环境的。购买者认可并同 意，对并非指定面
向军事或航空航天用途的 TI 组件进行军事或航空航天方面的应用，其风险由客户单独承担，并且由客户独 力负责满足与此类使用相关的所有
法律和法规要求。
TI 已明确指定符合 ISO/TS16949 要求的产品，这些产品主要用于汽车。在任何情况下，因使用非指定产品而无法达到 ISO/TS16949 要
求，TI不承担任何责任。
产品
应用
数字音频
www.ti.com.cn/audio
通信与电信
www.ti.com.cn/telecom
放大器和线性器件
www.ti.com.cn/amplifiers
计算机及周边
www.ti.com.cn/computer
数据转换器
www.ti.com.cn/dataconverters
消费电子
www.ti.com/consumer-apps
DLP® 产品
www.dlp.com
能源
www.ti.com/energy
DSP - 数字信号处理器
www.ti.com.cn/dsp
工业应用
www.ti.com.cn/industrial
时钟和计时器
www.ti.com.cn/clockandtimers
医疗电子
www.ti.com.cn/medical
接口
www.ti.com.cn/interface
安防应用
www.ti.com.cn/security
逻辑
www.ti.com.cn/logic
汽车电子
www.ti.com.cn/automotive
电源管理
www.ti.com.cn/power
视频和影像
www.ti.com.cn/video
微控制器 (MCU)
www.ti.com.cn/microcontrollers
RFID 系统
www.ti.com.cn/rfidsys
OMAP应用处理器
www.ti.com/omap
无线连通性
www.ti.com.cn/wirelessconnectivity
德州仪器在线技术支持社区
www.deyisupport.com
IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2016, Texas Instruments Incorporated
