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ISO7220CDG4

ISO7220CDG4

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    SOIC8_150MIL

  • 描述:

    General Purpose Digital Isolator 2500Vrms 2 Channel 25Mbps 25kV/µs CMTI 8-SOIC (0.154", 3.90mm Width...

  • 数据手册
  • 价格&库存
ISO7220CDG4 数据手册
www.ti.com ISO7220A, ISO7220B, ISO7220C, ISO7220M, ISO7221A, ISO7221B, ISO7221C, ISO7221M ISO7220A, ISO7220B, ISO7220C, ISO7220M, ISO7221A, ISO7221B, ISO7221M SLLS755Q – JULY 2006 ISO7221C, – REVISED JANUARY 2021 SLLS755Q – JULY 2006 – REVISED JANUARY 2021 ISO722x Dual-Channel Digital Isolators 1 Features • • • • • • • • 1, 5, 25, and 150-Mbps Signaling Rate Options – Low Channel-to-Channel Output Skew; 1-ns Max – Low Pulse-Width Distortion (PWD); 1-ns Max – Low Jitter Content; 1 ns Typ at 150 Mbps 50 kV/μs Typical Transient Immunity Operates with 2.8-V (C-Grade), 3.3-V, or 5-V Supplies 4-kV ESD Protection High Electromagnetic Immunity –40°C to +125°C Operating Range Typical 28-Year Life at Rated Voltage (see High-Voltage Lifetime of the ISO72x Family of Digital Isolators and Isolation Capacitor Lifetime Projection) Safety-Related Certifications – VDE Basic Insulation with 4000-VPK VIOTM, 560 VPK VIORM per DIN VDE V 0884-11:2017-01 and DIN EN 61010-1 (VDE 0411-1) – 2500 VRMS Isolation per UL 1577 – CSA Approved for IEC 60950-1 and IEC 62368-1 2 Applications • • • • Industrial Fieldbus – Modbus – Profibus™ – DeviceNet™ Data Buses Computer Peripheral Interface Servo Control Interface Data Acquisition 3 Description The ISO7220x and ISO7221x family devices are dualchannel digital isolators. To facilitate PCB layout, the channels are oriented in the same direction in the ISO7220x and in opposite directions in the ISO7221x. These devices have a logic input and output buffer separated by TI’s silicon-dioxide (SiO2) isolation barrier, providing galvanic isolation of up to 4000 VPK per VDE. Used in conjunction with isolated power supplies, these devices block high voltage and isolate grounds, as well as prevent noise currents on a data bus or other circuits from entering the local ground and interfering with or damaging sensitive circuitry. isolation barrier. Across the isolation barrier, a differential comparator receives the logic transition information, then sets or resets a flip-flop and the output circuit accordingly. A periodic update pulse is sent across the barrier to ensure the proper dc level of the output. If this dc-refresh pulse is not received every 4 μs, the input is assumed to be unpowered or not being actively driven, and the failsafe circuit drives the output to a logic high state. The small capacitance and resulting time constant provide fast operation with signaling rates available from 0 Mbps (DC) to 150 Mbps (The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps). The Aoption, B-option, and C-option devices have TTL input thresholds and a noise filter at the input that prevents transient pulses from being passed to the output of the device. The M-option devices have CMOS VCC/2 input thresholds and do not have the input noise filter and the additional propagation delay. The ISO7220x and ISO7221x family of devices require two supply voltages of 2.8 V (C-Grade), 3.3 V, 5 V, or any combination. All inputs are 5-V tolerant when supplied from a 2.8-V or 3.3-V supply and all outputs are 4-mA CMOS. The ISO7220x and ISO7221x family of devices are characterized for operation over the ambient temperature range of –40°C to +125°C. Device Information (1) PART NUMBER PACKAGE ISO7220x SOIC (8) ISO7221x (1) BODY SIZE (NOM) 4.90 mm × 3.91 mm For all available packages, see the orderable addendum at the end of the data sheet. VCCI Isolation Capacitor VCCO INx OUTx GNDI GNDO VCCI and GNDI are supply and ground connections respectively for the input channels. VCCO and GNDO are supply and ground connections respectively for the output channels. Simplified Schematic A binary input signal is conditioned, translated to a balanced signal, then differentiated by the capacitive An©IMPORTANT NOTICEIncorporated at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, Copyright 2021 Texas Instruments Submit Document Feedback intellectual property matters and other important disclaimers. PRODUCTION DATA. 1 ISO7220A, ISO7220B, ISO7220C, ISO7220M, ISO7221A, ISO7221B, ISO7221C, ISO7221M SLLS755Q – JULY 2006 – REVISED JANUARY 2021 www.ti.com Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................6 6 Specifications.................................................................. 6 6.1 Absolute Maximum Ratings........................................ 6 6.2 ESD Ratings............................................................... 7 6.3 Recommended Operating Conditions.........................8 6.4 Thermal Information....................................................8 6.5 Power Ratings.............................................................8 6.6 Insulation Specifications............................................. 9 6.7 Safety-Related Certifications.................................... 10 6.8 Safety Limiting Values...............................................10 6.9 Electrical Characteristics—5-V VCC1 and VCC2 Supplies.......................................................................11 6.10 Electrical Characteristics—5-V VCC1 and 3.3-V VCC2 Supply.................................................................12 6.11 Electrical Characteristics—3.3-V VCC1 and 5-V VCC2 Supply.................................................................13 6.12 Electrical Characteristics—3.3-V VCC1 and VCC2 Supplies..............................................................14 6.13 Electrical Characteristics—2.8-V VCC1 and VCC2 Supplies..............................................................14 6.14 Switching Characteristics—5-V VCC1 and VCC2 Supplies.......................................................................16 6.15 Switching Characteristics—5-V VCC1 and 3.3-V VCC2 Supply.................................................................17 6.16 Switching Characteristics—3.3-VCC1 and 5-V VCC2 Supplies..............................................................18 6.17 Switching Characteristics—3.3-V VCC1 and VCC2 Supplies..............................................................19 6.18 Switching Characteristics—2.8-V VCC1 and VCC2 Supplies..............................................................19 6.19 Insulation Characteristics Curves........................... 20 6.20 Typical Characteristics............................................ 21 7 Parameter Measurement Information.......................... 23 8 Detailed Description......................................................25 8.1 Overview................................................................... 25 8.2 Functional Block Diagram......................................... 25 8.3 Feature Description...................................................26 8.4 Device Functional Modes..........................................26 9 Application and Implementation.................................. 27 9.1 Application Information............................................. 27 9.2 Typical Application.................................................... 27 10 Power Supply Recommendations..............................29 11 Layout........................................................................... 29 11.1 Layout Guidelines................................................... 29 11.2 Layout Example...................................................... 29 12 Device and Documentation Support..........................30 12.1 Device Support....................................................... 30 12.2 Documentation Support.......................................... 30 12.3 Related Links.......................................................... 30 12.4 Receiving Notification of Documentation Updates..30 12.5 Support Resources................................................. 30 12.6 Trademarks............................................................. 31 12.7 Electrostatic Discharge Caution..............................31 12.8 Glossary..................................................................31 13 Mechanical, Packaging, and Orderable Information.................................................................... 31 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision P (August 2018) to Revision Q (January 2021) Page • Removed nominal specifications in the RECOMMENDED OPERATING CONDITIONS table.......................... 8 Changes from Revision O (April 2017) to Revision P (August 2018) Page • Changed (VDE V 0884-10):2006-12 to DIN VDE V 0884-11:2017-01 throughout the document...................... 1 • Changed CSA Approved for Component Acceptance Notice 5A and IEC 60950-1 to CSA Approved for IEC 60950-1 and IEC 62368-1 throughout the document......................................................................................... 1 • Added the basic insulation working voltage for CSA in the Safety-Related Certifications table....................... 10 • Changed the VDE certification number from 40016131 to 40047657 in the Safety-Related Certifications table ..........................................................................................................................................................................10 • Changed the maximum propagation delay and pulse-width distortion in each Switching Characteristics table .. 16 • Added ± 10% for the VCC1 and VCC2 voltages in the condition statement of the Switching Characteristics—5-V VCC1 and VCC2 Supplies table ..........................................................................................................................16 • Changed ISO722x to ISO7220 for all part numbers for the Channel-to-channel output skew parameter in each Switching Characteristic table..................................................................................................................16 2 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated www.ti.com ISO7220A, ISO7220B, ISO7220C, ISO7220M, ISO7221A, ISO7221B, ISO7221C, ISO7221M SLLS755Q – JULY 2006 – REVISED JANUARY 2021 Changes from Revision N (September 2015) to Revision O (April 2017) Page • Changed the Dissipation Characteristics table to Power Ratings. Combined the DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 Insulation Characteristics table IEC Package Characteristics, and IEC 60664-1 Ratings Table in the Insulation Specifications table. Changed the Regulatory Information table to Safety-Related Certifications ...................................................................................................................................................... 8 • Deleted the maximum surge voltage, 4000 VPK for VDE in the Safety-Related Certifications table................ 10 • Changed the CSA information in the Safety-Related Certifications table.........................................................10 Changes from Revision M (October 2014) to Revision N (September 2015) Page • Changed the VDE Cerification from: DIN EN 60747-5-5 (VDE 0884-5) to: DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 throughout the document...................................................................................................... 1 • Updated the Simplified Schematic to a higher quality version............................................................................1 • Changed the max value of the IN and OUT voltage from 6 to VCC + 0.5 in the Absolute Maximum Ratings table.................................................................................................................................................................... 6 • Changed L(I01) MIN value from 4.8 to 4 in the IEC Package Characteristics table........................................... 9 • Added the JEDEC package dimensions note in the IEC Package Characteristics table................................... 9 • Changed L(I01) MIN value from 4.8 to 4 in the IEC Package Characteristics table........................................... 9 • Added the DTI parameter to the IEC Package Characteristics table..................................................................9 • Changed the DTI test condition From: IEC 60112 / VDE 0303 Part 1 To: DIN EN 60112 (VDE 0303-11); IEC 60112.................................................................................................................................................................. 9 • Added = 150°C to insulation resistance test condition in the DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 Insulation Characteristics table. .........................................................................................................................9 • Added table row with input side VCC = X to the ISO7220x or ISO7221x Function table.................................. 26 Changes from Revision L (January 2012) to Revision M (August 2014) Page • Changed the title of this data sheet to ISO722x Dual Channel Digital Isolators ................................................1 • Added Pin Configuration and Functions section, Handling Rating table, Dissipation Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section, changed Thermal Information table ........................................1 • Updated the Features section ............................................................................................................................1 • Added per VDE to 4000 VPK in second sentence of Description .......................................................................1 • Updated the Regulatory Information Table......................................................................................................... 6 • Added the min and max values to the Storage temperature parameter in the Absolute Maximum Ratings table.................................................................................................................................................................... 6 • Changed in ROC table Max col, VIH row from VCC to 5.5 .................................................................................8 • Changed the L(I01) parameter name to external clearance (CLR) and L(I02) to external creepage (CPG). Also changed the input-to-output test voltage (VPR) parameter name to apparent charge (qpd) .......................9 • Changed the Device Options table, Input Threshold column from ≠ symbol to ~ symbol 6 places ................. 26 • Changed Isolation Glossary .............................................................................................................................30 Changes from Revision K (January 2010) to Revision L (January 2012) Page • Changed Feature From: Operates with 3.3-V or 5-V Supplies To: Operates with 2.8-V (C-Grade), 3.3-V or 5-V Supplies.............................................................................................................................................................. 1 • Changed Feature From: 4000-Vpeak Isolation, 560 Vpeak VIORM To: 4000-VPK VIOTM, 560 VPK VIORM per IEC 60747-5-2 (VDE 0884, Rev2) ............................................................................................................................ 1 • Added device options to VCC in the RECOMMENDED OPERATING CONDITIONS table................................ 8 • Changed Note: (1) in the RECOMMENDED OPERATING CONDITIONS table................................................ 8 • Changed the CTI MIN value From: ≥175 V To: ≥400 V...................................................................................... 9 • Updated the Regulatory Information table........................................................................................................ 10 • Changed ICC1 and ICC2 test conditions in the 5-V table.................................................................................... 11 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 3 ISO7220A, ISO7220B, ISO7220C, ISO7220M, ISO7221A, ISO7221B, ISO7221C, ISO7221M SLLS755Q – JULY 2006 – REVISED JANUARY 2021 • • • • • • • • • • www.ti.com Changed Table Note: (1)...................................................................................................................................11 Changed ICC1 and ICC2 test conditions in the VCC1 at 5 V, VCC2 at 3.3 V table.................................................12 Changed Table Note: (1)...................................................................................................................................12 Changed ICC1 and ICC2 test conditions in the VCC1 at 3.3 V, VCC2 at 5 V table.................................................13 Changed Table Note (1)....................................................................................................................................13 Changed ICC1 and ICC2 test conditions in the VCC1 and VCC2 at 3.3 V table.....................................................14 Changed Table Note (1)....................................................................................................................................14 Added ELECTRICAL and Switching CHARACTERISTICS table for VCC1 and VCC2 at 2.8 V (ISO722xC-Only) ..........................................................................................................................................................................14 Changed VCC Undervoltage Threshold vs Free-Air Temperature ....................................................................21 Changed Failsafe Delay Time Test Circuit and Voltage Waveforms ............................................................... 23 Changes from Revision J (May 2009) to Revision K () Page • Changed the RECOMMENDED OPERATING CONDITIONS so that Note (2) is associated with all device options in the Input pulse width and Signaling rate............................................................................................ 8 • Changed Note (2) From: Typical signaling rate under ideal conditions at 25°C. To: Typical signaling rate and Input pulse width are measured at ideal conditions at 25°C...............................................................................8 • Changed column 2 of the AVAILABLE OPTIONS table From: Signaling Rate To: Max Signaling Rate........... 26 Changes from Revision I (December 2008) to Revision J () Page • Changed ISO7221C Marked As column From: TI7221C To: I7221C in the AVAILABLE OPTIONS table....... 26 Changes from Revision H (May 2008) to Revision I () Page • Added "IEC 61010-1, IEC 60950-1 and CSA Approved" to the UL 1577 FEATURES bullet..............................1 Changes from Revision G (March 2008) to Revision H () Page • Added Note: (1) to the RECOMMENDED OPERATING CONDITIONS table.................................................... 8 • Added Note: (1) to the ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 5-V table................................11 • Added Note: (1) to the ELECTRICAL CHARACTERISTICS: VCC1 at 5 V, VCC2 at 3.3 V table........................ 12 • Added Note (1): to the ELECTRICAL CHARACTERISTICS: VCC1 at 3.3 V, VCC2 at 5 V table........................ 13 • Added Note (1): to the ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 3.3 V..................................... 14 Changes from Revision F (August 2007) to Revision G () Page • Added Part Numbers ISO7220B and ISO7221B to the data sheet.................................................................... 1 • Added 5-Mbps Signaling rate to the FEATURES list.......................................................................................... 1 • Added Part Numbers ISO7220B and ISO7221B to the ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 5-V table............................................................................................................................................................11 • Added Part Numbers ISO7220B and ISO7221B to the ELECTRICAL CHARACTERISTICS: VCC1 at 5 V, VCC2 at 3.3 V table.....................................................................................................................................................12 • Added Part Numbers ISO7220B and ISO7221B to the ELECTRICAL CHARACTERISTICS: VCC1 at 3.3 V, VCC2 at 5 V table...............................................................................................................................................13 • Added Part Numbers ISO7220B and ISO7221B to the ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 3.3 V................................................................................................................................................................. 14 • Added PROPAGATION DELAY vs FREE-AIR TEMPERATURE, ISO722xB, Propagation Delay vs Free-Air Temperature, ISO722xB .................................................................................................................................. 21 • Added Part Numbers ISO7220B and ISO7221B to the AVAILABLE OPTIONS table...................................... 26 Changes from Revision E (July 2007) to Revision F () Page • Added tsk(pp) footnote to the SWITCHING CHARACTERISTICS: VCC1 and VCC2 at 5-V OPERATION table.. 16 • Added tsk(o) footnote to the SWITCHING CHARACTERISTICS: VCC1 and VCC2 at 5-V OPERATION table.... 16 4 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated www.ti.com • • • • • • • ISO7220A, ISO7220B, ISO7220C, ISO7220M, ISO7221A, ISO7221B, ISO7221C, ISO7221M SLLS755Q – JULY 2006 – REVISED JANUARY 2021 Added tsk(pp) footnote to the SWITCHING CHARACTERISTICS: VCC1 at 5 V, VCC2 at 3.3 V OPERATION table ..........................................................................................................................................................................17 Added tsk(o) footnote to the SWITCHING CHARACTERISTICS: VCC1 at 5 V, VCC2 at 3.3 V OPERATION table ..........................................................................................................................................................................17 Added tsk(pp) footnote to the SWITCHING CHARACTERISTICS: VCC1 at 3.3 V, VCC2 at 5 V OPERATION table ..........................................................................................................................................................................18 Added tsk(o) footnote to the SWITCHING CHARACTERISTICS: VCC1 at 3.3 V, VCC2 at 5 V OPERATION table ..........................................................................................................................................................................18 Added tsk(pp) footnote to the SWITCHING CHARACTERISTICS table.............................................................19 Changed 3.3-VRMS Supply Current vs Signaling Rate - Re-scaled the Y-axis..................................................21 Changed 5-VRMS Supply Current vs Signaling Rate - New Curves..................................................................21 Changes from Revision D (June 2007) to Revision E () Page • Changed 3.3-VRMS Supply Current vs Signaling Rate - New Curves...............................................................21 • Changed 5-VRMS Supply Current vs Signaling Rate - Re-scaled the Y-axis ....................................................21 Changes from Revision C (May 2007) to Revision D () Page • Changed Typical ISO7220x Circuit Hook-Up - Pin 2 (INA) label From: OUTPUT to INPUT............................ 28 Changes from Revision B (May 2007) to Revision C () Page • Added the Signaling rate values to the RECOMMENDED OPERATING CONDITIONS table...........................8 • Changed the IEC 60664-1 RATINGS TABLE - Specification I-III test conditions From: Rated mains voltage ≤150 VRMS To: Rated mains voltage ≤300 VRMS. Added a row for the I-II specifications............................... 9 • Added ISO722xM Jitter vs Signaling Rate cross reference to the Peak-to-peak eye-pattern jitter of the SWITCHING CHARACTERISTICS table......................................................................................................... 16 • Added Time-Dependent Dielectric Breakdown Test Results ........................................................................... 28 Changes from Revision A (August 2006) to Revision B () Page • Added the TYPICAL CHARACTERISTIC CURVES to the data sheet............................................................. 21 • Added the PARAMETER MEASUREMENT INFORMATION to the data sheet................................................23 • Added the APPLICATION INFORMATION section to the data sheet...............................................................27 • Added the ISOLATION GLOSSARY section to the data sheet ........................................................................30 Changes from Revision * (July 2006) to Revision A () Page • Deleted "and CSA Apporved" from the UL 1577 FEATURES bullet...................................................................1 • Added option A to the AVAILABLE OPTIONS table......................................................................................... 26 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 5 ISO7220A, ISO7220B, ISO7220C, ISO7220M, ISO7221A, ISO7221B, ISO7221C, ISO7221M www.ti.com SLLS755Q – JULY 2006 – REVISED JANUARY 2021 5 Pin Configuration and Functions INA 2 INB 3 8 VCC2 ISOLATION VCC1 1 7 OUTA 6 OUTB 5 GND2 GND1 4 Figure 5-1. ISO7220x D Package 8-Pin SOIC Top View OUTA 2 INB 3 8 VCC2 ISOLATION VCC1 1 GND1 4 7 INA 6 OUTB 5 GND2 Figure 5-2. ISO7221x D Package 8-Pin SOIC Top View Table 5-1. Pin Functions PIN NAME ISO7220x ISO7221x INA 2 7 INB 3 GND1 4 GND2 OUTA I/O DESCRIPTION I Input, channel A 3 I Input, channel B 4 — Ground connection for VCC1 5 5 — Ground connection for VCC2 7 2 O Output, channel A OUTB 6 6 O Output, channel B VCC1 1 1 — Power supply, VCC1 VCC2 8 8 — Power supply, VCC2 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VCC Supply voltage(2), VCC1, VCC2 –0.5 6 V VI Voltage at IN, OUT –0.5 VCC + 0.5(3) V –15 IO Output current TJ Maximum junction temperature Tstg Storage temperature (1) (2) (3) 6 –65 15 mA 170 °C 150 °C Stresses beyond those listed under Absolute Maximum Ratings can cause permanent damage to the device. These ratings are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods can affect device reliability. All voltage values except differential I/O bus voltages are with respect to network ground pin and are peak voltage values. Maximum voltage must not exceed 6 V. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated www.ti.com ISO7220A, ISO7220B, ISO7220C, ISO7220M, ISO7221A, ISO7221B, ISO7221C, ISO7221M SLLS755Q – JULY 2006 – REVISED JANUARY 2021 6.2 ESD Ratings Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all V(ESD) (1) (2) Electrostatic discharge pins(1) VALUE UNIT ±4000 V Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±1000 V Machine Model, ANSI/ESDS5.2-1996 ±200 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 7 ISO7220A, ISO7220B, ISO7220C, ISO7220M, ISO7221A, ISO7221B, ISO7221C, ISO7221M www.ti.com SLLS755Q – JULY 2006 – REVISED JANUARY 2021 6.3 Recommended Operating Conditions MIN VCC Supply voltage(2), VCC1, VCC2 IOH High-level output current IOL Low-level output current ISO722xA, ISO722xB, ISO722xM ISO722xC 5.5 2.8 5.5 UNIT V mA 4 Signaling rate(1) 1/tui MAX –4 Input pulse width(1) tui NOM 3 ISO722xA 1 ISO722xB 200 ISO722xC 40 ISO722xM 6.67 ISO722xA 0 1000 ISO722xB 0 5 ISO722xC 0 25 ISO722xM 0 150 mA μs ns kbps Mbps VIH High-level input voltage ISO722xA, ISO722xB, ISO722xC 2 5.5 V VIL Low-level input voltage ISO722xA, ISO722xB, ISO722xC 0 0.8 V VIH High-level input voltage ISO722xM 0.7 VCC VCC V VIL Low-level input voltage ISO722xM 0 0.3 VCC V TJ Junction temperature –40 150 °C H External magnetic field-strength immunity per IEC 61000-4-8 and IEC 61000-4-9 certification 1000 A/m (1) (2) Typical signaling rate and Input pulse width are measured at ideal conditions at 25°C. For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V. For the 3.3-V operation, VCC1 or VCC2 is specified from 3 V to 3.6 V. For the 2.8-V operation, VCC1 or VCC2 is specified at 2.8 V. 6.4 Thermal Information ISO7220x ISO7221x THERMAL METRIC(1) UNIT D (SOIC) 8 PINS RθJA Junction-to-ambient thermal resistance Low-K Thermal Resistance(2) 212 High-K Thermal Resistance °C/W 122 RθJC(top) Junction-to-case (top) thermal resistance 69.1 °C/W RθJB Junction-to-board thermal resistance 47.7 °C/W ψJT Junction-to-top characterization parameter 15.2 °C/W ψJB Junction-to-board characterization parameter 47.2 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance — °C/W (1) (2) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Tested in accordance with the Low-K or High-K thermal metric definitions of EIA/JESD51-3 for leaded surface mount packages. 6.5 Power Ratings VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF, Input a 150 Mbps 50% duty cycle square wave PARAMETER PD 8 Device power dissipation, ISO722xM Submit Document Feedback TEST CONDITIONS MIN TYP MAX UNIT 390 mW Copyright © 2021 Texas Instruments Incorporated ISO7220A, ISO7220B, ISO7220C, ISO7220M, ISO7221A, ISO7221B, ISO7221C, ISO7221M www.ti.com SLLS755Q – JULY 2006 – REVISED JANUARY 2021 6.6 Insulation Specifications PARAMETER TEST CONDITIONS VALUE UNIT GENERAL CLR External clearance(1) Shortest terminal-to-terminal distance through air 4 mm CPG External creepage(1) Shortest terminal-to-terminal distance across the package surface 4 mm DTI Distance through the insulation Minimum internal gap (internal clearance) 0.008 mm CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112 400 V Rated mains voltage ≤150 VRMS I-IV Rated mains voltage ≤300 VRMS I-III Rated mains voltage ≤400 VRMS I-II Material group Overvoltage category DIN VDE V II 0884-11:2017-01(2) VIORM Maximum repetitive peak isolation voltage AC voltage (bipolar) VIOTM Maximum transient isolation voltage qpd Apparent charge(3) Barrier capacitance, input to output(4) CIO Isolation resistance, input to output(4) RIO VTEST = VIOTM t = 60 s (qualification), t = 1 s (100% production) 560 VPK 4000 VPK Method a: After I/O safety test subgroup 2/3, Vini = VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM , tm = 10 s ≤5 Method a: After environmental tests subgroup 1, Vini = VIOTM, tini = 60 s; Vpd(m) = 1.3 × VIORM, tm = 10 s ≤5 Method b1: At routine test (100% production) and preconditioning (type test) Vini = VIOTM, tini = 1 s; Vpd(m) = 1.5 × VIORM, tm = 1 s ≤5 VIO = 0.4 sin (4E6πt) 1 VIO = 500 V, TA = 25°C >1012 VIO = 500 V, 100°C ≤ TA ≤ 125°C >1011 VIO = 500 V at TS = 150°C >109 Pollution degree 2 Climatic category 40/125/21 pC pF Ω UL 1577 VISO (1) (2) (3) (4) Withstand isolation voltage VTEST = VISO = 2500 VRMS, t = 60 s (qualification); VTEST = 1.2 × VISO = 3000 VRMS, t = 1 s (100% production) 2500 VRMS Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications. This coupler is suitable for basic electrical insulation only within the maximum operating ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits. Apparent charge is electrical discharge caused by a partial discharge (pd). All pins on each side of the barrier tied together creating a two-terminal device Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 9 ISO7220A, ISO7220B, ISO7220C, ISO7220M, ISO7221A, ISO7221B, ISO7221C, ISO7221M www.ti.com SLLS755Q – JULY 2006 – REVISED JANUARY 2021 6.7 Safety-Related Certifications VDE CSA UL Certified according to DIN VDE V 0884-11:2017-01 and DIN EN 61010-1 (VDE 0411-1):2011-07 Certified according to IEC 60950-1 and IEC 62368-1 Recognized under UL 1577 Component Recognition Program Basic Insulation Maximum Transient Overvoltage, 4000 VPK; Maximum Repetitive Peak Isolation Voltage, 560 VPK 2000 VRMS Isolation rating 400 VRMS Basic insulation and 148 VRMS Reinforced insulation working voltage per CSA 60950-1-07+A1+A2 and IEC 60950-1 2nd Ed. +A1+A2. 300 VRMS Basic insulation working voltage per CSA 62369-1-14 and IEC 62368-1:2014 Ed. 2. Single protection, 2500 VRMS Certificate number: 40047657 Master contract number: 220991 File number: E181974 6.8 Safety Limiting Values Safety limiting(1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier, potentially leading to secondary system failures. PARAMETER IS TS (1) 10 Safety input, output, or supply current Safety temperature TEST CONDITIONS MIN TYP MAX RθJA = 212°C/W, VI = 5.5 V, TJ = 170°C, TA = 25°C, see Figure 6-1 124 RθJA = 212°C/W, VI = 3.6 V, TJ = 170°C, TA = 25°C, see Figure 6-1 190 UNIT mA 150 °C The safety-limiting constraint is the maximum junction temperature specified in the data sheet. The power dissipation and junction-toair thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junctionto-air thermal resistance in the Section 6.4 table is that of a device installed on a high-K test board for leaded surface-mount packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated ISO7220A, ISO7220B, ISO7220C, ISO7220M, ISO7221A, ISO7221B, ISO7221C, ISO7221M www.ti.com SLLS755Q – JULY 2006 – REVISED JANUARY 2021 6.9 Electrical Characteristics—5-V VCC1 and VCC2 Supplies VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted.) PARAMETER TEST CONDITIONS MIN ISO7220x quiescent, VI = VCC or 0 V, no load ICC1 VCC1 supply current VCC2 supply current VOH High-level output voltage VOL Low-level output voltage VI(HYS) Input voltage hysteresis IIH High-level input current 1 2 8.5 17 ISO7220A and ISO7220B 1 Mbps, 0.5-MHz input clock signal, no load 2 3 10 18 4 9 ISO7221C and ISO7221M 25 Mbps, 12.5-MHz input clock signal, no load 12 22 ISO7220x quiescent, VI = VCC or 0 V, no load 16 31 ISO7221x quiescent, VI = VCC or 0 V, no load 8.5 17 ISO7220A and ISO7220B 1 Mbps, 0.5-MHz input clock signal, no load 17 32 ISO7221A, ISO7221B 1 Mbps, 0.5-MHz input clock signal, no load 10 18 ISO7220C, ISO7220M 25 Mbps, 12.5-MHz input clock signal, no load 20 34 ISO7221C and ISO7221M 25 Mbps, 12.5-MHz input clock signal, no load 12 22 mA VCC – 0.8 4.6 VCC – 0.1 5 V IOL = 4 mA, See Figure 7-1 0.2 0.4 IOL = 20 μA, See Figure 7-1 0 0.1 150 IN from 0 V to VCC Low-level input current IN from 0 V to VCC IN at VCC, VI = 0.4 sin (4E6πt) CMTI Common-mode transient immunity VI = VCC or 0 V, See Figure 7-3 mA mA IOH = –20 μA, See Figure 7-1 Input capacitance to ground mA mA IOH = –4 mA, See Figure 7-1 CI UNIT mA ISO7221A, ISO7221B 1 Mbps, 0.5-MHz input clock signal, no load IIL Copyright © 2021 Texas Instruments Incorporated MAX ISO7221 quiescent, VI = VCC or 0 V, no load ISO7220C, ISO7220M 25 Mbps, 12.5-MHz input clock signal, no load ICC2 TYP mV 10 –10 25 V μA μA 1 pF 50 kV/μs Submit Document Feedback 11 ISO7220A, ISO7220B, ISO7220C, ISO7220M, ISO7221A, ISO7221B, ISO7221C, ISO7221M www.ti.com SLLS755Q – JULY 2006 – REVISED JANUARY 2021 6.10 Electrical Characteristics—5-V VCC1 and 3.3-V VCC2 Supply VCC1 at 5 V ± 10%, VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted.) PARAMETER ICC1 ICC2 VOH VOL VCC1 supply current VCC2 supply current High-level output voltage Low-level output voltage VI(HYS) Input voltage hysteresis IIH High-level input current TYP MAX ISO7220x quiescent, VI = VCC or 0 V, no load TEST CONDITIONS 1 2 ISO7221x quiescent, VI = VCC or 0 V, no load 8.5 17 ISO7220A and ISO7220B 1 Mbps, 0.5-MHz input clock signal, no load 2 3 ISO7221A and ISO7221B 1 Mbps, 0.5-MHz input clock signal, no load 10 18 ISO7220C and ISO7220M 25 Mbps, 12.5-MHz input clock signal, no load 4 9 ISO7221C and ISO7221M 25 Mbps, 12.5-MHz input clock signal, no load 12 22 8 18 4.3 9.5 ISO7220A and ISO7220B 1 Mbps, 0.5-MHz input clock signal, no load 9 19 ISO7221A and ISO7221B 1 Mbps, 0.5-MHz input clock signal, no load 5 11 ISO7220C and ISO7220M 25 Mbps, 12.5-MHz input clock signal, no load 10 20 ISO7221C and ISO7221M 25 Mbps, 12.5-MHz input clock signal, no load 6 12 ISO7221x (5-V side), IOH = –4 mA, See Figure 7-1 VCC – 0.8 All devices, IOH = –20 μA, See Figure 7-1 VCC – 0.1 V IOL = 4 mA, See Figure 7-1 0.4 IOL = 20 μA, See Figure 7-1 0.1 150 IN from 0 V to VCC IN from 0 V to VCC IN at VCC, VI = 0.4 sin (4E6πt) CMTI Common-mode transient immunity VI = VCC or 0 V, See Figure 7-3 Submit Document Feedback mA VCC – 0.4 Low-level input current mA mA ISO7220x, ISO7221x (3.3-V side), IOH = –4 mA, See Figure 7-1 Input capacitance to ground mA mA ISO7221x quiescent, VI = VCC or 0 V, no load CI UNIT mA ISO7220x quiescent, VI = VCC or 0 V, no load IIL 12 MIN mV 10 –10 15 V μA μA 1 pF 40 kV/μs Copyright © 2021 Texas Instruments Incorporated ISO7220A, ISO7220B, ISO7220C, ISO7220M, ISO7221A, ISO7221B, ISO7221C, ISO7221M www.ti.com SLLS755Q – JULY 2006 – REVISED JANUARY 2021 6.11 Electrical Characteristics—3.3-V VCC1 and 5-V VCC2 Supply VCC1 at 3.3 V ± 10%, VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted.) PARAMETER ICC1 ICC2 VOH VCC1 supply current VCC2 supply current High-level output voltage VOL Low-level output voltage VI(HYS) Input threshold voltage hysteresis IIH High-level input current TYP MAX ISO7220x quiescent, VI = VCC or 0 V, no load TEST CONDITIONS 0.6 1 ISO7221x quiescent, VI = VCC or 0 V, no load 4.3 9.5 ISO7220A and ISO7220B 1 Mbps, 0.5-MHz input clock signal, no load 1 2 ISO7221A and ISO7221B 1 Mbps, 0.5-MHz input clock signal, no load 5 11 ISO7220C and ISO7220M 25 Mbps, 12.5-MHz input clock signal, no load 2 4 ISO7221C and ISO7221M 25 Mbps, 12.5-MHz input clock signal, no load 6 12 ISO7220x quiescent, VI = VCC or 0 V, no load 16 31 ISO7221x quiescent, VI = VCC or 0 V, no load 8.5 17 ISO7220A and ISO7220B 1 Mbps, 0.5-MHz input clock signal, no load 18 32 ISO7221A and ISO7221B 1 Mbps, 0.5-MHz input clock signal, no load 10 18 ISO7220C and ISO7220M 25 Mbps, 12.5-MHz input clock signal, no load 20 34 ISO7221C and ISO7221M 25 Mbps, 12.5-MHz input clock signal, no load 12 22 mA VCC – 0.4 All devices, IOH = –20 μA, See Figure 7-1 VCC – 0.1 V IOL = 4 mA, See Figure 7-1 0.4 IOL = 20 μA, See Figure 7-1 0 0.1 150 IN from 0 V or VCC Low-level input current IN from 0 V or VCC IN at VCC, VI = 0.4 sin (4E6πt) CMTI Common-mode transient immunity VI = VCC or 0 V, See Figure 7-3 mA mA ISO7221x (3.3-V side), IOH = –4 mA, See Figure 7-1 Input capacitance to ground mA mA VCC – 0.8 CI UNIT mA ISO7220x and ISO7221x (5-V side), IOH = –4 mA, See Figure 7-1 IIL Copyright © 2021 Texas Instruments Incorporated MIN mV 10 –10 15 μA μA 1 pF 40 kV/μs Submit Document Feedback 13 ISO7220A, ISO7220B, ISO7220C, ISO7220M, ISO7221A, ISO7221B, ISO7221C, ISO7221M www.ti.com SLLS755Q – JULY 2006 – REVISED JANUARY 2021 6.12 Electrical Characteristics—3.3-V VCC1 and VCC2 Supplies VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted.)(1) PARAMETER ICC1 VCC2 supply current ICC2 VCC2 supply current TYP MAX ISO7220x quiescent, VI = VCC or 0 V, no load TEST CONDITIONS 0.6 1 ISO7221x quiescent, VI = VCC or 0 V, no load 4.3 9.5 ISO7220A and ISO7220B 1 Mbps, 0.5-MHz input clock signal, no load 1 2 ISO7221A and ISO7221B 1 Mbps, 0.5-MHz input clock signal, no load 5 11 ISO7220C and ISO7220M 25 Mbps, 12.5-MHz input clock signal, no load 2 4 ISO7221C and ISO7221M 25 Mbps, 12.5-MHz input clock signal, no load 6 12 8 18 4.3 9.5 ISO7220A and ISO7220B 1 Mbps, 0.5-MHz input clock signal, no load 9 19 ISO7221A and ISO7221B 1 Mbps, 0.5-MHz input clock signal, no load 5 11 ISO7220C and ISO7220M 25 Mbps, 12.5-MHz input clock signal, no load 10 20 ISO7221C and ISO7221M 25 Mbps, 12.5-MHz input clock signal, no load 6 12 mA IOH = –4 mA, See Figure 7-1 VCC – 0.4 3 VCC – 0.1 3.3 Low-level output voltage VI(HYS) Input voltage hysteresis IIH High-level input current IN from 0 V or VCC IIL Low-level input current IN from 0 V or VCC CI Input capacitance to ground IN at VCC, VI = 0.4 sin (4E6πt) CMTI Common-mode transient immunity VI = VCC or 0 V, See Figure 7-3 mA mA IOH = –20 μA, See Figure 7-1 VOL mA mA ISO7220x quiescent, VI = VCC or 0 V, no load High-level output voltage UNIT mA ISO7221x quiescent, VI = VCC or 0 V, no load VOH (1) MIN IOL = 4 mA, See Figure 7-1 IOL = 20 μA, See Figure 7-1 0.2 0.4 0 0.1 150 mV 10 –10 15 V μA μA 1 pF 40 kV/μs For the 3.3-V operation, VCC1 or VCC2 is specified from 3 V to 3.6 V. 6.13 Electrical Characteristics—2.8-V VCC1 and VCC2 Supplies VCC1 and VCC2 at 2.8 V (over recommended operating conditions unless otherwise noted.) 2.8-V operation is only specified for ISO722xC with production screening starting in January 2012. The first two digits of the Lot Trace Code (YMSLLLLG4) written on top of each device can be used to identify year and month of production respectively. PARAMETER ICC1 ICC2 VOH VCC1 supply current VCC2 supply current High-level output voltage TYP MAX ISO7220C quiescent, VI = VCC or 0 V, no load TEST CONDITIONS 0.4 0.9 ISO7221C quiescent, VI = VCC or 0 V, no load 3.7 7.5 ISO7220C 25 Mbps, 12.5-MHz input clock signal, no load 1.5 3.5 ISO7221C 25 Mbps, 12.5-MHz input clock signal, no load 4.5 10 ISO7220C quiescent, VI = VCC or 0 V, no load 6.8 15 ISO7221C quiescent, VI = VCC or 0 V, no load 3.7 7.5 ISO7220C 25 Mbps, 12.5-MHz input clock signal, no load 9 17 ISO7221C 25 Mbps, 12.5-MHz input clock signal, no load 4.5 10 IOH = –4 mA, See Figure 7-1 VCC – 0.6 IOH = –20 μA, See Figure 7-1 VCC – 0.1 IOL = 4 mA, See Figure 7-1 VOL Low-level output voltage VI(HYS) Input voltage hysteresis IIH High-level input current IN from 0 V or VCC IIL Low-level input current IN from 0 V or VCC 14 Submit Document Feedback MIN IOL = 20 μA, See Figure 7-1 mA mA mA mA 2.55 2.8 0.25 0.6 0 0.1 150 V mV 10 –10 UNIT μA μA Copyright © 2021 Texas Instruments Incorporated ISO7220A, ISO7220B, ISO7220C, ISO7220M, ISO7221A, ISO7221B, ISO7221C, ISO7221M www.ti.com SLLS755Q – JULY 2006 – REVISED JANUARY 2021 VCC1 and VCC2 at 2.8 V (over recommended operating conditions unless otherwise noted.) 2.8-V operation is only specified for ISO722xC with production screening starting in January 2012. The first two digits of the Lot Trace Code (YMSLLLLG4) written on top of each device can be used to identify year and month of production respectively. PARAMETER TEST CONDITIONS CI Input capacitance to ground IN at VCC, VI = 0.4 sin (4E6πt) CMTI Common-mode transient immunity VI = VCC or 0 V, See Figure 7-3 Copyright © 2021 Texas Instruments Incorporated MIN 10 TYP MAX UNIT 1 pF 30 kV/μs Submit Document Feedback 15 ISO7220A, ISO7220B, ISO7220C, ISO7220M, ISO7221A, ISO7221B, ISO7221C, ISO7221M www.ti.com SLLS755Q – JULY 2006 – REVISED JANUARY 2021 6.14 Switching Characteristics—5-V VCC1 and VCC2 Supplies VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted.) PARAMETER TEST CONDITIONS tPLH, tPHL Propagation delay PWD Pulse-width distortion |tPHL – tPLH|(1) tPLH, tPHL Propagation delay tPLH|(1) PWD Pulse-width distortion |tPHL – tPLH, tPHL Propagation delay PWD Pulse-width distortion |tPHL – tPLH|(1) tPLH, tPHL Propagation delay PWD Pulse-width distortion |tPHL – tPLH|(1) tsk(pp) Part-to-part skew (2) ISO722xA, see Figure 7-1 ISO722xB, see Figure 7-1 ISO722xC, see Figure 7-1 MIN TYP MAX UNIT 280 405 600 ns 1 18 ns 42 55 70 ns 1 3 ns 22 32 42 ns 1 2 ns 10 16 ns 0.5 1 ns 6 ISO722xM, see Figure 7-1 ISO722xA 180 ISO722xB 17 ISO722xC 10 ISO722xM tsk(o) Channel-to-channel output skew (3) tr Output signal rise time tf Output signal fall time tfs Failsafe output delay time from input power loss tjit(pp) Peak-to-peak eye-pattern jitter (1) (2) (3) 16 ns 3 ISO7220A 3 15 ISO7220B 0.6 3 ISO7220C, ISO7220M 0.2 1 ns 1 ns 1 ns See Figure 7-2 3 μs ISO722xM, 150 Mbps PRBS NRZ data, 5-bit max same polarity input, both channels, See Figure 7-4, Figure 6-13 1 ISO722xM, 150 Mbps unrestricted bit run length data input, both channels, See Figure 7-4 2 See Figure 7-1 ns Also referred to as pulse skew. tsk(pp) is the magnitude of the difference in propagation delay times between any specified pins of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical specified loads. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated ISO7220A, ISO7220B, ISO7220C, ISO7220M, ISO7221A, ISO7221B, ISO7221C, ISO7221M www.ti.com SLLS755Q – JULY 2006 – REVISED JANUARY 2021 6.15 Switching Characteristics—5-V VCC1 and 3.3-V VCC2 Supply VCC1 at 5 V ± 10%, VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted.) PARAMETER TEST CONDITIONS tPLH, tPHL Propagation delay PWD Pulse-width distortion |tPHL – tPLH|(1) tPLH, tPHL Propagation delay |(1) PWD Pulse-width distortion |tPHL – tPLH tPLH, tPHL Propagation delay PWD Pulse-width distortion |tPHL – tPLH|(1) tPLH, tPHL Propagation delay PWD Pulse-width distortion |tPHL – tPLH|(1) tsk(pp) Part-to-part skew (2) ISO722xA, see Figure 7-1 ISO722xB, see Figure 7-1 ISO722xC, see Figure 7-1 ISO722xM, see Figure 7-1 MIN TYP MAX UNIT 285 410 585 ns 1 18 ns 45 58 75 ns 1 3 ns 25 36 48 ns 1 2 ns 12 20 ns 0.5 1 ns 7 ISO722xA 180 ISO722xB 17 ISO722xC 10 ISO722xM tsk(o) Channel-to-channel output skew (3) tr Output signal rise time tf Output signal fall time tfs Failsafe output delay time from input power loss tjit(pp) (1) (2) (3) Peak-to-peak eye-pattern jitter ns 5 ISO7220A 3 15 ISO7220B 0.6 3 ISO7220C, ISO7220M 0.2 1 ns 2 ns 2 ns See Figure 7-2 3 μs ISO722xM, 150 Mbps PRBS NRZ data, 5-bit max same polarity input, both channels, See Figure 7-4, Figure 6-13 1 ISO722xM, 150 Mbps unrestricted bit run length data input, both channels, See Figure 7-4 2 See Figure 7-1 ns Also referred to as pulse skew. tsk(pp) is the magnitude of the difference in propagation delay times between any specified pins of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical specified loads. Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 17 ISO7220A, ISO7220B, ISO7220C, ISO7220M, ISO7221A, ISO7221B, ISO7221C, ISO7221M www.ti.com SLLS755Q – JULY 2006 – REVISED JANUARY 2021 6.16 Switching Characteristics—3.3-VCC1 and 5-V VCC2 Supplies VCC1 at 3.3 V ± 10%, VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted.) PARAMETER TEST CONDITIONS tPLH, tPHL Propagation delay PWD Pulse-width distortion |tPHL – tPLH|(1) tPLH, tPHL Propagation delay tPLH|(1) PWD Pulse-width distortion |tPHL – tPLH, tPHL Propagation delay PWD Pulse-width distortion |tPHL – tPLH|(1) tPLH, tPHL Propagation delay PWD Pulse-width distortion |tPHL – tPLH|(1) tsk(pp) Part-to-part skew (2) ISO722xA, see Figure 7-1 ISO722xB, see Figure 7-1 ISO722xC, see Figure 7-1 MIN TYP MAX UNIT 285 395 605 ns 1 22 ns 45 58 75 ns 1 4 ns 25 36 48 ns 1 3 ns 12 21 ns 0.5 1 ns 7 ISO722xM, see Figure 7-1 ISO722xA 190 ISO722xB 17 ISO722xC 10 ISO722xM tsk(o) Channel-to-channel output skew (3) tr Output signal rise time tf Output signal fall time tfs Failsafe output delay time from input power loss tjit(pp) Peak-to-peak eye-pattern jitter (1) (2) (3) 18 ns 5 ISO7220A 3 15 ISO7220B 0.6 3 ISO7220C, ISO7220M 0.2 1 ns 1 ns 1 ns See Figure 7-2 3 μs ISO722xM, 150 Mbps PRBS NRZ data, 5-bit max same polarity input, both channels, see Figure 7-4, Figure 6-13 1 ISO722xM, 150 Mbps unrestricted bit run length data input, both channels, see Figure 7-4 2 See Figure 7-1 ns Also referred to as pulse skew. tsk(pp) is the magnitude of the difference in propagation delay times between any specified pins of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical specified loads. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated ISO7220A, ISO7220B, ISO7220C, ISO7220M, ISO7221A, ISO7221B, ISO7221C, ISO7221M www.ti.com SLLS755Q – JULY 2006 – REVISED JANUARY 2021 6.17 Switching Characteristics—3.3-V VCC1 and VCC2 Supplies VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted.) PARAMETER TEST CONDITIONS tPLH, tPHL Propagation delay PWD Pulse-width distortion |tPHL – tPLH|(1) tPLH, tPHL Propagation delay tPLH|(1) PWD Pulse-width distortion |tPHL – tPLH, tPHL Propagation delay PWD Pulse-width distortion |tPHL – tPLH|(1) tPLH, tPHL Propagation delay PWD Pulse-width distortion |tPHL – tPLH|(1) Part-to-part skew(2) tsk(pp) ISO722xA, see Figure 7-1 ISO722xB, see Figure 7-1 ISO722xC, see Figure 7-1 ISO722xM, see Figure 7-1 MIN TYP MAX UNIT 290 400 610 ns 1 22 ns 46 62 78 ns 1 4 ns 26 40 52 ns 1 3 ns 16 25 ns 0.5 1 ns 8 ISO722xA 190 ISO722xB 17 ISO722xC 10 ISO722xM Channel-to-channel output skew (3) tsk(o) tr Output signal rise time tf Output signal fall time tfs Failsafe output delay time from input power loss tjit(pp) (1) (2) (3) Peak-to-peak eye-pattern jitter ns 5 ISO7220A 3 15 ISO7220B 0.6 3 ISO7220C, ISO7220M 0.2 1 ns 2 ns 2 ns See Figure 7-2 3 μs ISO722xM, 150 Mbps PRBS NRZ data, 5-bit max same polarity input, both channels, See Figure 7-4, Figure 6-13 1 ISO722xM, 150 Mbps unrestricted bit run length data input, both channels, See Figure 7-4 2 See Figure 7-1 ns Also referred to as pulse skew. tsk(pp) is the magnitude of the difference in propagation delay times between any specified pins of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical specified loads. 6.18 Switching Characteristics—2.8-V VCC1 and VCC2 Supplies VCC1 and VCC2 at 2.8 V (over recommended operating conditions unless otherwise noted.) PARAMETER TEST CONDITIONS tPLH, tPHL Propagation delay PWD Pulse-width distortion |tPHL – tPLH|(1) tsk(pp) Part-to-part skew(2) ISO722xC tsk(o) Channel-to-channel output skew (3) ISO7220C tr Output signal rise time tf Output signal fall time tfs Failsafe output delay time from input power loss (1) (2) (3) ISO722xC, see Figure 7-1 See Figure 7-1 See Figure 7-2 MIN TYP MAX 26 45 65 ns 1.5 5 ns 12 ns 5 ns 0.2 UNIT 2 ns 2 ns 4.6 μs Also referred to as pulse skew. tsk(pp) is the magnitude of the difference in propagation delay times between any specified pins of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical specified loads. Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 19 ISO7220A, ISO7220B, ISO7220C, ISO7220M, ISO7221A, ISO7221B, ISO7221C, ISO7221M SLLS755Q – JULY 2006 – REVISED JANUARY 2021 www.ti.com 6.19 Insulation Characteristics Curves 250 Safety Limiting Current - mA 225 VCC1,2 at 3.6 V 200 175 150 125 VCC1,2 at 5.5 V 100 75 50 25 0 0 50 100 150 TC - Case Temperature - °C 200 Figure 6-1. Thermal Derating Curve for Limiting Current per VDE 20 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated ISO7220A, ISO7220B, ISO7220C, ISO7220M, ISO7221A, ISO7221B, ISO7221C, ISO7221M www.ti.com SLLS755Q – JULY 2006 – REVISED JANUARY 2021 6.20 Typical Characteristics 20 30 TA = 25°C, 15 pF Load 18 26 16 ISO7220x ICC2 12 10 ISO7221x ICC1&2 8 6 4 ISO7220x ICC1 22 20 ISO7221x ICC1&2 18 16 14 12 10 ISO7220x ICC1 8 6 4 2 2 0 0 0 25 50 75 100 0 25 Signaling Rate - Mbps Figure 6-2. 3.3-VRMS Supply Current vs Signaling Rate (Mbps) 50 75 Signaling Rate - Mbps 100 Figure 6-3. 5-VRMS Supply Current vs Signaling Rate (Mbps) 450 70 TA = 25°C, 15 pF Load 15 pF Load 440 65 Propagation Delay - ns 430 Propagation Delay - ns ISO7220x ICC2 24 14 ICC - Supply Current - mA ICC - Supply Current - mA TA = 25°C, 15 pF Load 28 420 VCC = 3.3 V 410 tpLH & tpHL 400 VCC = 5 V 390 tpLH & tpHL 380 370 tPLH & tPHL VCC = 3.3 V 60 VCC = 5 V 55 tPLH & tPHL 50 360 350 -40 -15 10 35 60 85 45 -40 110 125 25 Temperature - °C Temperature - °C Figure 6-4. Propagation Delay vs Free-Air Temperature, ISO722xA Figure 6-5. Propagation Delay vs Free-Air Temperature, ISO722xB 30 20 VCC = 3.3 V 25 VCC = 3.3 V tpLH & tpHL 15 Propagation Delay - ns Propagation Delay - ns 125 20 15 tpLH & tpHL VCC = 5 V 10 tpLH & tpHL 10 tpLH & tpHL VCC = 5 V 5 5 0 -40 15 pF Load -15 10 35 60 85 110 125 Temperature - °C Figure 6-6. Propagation Delay vs Free-Air Temperature, ISO722xC Copyright © 2021 Texas Instruments Incorporated 15 pF Load 0 -40 -15 10 35 60 85 110 125 Temperature - °C Figure 6-7. Propagation Delay vs Free-Air Temperature, ISO722xM Submit Document Feedback 21 ISO7220A, ISO7220B, ISO7220C, ISO7220M, ISO7221A, ISO7221B, ISO7221C, ISO7221M www.ti.com SLLS755Q – JULY 2006 – REVISED JANUARY 2021 2.5 1.4 2.4 5-V Vth+ 1.35 5-V Vth+ 1.3 Input Voltage Threshold - V Input Voltage Threshold - V 2.3 3.3-V Vth+ 1.25 15 pF Load 1.2 1.15 5-V Vth1.1 2.2 5-V Vth- 2.1 2 15 pF Load 1.9 1.8 3.3-V Vth+ 1.7 1.6 1.05 1.5 3.3-V Vth-40 -25 -10 5 20 35 50 65 80 95 3.3-V Vth- 1.4 -40 -25 -10 1 110 125 5 20 35 50 65 80 95 110 125 Temperature - °C Temperature - °C Figure 6-9. ISO722xM Input Voltage High-to-Low vs Figure 6-8. ISO722xA, ISO722xB and ISO722xC Free-Air Temperature Input Voltage Low-to-High Switching Threshold vs Free-Air Temperature -80 15 pF Load TA = 25°C -70 2.64 -60 VCC = 5 V VCC Rising -50 2.6 IOUT - mA Power Supply Undervoltage Threshold - V 2.68 2.56 -40 -30 VCC Falling VCC = 3.3 V -20 2.52 -10 2.48 -40 -25 -10 0 5 20 35 50 65 80 95 110 125 0 2 Free-Air Temperature - °C Figure 6-10. VCC Undervoltage Threshold vs FreeAir Temperature 6 Figure 6-11. High-Level Output Current vs HighLevel Output Voltage 70 2000 15 pF Load TA = 25°C 60 15 pF Load TA = 25°C 1800 VCC = 5 V 1600 50 1400 1200 40 Jitter − ps IOUT - mA 4 VOUT - V VCC = 3.3 V 30 VCC1 = VCC2 = 5 V 1000 800 600 20 VCC1 = VCC2 = 3.3 V 400 10 200 0 0 0 1 2 3 4 5 VOUT - V Figure 6-12. Low-Level Output Current vs LowLevel Output Voltage 22 Submit Document Feedback 0 50 100 150 200 Signaling Rate - Mbps Figure 6-13. ISO722xM Jitter vs Signaling Rate Copyright © 2021 Texas Instruments Incorporated ISO7220A, ISO7220B, ISO7220C, ISO7220M, ISO7221A, ISO7221B, ISO7221C, ISO7221M www.ti.com SLLS755Q – JULY 2006 – REVISED JANUARY 2021 ISOLATION BARRIER 7 Parameter Measurement Information IN Input Generator VI 50 W NOTE A VCC VI VCC/2 VCC/2 OUT 0V tPHL tPLH CL NOTE B VO VO VOH 90% 50% 50% 10% tr tf VOL A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω. B. CL = 15 pF and includes instrumentation and fixture capacitance within ± 20%. Figure 7-1. Switching Characteristic Test Circuit and Voltage Waveforms VI ISOLATION BARRIER VCC IN = 0 V VCC OUT VI 2.7 V VO 0V VOH tfs CL NOTE A VO FAILSAFE HIGH VOL 50% A. CL = 15 pF and includes instrumentation and fixture capacitance within ± 20%. Figure 7-2. Failsafe Delay Time Test Circuit and Voltage Waveforms VCCI VCCO S1 Isolation Barrier C = 0.1 µF ±1% IN C = 0.1 µF ±1% Pass-fail criteria: The output must remain stable. OUT + EN CL See Note A GNDI + VCM ± VOH or VOL ± GNDO Copyright © 2016, Texas Instruments Incorporated A. CL = 15 pF and includes instrumentation and fixture capacitance within ± 20%. Figure 7-3. Common-Mode Transient Immunity Test Circuit Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 23 ISO7220A, ISO7220B, ISO7220C, ISO7220M, ISO7221A, ISO7221B, ISO7221C, ISO7221M www.ti.com SLLS755Q – JULY 2006 – REVISED JANUARY 2021 VCC DUT Tektronix HFS9009 IN OUT 0V Tektronix 784D PATTERN GENERATOR VCC/2 Jitter PRBS bit pattern run length is 216 – 1. Transition time is 800 ps. Figure 7-4. Peak-to-Peak Eye-Pattern Jitter Test Circuit and Voltage Waveform 24 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated ISO7220A, ISO7220B, ISO7220C, ISO7220M, ISO7221A, ISO7221B, ISO7221C, ISO7221M www.ti.com SLLS755Q – JULY 2006 – REVISED JANUARY 2021 8 Detailed Description 8.1 Overview The isolator in theSection 8.2 is based on a capacitive isolation barrier technique. The I/O channel of the ISO7220x and ISO7221x family of devices consists of two internal data channels, a high-frequency channel (HF) with a bandwidth from 100 kbps up to 150 Mbps, and a low-frequency channel (LF) covering the range from 100 kbps down to DC. In principle, a single-ended input signal entering the HF-channel is split into a differential signal via the inverter gate at the input. The following capacitor-resistor networks differentiate the signal into transients, which then are converted into differential pulses by two comparators. The comparator outputs drive a NOR-gate flip-flop whose output feeds an output multiplexer. A decision logic (DCL) at the driving output of the flip-flop measures the durations between signal transients. If the duration between two consecutive transients exceeds a certain time limit, (as in the case of a low-frequency signal), the DCL forces the output-multiplexer to switch from the high-frequency to the low-frequency channel. Because low-frequency input signals require the internal capacitors to assume prohibitively large values, these signals are pulse-width modulated (PWM) with the carrier frequency of an internal oscillator, thus creating a sufficiently high frequency signal, capable of passing the capacitive barrier. As the input is modulated, a lowpass filter (LPF) is needed to remove the high-frequency carrier from the actual data before passing it on to the output multiplexer. 8.2 Functional Block Diagram Isolation Barrier OSC LPF Low t Frequency Channel (DC...100 kbps) PWM VREF 0 OUT 1 S IN DCL High t Frequency Channel (100 kbps...150 Mbps) VREF Copyright © 2016, Texas Instruments Incorporated Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 25 ISO7220A, ISO7220B, ISO7220C, ISO7220M, ISO7221A, ISO7221B, ISO7221C, ISO7221M www.ti.com SLLS755Q – JULY 2006 – REVISED JANUARY 2021 8.3 Feature Description Table 8-1 provides an overview of the device features. Table 8-1. Device Features PART NUMBER MAXIMUM SIGNALING RATE INPUT THRESHOLD CHANNEL DIRECTION ISO7220A 1 Mbps ≈ 1.5 V (TTL) (CMOS compatible) ISO7220B 5 Mbps ≈ 1.5 V (TTL) (CMOS compatible ISO7220C 25 Mbps ≈ 1.5 V (TTL) (CMOS compatible) ISO7220M 150 Mbps VCC/ 2 (CMOS) ISO7221A 1 Mbps ≈ 1.5 V (TTL) (CMOS compatible) ISO7221B 5 Mbps ≈ 1.5 V (TTL) (CMOS compatible) ISO7221C 25 Mbps ≈ 1.5 V (TTL) (CMOS compatible) ISO7221M 150 Mbps VCC/ 2 (CMOS) Same direction Opposite directions 8.4 Device Functional Modes The ISO7220x and ISO7221x family of devices functional modes are listed in Table 8-2. Table 8-2. ISO7220x or ISO7221x Function Table (1) (1) INPUT SIDE VCC OUTPUT SIDE VCC PU PU PD PU X PD INPUT (IN) OUTPUT (OUT) H H L L Open H X H X Undetermined PU = Powered Up (VCC ≥ 3.0 V), PD = Powered Down (VCC ≤ 2.5 V), X = Irrelevant, H = High Level, L = Low Level Input VCC1 VCC1 VCC1 Output VCC2 750 kW IN 500 W 8W OUT 13 W Figure 8-1. Device I/O Schematics 26 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated ISO7220A, ISO7220B, ISO7220C, ISO7220M, ISO7221A, ISO7221B, ISO7221C, ISO7221M www.ti.com SLLS755Q – JULY 2006 – REVISED JANUARY 2021 9 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 9.1 Application Information The ISO7220x and ISO7221x family devices use single-ended TTL or CMOS-logic switching technology. The supply voltage range is from 3 V (2.8 V for C-grade) to 5.5 V for both supplies, VCC1 and VCC2. When designing with digital isolators, because of the single-ended design structure, digital isolators do not conform to any specific interface standard and are only intended for isolating single-ended CMOS or TTL digital signal lines. The isolator is typically placed between the data controller (that is, μC or UART), and a data converter or a line transceiver, regardless of the interface type or standard. 9.2 Typical Application The ISO7221x family of devices can be used with Texas Instruments' mixed signal micro-controller, digital-toanalog converter, transformer driver, and voltage regulator to create an isolated 4- to 20-mA current loop. VS 3.3 V 0.1 F 2 VCC D2 3 1:1.33 MBR0520L 1 SN6501 10 F GND D1 0.1 F IN OUT 3.3VISO 5 10 F TPS76333 3 1 EN GND 2 10 F MBR0520L 4, 5 0.1 F ISO-BARRIER 0.1 F 20 LOOP+ 0.1 F 0.1 F 15 0.1 F 10 1 8 2 5 6 VCC1 DVCC XOUT XIN MSP430 G2132 8 VCC2 2 OUTA P3.0 11 12 P3.1 INA ISO7221 3 INB GND1 DVSS 4 4 OUTB GND2 5 7 5 6 4 3 VA VD LOW BASE ERRLVL 16 0.1 F DAC161P997 22 DBACK DIN C1 14 3 × 22 nF 1 F C2 13 C3 COMA 12 1 OUT COMD 9 LOOP± 2 Figure 9-1. Isolated 4- to 20-mA Current Loop 9.2.1 Design Requirements Unlike optocouplers, which require external components to improve performance, provide bias (or limit current), the ISO7220x and ISO7221x devices require only two external bypass capacitors to operate. Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 27 ISO7220A, ISO7220B, ISO7220C, ISO7220M, ISO7221A, ISO7221B, ISO7221C, ISO7221M www.ti.com SLLS755Q – JULY 2006 – REVISED JANUARY 2021 9.2.2 Detailed Design Procedure Figure 9-2 and Figure 9-3 show the hookup of a typical ISO7220x and ISO7221x circuit. The only external components are two bypass capacitors. V CC1 V CC 2 0.1mF 2 mm max . from Vcc 1 INA INPUT INB INPUT 1 2 3 4 8 OUTA 7 OUTB 6 5 2 mm max . from Vcc 2 0.1mF OUTPUT OUTPUT ISO7220 GND 1 GND 2 Figure 9-2. Typical ISO7220x Circuit Hook-Up V CC1 V CC2 0.1mF 2 mm max . from Vcc1 OUTPUT 1 OUTA 2 INB INPUT 3 4 8 INA 7 OUTB 6 5 2 mm max . from Vcc 2 0.1mF INPUT OUTPUT ISO7221 GND 1 GND 2 Figure 9-3. Typical ISO7221x Circuit Hook-Up 9.2.3 Application Curve At maximum working voltage, the isolation barrier of the ISO7220x and ISO7221x family of devices has more than 28 years of life. Working Life (Years) 100 VIORM at 560 VPK 28 10 0 120 250 500 750 880 1000 Working Voltage, VIORM (VPK) Figure 9-4. Time-Dependent Dielectric Breakdown Test Results 28 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated ISO7220A, ISO7220B, ISO7220C, ISO7220M, ISO7221A, ISO7221B, ISO7221C, ISO7221M www.ti.com SLLS755Q – JULY 2006 – REVISED JANUARY 2021 10 Power Supply Recommendations To help ensure reliable operation at all data rates and supply voltages, a 0.1-μF bypass capacitor is recommended at input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins as possible. If only a single primary-side power supply is available in an application, isolated power can be generated for the secondary-side with the help of a transformer driver such as Texas Instruments SN6501 device. For such applications, detailed power supply design and transformer selection recommendations are available in SN6501 Transformer Driver for Isolated Power Supplies. 11 Layout 11.1 Layout Guidelines A minimum of four layers are required to accomplish a low EMI PCB design (see Figure 11-1). Layer stacking should be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and lowfrequency signal layer. • Route the high-speed traces on the top layer to avoid the use of vias (and the introduction of the inductances) and allow for clean interconnects between the isolator and the transmitter and receiver circuits of the data link. • Place a solid ground plane next to the high-speed signal layer to establish controlled impedance for transmission line interconnects and provide an excellent low-inductance path for the return current flow. • Place the power plane next to the ground plane to create additional high-frequency bypass capacitance of approximately 100 pF/in2. • Route the slower speed control signals on the bottom layer to allow for greater flexibility as these signal links usually have margin to tolerate discontinuities such as vias. If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to the stack to keep it symmetrical. Adding a second plane system to the stack makes the stack mechanically stable and prevents it from warping. The power and ground plane of each power system can be placed closer together, thus increasing the high-frequency bypass capacitance significantly. For detailed layout recommendations, refer to the Digital Isolator Design Guide. 11.1.1 PCB Material For digital circuit boards operating at less than 150 Mbps, (or rise and fall times greater than 1 ns), and trace lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and the self-extinguishing flammability-characteristics. 11.2 Layout Example High-speed traces 10 mils Ground plane 40 mils Keep this space free from planes, traces, pads, and vias FR-4 0r ~ 4.5 Power plane 10 mils Low-speed traces Figure 11-1. Recommended Layer Stack Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 29 ISO7220A, ISO7220B, ISO7220C, ISO7220M, ISO7221A, ISO7221B, ISO7221C, ISO7221M www.ti.com SLLS755Q – JULY 2006 – REVISED JANUARY 2021 12 Device and Documentation Support 12.1 Device Support 12.1.1 Development Support For development support, refer to: • • • • • AC-mains LED Lighting with DALI DMX512 & Power Line Communications Reference Design Industrial Servo Drive and AC Inverter Drive Reference Design Low-Cost Single/Dual-Phase Isolated Electricity Measurement Reference Design Noise Tolerant Capacitive Touch HMI Reference Design Type 2 PoE PSE, 6kV Lightning Surge Reference Design 12.2 Documentation Support 12.2.1 Related Documentation For related documentation, see the following: • Texas Instruments, DAC161P997 Single-Wire 16-bit DAC for 4- to 20-mA Loops data sheet • Texas Instruments, Digital Isolator Design Guide • Texas Instruments, High-Voltage Lifetime of the ISO72x Family of Digital Isolators application report • Texas Instruments, Isolation Glossary • Texas Instruments, MSP430G2x32 Mixed Signal Microcontroller data sheet • Texas Instruments, SN6501 Transformer Driver for Isolated Power Supplies data sheet • Texas Instruments, TPS763xx Low-Power 150-mA Low-Dropout Linear Regulators data sheet 12.3 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 12-1. Related Links PARTS PRODUCT FOLDER ORDER NOW TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY ISO7220A Click here Click here Click here Click here Click here ISO7220B Click here Click here Click here Click here Click here ISO7220C Click here Click here Click here Click here Click here ISO7220M Click here Click here Click here Click here Click here ISO7221A Click here Click here Click here Click here Click here ISO7221B Click here Click here Click here Click here Click here ISO7221C Click here Click here Click here Click here Click here ISO7221M Click here Click here Click here Click here Click here 12.4 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.5 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 30 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated ISO7220A, ISO7220B, ISO7220C, ISO7220M, ISO7221A, ISO7221B, ISO7221C, ISO7221M www.ti.com SLLS755Q – JULY 2006 – REVISED JANUARY 2021 12.6 Trademarks Profibus™ is a trademark of Profibus. DeviceNet™ is a trademark of Open DeviceNet Vendors Association. TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 12.7 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.8 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 31 ISO7220A, ISO7220B, ISO7220C, ISO7220M, ISO7221A, ISO7221B, ISO7221C, ISO7221M www.ti.com SLLS755Q – JULY 2006 – REVISED JANUARY 2021 PACKAGE OUTLINE D0008B SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] A .004 [0.1] C PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .150 [3.81] .189-.197 [4.81-5.00] NOTE 3 4X (0 -15 ) 4 5 B 8X .012-.020 [0.31-0.51] .150-.157 [3.81-3.98] NOTE 4 .010 [0.25] C A B .069 MAX [1.75] .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 [0.11-0.25] 0 -8 .016-.050 [0.41-1.27] DETAIL A .041 [1.04] TYPICAL 4221445/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15], per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com 32 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated ISO7220A, ISO7220B, ISO7220C, ISO7220M, ISO7221A, ISO7221B, ISO7221C, ISO7221M www.ti.com SLLS755Q – JULY 2006 – REVISED JANUARY 2021 EXAMPLE BOARD LAYOUT D0008B SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] 8X (.055) [1.4] SEE DETAILS SYMM SEE DETAILS SYMM 1 1 8 8X (.024) [0.6] 8 SYMM 5 4 6X (.050 ) [1.27] 8X (.024) [0.6] (R.002 ) TYP [0.05] SYMM 5 4 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) [0.05] TYP (.217) [5.5] HV / ISOLATION OPTION .162 [4.1] CLEARANCE / CREEPAGE IPC-7351 NOMINAL .150 [3.85] CLEARANCE / CREEPAGE LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:6X SOLDER MASK OPENING METAL EXPOSDE METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL .0028 MIN [0.07] ALL AROUND .0028 MAX [0.07] ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS 4221445/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 33 ISO7220A, ISO7220B, ISO7220C, ISO7220M, ISO7221A, ISO7221B, ISO7221C, ISO7221M www.ti.com SLLS755Q – JULY 2006 – REVISED JANUARY 2021 EXAMPLE STENCIL DESIGN D0008B SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] 8X (.055) [1.4] SYMM SYMM 1 1 8 8X (.024) [0.6] 6X (.050 ) [1.27] 8 SYMM 5 4 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 6X (.050 ) [1.27] 5 4 (R.002 ) [0.05] TYP (.217) [5.5] (.213) [5.4] HV / ISOLATION OPTION .162 [4.1] CLEARANCE / CREEPAGE IPC-7351 NOMINAL .150 [3.85] CLEARANCE / CREEPAGE SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.127 MM] THICK STENCIL SCALE:6X 4221445/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com 34 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) ISO7220AD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 I7220A Samples ISO7220ADG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 I7220A Samples ISO7220ADR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 I7220A Samples ISO7220ADRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 I7220A Samples ISO7220BD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 I7220B Samples ISO7220BDG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 I7220B Samples ISO7220BDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 I7220B Samples ISO7220CD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 I7220C Samples ISO7220CDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 I7220C Samples ISO7220MD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 I7220M Samples ISO7220MDG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 I7220M Samples ISO7220MDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 I7220M Samples ISO7220MDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 I7220M Samples ISO7221AD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 I7221A Samples ISO7221ADG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 I7221A Samples ISO7221ADR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 I7221A Samples ISO7221ADRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 I7221A Samples ISO7221BD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 I7221B Samples ISO7221BDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 I7221B Samples ISO7221BDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 I7221B Samples Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) ISO7221CD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 I7221C Samples ISO7221CDG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 I7221C Samples ISO7221CDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 I7221C Samples ISO7221CDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 I7221C Samples ISO7221MD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 I7221M Samples ISO7221MDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 I7221M Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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