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ISO721, ISO721M, ISO722, ISO722M
SLLS629L – JANUARY 2006 – REVISED OCTOBER 2015
ISO72x Single Channel High-Speed Digital Isolators
1 Features
•
•
•
•
•
•
•
•
1
•
•
•
•
100 and 150-Mbps Signaling Rate Options
Low Propagation Delay
Low Pulse Skew
Low-Power Sleep Mode
High Electromagnetic Immunity
Low Input-Current Requirement
Failsafe Output
Drop-In Replacement for Most Opto and Magnetic
Isolators
Operates from 3.3 V and 5 V Supplies
-40°C to 125°C Operating Temperature Range
50 kV/µs Transient Immunity, Typical
Safety and Regulatory Approvals
– VDE Basic Insulation with 4000-VPK VIOTM, 560
VPK VIORM
– 2500 VRMS Isolation per UL 1577
– CSA Approved for Component Acceptance
Notice 5A and IEC 60950-1
2 Applications
•
•
•
•
Industrial Fieldbus
– Modbus
– Profibus
– DeviceNet™ Data Buses
– Smart Distributed Systems (SDS™)
Computer Peripheral Interface
Servo Control Interface
Data Acquisition
If this dc-refresh pulse is not received for more than 4
μs, the input is assumed to be unpowered or not
being actively driven, and the failsafe circuit drives
the output to a logic-high state.
The symmetry of the dielectric and capacitor within
the integrated circuitry provides for close capacitive
matching, and allows fast transient voltage changes
between the input and output grounds without
corrupting the output. The small capacitance and
resulting time constant provide for fast operation with
signaling rates from 0 Mbps (DC) to 100 Mbps for the
ISO721 and the ISO722 devices, and 0 Mbps to 150
Mbps with the ISO721M and the ISO722M devices.
These devices require two supply voltages of 3.3 V, 5
V, or any combination. All inputs are 5-V tolerant
when supplied from a 3.3-V supply and all outputs
are 4 mA CMOS.
The ISO722 and ISO722M devices include an activelow output enable that when driven to a high logic
level, places the output in a high-impedance state
and turns off internal bias circuitry to conserve power.
Both the ISO721 and ISO722 devices have TTL input
thresholds and a noise filter at the input that prevent
transient pulses of up to 2 ns in duration from being
passed to the output of the device.
The ISO721M and ISO722M devices have CMOS
VCC / 2 input thresholds, but do not have the noisefilter and the additional propagation delay. These
features of the ISO721M device also provide for
reduced-jitter operation.
The ISO721, ISO721M, ISO722, and ISO722M
devices are characterized for operation over the
ambient temperature range of –40°C to 125°C.
Device Information(1)
3 Description
The ISO721, ISO721M, ISO722, and ISO722M are
digital isolators with a logic input and output buffer
separated by a silicon dioxide (SiO2) insulation
barrier. This barrier provides galvanic isolation of up
to 4000 VPK per VDE. Used in conjunction with
isolated power supplies, these devices prevent noise
currents on a data bus or other circuits from entering
the local ground, and interfering with or damaging
sensitive circuitry.
A binary input signal is conditioned, translated to a
balanced signal, then differentiated by the capacitive
isolation barrier. Across the isolation barrier, a
differential comparator receives the logic transition
information, then sets or resets a flip-flop and the
output circuit accordingly. A periodic update pulse is
sent across the barrier to ensure the proper dc level
of the output.
PART NUMBER
ISO721
PACKAGE
BODY SIZE (NOM)
SOP (8)
9.50mm x 6.57mm
SOIC (8)
4.90mm x 3.91mm
ISO721
ISO721M
ISO722
ISO722M
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
VCC1
VCC2
Isolation
Capacitor
IN
OUT
EN (ISO722/M-only)
GND1
GND2
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ISO721, ISO721M, ISO722, ISO722M
SLLS629L – JANUARY 2006 – REVISED OCTOBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
7.14
1
1
1
2
4
4
5
Absolute Maximum Ratings ..................................... 5
ESD Ratings ............................................................ 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 6
Electrical Characteristics, 5 V ................................... 6
Electrical Characteristics, 5 V, 3.3 V......................... 7
Electrical Characteristics, 3.3 V, 5 V......................... 7
Electrical Characteristics, 3.3 V ............................... 8
Power Dissipation ..................................................... 8
Switching Characteristics, 5 V ................................ 9
Switching Characteristics, 5 V, 3.3 V.................... 10
Switching Characteristics, 3.3 V, 5 V.................... 11
Switching Characteristics, 3.3 V .......................... 12
Typical Characteristics .......................................... 13
8
9
Parameter Measurement Information ................ 15
Detailed Description ............................................ 18
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Features Description ...............................................
Device Functional Modes........................................
18
18
19
21
10 Application and Implementation........................ 22
10.1 Application Information.......................................... 22
10.2 Typical Application ................................................ 22
11 Power Supply Recommendations ..................... 24
12 Layout................................................................... 24
12.1 Layout Guidelines ................................................. 24
12.2 Layout Example .................................................... 25
13 Device and Documentation Support ................. 26
13.1
13.2
13.3
13.4
13.5
Documentation Support .......................................
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
26
26
26
26
26
14 Mechanical, Packaging, and Orderable
Information ........................................................... 26
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision K (February 2012) to Revision L
Page
•
Moved Power Dissipation metric into new table, called Power Dissipation .......................................................................... 8
•
Added header row above "VIORM" row with the text "DIN V VDE V 0884-10 (VDE V 0884-10):2006-12" in the
Insulation Characteristics table............................................................................................................................................. 19
•
Added "UL 1577" header row over "VISO" row in the Insulation Characteristics table. ........................................................ 19
•
Moved "VISO" row to the bottom of the Insulation Characteristics table. ............................................................................. 19
•
Deleted "per UL" in "Isolation voltage" in the Insulation Characteristics table. ................................................................... 19
•
Changed the D-8 MIN value of L(101) from "4.8" to "4" in the Package Insulation Characteristics table. ......................... 20
•
Changed the D-8 MIN value of L(102) from "4.3" to "4" in the Package Insulation Characteristics table. ......................... 20
•
Changed Test Condition "DIN IEC 60112/VDE 0303 Part 1" to "DIN EN 60112 (VDE 0303-11); IEC 60112" in the
Package Insulation Characteristics table. ............................................................................................................................ 20
•
Deleted bottom row of the Package Insulation Characteristics table. ................................................................................. 20
Changes from Revision J (July 2010) to Revision K
Page
•
Added ESD Rating table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information............................................................................................................... 1
•
Changed the Title From: 3.3-V / 5-V High-Speed Digital Isolators To: ISO72x Single Channel High-Speed Digital
Isolators .................................................................................................................................................................................. 1
•
Changed the Features List .................................................................................................................................................... 1
•
Changed the second paragraph of the Description From: "4000 V" To: "4000 VPK per VDE..."............................................ 1
•
Changed the Thermal Information table ................................................................................................................................. 6
•
Changed Figure 1................................................................................................................................................................. 13
•
Changed the Basic isolation group Specification From: IIIa To: II in IEC 60664-1 Ratings Table....................................... 19
2
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SLLS629L – JANUARY 2006 – REVISED OCTOBER 2015
•
Changed VDE text From: "DIN EN 60747-5-5 (VDE 0884-5)" To: "DIN V VDE V 0884-10 (VDE V 0884-10):2006-12"
in the Regulatory Information table....................................................................................................................................... 19
•
Changed CSA File number: 1698195 To: 220991 in the Regulatory Information table....................................................... 19
•
Changed the CTI MIN value From: ≥ 175 V To: 400 V in the Package Insulation Characteristics table.............................. 20
•
Changed RIO Test Condition From: TA < 100°C To: TA = 25°C in Package Insulation Characteristics .............................. 20
•
Moved the RIO values from the TYP column to the MIN column of Package Insulation Characteristics ............................ 20
•
Changed the title of Figure 16 From: θJC Thermal Derating Curve per DIN EN 60747-5-5 To: θJC Thermal Derating
Curve per VDE ..................................................................................................................................................................... 20
•
Changed Table 1, added row X, PD, X, Undetermined ....................................................................................................... 21
•
Changed Table 2, added row X, PD, X, Undetermined ....................................................................................................... 21
•
Changed Figure 17 .............................................................................................................................................................. 21
Changes from Revision I (February 2010) to Revision J
Page
•
Changed Note 1 of the Electrical Characteristics, 5 V table .................................................................................................. 6
•
Changed Note 1 of the Electrical Characteristics, 5 V, 3.3 V table........................................................................................ 7
•
Changed Note 1 of the Electrical Characteristics, 3.3 V, 5 V table........................................................................................ 7
•
Changed Note 1 of the Electrical Characteristics, 3.3 V table ............................................................................................... 8
•
Changed V to Vpeak in UNIT column of IEC Insulation Characteristics table ..................................................................... 19
•
Added row for VISO to Insulation Characteristics table ......................................................................................................... 19
•
Changed the title From: Package Characteristics To: Package Insulation Characteristics ................................................. 20
Changes from Revision H (June 2009) to Revision I
•
Page
Changed Features From: 50 kV/s Transient Immunity, Typical To: 50 kV/µs Transient Immunity, Typical .......................... 1
Changes from Revision G (December 2008) to Revision H
Page
•
Changed the first paragraph of the Description From: "silicon oxide (SiO2).." To: "silicon dioxide (SiO2)..".......................... 1
•
Added the DUB 8 pin package to the Pin Configuration and Functions ................................................................................ 4
•
Added package designators D-8 and DUB-8 to the table Descriptions/Test Conditions of the Package Insulation
Characteristics table ............................................................................................................................................................. 20
Changes from Revision F (November 2008) to Revision G
•
Page
Changed the Features List From: 4000-V(peak) Isolation To: 4000-V(peak) Isolation, 560-Vpeak VIORM ...................................... 1
Changes from Revision E (May 2008) to Revision F
Page
•
Changed Figure 19 text From: 20 mm max. from VCC1 To: 2 mm max. from VCC1 .............................................................. 23
•
Changed Note in Table 3 From: The ISO72x pin 1 and pin 3 are internally connected together. Either or both may
be used as VCC1. To: Pin 1 should be used as VCC1. Pin 3 may also be used as VCC1 or left open as long as Pin 1 is
connected to VCC1 ................................................................................................................................................................ 23
•
Changed Note in Table 3 From: The ISO721 and ISO721M pin 5 and pin 7 are internally connected together. Either
or both may be used as GND2. To: Pin 5 should be used as GND2. Pin 7 may also be used as GND2 or left open
as long as Pin 5 is connected to GND2. .............................................................................................................................. 23
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Changes from Revision D (February 2007) to Revision E
Page
•
Changed changed the VCC MIN value From: 4.5 V To: 3 V in the Recommended Operating Conditions table ................... 5
•
Added Note 1 to the Recommended Operating Conditions table .......................................................................................... 5
•
Added Note 1 to the Electrical Characteristics, 5 V table....................................................................................................... 6
•
Added Note 1 to the Electrical Characteristics, 5 V, 3.3 V table ........................................................................................... 7
•
Added Note 1 to the Electrical Characteristics, 3.3 V, 5 V table ............................................................................................ 7
•
Added Note 1 to the Electrical Characteristics, 3.3 V table.................................................................................................... 8
4
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SLLS629L – JANUARY 2006 – REVISED OCTOBER 2015
5 Device Comparison Table
PRODUCT
SIGNALING RATE
OUTPUT
ENABLED
INPUT
THRESHOLDS
NOISE
FILTER
ISO721
100 Mbps
NO
TTL
YES
ISO721M
150 Mbps
NO
CMOS
NO
ISO722
100 Mbps
YES
TTL
YES
ISO722M
150 Mbps
YES
CMOS
NO
6 Pin Configuration and Functions
1
IN
2
VCC1
3
GND1
4
ISO722, ISO722M
SOIC (D) Package
Top View
8
VCC2
7
GND2
6
OUT
5
VCC1
1
IN
2
VCC1
3
GND1
4
GND2
Isolation
VCC1
Isolation
ISO721, ISO721M
SOIC (D) Package
Top View
8
VCC2
7
EN
6
OUT
5
GND2
VCC1
1
IN
2
VCC1
3
GND1
4
Isolation
ISO721
SOP (DUB) Package
Top View
8
VCC2
7
GND2
6
OUT
5
GND2
Pin Functions
PIN
ISO721x
NO.
ISO722x
NO.
I/O
VCC1
1, 3
1, 3
-
Power supply, VCC1
VCC2
8
8
-
Power supply, VCC2
IN
2
2
I
Input
OUT
6
6
O
Output
EN
-
7
I
Output enable. OUT is enabled when EN is low or disconnected and disabled
when EN is high.
GND1
4
4
-
Ground connection for VCC1
GND2
5, 7
5
-
Ground connection for VCC2
NAME
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DESCRIPTION
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
Supply voltage
VCC1, VCC2
MAX
6
V
VCC + 0.5
(2)
Input voltage
IO
Output current
±15
mA
TJ
Maximum junction temperature
170
°C
Tstg
Storage temperature
150
°C
(2)
–0.5
UNIT
VI
(1)
IN, OUT, or EN
MIN
–0.5
–65
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Maximum voltage must not exceed 6 V.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged device model (CDM), per JEDEC specification JESD22C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN
Supply voltage (1), VCC1, VCC2
VCC
IOH
Input pulse duration
1 / tui
Signaling Rate
VIH
High-level input voltage (IN, EN)
VIL
Low-level input voltage (IN, EN)
VIH
High-level input voltage (IN, EN)
VIL
Low-level input voltage (IN, EN)
TA
Ambient temperature
TJ
Junction temperature
H
External magnetic field intensity per IEC 61000-4-8 and IEC 61000-4-9
certification
6
5.5
–4
ISO72x
tui
(1)
MAX
4
Output current
IOL
TYP
3
ISO72xM
UNIT
V
mA
mA
10
ns
6.67
ISO72x
0
100
ISO72xM
0
150
2
5.5
V
ISO72x
IOS72xM
Mbps
0
0.8
V
0.7 VCC
VCC
V
0
0.3 VCC
V
125
°C
150
°C
1000
A/m
–40
See Thermal Information
25
For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V. For the 3-V operation, VCC1 or VCC2 is specified from 3 V to 3.6 V.
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7.4 Thermal Information
ISO721
THERMAL METRIC (1)
RθJA
Junction-to-ambient thermal resistance
ISO72x
DUB
D
8 PINS
8 PINS
UNIT
High-K Board
86.6
114.7
Low-K Board
N/A
263
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
70.3
63
°C/W
RθJB
Junction-to-board thermal resistance
50.2
54.8
°C/W
ψJT
Junction-to-top characterization parameter
34.3
18.9
°C/W
ψJB
Junction-to-board characterization parameter
49.8
54.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.5 Electrical Characteristics, 5 V
VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted.)
PARAMETER
ICC1
VCC1 supply current
TEST CONDITIONS
Quiescent
25 Mbps
ISO722/722M Sleep Mode
ICC2
VCC2 supply current
VI = VCC or 0 V, no load
Quiescent
25 Mbps
VI = VCC or 0 V, no load
High-level output voltage
VOL
Low-level output voltage
TYP
MAX
0.5
1
2
4
EN at VCC
VI = VCC or 0 V,
No load
VOH
MIN
200
EN at 0 V or
ISO721/721M
8
12
10
14
IOH = –4 mA, See Figure 10
VCC – 0.8
4.6
IOH = –20 μA, See Figure 10
VCC – 0.1
5
0.2
0.4
IOL = 20 μA, See Figure 10
0
0.1
150
IIH
High-level input current
EN, IN at 2 V
IIL
Low-level input current
EN, IN at 0.8 V
IOZ
High-impedance
output current
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4 × 106πt)
CMTI
Common-mode transient immunity
VI = VCC or 0 V, See Figure 14
ISO722, ISO722M
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10
1
25
mA
V
μA
μA
1
pF
50
kV/μs
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μA
mV
–10
EN, IN at VCC
mA
V
IOL = 4 mA, See Figure 10
VI(HYS) Input voltage hysteresis
UNIT
7
ISO721, ISO721M, ISO722, ISO722M
SLLS629L – JANUARY 2006 – REVISED OCTOBER 2015
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7.6 Electrical Characteristics, 5 V, 3.3 V
VCC1 at 5 V ± 10%, VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted.)
PARAMETER
ICC1
VCC1 supply current
TEST CONDITIONS
Quiescent
25 Mbps
ISO722/722M
Sleep mode
ICC2
VCC2 supply current
Quiescent
25 Mbps
VOH
High-level output voltage
VOL
Low-level output voltage
MIN
VI = VCC or 0 V, no load
VI = VCC or 0 V,
No load
TYP
MAX
0.5
1
2
4
EN at VCC
150
EN at 0 V or
ISO721/721M
VI = VCC or 0 V, no load
4
6.5
5
7.5
IOH = –4 mA, See Figure 10
VCC – 0.4
3
IOH = –20 μA, See Figure 10
VCC – 0.1
3.3
0.2
0.4
IOL = 20 μA, See Figure 10
0
0.1
150
IIH
High-level input current
EN, IN at 2 V
IIL
Low-level input current
EN, IN at 0.8 V
IOZ
High-impedance
output current
ISO722, ISO722M
EN, IN at VCC
1
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4 × 10 πt)
CMTI
Common-mode transient immunity
VI = VCC or 0 V, See Figure 14
25
mA
V
μA
μA
–10
CI
μA
mV
10
6
mA
V
IOL = 4 mA, See Figure 10
VI(HYS) Input voltage hysteresis
UNIT
μA
1
pF
40
kV/μs
7.7 Electrical Characteristics, 3.3 V, 5 V
VCC1 at 3.3 V ± 10%, VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted.)
PARAMETER
ICC1
VCC1 supply current
TEST CONDITIONS
Quiescent
25 Mbps
ISO722/722M
Sleep mode
ICC2
VCC2 supply current
Quiescent
25 Mbps
VOH
High-level output voltage
VOL
Low-level output voltage
MIN
VI = VCC or 0 V, no load
MAX
0.3
0.5
1
2
EN at VCC
VI = VCC or 0 V,
No load
200
EN at 0 V or
ISO721/721
M
VI = VCC or 0 V, No load
8
12
10
14
IOH = –4 mA, See Figure 10
VCC – 0.8
4.6
IOH = –20 μA, See Figure 10
VCC – 0.1
5
0.2
0.4
IOL = 20 μA, See Figure 10
0
0.1
150
IIH
High-level input current
EN, IN at 2 V
IIL
Low-level input current
EN, IN at 0.8 V
IOZ
High-impedance
output current
ISO722, ISO722M
EN, IN at VCC
1
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4 × 10 πt)
CMTI
Common-mode transient immunity
VI = VCC or 0 V, See Figure 14
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25
μA
mA
V
μA
μA
–10
CI
mA
mV
10
6
UNIT
V
IOL = 4 mA, See Figure 10
VI(HYS) Input voltage hysteresis
8
TYP
μA
1
pF
40
kV/μs
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7.8 Electrical Characteristics, 3.3 V
VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted.)
PARAMETER
ICC1
VCC1 supply current
TEST CONDITIONS
Quiescent
25 Mbps
VI = VCC or 0 V, no load
ISO722/722M
Sleep Mode
ICC2
VCC2 supply current
Quiescent
25 Mbps
VOH
High-level output voltage
VOL
Low-level output voltage
MIN
TYP
MAX
0.3
0.5
1
2
EN at VCC
VI = VCC or 0 V,
No load
150
EN at 0 V
or
ISO721/721
M
VI = VCC or 0 V, no load
4
6.5
5
7.5
IOH = –4 mA, See Figure 10
VCC – 0.4
3
IOH = –20 μA, See Figure 10
VCC – 0.1
3.3
0.2
0.4
IOL = 20 μA, See Figure 10
0
0.1
150
IIH
High-level input current
EN, IN at 2 V
IIL
Low-level input current
EN, IN at 0.8 V
IOZ
High-impedance
output current
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4 × 106πt)
CMTI
Common-mode transient immunity
VI = VCC or 0 V, See Figure 14
ISO722, ISO722M
mA
μA
mA
V
IOL = 4 mA, See Figure 10
VI(HYS) Input voltage hysteresis
UNIT
V
mV
10
μA
μA
–10
EN, IN at VCC
1
25
μA
1
pF
40
kV/μs
7.9 Power Dissipation
over operating free-air temperature range (unless otherwise noted)
PARAMETER
PD
Power Dissipation
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TEST CONDITIONS
ISO721
DUB
8 PINS
ISO72x
D
8 PINS
UNIT
ISO72x
VCC1 = VCC2 = 5.5 V, TJ =
150°C, CL = 15 pF, Input a
100-Mbps 50% duty-cycle
square wave
159
mW
ISO72xM
VCC1 = VCC2 = 5.5 V, TJ =
150°C, CL = 15 pF, Input a
100-Mbps 50% duty-cycle
square wave
195
mW
ISO721
VCC1 = VCC2 = 5.5 V, TJ =
150°C, CL = 15 pF, Input a
100-Mbps 50% duty-cycle
square wave
159
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7.10 Switching Characteristics, 5 V
VCC1 and VCC2at 5 V ± 10% (over recommended operating conditions unless otherwise noted.)
PARAMETER
TEST CONDITIONS
tPLH
Propagation delay, low-to-high-level output
tPHL
Propagation delay, high-to-low-level output
tsk(p)
Pulse skew |tPHL – tPLH|
tPLH
Propagation delay, low-to-high-level output
tPHL
Propagation delay, high-to-low-level output
tsk(p)
Pulse skew |tPHL – tPLH|
tsk(pp) (1)
Part-to-part skew
tr
Output signal rise time
tf
Output signal fall time
tpHZ
Sleep-mode propagation delay,
high-level-to-high-mpedance output
Sleep-mode propagation delay,
high-impedance-to-high-level output
tpLZ
Sleep-mode propagation delay,
low-level-to-high-impedance output
13
17
24
ns
13
17
24
ns
0.5
2
ns
10
16
ns
8
ISO72xM
8
10
16
ns
1
ns
0
3
ns
ns
1
6
8
15
ns
3.5
4
8
μs
5.5
8
15
ns
4
5
8
μs
See Figure 12
tfs
Failsafe output delay time from input power loss
See Figure 13
3
100-Mbps NRZ data input, See Figure 15
2
100-Mbps unrestricted bit run length data
input, See Figure 15
3
150-Mbps NRZ data input, See Figure 15
1
ISO72xM 150-Mbps unrestricted bit run length data
input, See Figure 15
2
ISO72x
Peak-to-peak eye-pattern jitter
UNIT
0.5
1
ISO722
ISO722M
Sleep-mode propagation delay,
high-impedance-to-low-level output
10
MAX
See Figure 11
tpZL
(1)
EN at 0 V,
See Figure 10
TYP
EN at 0 V,
See Figure 10
tpZH
tjit(PP)
ISO72x
MIN
μs
ns
tsk(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
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7.11 Switching Characteristics, 5 V, 3.3 V
VCC1 at 5 V ± 10%, VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted.)
PARAMETER
TEST CONDITIONS
tPLH
Propagation delay, low-to-high-level output
tPHL
Propagation delay , high-to-low-level output
tsk(p)
Pulse skew |tPHL – tPLH|
tPLH
Propagation delay, low-to-high-level output
tPHL
Propagation delay, high-to-low-level output
tsk(p)
Pulse skew |tPHL – tPLH|
tsk(pp) (1)
Part-to-part skew
tr
Output signal rise time
tf
Output signal fall time
tpHZ
Sleep-mode propagation delay,
high-level-to-high-mpedance output
Sleep-mode propagation delay,
high-impedance-to-high-level output
tpLZ
Sleep-mode propagation delay,
low-level-to-high-impedance output
MAX
15
19
30
ns
15
19
30
ns
0.5
3
ns
12
20
ns
10
ISO72xM
10
ISO722
ISO722M
12
20
ns
0.5
1
ns
0
5
ns
2
ns
2
ns
7
11
25
ns
4.5
6
8
μs
7
13
25
ns
4.5
6
8
μs
See Figure 12
Sleep-mode propagation delay,
high-impedance-to-low-level output
tfs
Failsafe output delay time from input power loss
See Figure 13
3
100-Mbps NRZ data input, See Figure 15
2
100-Mbps unrestricted bit run length data
input, See Figure 15
3
150-Mbps NRZ data input, See Figure 15
1
ISO72xM 150-Mbps unrestricted bit run length data
input, See Figure 15
2
ISO72x
Peak-to-peak eye-pattern jitter
UNIT
See Figure 11
tpZL
(1)
EN at 0 V,
See Figure 10
TYP
EN at 0 V,
See Figure 10
tpZH
tjit(PP)
ISO72x
MIN
μs
ns
tsk(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
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7.12 Switching Characteristics, 3.3 V, 5 V
VCC1 at 3.3 V ± 10%, VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted.)
PARAMETER
TEST CONDITIONS
tPLH
Propagation delay, low-to-high-level output
tPHL
Propagation delay , high-to-low-level output
tsk(p)
Pulse skew |tPHL – tPLH|
tPLH
Propagation delay, low-to-high-level output
tPHL
Propagation delay, high-to-low-level output
tsk(p)
Pulse skew |tPHL – tPLH|
tsk(pp) (1)
Part-to-part skew
tr
Output signal rise time
tf
Output signal fall time
tpHZ
Sleep-mode propagation delay,
high-level-to-high-mpedance output
Sleep-mode propagation delay,
high-impedance-to-high-level output
tpLZ
Sleep-mode propagation delay,
low-level-to-high-impedance output
17
30
ns
15
17
30
ns
0.5
2
ns
12
21
ns
10
10
ISO722
ISO722M
tfs
Failsafe output delay time from input power loss
21
ns
1
ns
0
5
ns
1
ns
1
ns
7
9
15
ns
4.5
5
8
μs
7
9
15
ns
4.5
5
8
μs
See Figure 13
3
100-Mbps NRZ data input, See Figure 15
2
100-Mbps unrestricted bit run length data
input, See Figure 15
3
150-Mbps NRZ data input, See Figure 15
1
ISO72xM 150-Mbps unrestricted bit run length data
input, See Figure 15
2
ISO72x
Peak-to-peak eye-pattern jitter
12
0.5
See Figure 12
Sleep-mode propagation delay,
high-impedance-to-low-level output
12
ISO72xM
UNIT
See Figure 11
tpZL
(1)
EN at 0 V,
See Figure 10
TYP MAX
15
EN at 0 V,
See Figure 10
tpZH
tjit(PP)
ISO72x
MIN
μs
ns
tsk(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
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7.13 Switching Characteristics, 3.3 V
VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted.)
PARAMETER
TEST CONDITIONS
tPLH
Propagation delay, low-to-high-level output
tPHL
Propagation delay , high-to-low-level output
tsk(p)
Pulse skew |tPHL – tPLH|
tPLH
Propagation delay, low-to-high-level output
tPHL
Propagation delay, high-to-low-level output
tsk(p)
Pulse skew |tPHL – tPLH|
tsk(pp) (1)
Part-to-part skew
tr
Output signal rise time
tf
Output signal fall time
tpHZ
Sleep-mode propagation delay,
high-level-to-high-mpedance output
Sleep-mode propagation delay,
high-impedance-to-high-level output
tpLZ
Sleep-mode propagation delay,
low-level-to-high-impedance output
20
34
ns
17
20
34
ns
0.5
3
ns
12
25
ns
10
ISO72xM
10
12
25
ns
0.5
1
ns
0
5
ns
2
ns
2
ISO722
ISO722M
7
13
25
ns
5
6
8
µs
7
13
25
ns
5
6
8
μs
See Figure 12
Sleep-mode propagation delay,
high-impedance-to-low-level output
tfs
Failsafe output delay time from input power loss
See Figure 13
3
100-Mbps NRZ data input, See Figure 15
2
100-Mbps unrestricted bit run length data
input, See Figure 15
3
150-Mbps NRZ data input, See Figure 15
1
ISO72xM 150-Mbps unrestricted bit run length data
input, See Figure 15
2
ISO72x
Peak-to-peak eye-pattern jitter
UNIT
See Figure 11
tpZL
(1)
EN at 0 V,
See Figure 10
TYP MAX
17
EN at 0 V,
See Figure 10
tpZH
tjit(PP)
ISO72x
MIN
μs
ns
tsk(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
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7.14 Typical Characteristics
15
9
VCC1 = 3.3 V,
VCC2 = 3.3 V,
o
TA = 25 C,
CL = 15 pF
7
VCC1 = 5 V,
VCC2 = 5 V,
o
TA = 25 C,
CL = 15 pF
13
ICC − Supply Current − (mARMS)
ICC − Supply Current − (mARMS)
8
14
6
ICC2
5
4
3
ICC1
2
12
11
10
ICC2
9
8
7
ICC1
6
5
4
3
2
1
1
0
0
0
20
60
40
80
0
100
25
16
20
tPLH
15
tPHL
ISO72xM
10
VCC1 = 3.3 V,
VCC2 = 3.3 V,
CL = 15 pF,
Air Flow at 7 cf/m
5
-10
5
20
35
50
80
65
95
Propagation Delay − ns
Propagation Delay − ns
ISO72x
tPHL
tPHL
ISO72x
-25
tPLH
18
tPLH
14
tPLH
12
tPHL
10
8
ISO72xM
6
VCC1 = 5 V,
VCC2 = 5 V,
CL = 15 pF,
Air Flow at 7 cf/m
4
2
0
-40
110 125
-25
-10
o
20
35
50
80
65
95
110 125
TA − Free-Air Temperature − C
Figure 3. Propagation Delay vs Free-Air Temperature
Figure 4. Propagation Delay vs Free-Air Temperature
1.4
2.5
5-V (VIT+)
2.4
1.3
3.3-V (VIT+)
1.25
1.2
Air Flow at 7 cf/m
1.15
5-V (VIT- )
1.1
VIT − Input Voltage Threshold − V
1.35
VIT − Input Voltage Threshold − V
5
o
TA − Free-Air Temperature − C
5-V (VIT+)
2.3
2.2
5-V (VIT-)
2.1
2
Air Flow at 7 cf/m
1.9
1.8
3.3-V (VIT+)
1.7
1.6
1.05
3.3-V (VIT- )
-25
-10
5
20
35
50
80
65
95
110 125
o
Figure 5. ISO72x Input Threshold Voltage vs Free-Air
Temperature
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3.3-V (VIT-)
1.5
TA − Free-Air Temperature − C
14
100
20
25
1
-40
75
Figure 2. RMS Supply Current vs Signaling Rate
Figure 1. RMS Supply Current vs Signaling Rate
30
0
-40
50
Signaling Rate (Mbps)
Signaling Rate (Mbps)
1.4
-40
-25
-10
5
20
35
50
80
65
95
110 125
o
TA − Free-Air Temperature − C
Figure 6. ISO72xM Input Threshold Voltage vs Free-Air
Temperature
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2.92
-80
2.9
-70
IOH − High-Level Output Current − mA
VCC1 Failsafe Voltage − V
Typical Characteristics (continued)
Vfs+
2.88
VCC = 5 V or 3.3 V,
CL = 15 pF,
Air Flow at 7 cf/m
2.86
2.84
2.82
Vfs-
2.8
2.78
-40
o
TA = 25 C
VCC = 5 V
-60
-50
-40
VCC = 3.3 V
-30
-20
-10
0
-25
-10
5
20
35
50
80
65
95
0
110 125
1
2
3
4
5
6
VOH − High-Level Output Voltage − V
o
TA − Free-Air Temperature − C
Figure 8. High-Level Output Current vs High-Level Output
Voltage
Figure 7. VCC1 Failsafe Threshold Voltage vs Free-Air
Temperature
70
o
IOL − Low-Level Output Current − mA
TA = 25 C
60
VCC = 5 V
50
40
30
VCC = 3.3 V
20
10
0
0
1
2
3
4
5
VOL − Low-Level Output Voltage − V
Figure 9. Low-Level Output Current vs Low-Level Output Voltage
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ISOLATION BARRIER
8 Parameter Measurement Information
IN
Input
Generator
NOTE A
+
VI
50 W
-
VCC1
IO
OUT
VCC1/2
VI
0V
EN
tPHL
VOH
tPLH
+
ISO722
and
ISO722M
VCC1/2
CL
Note B
VO
-
90%
50%
VO
50%
10%
VOL
tf
tr
3V
ISOLATION BARRIER
Figure 10. Switching Characteristic Test Circuit and Voltage Waveforms
IN
Input
Generator
NOTE A
VO
OUT
VCC2
VI
VCC2/2
0V
EN
RL = 1 kW ±1 %
CL
NOTE B
+
tPZH
VOH
50%
VO
VI
VCC2/2
50 W
0.5 V
0V
tPHZ
-
Figure 11. ISO722 Sleep-Mode High-Level Output Test Circuit and Voltage Waveforms
0V
ISOLATION BARRIER
VCC2
IN
Input
Generator
NOTE A
RL = 1 kW ±1%
OUT
EN
CL
NOTE B
+
VI
VCC2
VI
VO
VCC2/2
0V
tPZL
VO
VCC2/2
tPLZ
50%
VCC2
0.5 V
VOL
50 W
-
Figure 12. ISO722 Sleep-Mode Low-Level Output Test Circuit and Voltage Waveforms
NOTE
A: The input pulse is supplied by a generator having the following characteristics:
PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω.
B: CL = 15 pF ± 20% and includes instrumentation and fixture capacitance.
16
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Parameter Measurement Information (continued)
VCC1
0V
IN
ISOLATION BARRIER
VI
VCC1
VI
OUT
VO
0V
tfs
VOH
50%
VO
CL
15 pF
±20%
EN
ISO722
and
ISO722M
2.7 V
VOL
NOTE: VI transition time is 100 ns.
VCC1
IN
VCC
or
0V
CI = 0.1 mF,
GND1
ISOLATION BARRIER
Figure 13. Failsafe Delay Time Test Circuit and Voltage Waveforms
±1%
VCC2
OUT
GND2
CL
15 pF
±20%
VO
VCM
NOTE: Pass/fail criterion is no change in VO.
Figure 14. Common-Mode Transient-Immunity Test Circuit and Voltage Waveform
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Parameter Measurement Information (continued)
Tektronix
HFS9009
Tektronix
784D
PATTERN
GENERATOR
VCC1
In p u t
0V
O u tp u t
VCC2/2
J itte r
NOTE: Bit pattern run length is 216 – 1. Transition time is 800 ps. NRZ data input has no more than five consecutive
1s or 0s.
Figure 15. Peak-to-Peak Eye-Pattern Jitter Test Circuit and Voltage Waveform
18
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9 Detailed Description
9.1 Overview
The isolator in the Functional Block Diagram is based on a capacitive isolation barrier technique. The I/O channel
of the device consists of two internal data channels, a high-frequency channel (HF) with a bandwidth from 100
kbps up to 150 Mbps, and a low-frequency channel (LF) covering the range from 100 kbps down to DC. In
principle, a single ended input signal entering the HF-channel is split into a differential signal via the inverter gate
at the input. The following capacitor-resistor networks differentiate the signal into transients, which then are
converted into differential pulses by two comparators. The comparator outputs drive a NOR-gate flip-flop whose
output feeds an output multiplexer. A decision logic (DCL) at the driving output of the flip-flop measures the
durations between signal transients. If the duration between two consecutive transients exceeds a certain time
limit, (as in the case of a low-frequency signal), the DCL forces the output-multiplexer to switch from the highfrequency to the low-frequency channel.
Because low-frequency input signals require the internal capacitors to assume prohibitively large values, these
signals are pulse-width modulated (PWM) with the carrier frequency of an internal oscillator, creating a
sufficiently high-frequency signal capable of passing the capacitive barrier. As the input is modulated, a low-pass
filter (LPF) is needed to remove the high-frequency carrier from the actual data before passing the carrier on to
the output multiplexer.
9.2 Functional Block Diagram
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9.3 Features Description
Insulation characteristics and regulatory information of ISO72x family is provided in this section.
9.3.1 Insulation Characteristics
over recommended operating conditions (unless otherwise noted.)
PARAMETER
TEST CONDITIONS
SPECIFICATIONS
UNIT
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 (1)
VIORM
Maximum working insulation voltage
VPR
Input to output test voltage
560
Vpeak
After Input/Output Safety Test Subgroup 2/3
VPR = VIORM × 1.2, t = 10 s,
Partial discharge < 5 pC
672
Vpeak
Method a, VPR = VIORM × 1.6,
Type and sample test with t = 10 s,
Partial discharge < 5 pC
896
Vpeak
Method b1, VPR = VIORM × 1.875,
100% production test with t = 1 s,
Partial discharge < 5 pC
1050
Vpeak
VIOTM
Transient overvoltage
t = 60 s
4000
Vpeak
RS
Insulation resistance
VIO = 500 V at TS
> 109
Ω
Pollution degree
2
UL 1577
VISO
(1)
(2)
Isolation voltage
VTEST = VISO, t = 60 s (qualification)
3535 / 2500
VTEST = 1.2 × VISO, t = 1 s (100% production) (2)
4242 / 3000
Vpeak/Vrms
Climatic classification 40/125/21
Based on lifetime curve (see the High-Voltage Lifetime of the ISO72x Family of Digital Isolators application report, SLLA197); these
devices can withstand 4242 Vpeak / 3000 Vrms for > 10,000 s at 150oC.
9.3.2 IEC 60664-1 Ratings Table
PARAMETER
TEST CONDITIONS
Basic isolation group
SPECIFICATION
Material group
Installation classification
II
Rated mains voltage ≤150 VRMS
I-IV
Rated mains voltage ≤300 VRMS
I-III
9.3.3 Regulatory Information
VDE
CSA
UL
Certified according to DIN V VDE V 0884-10
(VDE V 0884-10):2006-12 and DIN EN
61010-1 (VDE 0411-1)
Approved according to CSA Component
Acceptance Notice 5A and IEC 60950-1
Recognized under UL 1577 Component
Recognition Program
Basic Insulation
Maximum Transient Overvoltage, 4000 VPK
Maximum Working Voltage, 560 VPK
Maximum Surge Voltage, 4000 VPK
Evaluated to CSA 60950-1-07 and IEC
60950-1 (2nd Ed) with 2000 VRMS Isolation
rating for products with working voltages ≤
125 VRMS for reinforced insulation and ≤ 390
VRMS for basic insulation
Single Protection, 2500 VRMS (1)
Certificate number: 40016131
Master contract number: 220991
File number: E181974
(1)
20
Production tested ≥ 3000 VRMS for 1 second in accordance with UL 1577.
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9.3.4 Package Insulation Characteristics
PARAMETER
DESCRIPTIONS / TEST CONDITIONS
L(101)
Minimum air gap (clearance) (1)
Shortest terminal-to-terminal distance through air
L(102)
Minimum external tracking
(creepage) (1)
Shortest terminal-to-terminal distance across the
package surface
CTI
Tracking resistance (comparative
DIN EN 60112 (VDE 0303-11); IEC 60112
tracking index)
DTI
Distance through insulation
RIO
CIO
(1)
MIN
D-8
Barrier capacitance
Input-to-output
MAX
4
DUB-8
D-8
4
DUB-8
UNIT
mm
6.1
mm
6.8
400
Minimum internal gap (internal clearance)
Isolation resistance
TYP
V
0.008
mm
Input to output, VIO = 500 V; all pins on each side of the
barrier tied together, creating a two-terminal device; TA = 25°C
1012
Ω
Input to output, VIO = 500 V,
100°C ≤ TA< TA max.
1011
Ω
VI = 0.4 sin (4 × 106πt)
1
pF
Creepage and clearance requirements are applied according to the specific equipment isolation standards of an application. Maintain
the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed circuit board do
not reduce this distance.
Creepage and clearance on a printed circuit board become equal according to the measurement techniques shown in the Isolation
Glossary in the Related Documentation section. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to
help increase these specifications.
9.3.5 Safety Limiting Values
Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry.
A failure of the I/O can allow low resistance to ground or the supply, and without current limiting, dissipate
sufficient power to overheat the die and damage the isolation barrier, potentially leading to secondary system
failures.
PARAMETER
TEST CONDITIONS
IS
Safety input, output, or supply current
TS
Maximum case temperature
MIN
TYP
MAX
θJA = 263°C/W, VI = 5.5 V, TJ = 170°C, TA = 25°C
100
θJA = 263°C/W, VI = 3.6 V, TJ = 170°C, TA = 25°C
153
150
UNIT
mA
°C
The safety-limiting constraint is the absolute maximum junction temperature specified in the absolute maximum
ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the
application hardware determines the junction temperature. The junction-to-air thermal resistance in the Thermal
Information table is that of a device installed in the JESD51-3, Low Effective Thermal Conductivity Test Board for
Leaded Surface Mount Packages and is conservative.
200
Safety Limiting Current − mA
175
VCC1, VCC2 = 3.6 V
150
125
100
75
VCC1, VCC2 = 5.5 V
50
25
0
0
50
100
150
200
o
Case Temperature − C
Figure 16. θJC Thermal Derating Curve per VDE
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9.4 Device Functional Modes
Functional modes of ISO72x are shown in Table 1 and Table 2.
Table 1. ISO721 Functional Table
VCC1
VCC2
PU
PU
INPUT
(IN)
OUTPUT
(OUT)
H
H
L
L
Open
H
PD
PU
X
H
X
PD
X
Undetermined
Table 2. ISO722 Functional Table
VCC1
VCC2
PU
PU
INPUT
(IN)
OUTPUT ENABLE
(EN)
OUTPUT
(OUT)
H
L or open
H
L
L or open
L
X
H
Z
Open
L or open
H
H
PD
PU
X
L or open
PD
PU
X
H
Z
X
PD
X
X
Undetermined
9.4.1 Device I/O Schematic
Output
Input
Enable
VCC2
VCC1
VCC1
VCC2
VCC1
VCC2
8W
750 kW
OUT
500 W
IN
500 W
EN
13 W
1 MW
Figure 17. Equivalent Input and Output Schematic Diagrams
22
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The ISO72x devices use single-ended TTL or CMOS-logic-switching technology. The supply voltage range of the
devices is from 3 V to 5.5 V for both supplies, VCC1 and VCC2. When designing with digital isolators, due to the
single-ended design structure, digital isolators do not conform to any specific interface standard and are only
intended for isolating single-ended CMOS or TTL digital signal lines. The isolator is typically placed between the
data controller (μC or UART), and a data converter or a line transceiver, regardless of the interface type or
standard.
10.2 Typical Application
The ISO721 device can be used with Texas Instruments’ microcontroller, CAN transceiver, transformer driver,
and low-dropout voltage regulator to create an Isolated CAN Interface as shown in Figure 18.
VS
10 F
3.3V
2
Vcc
D2
1:2.2 MBR0520L
3
1
SN6501
10 F 0.1 F
D1
GND
4
IN
OUT
ISO 5V
5
TPS76350
3
1
EN
GND
10 F
2
MBR0520L
GND
5
ISO-BARRIER
5,7
GND2
(See Note 1)
0.1 F
6
8
6MHz
18pF
18pF
40 12(1) 3
37
9(1)
VDDC RST VDD VDDA VBAT 25
30
CAN0Rx
OSC0 STELLARIS
26
31
OSC1 LM3S5Y36 CAN0Tx
7
LDO GND GNDA WAKE
0.1 F
10(1)
4
32
(See Note 1)
(1)
OUT ISO721
VCC2
0.1 F
0.1 F
VCC1
0.1 F
4
GND1
IN
VCC1
0.1 F
0.1 F
VCC2
2
1,3
1,3
8
2 IN ISO721 OUT 6
GND1
GND2
4
5,7
4
1
3
VCC
RXD
S 8
CANH
SN65HVD1050
TXD
GND
2
7
6
10
(opt)
10
(opt)
CANL
Vref 5
SM712
4.7nF/
2kV
Multiple pins and capacitors omitted for clarity purpose.
Figure 18. Isolated CAN Interface
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Typical Application (continued)
10.2.1 Design Requirements
Unlike optocouplers which need external components to improve performance and provide bias (or limit current),
the ISO72x devices need only two external bypass capacitors to operate.
10.2.2 Detailed Design Procedure
Typical ISO721 circuit hook-up is shown in Figure 19.
VCC1
VCC2
0.1mF
2 mm
max.
from
VCC1
ISO721
or ISO 721M
1
8
2 mm
max.
from
VCC2
0.1mF
2 IN
7
6
3
OUT
4
5
INPUT
OUTPUT
GND1
GND2
Figure 19. Typical ISO721 Circuit Hook-up
The ISO72x isolators have the same functional pinout as those of most other vendors as shown in Figure 20,
and they are often pin-for-pin drop-in replacements. The notable differences in the products are propagation
delay, signaling rate, power consumption, and transient protection rating. Table 3 is used as a guide for replacing
other isolators with the ISO72x family of single channel isolators.
GND1 4
IN 2
VCC1 3
6 OUT
5 GND2
GND1 4
8 VCC2
7 GND2
VDD1 1
VI 2
VDD1 3
6 OUT
5 GND2
GND1 4
8 VDD2
7 GND2
6 VO
5 GND2
VI 2
*
3
GND1 4
IL710
VDD1
8 VDD2
VI
7 NC
6 VO
NC
5 GND2 GND1
1
2
3
4
Isolation
VCC1 1
VDD1 1
Isolation
8 VCC2
7 EN
HCPL-xxxx
ADuM1100
Isolation
IN 2
VCC1 3
ISO721
or
ISO721M
Isolation
VCC1 1
Isolation
ISO722
or
ISO722M
8 VDD2
7 VOE
6 VO
5 GND2
Figure 20. Pin Cross Reference
Table 3. Cross Reference
PIN 7
ISOLATOR
PIN 1
PIN 2
PIN 3
PIN 4
PIN 5
PIN 6
ISO721
OR
ISO721M
ISO722
OR
ISO722M
PIN 8
ISO721 (1) (2)
VCC1
IN
VCC1
GND1
GND2
OUT
GND2
EN
VCC2
ADuM1100 (1) (2)
VDD1
VI
VDD1
GND1
GND2
VO
GND2
VDD2
GND1
GND2
VO
NC
(4)
VDD2
GND1
GND2
VO
V OE
(1)
(2)
(3)
(4)
(5)
24
HCPL-xxxx
VDD1
VI
*Leave
Open (3)
IL710
VDD1
VI
NC (5)
VDD2
Pin 1 should be used as VCC1. Pin 3 can also be used as VCC1 or left open, as long as pin 1 is connected to VCC1.
Pin 5 should be used as GND2. Pin 7 can also be used as GND2 or left open, as long as pin 5 is connected to GND2.
Pin 3 of the HCPL devices must be left open. This is not a problem when substituting an ISO72x device, because the extra VCC1 on pin
3 can be left an open circuit as well.
An HCPL device pin 7 must be left floating (open) or grounded when an ISO722 or ISO722M device is to be used as a drop-in
replacement. If pin 7 of the ISO722 or ISO722M device is placed in a high logic state, the output of the device is disabled.
Pin 3 of the IL710 must not be tied to ground on the circuit board because this shorts the ISO72x VCC1 to ground. The IL710 pin 3 can
only be tied to VCC or left open to drop in an ISO72x device.
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10.2.3 Application Curves
Figure 21. ISO721M Eye Diagram at 25 Mbps,
3.3 V and 25°C
Figure 22. ISO721M Eye Diagram at 150 Mbps,
3.3 V and 25°C
11 Power Supply Recommendations
To ensure reliable operation at all data rates and supply voltages, a 0.1-μF bypass capacitor should be placed at
input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins as
possible. If only a single primary-side power supply is available in an application, isolated power can be
generated for the secondary-side with the help of a transformer driver such as Texas Instruments SN6501 data
sheet. For such applications, detailed power supply design and transformer selection recommendations are
available in the data sheet, SN6501 Transformer Driver for Isolated Power Supplies (SLLSEA0).
12 Layout
12.1 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design as shown in Figure 23. Layer stacking
should be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane, and lowfrequency signal layer.
• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/in2.
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power/ground plane system to the
stack to keep it symmetrical. Adding a second plane system makes the stack mechanically stable and prevents it
from warping. Also the power and ground plane of each power system can be placed closer together, thus
increasing the high-frequency bypass capacitance significantly. For detailed layout recommendations, see the
Application Note Digital Isolator Design Guide (SLLA284).
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Layout Guidelines (continued)
12.1.1 PCB Material
For digital circuit boards operating below 150 Mbps, (or rise and fall times higher than 1 ns), and trace lengths of
up to 10 inches, use standard FR-4 epoxy-glass as PCB material. FR-4 (Flame Retardant 4) meets the
requirements of Underwriters Laboratories UL94-V0, and is preferred over cheaper alternatives due to its lower
dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and its selfextinguishing flammability-characteristics.
12.2 Layout Example
High-speed traces
10 mils
Ground plane
40 mils
Keep this
space free
from planes,
traces, pads,
and vias
FR-4
0r ~ 4.5
Power plane
10 mils
Low-speed traces
Figure 23. Recommended Layer Stack
26
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13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
Transformer Driver for Isolated Power Supplies, SLLSEA0.
Digital Isolator Design Guide, SLLA284.
Isolation Glossary, SLLA353
13.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 4. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
ISO721
Click here
Click here
Click here
Click here
Click here
ISO721M
Click here
Click here
Click here
Click here
Click here
ISO722
Click here
Click here
Click here
Click here
Click here
ISO722M
Click here
Click here
Click here
Click here
Click here
13.3 Trademarks
SDS is a trademark of Honeywell.
DeviceNet is a trademark of Open Devicenet Vendors Association, Inc.
All other trademarks are the property of their respective owners.
13.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
ISO721D
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
ISO721
Samples
ISO721DG4
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
ISO721
Samples
ISO721DR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
ISO721
Samples
ISO721MD
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
IS721M
Samples
ISO721MDG4
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
IS721M
Samples
ISO721MDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
IS721M
Samples
ISO722D
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
ISO722
Samples
ISO722DR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
ISO722
Samples
ISO722MD
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
IS722M
Samples
ISO722MDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
IS722M
Samples
ISO722MDRG4
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
IS722M
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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