ISO7230C-Q1
ISO7231C-Q1
SLLSE71 – SEPTEMBER 2011
www.ti.com
HIGH SPEED, TRIPLE DIGITAL ISOLATORS
Check for Samples: ISO7230C-Q1, ISO7231C-Q1
FEATURES
1
•
•
•
•
•
•
Qualified for Automotive Applications
25 and 150-Mbps Signaling Rate Options
– Low Channel-to-Channel Output Skew
– Low Pulse-Width Distortion (PWD)
– Low Jitter Content; 1 ns Typ at 150 Mbps
Typical 25-Year Life at Rated Working Voltage
(See Application Note SLLA197 and Figure 14)
4000-Vpeak Isolation, 560-Vpeak VIORM
– UL 1577, IEC 60747-5-2 (VDE 0884, Rev 2),
IE 61010-1, IEC 60950-1 and CSA Approved
4 kV ESD Protection
Operate With 3.3-V or 5-V Supplies
•
•
High Electromagnetic Immunity
(See Application Note SLLA181)
–40°C to 125°C Operating Range
DESCRIPTION
The ISO7230C-Q1 and ISO7231C-Q1 are triple-channel digital isolators each with multiple channel
configurations and output enable functions. These devices have logic input and output buffers separated by TI’s
silicon dioxide (SiO2) isolation barrier. Used in conjunction with isolated power supplies, these devices block high
voltage, isolate grounds, and prevent noise currents on a data bus or other circuits from entering the local ground
and interfering with or damaging sensitive circuitry.
The ISO7230C-Q1 triple-channel device has all three channels in the same direction while the ISO7231C-Q1 has
two channels in one direction and one channel in opposition. These devices have an active-high output enable
that when driven to a low level, places the output in a high-impedance state.
The ISO7230C-Q1 and ISO7231C-Q1 have TTL input thresholds and a noise-filter at the input that prevents
transient pulses of up to 2 ns in duration from being passed to the output of the device.
In each device, a periodic update pulse is sent across the isolation barrier to ensure the proper dc level of the
output. If this dc-refresh pulse is not received, the input is assumed to be unpowered or not being actively driven,
and the failsafe circuit drives the output to a logic high state. (Contact TI for a logic low failsafe option).
These devices require two supply voltages of 3.3-V, 5-V, or any combination. All inputs are 5-V tolerant when
supplied from a 3.3-V supply and all outputs are 4-mA CMOS. These devices are characterized for operation
over the ambient temperature range of –40°C to 125°C.
ISO7231
DW PACKAGE
ISO7230
DW PACKAGE
VCC1
GND1
INA
INB
INC
NC
NC
GND1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC2
GND2
OUTA
OUTB
OUTC
NC
EN
GND2
VCC1
GND1
INA
INB
OUTC
NC
EN1
GND1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC2
GND2
OUTA
OUTB
INC
NC
EN2
GND2
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
ISO7230C-Q1
ISO7231C-Q1
SLLSE71 – SEPTEMBER 2011
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
FUNCTION DIAGRAM
Galvanic Isolation
Barrier
DC Channel
Filter
OSC
+
PWM
Pulse Width
Demodulation
Vref
Carrier Detect
EN
IN
Input
+
Filter
Data MUX
AC Detect
Vref
OUT
Output Buffer
AC Channel
Table 1. Device Function Table ISO723xC-Q1
INPUT VCC
(1)
OUTPUT VCC
PU
PU
PD
PU
PD
PU
(1)
INPUT
(IN)
OUTPUT ENABLE
(EN)
OUTPUT
(OUT)
H
H or Open
H
L
H or Open
L
X
L
Z
Open
H or Open
H
X
H or Open
H
X
L
Z
PU = Powered Up; PD = Powered Down ; X = Irrelevant; H = High Level; L = Low Level
ORDERING INFORMATION (1)
TA
–40°C to 125°C
(1)
2
PACKAGE
SOIC - DW
Reel of 2000
ORDERABLE PART NUMBER
TOP-SIDE MARKING
ISO7230CQDWRQ1
PREVIEW
ISO7231CQDWRQ1
ISO7231CQ
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): ISO7230C-Q1 ISO7231C-Q1
ISO7230C-Q1
ISO7231C-Q1
SLLSE71 – SEPTEMBER 2011
www.ti.com
ABSOLUTE MAXIMUM RATINGS (1)
VALUE
UNIT
VCC
Supply voltage (2), VCC1, VCC2
–0.5 to 6
V
VI
Voltage at IN, OUT, EN
–0.5 to 6
V
IO
Output current
±15
mA
ESD
Human Body Model
Electrostatic
Field-Induced-Charged Device Model
discharge
Machine Model
TJ
(1)
(2)
±4
All pins
Maximum junction temperature
kV
±1
±200
V
150
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal and are peak voltage values.
RECOMMENDED OPERATING CONDITIONS
MIN
TYP
MAX
VCC
Supply voltage (1), VCC1, VCC2
IOH
High-level output current
IOL
Low-level output current
tui
Input pulse width
1/tui
Signaling rate
0
VIH
High-level input voltage (IN) (EN on all devices)
2
VCC
VIL
Low-level input voltage (IN) (EN on all devices)
0
0.8
TA
Operating free-air temperature
-40
125
H
External magnetic field-strength immunity per IEC 61000-4-8 and IEC
61000-4-9 certification
(1)
(2)
3.15
UNIT
5.5
V
–4
mA
4
mA
25
Mbps
40
ns
30 (2)
1000
V
°C
A/m
For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V.
Typical sigalling rate under ideal conditions at 25°C.
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): ISO7230C-Q1 ISO7231C-Q1
3
ISO7230C-Q1
ISO7231C-Q1
SLLSE71 – SEPTEMBER 2011
www.ti.com
ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 5-V (1) OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
ISO7230C-Q1
ICC1
ISO7231C-Q1
ISO7230C-Q1
ICC2
ISO7231C-Q1
Quiescent
25 Mbps
Quiescent
25 Mbps
Quiescent
25 Mbps
Quiescent
25 Mbps
VI = VCC or 0 V, All channels, no load,
EN2 at 3 V
1
3
7
9.5
VI = VCC or 0 V, All channels, no load,
EN1 at 3 V, EN2 at 3 V
6.5
11
11
17
VI = VCC or 0 V, All channels, no load,
EN2 at 3 V
15
22
17
24
13
20
17.5
27
VI = VCC or 0 V, All channels, no load,
EN1 at 3 V, EN2 at 3 V
mA
mA
mA
mA
ELECTRICAL CHARACTERISTICS
IOFF
Sleep mode output current
EN at 0 V, Single channel
VCC – 0.8
IOH = –20 μA, See Figure 1
VCC – 0.1
VOH
High-level output voltage
VOL
Low-level output voltage
VI(HYS)
Input voltage hysteresis
IIH
High-level input current
IIL
Low-level input current
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6πt)
CMTI
Common-mode transient immunity
VI = VCC or 0 V, See Figure 4
(1)
4
μA
0
IOH = –4 mA, See Figure 1
V
IOL = 4 mA, See Figure 1
0.4
IOL = 20 μA, See Figure 1
0.1
150
IN from 0 V to VCC
mV
10
–10
25
V
μA
2
pF
50
kV/μs
For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V.
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): ISO7230C-Q1 ISO7231C-Q1
ISO7230C-Q1
ISO7231C-Q1
SLLSE71 – SEPTEMBER 2011
www.ti.com
SWITCHING CHARACTERISTICS: VCC1 and VCC2 at 5-V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tPLH, tPHL
Propagation delay
PWD
Pulse-width distortion (1) |tPHL – tPLH|
tsk(pp)
Part-to-part skew
tsk(o)
Channel-to-channel output skew
tr
Output signal rise time
tf
Output signal fall time
tPHZ
Propagation delay, high-level-to-high-impedance
output
tPZH
Propagation delay, high-impedance-to-high-level
output
(3)
18
tPZL
Propagation delay, high-impedance-to-low-level
output
tfs
Failsafe output delay time from input power loss
MAX
45
5
0
See Figure 1
Propagation delay, low-level-to-high-impedance
output
(3)
TYP
(2)
tPLZ
(1)
(2)
See Figure 1
MIN
ns
8
ns
4
ns
2
ns
2
15
25
15
25
15
25
15
25
See Figure 2
See Figure 3
UNIT
ns
12
μs
Also referred to as pulse skew.
tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): ISO7230C-Q1 ISO7231C-Q1
5
ISO7230C-Q1
ISO7231C-Q1
SLLSE71 – SEPTEMBER 2011
www.ti.com
ELECTRICAL CHARACTERISTICS: VCC1 at 5-V, VCC2 at 3.3-V (1) OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
SUPPLY CURRENT
ISO7230C-Q1
ICC1
ISO7231C-Q1
ISO7230C-Q1
ICC2
ISO7231C-Q1
Quiescent
25 Mbps
Quiescent
25 Mbps
Quiescent
25 Mbps
Quiescent
25 Mbps
VI = VCC or 0 V, All channels, no load, EN2 at 3 V
VI = VCC or 0 V, All channels, no load, EN1 at 3 V,
EN2 at 3 V
VI = VCC or 0 V, All channels, no load, EN2 at 3 V
VI = VCC or 0 V, All channels, no load, EN1 at 3 V,
EN2 at 3 V
1
3
7
9.5
6.5
11
11
17
9
15
10
17
8
12
10.5
16
mA
mA
mA
mA
ELECTRICAL CHARACTERISTICS
IOFF
Sleep mode output current
VOH
High-level output voltage
EN at 0 V, Single channel
IOH = –4 mA, See Figure 1
VCC – 0.4
ISO7231C-Q1
(5-V side)
VCC – 0.8
IOH = –20 μA, See Figure 1
VCC – 0.1
0.4
IOL = 20 μA, See Figure 1
0.1
Low-level output voltage
VI(HYS)
Input voltage hysteresis
IIH
High-level input current
IIL
Low-level input current
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6πt)
CMTI
Common-mode transient
immunity
VI = VCC or 0 V, See Figure 4
6
V
IOL = 4 mA, See Figure 1
VOL
(1)
μA
0
ISO7230C-Q1
150
IN from 0 V to VCC
mV
10
–10
25
V
μA
2
pF
50
kV/μs
For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V.
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): ISO7230C-Q1 ISO7231C-Q1
ISO7230C-Q1
ISO7231C-Q1
SLLSE71 – SEPTEMBER 2011
www.ti.com
SWITCHING CHARACTERISTICS: VCC1 at 5-V, VCC2 at 3.3-V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tPLH, tPHL
Propagation delay, low-to-high-level output
PWD
Pulse-width distortion (1) |tPHL – tPLH|
tsk(pp)
Part-to-part skew
tsk(o)
Channel-to-channel output skew
tr
Output signal rise time
tf
Output signal fall time
tPHZ
Propagation delay, high-level-to-high-impedance
output
tPZH
Propagation delay, high-impedance-to-high-level
output
(3)
20
tPZL
Propagation delay, high-impedance-to-low-level
output
tfs
Failsafe output delay time from input power loss
MAX
UNIT
50
4
0
See Figure 1
Propagation delay, low-level-to-high-impedance
output
(3)
TYP
(2)
tPLZ
(1)
(2)
See Figure 1
MIN
10
ns
4
ns
2
ns
2
15
25
15
25
15
25
15
25
See Figure 2
See Figure 3
ns
ns
18
μs
Also known as pulse skew
tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): ISO7230C-Q1 ISO7231C-Q1
7
ISO7230C-Q1
ISO7231C-Q1
SLLSE71 – SEPTEMBER 2011
www.ti.com
ELECTRICAL CHARACTERISTICS: VCC1 at 3.3-V, VCC2 at 5-V (1) OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
SUPPLY CURRENT
ISO7230C-Q1
ICC1
ISO7231C-Q1
ISO7230C-Q1
ICC2
ISO7231C-Q1
Quiescent
25 Mbps
Quiescent
25 Mbps
Quiescent
25 Mbps
Quiescent
25 Mbps
VI = VCC or 0 V, All channels, no load, EN2 at 3 V
VI = VCC or 0 V, All channels, no load, EN1 at 3 V,
EN2 at 3 V
VI = VCC or 0 V, All channels, no load, EN2 at 3 V
VI = VCC or 0 V, All channels, no load, EN1 at 3 V,
EN2 at 3 V
0.5
1
3
5
4.5
7
6.5
11
15
22
17
24
13
20
17.5
27
mA
mA
mA
mA
ELECTRICAL CHARACTERISTICS
IOFF
Sleep mode output current
EN at 0 V, Single channel
IOH = –4 mA, See Figure 1
VOH
High-level output voltage
VCC – 0.4
ISO7231C-Q1
(5-V side)
VCC – 0.8
IOH = –20 μA, See Figure 1
VCC – 0.1
0.4
IOL = 20 μA, See Figure 1
0.1
Low-level output voltage
VI(HYS)
Input voltage hysteresis
IIH
High-level input current
IIL
Low-level input current
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6πt)
CMTI
Common-mode transient
immunity
VI = VCC or 0 V, See Figure 4
8
V
IOL = 4 mA, See Figure 1
VOL
(1)
μA
0
ISO7230C-Q1
150
IN from 0 V to VCC
mV
10
–10
25
V
μA
2
pF
50
kV/μs
For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V.
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): ISO7230C-Q1 ISO7231C-Q1
ISO7230C-Q1
ISO7231C-Q1
SLLSE71 – SEPTEMBER 2011
www.ti.com
SWITCHING CHARACTERISTICS: VCC1 at 3.3-V and VCC2 at 5-V OPERATION
, over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tPLH, tPHL
Propagation delay
PWD
Pulse-width distortion (1) |tPHL – tPLH|
Part-to-part skew
tsk(o)
Channel-to-channel output skew
tr
Output signal rise time
tf
Output signal fall time
tPHZ
Propagation delay, high-level-to-high-impedance
output
tPZH
Propagation delay, high-impedance-to-high-level
output
(3)
Propagation delay, low-level-to-high-impedance
output
tPZL
Propagation delay, high-impedance-to-low-level
output
tfs
Failsafe output delay time from input power loss
MAX
51
4
0
See Figure 1
tPLZ
(3)
TYP
20
(2)
tsk(pp)
(1)
(2)
See Figure 1
MIN
ns
10
ns
4
ns
2
ns
2
15
25
15
25
15
25
15
25
See Figure 2
See Figure 3
UNIT
ns
12
μs
Also known as pulse skew
tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): ISO7230C-Q1 ISO7231C-Q1
9
ISO7230C-Q1
ISO7231C-Q1
SLLSE71 – SEPTEMBER 2011
www.ti.com
ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 3.3 V (1) OPERATION
, over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
VI = VCC or 0 V, all channels, no load,
EN2 at 3 V
0.5
1
3
5
VI = VCC or 0 V, all channels, no load,
EN1 at 3 V, EN2 at 3 V
4.5
7
6.5
11
UNIT
SUPPLY CURRENT
ISO7230C-Q1
ICC1
ISO7231C-Q1
ISO7230C-Q1
ICC2
ISO7231C-Q1
Quiescent
25 Mbps
Quiescent
25 Mbps
Quiescent
25 Mbps
Quiescent
25 Mbps
VI = VCC or 0 V, all channels, no load,
EN2 at 3 V
9
15
10
17
VI = VCC or 0 V, all channels, no load,
EN1 at 3 V, EN2 at 3 V
8
12
10.5
16
mA
mA
mA
mA
ELECTRICAL CHARACTERISTICS
IOFF
Sleep mode output current
EN at 0 V, single channel
VCC – 0.4
IOH = –20 μA, See Figure 1
VCC – 0.1
VOH
High-level output voltage
VOL
Low-level output voltage
VI(HYS)
Input voltage hysteresis
IIH
High-level input current
IIL
Low-level input current
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6πt)
CMTI
Common-mode transient immunity
VI = VCC or 0 V, See Figure 4
(1)
10
μA
0
IOH = –4 mA, See Figure 1
V
IOL = 4 mA, See Figure 1
0.4
IOL = 20 μA, See Figure 1
0.1
150
IN from 0 V or VCC
mV
10
–10
25
V
μA
2
pF
50
kV/μs
For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V.
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): ISO7230C-Q1 ISO7231C-Q1
ISO7230C-Q1
ISO7231C-Q1
SLLSE71 – SEPTEMBER 2011
www.ti.com
SWITCHING CHARACTERISTICS: VCC1 and VCC2 at 3.3-V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tPLH, tPHL
Propagation delay
PWD
Pulse-width distortion (1) |tPHL – tPLH|
See Figure 1
MIN
TYP
25
4
tsk(pp)
Part-to-part skew
tsk(o)
Channel-to-channel output skew
0
tr
Output signal rise time
2
tf
Output signal fall time
tPHZ
Propagation delay,
high-level-to-high-impedance output
tPZH
Propagation delay,
high-impedance-to-high-level output
tPLZ
Propagation delay,
low-level-to-high-impedance output
tPZL
Propagation delay,
high-impedance-to-low-level output
tfs
(1)
(2)
Failsafe output delay time from input power
loss
UNIT
56
(2)
See Figure 1
MAX
10
ns
4
ns
ns
2
15
25
15
25
15
25
15
25
See Figure 2
See Figure 3
ns
ns
18
μs
Also referred to as pulse skew.
tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): ISO7230C-Q1 ISO7231C-Q1
11
ISO7230C-Q1
ISO7231C-Q1
SLLSE71 – SEPTEMBER 2011
www.ti.com
ISOLATION BARRIER
PARAMETER MEASUREMENT INFORMATION
IN
Input
Generator
VI
50 W
NOTE A
VCC
VI
VCC/2
VCC/2
OUT
0V
tPHL
tPLH
CL
NOTE B
VO
VO
VOH
90%
50%
50%
10%
tr
VOL
tf
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50Ω.
B.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 1. Switching Characteristic Test Circuit and Voltage Waveforms
VCC
VCC
ISOLATION BARRIER
RL = 1 kW ±1%
IN
0V
Input
Generator
VI
OUT
EN
t PZL
VO
CL
VCC/2
VI
VO
VCC/2
0V
t PLZ
VCC
0.5 V
50%
NOTE
B
50 W
VOL
NOTE A
ISOLATION BARRIER
3V
VCC
IN
Input
Generator
VI
OUT
VO
VCC/2
VI
VCC/2
0V
t PZH
EN
50 W
CL
NOTE
B
RL = 1 kW ±1%
VO
VOH
50%
0.5 V
t PHZ
0V
NOTE A
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50Ω.
B.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 2. Enable/Disable Propagation Delay Time Test Circuit and Waveform
12
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): ISO7230C-Q1 ISO7231C-Q1
ISO7230C-Q1
ISO7231C-Q1
SLLSE71 – SEPTEMBER 2011
www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
VI
0V
or
VCC
ISOLATION BARRIER
VCC
IN
VCC
OUT
VI
2.7 V
VO
0V
VOH
tfs
CL
NOTE B
VO
50%
VOL
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50Ω.
B.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 3. Failsafe Delay Time Test Circuit and Voltage Waveforms
VCC1
VCC2
ISOLATION BARRIER
C = 0.1 mF± 1%
IN
S1
GND1
C = 0.1 mF± 1%
OUT
NOTE B
Pass-fail criteria:
Output must
remain stable
VOH or VOL
GND2
VCM
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50Ω.
B.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 4. Common-Mode Transient Immunity Test Circuit and Voltage Waveform
VCC
DUT
Tektronix
HFS9009
IN
OUT
0V
Tektronix
784D
PATTERN
GENERATOR
VCC/2
Jitter
NOTE: PRBS bit pattern run length is 216 – 1. Transition time is 800 ps. NRZ data input has no more than five consecutive 1s
or 0s.
Figure 5. Peak-to-Peak Eye-Pattern Jitter Test Circuit and Voltage Waveform
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): ISO7230C-Q1 ISO7231C-Q1
13
ISO7230C-Q1
ISO7231C-Q1
SLLSE71 – SEPTEMBER 2011
www.ti.com
DEVICE INFORMATION
PACKAGE CHARACTERISTICS
PARAMETER
L(I01)
L(I02)
RIO
TEST CONDITIONS
MIN
TYP MAX
UNIT
Minimum air gap (Clearance)
Shortest terminal-to-terminal distance through air
8.34
mm
Minimum external tracking (Creepage)
Shortest terminal-to-terminal distance across the
package surface
8.1
mm
Minimum Internal Gap (Internal
Clearance)
Distance through the insulation
0.008
mm
Isolation resistance
Input to output, VIO = 500 V, all pins on each side of the
barrier tied together creating a two-terminal device,
TA < 100°C
>1012
Input to output, VIO = 500 V, 100°C ≤ TA ≤ TA max
>1011
Ω
Ω
CIO
Barrier capacitance Input to output
VI = 0.4 sin (4E6πt)
2
pF
CI
Input capacitance to ground
VI = 0.4 sin (4E6πt)
2
pF
REGULATORY INFORMATION
VDE
CSA
UL
Certified according to IEC
60747-5-2
Approved under CSA Component
Acceptance Notice
Recognized under 1577
Component Recognition
Program (1)
File Number: 40016131
File Number: 220991
File Number: E181974
(1)
Production tested ≥ 3000 VRMS for 1 second in accordance with UL 1577.
DEVICE I/O SCHEMATICS
Enable
VCC2
Output
Input
VCC2
VCC1
VCC2
VCC1
1 MW
VCC1
VCC2
1 MW
500 W
IN
EN
500 W
8W
OUT
13 W
NOTE: Input is assumed to be on VCC1 side and Output on VCC2 side.
THERMAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
Low-K Thermal Resistance (1)
168
High-K Thermal Resistance
96.1
UNIT
θJA
Junction-to-air
θJB
Junction-to-Board Thermal Resistance
61
°C/W
θJC
Junction-to-Case Thermal Resistance
48
°C/W
PD
Device Power Dissipation
(1)
14
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
Input a 50% duty cycle square wave
°C/W
220
mW
Tested in accordance with the Low-K or High-K thermal metric definitions of EIA/JESD51-3 for leaded surface mount packages.
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): ISO7230C-Q1 ISO7231C-Q1
ISO7230C-Q1
ISO7231C-Q1
SLLSE71 – SEPTEMBER 2011
www.ti.com
TYPICAL CHARACTERISTIC CURVES
ISO7230 C/M RMS SUPPLY CURRENT
vs
SIGNALING RATE
ISO7231 C/M RMS SUPPLY CURRENT
vs
SIGNALING RATE
45
40
ICC - Supply Current - mA/RMS
ICC - Supply Current - mA/RMS
40
45
TA = 25°C,
Load = 15 pF,
All Channels
35
30
5-V ICC2
3.3-V ICC2
25
20
15
5-V ICC1
10
3.3-V ICC1
5
35
5-V ICC1
30
25
5-V ICC2
20
15
10
25
50
75
100
125
0
0
150
3.3-V ICC2
3.3-V ICC1
5
0
0
25
50
75
100
125
Signaling Rate - Mbps
Signaling Rate - Mbps
Figure 6.
Figure 7.
PROPAGATION DELAY
vs
FREE-AIR TEMPERATURE
INPUT THRESHOLD VOLTAGE
vs
FREE-AIR TEMPERATURE
45
150
1.4
40
Input Voltage Threshold - V
35
C 5-V tpLH, tpHL
30
25
20
M 3.3-V tpLH, tpHL
15
M 5-V tpLH, tpHL
10
TA = 25°C,
Load = 15 pF,
All Channels
5
-25
-10
1.3
3.3 V Vth+
1.25
1.2
Air Flow at 7 cf/m,
Low-K Board
1.15
5 V Vth1.1
1.05
3.3 V Vth-
0
-40
5 V Vth+
1.35
C 3.3-V tpLH, tpHL
Propagation Delay - ns
TA = 25°C,
Load = 15 pF,
All Channels
5
80
65
35
20
50
TA - Free-Air Temperature - °C
95
110
125
1
-40
-25
-10
5
20
35
50
65
80
TA - Free-Air Temperature - °C
Figure 8.
95
110
125
Figure 9.
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): ISO7230C-Q1 ISO7231C-Q1
15
ISO7230C-Q1
ISO7231C-Q1
SLLSE71 – SEPTEMBER 2011
www.ti.com
TYPICAL CHARACTERISTIC CURVES (continued)
VCC1 FAILSAFE THRESHOLD
vs
FREE-AIR TEMPERATURE
HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
50
3
2.8
VCC = 5 V
Load = 15 pF,
TA = 25°C
40
2.7
IO - Output Current - mA
VCC1 - Failsafe Threshold - V
2.9
VCC at 5 V or 3.3 V,
Load = 15 pF,
Air Flow at 7/cf/m,
Low-K Board
Vfs+
2.6
2.5
Vfs-
2.4
2.3
2.2
VCC = 3.3 V
30
20
10
2.1
2
-40
-25
-10
5
20
35
50
65
80
95
110
0
0
125
2
TA - Free-Air Temperature - °C
Figure 10.
4
VO - Output Voltage - V
6
Figure 11.
LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
50
Load = 15 pF,
TA = 25°C
45
IO - Output Current - mA
40
35
VCC = 3.3 V
30
25
VCC = 5 V
20
15
10
5
0
0
1
2
3
VO - Output Voltage - V
4
5
Figure 12.
16
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): ISO7230C-Q1 ISO7231C-Q1
ISO7230C-Q1
ISO7231C-Q1
SLLSE71 – SEPTEMBER 2011
www.ti.com
APPLICATION INFORMATION
2 mm
max. from
VCC1
VCC1
2 mm
max. from
VCC2
VCC2
0.1 mF
0.1 mF
1
16
2
15
IN A
3
14
OUT A
IN B
4
13
OUT B
IN C
5
12
OUT C
NC
6
11
NC
7
10
8
9
GND2
GND1
NC
EN
GND2
GND1
ISO7230
Figure 13. Typical ISO7230 Application Circuit
LIFE EXPECTANCY vs WORKING VOLTAGE
WORKING LIFE -- YEARS
100
VIORM at 560-V
28 Years
10
0
120
250
500
750
880
1000
WORKING VOLTAGE (VIORM) -- V
Figure 14. Time Dependant Dielectric Breakdown Testing Results
Submit Documentation Feedback
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): ISO7230C-Q1 ISO7231C-Q1
17
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
ISO7231CQDWRQ1
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
ISO7231CQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
