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ISO7230C, ISO7230M, ISO7231C, ISO7231M
SLLS867K – SEPTEMBER 2007 – REVISED OCTOBER 2015
ISO723xx High-Speed, Triple-Channel Digital Isolators
1 Features
2 Applications
•
•
•
•
•
1
•
•
•
•
•
•
•
25 and 150-Mbps Signaling Rate Options
– Low Channel-to-Channel Output Skew;
1 ns Maximum
– Low Pulse-Width Distortion (PWD);
2 ns Maximum
– Low Jitter Content; 1 ns Typical at 150 Mbps
Typical 25-Year Life at Rated Working Voltage
(See Application Note SLLA197 and Figure 19)
4-kV ESD Protection
Operate With 3.3-V or 5-V Supplies
3.3-V and 5-V Level Translation
High Electromagnetic Immunity
(See Application Note SLLA181)
–40°C to 125°C Operating Range
Safety and Regulatory Approvals
– 4000-VPK Isolation per DIN V VDE V 0884-10
and DIN EN 61010-1
– 2500 VRMS Isolation for 1 minute per UL 1577
– CSA Component Acceptance Notice 5A and
IEC 60950-1 End Equipment Standard
Industrial Fieldbus
Computer Peripheral Interface
Servo Control Interface
Data Acquisition
3 Description
The ISO7230 and ISO7231 are triple-channel digital
isolators each with multiple channel configurations
and output enable functions. These devices have
logic input and output buffers separated by TI’s
silicon dioxide (SiO2) isolation barrier. Used in
conjunction with isolated power supplies, these
devices block high voltage, isolate grounds, and
prevent noise currents on a data bus or other circuits
from entering the local ground and interfering with or
damaging sensitive circuitry.
Device Information(1)
PART NUMBER
ISO7230C
ISO7230M
ISO7231C
ISO7231M
PACKAGE
BODY SIZE (NOM)
SOIC (16)
10.30 mm × 7.50 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
VCCI
Isolation
Capacitor
VCCO
INx
OUTx
ENx
GNDI
GNDO
(1)
VCCI and GNDI are supply and ground connections respectively for the input channels.
(2)
VCCO and GNDO are supply and ground connections respectively for the output channels.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ISO7230C, ISO7230M, ISO7231C, ISO7231M
SLLS867K – SEPTEMBER 2007 – REVISED OCTOBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
4
5
7.1
7.2
7.3
7.4
7.5
7.6
Absolute Maximum Ratings ..................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 6
Electrical Characteristics: VCC1 and VCC2 at 5-V ...... 6
Electrical Characteristics: VCC1 at 5-V, VCC2 at 3.3V................................................................................. 7
7.7 Electrical Characteristics: VCC1 at 3.3-V, VCC2 at 5-V
................................................................................... 8
7.8 Electrical Characteristics: VCC1 and VCC2 at 3.3 V ... 9
7.9 Power Dissipation Characteristics ............................ 9
7.10 Switching Characteristics: VCC1 and VCC2 at 5-V . 10
7.11 Switching Characteristics: VCC1 at 5-V, VCC2 at 3.3V............................................................................... 11
7.12 Switching Characteristics: VCC1 at 3.3-V and VCC2
at 5-V ....................................................................... 12
7.13 Switching Characteristics: VCC1 and VCC2 at 3.3-
V............................................................................... 12
7.14 Typical Characteristics .......................................... 13
8
9
Parameter Measurement Information ................ 15
Detailed Description ............................................ 17
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
17
17
18
19
10 Application and Implementation........................ 21
10.1 Application Information.......................................... 21
10.2 Typical Application ............................................... 21
11 Power Supply Recommendations ..................... 24
12 Layout................................................................... 24
12.1 Layout Guidelines ................................................. 24
12.2 Layout Example .................................................... 24
13 Device and Documentation Support ................. 25
13.1
13.2
13.3
13.4
13.5
13.6
Related Documentation.........................................
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
25
25
25
25
25
25
14 Mechanical, Packaging, and Orderable
Information ........................................................... 25
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision J (May 2015) to Revision K
Page
•
Added Note 1 to L(I01) and changed the MIN value From: 8.34 To 8 mm in the Package Insulation and SafetyRelated Specifications table ................................................................................................................................................ 18
•
Added Note 1 to LI02) and changed the MIN value From: 8.1 To 8 mm in the Package Insulation and SafetyRelated Specifications table ................................................................................................................................................ 18
•
Deleted Note 1 From the Regulatory Information table ....................................................................................................... 18
•
Changed The ground symbols on the Enable circuit in Figure 15 ....................................................................................... 20
Changes from Revision I (January 2011) to Revision J
Page
•
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
•
Updated Thermal Information ................................................................................................................................................ 6
•
Updated Regulatory Information........................................................................................................................................... 18
Changes from Revision H (December 2009) to Revision I
Page
•
Changed IOH Min value to -4 and deleted the Max value, in the Recommended Operating Conditions Table...................... 5
•
Changed IOL Max value to 4 and deleted the Min value, in the Recommended Operating Conditions Table ....................... 5
•
Changed Figure 8, Figure 10, Figure 11, and Figure 12...................................................................................................... 15
•
Changed File Number: 1698195 To: 220991 ....................................................................................................................... 18
2
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SLLS867K – SEPTEMBER 2007 – REVISED OCTOBER 2015
Changes from Revision G (September 2009) to Revision H
•
Page
Changed The Input circuit in Figure 15 ................................................................................................................................ 20
Changes from Revision F (December 2008) to Revision G
•
Page
Added IEC 60950-1 and CSA Approved to the Features list ................................................................................................. 1
Changes from Revision E (June 2008) to Revision F
Page
•
Deleted device numbers ISO7230A and ISO7231A from the data sheet. ............................................................................. 1
•
Added tsk(pp) footnote............................................................................................................................................................. 10
•
Added tsk(o) footnote. ............................................................................................................................................................. 10
•
Added tsk(pp) footnote............................................................................................................................................................. 12
•
Added tsk(o) footnote. ............................................................................................................................................................. 12
•
Changed the Package Insulation and Safety-Related Specifications table, line 1, L(IO1) MIN from 7.7 to 8.34 ................... 18
Changes from Revision D (May 2008) to Revision E
Page
•
Added Note: For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V. For the 3-V operation, VCC1 or
VCC2 is specified from 3.15 V to 3.6 V.................................................................................................................................. 6
•
Added Note: For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V. For the 3-V operation, VCC1 or
VCC2 is specified from 3.15 V to 3.6 V.................................................................................................................................. 7
•
Added Note: For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V. For the 3-V operation, VCC1 or
VCC2 is specified from 3.15 V to 3.6 V.................................................................................................................................. 8
•
Added Note: For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V. For the 3-V operation, VCC1 or
VCC2 is specified from 3.15 V to 3.6 V.................................................................................................................................. 9
Changes from Revision C (April 2008) to Revision D
Page
•
Changed Features bullet 4000-Vpeak Isolation to the Features list ......................................................................................... 1
•
Added tsk(pp) Part-to-part skew .............................................................................................................................................. 10
•
Added tsk(pp) Part-to-part skew .............................................................................................................................................. 11
•
Added tsk(pp) Part-to-part skew .............................................................................................................................................. 12
•
Added tsk(pp) Part-to-part skew .............................................................................................................................................. 12
Changes from Revision B (April 2008) to Revision C
Page
•
Deleted Min = 4.5 V and max = 5.5 V for Supply Voltage of the Recommended Operating Conditions Table .................... 5
•
Changed Supply Voltage of the Recommended Operating Conditions Table From: 3.6 To: 5.5 ......................................... 5
Changes from Revision A (December 2007) to Revision B
•
Page
Changed Supply Voltage of the ROC Table From: 3.45 To: 3.6 ........................................................................................... 5
Changes from Original (September 2007) to Revision A
Page
•
Deleted Product Preview note ................................................................................................................................................ 4
•
Changed TBD to actual values............................................................................................................................................... 6
•
Changed VCC – 0.4 To: VCC – 0.8........................................................................................................................................... 6
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ISO7230C, ISO7230M, ISO7231C, ISO7231M
SLLS867K – SEPTEMBER 2007 – REVISED OCTOBER 2015
www.ti.com
•
Changed CI - Typical value from 1 To: 2................................................................................................................................ 6
•
Changed CI - Typical value from 1 To: 2................................................................................................................................ 7
•
Changed CI - Typical value from 1 To: 2................................................................................................................................ 8
•
Changed CI - Typical value from 1 To: 2................................................................................................................................ 9
•
Changed Propagation delay max From: 22 To: 23 .............................................................................................................. 10
•
Changed Propagation delay max From: 46 To: 50 .............................................................................................................. 11
•
Changed Propagation delay max From: 28 To: 29 .............................................................................................................. 11
•
Changed Propagation delay max From: 26 To: 30 .............................................................................................................. 12
•
Changed Propagation delay max From: 32 To: 34 .............................................................................................................. 12
•
Changed CIO - Typical value from 1 To: 2............................................................................................................................ 18
4
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SLLS867K – SEPTEMBER 2007 – REVISED OCTOBER 2015
5 Device Comparison Table
PRODUCT
SIGNALING
RATE
INPUT
THRESHOLD
CHANNEL
CONFIGURATION
ISO7230C
25 Mbps
~1.5 V (TTL)
(CMOS
compatible)
3/0
ISO7230M
150 Mbps
VCC/2 (CMOS)
ISO7231C
25 Mbps
~1.5 V (TTL)
(CMOS
compatible)
ISO7231M
150 Mbps
VCC/2 (CMOS)
ISOLATION
RATING
4000 VPK,
2500 VRMS
2/1
6 Pin Configuration and Functions
DW Package
16-Pin SOIC
Top View
ISO7231
ISO7230
VCC1
GND1
INA
INB
INC
NC
NC
GND1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC2
GND2
OUTA
OUTB
OUTC
NC
EN
GND2
VCC1
GND1
INA
INB
OUTC
NC
EN1
GND1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC2
GND2
OUTA
OUTB
INC
NC
EN2
GND2
Pin Functions
PIN
NAME
TYPE
DESCRIPTION
ISO7230
ISO7231
EN
10
–
I
Enable, channel A, B, and C
EN1
–
7
I
Enable, channel C
EN2
–
10
I
Enable, channel A and B
GND1
2, 8
2, 8
–
Ground connection for VCC1
GND2
9, 15
9. 15
–
Ground connection for VCC2
INA
3
3
I
Input, channel A
INB
4
4
I
Input, channel B
INC
5
12
I
Input, channel C
NC
6, 7, 11
6, 11
–
Not connected
OUTA
14
14
O
Output, channel A
OUTB
13
13
O
Output, channel B
OUTC
12
5
O
Output, channel C
VCC1
1
1
–
Power supply, VCC1
VCC2
16
16
–
Power supply, VCC2
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ISO7230C, ISO7230M, ISO7231C, ISO7231M
SLLS867K – SEPTEMBER 2007 – REVISED OCTOBER 2015
www.ti.com
7 Specifications
7.1 Absolute Maximum Ratings (1)
MIN
MAX
UNIT
VCC
Supply voltage (2), VCC1, VCC2
–0.5
6
V
VI
Voltage at INx, OUTx, ENx
–0.5
VCC + 0.5 (3)
V
IO
Output current
–15
15
mA
TJ
Maximum junction temperature
170
°C
Tstg
Storage temperature
150
°C
(1)
(2)
(3)
–65
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal and are peak voltage values.
Maximum voltage must not exceed 6 V.
7.2 ESD Ratings
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
±4000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1000
Machine model (MM), ANSI/ESDS5.2-1996
±200
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN
VCC1,
VCC2
Supply voltage - 3.3-V Operation
IOH
High-level output current
IOL
Low-level output current
3.15
Supply voltage - 5-V Operation
Input pulse width
1/tui
Signaling rate
VIH
High-level input voltage (IN)
VIL
Low-level input voltage (IN)
VIH
High-level input voltage (IN) (EN on all
devices)
5.5
–4
40
ISO723xM
6.67
5
ISO723xC
0
30 (1)
25
ISO723xM
0
200 (1)
150
ISO723xM
UNIT
V
mA
ISO723xC
mA
ns
0.7 VCC
VCC
0
0.3 VCC
2
5.5
0
0.8
ISO723xC
Mbps
V
V
VIL
Low-level input voltage (IN) (EN on all
devices)
TA
Ambient temperature
TJ
Junction temperature
H
External magnetic field-strength immunity per IEC 61000-4-8 and IEC 61000-4-9
6
MAX
4
tui
(1)
NOM
-40
25
125
°C
150
°C
1000
A/m
Typical sigalling rate under ideal conditions at 25°C.
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7.4 Thermal Information
ISO7230C,
ISO7230M
ISO7231C,
ISO7231M
THERMAL METRIC (1)
UNIT
DW (SOIC)
16 PINS
168
°C/W
77.3
°C/W
39.5
°C/W
Junction-to-board thermal resistance
41.9
°C/W
ψJT
Junction-to-top characterization parameter
13.5
°C/W
ψJB
Junction-to-board characterization parameter
41.9
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
°C/W
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
RθJB
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
7.5 Electrical Characteristics: VCC1 and VCC2 at 5-V (1)
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
Quiescent
ISO7230C/M
25 Mbps
ICC1
Quiescent
ISO7231C/M
25 Mbps
Quiescent
ISO7230C/M
25 Mbps
ICC2
Quiescent
ISO7231C/M
25 Mbps
VI = VCCI or 0 V, all channels, no load,
EN at 3 V
1
3
7
9.5
VI = VCCI or 0 V, all channels, no load,
EN1 at 3 V, EN2 at 3 V
6.5
11
11
17
VI = VCCI or 0 V, all channels, no load,
EN at 3 V
15
22
17
24
VI = VCCI or 0 V, all channels, no load,
EN1 at 3 V, EN2 at 3 V
13
20
17.5
27
mA
mA
mA
mA
ELECTRICAL CHARACTERISTICS
IOFF
Sleep mode output current
ENx at 0 V, single channel
IOH = –4 mA, See Figure 8
VCCO –
0.8
IOH = –20 μA, See Figure 8
VCCO –
0.1
VOH
High-level output voltage
VOL
Low-level output voltage
VI(HYS)
Input voltage hysteresis
IIH
High-level input current
INx at VCCI
IIL
Low-level input current
INx at 0 V
CI
Input capacitance to ground
INx at VCCI, VI = 0.4 sin (4E6πt)
CMTI
Common-mode transient immunity
VI = VCCI or 0 V, See Figure 11
(1)
μA
0
V
IOL = 4 mA, See Figure 8
0.4
IOL = 20 μA, See Figure 8
0.1
V
150
mV
10
μA
–10
25
2
pF
50
kV/μs
For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3.3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V.
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7.6 Electrical Characteristics: VCC1 at 5-V, VCC2 at 3.3-V (1)
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
ISO7230C/M
ICC1
ISO7231C/M
ISO7230C/M
ICC2
ISO7231C/M
Quiescent
25 Mbps
Quiescent
25 Mbps
Quiescent
25 Mbps
Quiescent
25 Mbps
VI = VCCI or 0 V, all channels, no load, EN at 3 V
VI = VCCI or 0 V, all channels, no load, EN1 at 3 V,
EN2 at 3 V
VI = VCCI or 0 V, all channels, no load, EN at 3 V
VI = VCCI or 0 V, all channels, no load, EN1 at 3 V,
EN2 at 3 V
1
3
7
9.5
6.5
11
11
17
9
15
10
17
8
12
10.5
16
mA
mA
mA
mA
ELECTRICAL CHARACTERISTICS
IOFF
Sleep mode output current
VOH
High-level output voltage
ENx at 0 V, Single channel
IOH = –4 mA, See Figure 8
IOH = –20 μA, See Figure 8
ISO7231
(5-V side)
VCCO – 0.8
V
VCCO – 0.1
0.4
IOL = 20 μA, See Figure 8
0.1
Low-level output voltage
VI(HYS)
Input voltage hysteresis
IIH
High-level input current
INx at VCCI
IIL
Low-level input current
INx at 0 V
CI
Input capacitance to ground
INx at VCCI, VI = 0.4 sin (4E6πt)
CMTI
Common-mode transient
immunity
VI = VCCI or 0 V, See Figure 11
8
VCCO – 0.4
IOL = 4 mA, See Figure 8
VOL
(1)
μA
0
ISO7230
150
mV
10
–10
25
V
μA
2
pF
50
kV/μs
For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3.3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V.
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7.7 Electrical Characteristics: VCC1 at 3.3-V, VCC2 at 5-V (1)
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.5
1
3
5
4.5
7
6.5
11
15
22
17
24
13
20
17.5
27
UNIT
SUPPLY CURRENT
ISO7230C/M
ICC1
ISO7231C/M
ISO7230C/M
ICC2
ISO7231C/M
Quiescent
25 Mbps
Quiescent
25 Mbps
Quiescent
25 Mbps
Quiescent
25 Mbps
VI = VCCI or 0 V, all channels, no load, EN at 3 V
VI = VCCI or 0 V, all channels, no load, EN1 at 3 V,
EN2 at 3 V
VI = VCCI or 0 V, all channels, no load, EN at 3 V
VI = VCCI or 0 V, all channels, no load, EN1 at 3 V,
EN2 at 3 V
mA
mA
mA
mA
ELECTRICAL CHARACTERISTICS
IOFF
Sleep mode output current
ENx at 0 V, Single channel
IOH = –4 mA, See Figure 8
VOH
High-level output voltage
IOH = –20 μA, See Figure 8
VCCO – 0.4
ISO7231
(5-V side)
VCCO – 0.8
V
VCCO – 0.1
IOL = 4 mA, See Figure 8
0.4
IOL = 20 μA, See Figure 8
0.1
VOL
Low-level output voltage
VI(HYS)
Input voltage hysteresis
IIH
High-level input current
INx at VCCI
IIL
Low-level input current
INx at 0 V
CI
Input capacitance to ground
INx at VCCI, VI = 0.4 sin (4E6πt)
CMTI
Common-mode transient
immunity
VI = VCCI or 0 V, See Figure 11
(1)
μA
0
ISO7230
V
150
mV
10
μA
–10
25
2
pF
50
kV/μs
For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3.3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V.
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7.8 Electrical Characteristics: VCC1 and VCC2 at 3.3 V (1)
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
VI = VCCI or 0 V, all channels, no load,
EN at 3 V
0.5
1
3
5
VI = VCCI or 0 V, all channels, no load,
EN1 at 3 V, EN2 at 3 V
4.5
7
6.5
11
UNIT
SUPPLY CURRENT
Quiescent
ISO7230C/M
25 Mbps
ICC1
Quiescent
ISO7231C/M
25 Mbps
Quiescent
ISO7230C/M
25 Mbps
ICC2
Quiescent
ISO7231C/M
25 Mbps
VI = VCCI or 0 V, all channels, no load,
EN at 3 V
9
15
10
17
VI = VCCI or 0 V, all channels, no load,
EN1 at 3 V, EN2 at 3 V
8
12
10.5
16
mA
mA
mA
mA
ELECTRICAL CHARACTERISTICS
IOFF
Sleep mode output current
ENx at 0 V, single channel
VCCO – 0.4
IOH = –20 μA, See Figure 8
VCCO – 0.1
VOH
High-level output voltage
VOL
Low-level output voltage
VI(HYS)
Input voltage hysteresis
IIH
High-level input current
INx at VCCI
IIL
Low-level input current
INx at 0 V
CI
Input capacitance to ground
INx at VCCI, VI = 0.4 sin (4E6πt)
CMTI
Common-mode transient immunity
VI = VCCI or 0 V, See Figure 11
(1)
μA
0
IOH = –4 mA, See Figure 8
V
IOL = 4 mA, See Figure 8
0.4
IOL = 20 μA, See Figure 8
0.1
V
150
mV
10
μA
–10
25
2
pF
50
kV/μs
For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3.3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V.
7.9 Power Dissipation Characteristics
over operating free-air temperature range (unless otherwise noted)
ISO7230C, ISO7230M, ISO7231C, ISO7231M
PARAMETER
DW (SOIC)
UNIT
16 PINS
PD
10
Device power dissipation, VCC1 = VCC2 = 5.5 V, TJ = 150°C,
CL = 15 pF, D Input a 50% duty cycle square wave
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mW
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7.10 Switching Characteristics: VCC1 and VCC2 at 5-V
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
tPLH, tPHL
Propagation delay
PWD
Pulse-width distortion (1) |tPHL – tPLH|
tPLH, tPHL
Propagation delay
PWD
Pulse-width distortion (1) |tPHL – tPLH|
tsk(pp)
Part-to-part skew
tsk(o)
Channel-to-channel output skew
tr
Output signal rise time
tf
Output signal fall time
tPHZ
Propagation delay, high-level-to-high-impedance output
15
20
tPZH
Propagation delay, high-impedance-to-high-level output
15
20
tPLZ
Propagation delay, low-level-to-high-impedance output
15
20
tPZL
Propagation delay, high-impedance-to-low-level output
15
20
tfs
Failsafe output delay time from input power loss
See Figure 10
Peak-to-peak eye-pattern jitter
150 Mbps PRBS NRZ data input,
Same polarity inputon all channels,
See Figure 12
tjit(pp)
(1)
(2)
(3)
18
ISO723xC
42
2.5
See Figure 8
10
ISO723xM
23
1
ISO723xC
(2)
(3)
2
8
ISO723xM
0
3
ISO723xC
0
2
ISO723xM
0
1
2
See Figure 8
ISO723xM
ns
ns
ns
ns
ns
2
See Figure 9
UNIT
ns
12
μs
1
ns
Also referred to as pulse skew.
tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
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7.11 Switching Characteristics: VCC1 at 5-V, VCC2 at 3.3-V
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
20
50
tPLH, tPHL
Propagation delay, low-to-high-level output
PWD
Pulse-width distortion (1) |tPHL – tPLH|
tPLH, tPHL
Propagation delay, low-to-high-level output
PWD
Pulse-width distortion (1) |tPHL – tPLH|
tsk(pp)
Part-to-part skew
tsk(o)
Channel-to-channel output skew
tr
Output signal rise time
tf
Output signal fall time
tPHZ
Propagation delay, high-level-to-high-impedance output
15
20
tPZH
Propagation delay, high-impedance-to-high-level output
15
20
tPLZ
Propagation delay, low-level-to-high-impedance output
15
20
tPZL
Propagation delay, high-impedance-to-low-level output
15
20
tfs
Failsafe output delay time from input power loss
See Figure 10
Peak-to-peak eye-pattern jitter
150 Mbps PRBS NRZ data
input, Same polarity input on
all channels, See Figure 12
tjit(pp)
(1)
(2)
(3)
12
ISO723xC
3
See Figure 8
12
ISO723xM
29
1
ISO723xC
(2)
(3)
2
10
ISO723xM
0
5
ISO723xC
0
2.5
ISO723xM
0
1
2
See Figure 8
ISO723xM
ns
ns
ns
ns
ns
2
See Figure 9
UNIT
ns
18
μs
1
ns
Also known as pulse skew
tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
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7.12 Switching Characteristics: VCC1 at 3.3-V and VCC2 at 5-V
, over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tPLH, tPHL
Propagation delay
PWD
Pulse-width distortion (1) |tPHL – tPLH|
tPLH, tPHL
Propagation delay
PWD
Pulse-width distortion(1) |tPHL – tPLH|
MIN
ISO723xC
TYP
51
12
30
ISO723xM
1
ISO723xC
Part-to-part skew
tsk(o)
Channel-to-channel output skew
tr
Output signal rise time
tf
Output signal fall time
tPHZ
Propagation delay, high-level-to-high-impedance output
15
20
tPZH
Propagation delay, high-impedance-to-high-level output
15
20
tPLZ
Propagation delay, low-level-to-high-impedance output
15
20
tPZL
Propagation delay, high-impedance-to-low-level output
15
20
tfs
Failsafe output delay time from input power loss
See Figure 10
Peak-to-peak eye-pattern jitter
150 Mbps PRBS NRZ data input, Same
polarity input on all channels, See Figure 12
tjit(pp)
(1)
(2)
(3)
ISO723xM
0
5
ISO723xC
0
2.5
ISO723xM
0
1
2
See Figure 8
ISO723xM
ns
ns
ns
2
See Figure 9
ns
2
10
tsk(pp)
(3)
UNIT
3
See Figure 8
(2)
MAX
22
ns
12
μs
1
ns
Also known as pulse skew
tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
7.13 Switching Characteristics: VCC1 and VCC2 at 3.3-V
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
Propagation delay
PWD
Pulse-width distortion (1) |tPHL – tPLH|
tpLH, tpHL
Propagation delay
PWD
Pulse-width distortion (1) |tPHL – tPLH|
tsk(pp)
Part-to-part skew
tsk(o)
Channel-to-channel output skew
tr
Output signal rise time
tf
Output signal fall time
tPHZ
Propagation delay, high-level-to-high-impedance output
15
20
tPZH
Propagation delay, high-impedance-to-high-level output
15
20
tPLZ
Propagation delay, low-level-to-high-impedance output
15
20
tPZL
Propagation delay, high-impedance-to-low-level output
15
20
tfs
Failsafe output delay time from input power loss
See Figure 10
Peak-to-peak eye-pattern jitter
150 Mbps PRBS NRZ data input, same
polarity input on all channels, See Figure 12
tjit(pp)
(1)
(2)
(3)
25
MAX
tPLH, tPHL
ISO723xC
56
4
See Figure 8
12
ISO723xM
34
1
ISO723xC
(2)
(3)
2
10
ISO723xM
0
5
ISO723xC
0
3
ISO723xM
0
1
2
See Figure 8
ISO723xM
ns
ns
ns
ns
ns
2
See Figure 9
UNIT
ns
18
μs
1
ns
Also referred to as pulse skew.
tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
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7.14 Typical Characteristics
45
40
ICC - Supply Current - mA/RMS
ICC - Supply Current - mA/RMS
40
45
TA = 25°C,
Load = 15 pF,
All Channels
35
30
5-V ICC2
3.3-V ICC2
25
20
15
5-V ICC1
10
3.3-V ICC1
TA = 25°C,
Load = 15 pF,
All Channels
35
5-V ICC1
30
25
5-V ICC2
20
15
10
5
0
0
25
50
75
100
125
0
0
150
3.3-V ICC2
3.3-V ICC1
5
25
50
75
100
125
150
Signaling Rate - Mbps
Signaling Rate - Mbps
Figure 1. ISO7230C/M RMS Supply Current vs Signaling
Rate
Figure 2. ISO7231C/M RMS Supply Current vs Signaling
Rate
45
1.4
40
5 V Vth+
1.35
C 3.3-V tpLH, tpHL
Input Voltage Threshold - V
35
Propagation Delay - ns
C 5-V tpLH, tpHL
30
25
20
M 3.3-V tpLH, tpHL
15
M 5-V tpLH, tpHL
10
TA = 25°C,
Load = 15 pF,
All Channels
5
1.3
3.3 V Vth+
1.25
1.2
1.15
5 V Vth1.1
1.05
3.3 V Vth-
0
-40
-25
-10
5
80
65
35
20
50
TA - Free-Air Temperature - °C
95
110
1
-40
125
Figure 3. Propagation Delay vs Free-Air Temperature
-10
5
20
35
50
65
80
TA - Free-Air Temperature - °C
95
110
125
50
VCC at 5 V or 3.3 V,
Load = 15 pF,
Air Flow at 7/cf/m,
Low-K Board
VCC = 5 V
Load = 15 pF,
TA = 25°C
40
2.7
IO - Output Current - mA
VCC1 - Failsafe Threshold - V
2.8
-25
Figure 4. Input Threshold Voltage vs Free-Air Temperature
3
2.9
Air Flow at 7 cf/m,
Low-K Board
Vfs+
2.6
2.5
Vfs-
2.4
2.3
2.2
VCC = 3.3 V
30
20
10
2.1
2
-40
-25
-10
5
20
35
50
65
80
95
110
125
TA - Free-Air Temperature - °C
Figure 5. VCC1 Fail-Safe Threshold vs Free-Air Temperature
14
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0
0
2
4
VO - Output Voltage - V
6
Figure 6. High-Level Output Current vs High-Level Output
Voltage
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Typical Characteristics (continued)
50
Load = 15 pF,
TA = 25°C
45
IO - Output Current - mA
40
35
VCC = 3.3 V
30
25
VCC = 5 V
20
15
10
5
0
0
1
2
3
VO - Output Voltage - V
4
5
Figure 7. Low-Level Output Current vs Low-Level Output Voltage
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ISOLATION BARRIER
8 Parameter Measurement Information
IN
Input
Generator
50 W
VI
NOTE A
VCCI
VI
50%
50%
OUT
0V
tPHL
tPLH
CL
NOTE B
VO
VO
90%
50%
50%
10%
tr
VOH
VOL
tf
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50 Ω. At the input, a 50-Ω resistor is required to terminate the Input Generator signal. It is not
needed in actual application.
B.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 8. Switching Characteristic Test Circuit and Voltage Waveforms
VCCO
VCC
ISOLATION BARRIER
RL = 1 kW ±1%
IN
0V
Input
Generator
VI
OUT
EN
VCC/2
t PZL
VO
CL
VCC/2
VI
VO
0V
VCCO
t PLZ
0.5 V
50%
NOTE
B
50 W
VOL
NOTE A
ISOLATION BARRIER
3V
VCC
IN
Input
Generator
VI
OUT
VO
VCC/2
VI
VCC/2
0V
t PZH
EN
50 W
CL
NOTE
B
RL = 1 kW ±1%
VO
VOH
50%
0.5 V
t PHZ
0V
NOTE A
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50Ω.
B.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 9. Enable/Disable Propagation Delay Time Test Circuit and Waveform
16
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Parameter Measurement Information (continued)
VI
ISOLATION BARRIER
VCCI
IN
IN = 0 V
VCCI
VI
OUT
2.7 V
VO
0V
tfs
CL
VO
NOTE B
VOH
50%
VOL
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50 Ω.
B.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 10. Failsafe Delay Time Test Circuit and Voltage Waveforms
IN
S1
C = 0.1 μ F ±1%
Isolation Barrier
VCCI
GNDI
VCCO
C = 0.1 μ F ±1%
Pass-fail criteria –
output must remain
stable.
OUT
+
CL
Note A
GNDO
VOH or VOL
–
+ VCM –
A.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 11. Common-Mode Transient Immunity Test Circuit
VCC
DUT
Tektronix
HFS9009
IN
OUT
0V
Tektronix
784D
PATTERN
GENERATOR
VCC/2
Jitter
NOTE: PRBS bit pattern run length is 2
or 0s.
16
– 1. Transition time is 800 ps. NRZ data input has no more than five consecutive 1s
Figure 12. Peak-to-Peak Eye-Pattern Jitter Test Circuit and Voltage Waveform
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9 Detailed Description
9.1 Overview
The isolator in Figure 13 is based on a capacitive isolation barrier technique. The I/O channel of the device
consists of two internal data channels, a high-frequency channel (HF) with a bandwidth from 100 kbps up to 150
Mbps, and a low-frequency channel (LF) covering the range from 100 kbps down to DC. In principle, a singleended input signal entering the HF-channel is split into a differential signal via the inverter gate at the input. The
following capacitor-resistor networks differentiate the signal into transients, which then are converted into
differential pulses by two comparators. The comparator outputs drive a NOR-gate flip-flop whose output feeds an
output multiplexer. A decision logic (DCL) at the driving output of the flip-flop measures the durations between
signal transients. If the duration between two consecutive transients exceeds a certain time limit, (as in the case
of a low-frequency signal), the DCL forces the output-multiplexer to switch from the high- to the low-frequency
channel.
Because low-frequency input signals require the internal capacitors to assume prohibitively large values, these
signals are pulse-width modulated (PWM) with the carrier frequency of an internal oscillator, thus creating a
sufficiently high frequency signal, capable of passing the capacitive barrier. As the input is modulated, a low-pass
filter (LPF) is needed to remove the high-frequency carrier from the actual data before passing it on to the output
multiplexer.
9.2 Functional Block Diagram
Isolation Barrier
OSC
LPF
Low t Frequency
Channel
(DC...100 kbps)
PWM
VREF
0
OUT
1 S
IN
DCL
High t Frequency
Channel
(100 kbps...150 Mbps)
VREF
Figure 13. Conceptual Block Diagram of a Digital Capacitive Isolator
18
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9.3 Feature Description
9.3.1 Package Insulation and Safety-Related Specifications
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
L(I01)
Minimum air gap (Clearance) (1)
Shortest terminal-to-terminal distance through air
8
mm
L(I02)
Minimum external tracking
(Creepage) (1)
Shortest terminal-to-terminal distance across the
package surface
8
mm
CTI
Tracking resistance
(comparative tracking index)
DIN EN 60112 (VDE 0303-11); IEC 60112
DTI
Minimum Internal Gap
(Internal Clearance)
Distance through the insulation
RIO (2)
Isolation resistance
CIO (2)
Barrier capacitance Input to output
(1)
(2)
400
V
0.008
mm
>1012
Input to output, VIO = 500 V, TA = 25°C
Input to output, VIO = 500 V, 100°C ≤ TA ≤ TA max
Ω
11
Ω
2
pF
>10
VI = 0.4 sin (4E6πt)
per JEDEC package dimensions.
All pins on each side of the barrier tied together creating a two-terminal device.
9.3.2 Insulation Characteristics
PARAMETER
TEST CONDITIONS
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM
SPECIFICATION
UNIT
(1)
Maximum repetitive peak isolation voltage
560
VPK
1050
VPK
VPR
Input to output test voltage
Method b1, VPR = VIORM x 1.875,
100% production test with t = 1 s,
Partial discharge < 5 pC
VIOTM
Maximum transient isolation voltage
VTEST = VIOTM,
t = 60 s (qualification),
t = 1 s (100% production)
4000
VPK
RS
Isolation resistance
VIO = 500 V at TS = 150 °C
>109
Ω
Pollution degree
2
UL 1577
VISO
(1)
VTEST = VISO = 2500 VRMS, t = 60 s
(qualification),
VTEST = 1.2 x VISO = 3000 VRMS, t = 1 s (100%
production)
Withstanding isolation voltage
2500
VRMS
Climatic classification 40/125/21
Table 1. IEC 60664-1 Ratings Table
PARAMETER
TEST CONDITIONS
Basic isolation group
SPECIFICATION
Material group
Installation classification
II
Rated mains voltage ≤150 VRMS
I-IV
Rated mains voltage ≤300 VRMS
I-III
9.3.3 Regulatory Information
VDE
CSA
UL
Certified according to DIN V VDE V 0884-10
(VDE V 0884-10):2006-12 and DIN EN
61010-1 (VDE 0411-1):2011-07
Approved under CSA Component
Acceptance Notice 5A and IEC 60950-1
Recognized under UL 1577 Component
Recognition Program
Basic insulation;
Maximum transient isolation voltage, 4000
VPK;
Maximum repetitive peak isolation voltage,
560 VPK
4000 VPK Isolation rating;
384 VRMS Basic insulation working voltage
per CSA 60950-1-07+A1 and IEC 60950-1
2nd Ed.+A1
Single protection, 2500 VRMS
File Number: 40016131
Master Contract Number: 220991
File Number: E181974
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9.3.4 Safety Limiting Values
Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry.
A failure of the IO can allow low resistance to ground or the supply and, without current limiting, dissipate
sufficient power to overheat the die and damage the isolation barrier potentially leading to secondary system
failures.
PARAMETER
TEST CONDITIONS
IS
Safety input, output, or
supply current
SOIC16
TS
Maximum case temperature
SOIC16
MIN
TYP
MAX
θJA = 168°C/W, VI = 5.5 V, TJ = 170°C, TA = 25°C
156
θJA = 168°C/W, VI = 3.6 V, TJ = 170°C, TA = 25°C
239
150
UNIT
mA
°C
The safety-limiting constraint is the absolute maximum junction temperature specified in the absolute maximum
ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the
application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the
Thermal Characteristics table is that of a device installed in the JESD51-3, Low Effective Thermal Conductivity
Test Board for Leaded Surface Mount Packages and is conservative. The power is the recommended maximum
input voltage times the current. The junction temperature is then the ambient temperature plus the power times
the junction-to-air thermal resistance.
300
VCC1,2 at 3.6 V
Safety Limiting Current - mA
250
200
150
VCC1,2 at 5.5 V
100
50
0
0
50
100
150
TC - Case Temperature - °C
200
Figure 14. SOIC-16 ΘJC Thermal Derating Curve per VDE
9.4 Device Functional Modes
Table 2. Device Function Table ISO723x
VCCI
VCCO
PU
(1)
20
PU
(1)
INPUT
(INx)
OUTPUT ENABLE
(ENx)
OUTPUT
(OUTx)
H
H or Open
H
L
H or Open
L
X
L
Z
Open
H or Open
H
H
PD
PU
X
H or Open
PD
PU
X
L
Z
X
PD
X
X
Undetermined
VCCI = Input-side VCC; VCCO = Output-side VCC; PU = Powered Up; PD = Powered Down; X =
Irrelevant; H = High Level; L = Low Level
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VCCI
Enable
Output
Input
VCCI
VCCI
VCCO
VCCO
1 MW
VCCO
VCCO
1 MW
8W
500W
IN
500W
OUT
EN
13W
Figure 15. Device I/O Schematics
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SLLS867K – SEPTEMBER 2007 – REVISED OCTOBER 2015
www.ti.com
10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
ISO723x utilize single-ended TTL or CMOS-logic switching technologies. The supply voltage range is from 3.15
V to 5.5 V for both supplies, VCC1 and VCC2. When designing with digital isolators, it is important to keep in mind
that due to the single-ended design structure, digital isolators do not conform to any specific interface standard
and are only intended for isolating single-ended CMOS or TTL digital signal lines. The isolator is typically placed
between the data controller (that is, μC or UART), and a data converter or a line transceiver, regardless of the
interface type or standard.
10.2 Typical Application
ISO7231 combined with Texas Instruments' mixed signal micro-controller, RS-485 transceiver, transformer driver,
and voltage regulator can create an isolated RS-485 system as shown in Figure 16.
VIN
3.3V
0.1 F
2
Vcc D2 3
1:2.2 MBR0520L
1
SN6501
3
1
10 F
4,5
OUT
5
TPS76350
10 F 0.1 F
GND D1
IN
EN
GND
2
5VISO
10 F
MBR0520L
ISO-BARRIER
0.1 F
0.1 F
0.1 F
DVcc
6
P3.0
XOUT
XIN
11
15
MSP430 UCA0TXD
F2132
UCA0RXD 16
DVss
4
16
1
2
5
0.1 F
3
4
5
VCC1
VCC2
INA
OUTA
ISO7231
INB
OUTC
7 EN1
GND1
2,8
OUTB
INC
VCC
14
13
12
EN2 10
GND2
2
3
4
1
RE
DE
10
MELF
B
D
SN65HVD
3082E A
R
GND
10
MELF
SM712
9,15
4.7nF/
2kV
Figure 16. Isolated RS-485 Application Circuit
10.2.1 Design Requirements
Unlike optocouplers, which need external components to improve performance, provide bias, or limit current,
ISO723x only needs two external bypass capacitors to operate.
22
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ISO7230C, ISO7230M, ISO7231C, ISO7231M
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SLLS867K – SEPTEMBER 2007 – REVISED OCTOBER 2015
Typical Application (continued)
10.2.2 Detailed Design Procedure
ISO7230
0.1 µF
0.1 µF
VCC1
VCC2
1
16
2
15
INA
3
14
OUTA
INB
4
13
OUTB
INC
5
12
OUTC
NC
6
11
NC
7
10
8
9
GND1
GND2
GND1
NC
EN
GND2
Figure 17. Typical ISO7230 Circuit Hook-up
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SLLS867K – SEPTEMBER 2007 – REVISED OCTOBER 2015
www.ti.com
Typical Application (continued)
ISO7231
0.1 µF
0.1 µF
VCC2
VCC1
1
16
2
15
INA
3
14
OUTA
INB
4
13
OUTB
OUTC
5
12
INC
6
11
7
10
8
9
GND1
GND2
NC
NC
EN2
EN1
GND1
GND2
Figure 18. Typical ISO7231 Circuit Hook-up
10.2.3 Application Curve
WORKING LIFE -- YEARS
100
VIORM at 560-V
28 Years
10
0
120
250
500
750
880
1000
WORKING VOLTAGE (VIORM) -- V
Figure 19. Time Dependant Dielectric Breakdown Testing Results
24
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ISO7230C, ISO7230M, ISO7231C, ISO7231M
www.ti.com
SLLS867K – SEPTEMBER 2007 – REVISED OCTOBER 2015
11 Power Supply Recommendations
To ensure reliable operation at all data rates and supply voltages, a 0.1 μF bypass capacitor is recommended at
input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins as
possible. If only a single primary-side power supply is available in an application, isolated power can be
generated for the secondary-side with the help of a transformer driver such as Texas Instruments SN6501 data
sheet . For such applications, detailed power supply design and transformer selection recommendations are
available in SN6501 data sheet (SLLSEA0).
12 Layout
12.1 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 20). Layer stacking should
be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency
signal layer.
• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100pF/in2.
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power/ground plane system to the
stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the
power and ground plane of each power system can be placed closer together, thus increasing the high-frequency
bypass capacitance significantly. For detailed layout recommendations, see Application Note SLLA284, Digital
Isolator Design Guide.
12.1.1 PCB Material
For digital circuit boards operating below 150 Mbps, (or rise and fall times higher than 1 ns), and trace lengths of
up to 10 inches, use standard FR-4 epoxy-glass as PCB material. FR-4 (Flame Retardant 4) meets the
requirements of Underwriters Laboratories UL94-V0, and is preferred over cheaper alternatives due to its lower
dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and its selfextinguishing flammability-characteristics.
12.2 Layout Example
High-speed traces
10 mils
Ground plane
40 mils
Keep this
space free
from planes,
traces, pads,
and vias
FR-4
0r ~ 4.5
Power plane
10 mils
Low-speed traces
Figure 20. Recommended Layer Stack
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ISO7230C, ISO7230M, ISO7231C, ISO7231M
SLLS867K – SEPTEMBER 2007 – REVISED OCTOBER 2015
www.ti.com
13 Device and Documentation Support
13.1 Related Documentation
•
•
•
•
•
High-Voltage Lifetime of the ISO72x Family of Digital Isolators, SLLA197
ISO72x Digital Isolator Magnetic-Field Immunity, SLLA181
SN6501 Transformer Driver for Isolated Power Supplies, SLLSEA0
Digital Isolator Design Guide, SLLA284
Isolation Glossary, SLLA353
13.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 3. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
ISO7230C
Click here
Click here
Click here
Click here
Click here
ISO7230M
Click here
Click here
Click here
Click here
Click here
ISO7231C
Click here
Click here
Click here
Click here
Click here
ISO7231M
Click here
Click here
Click here
Click here
Click here
13.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
26
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Copyright © 2007–2015, Texas Instruments Incorporated
Product Folder Links: ISO7230C ISO7230M ISO7231C ISO7231M
PACKAGE OUTLINE
DW0016B
SOIC - 2.65 mm max height
SCALE 1.500
SOIC
C
PIN 1 ID
AREA
A
10.63
TYP
9.97
SEATING PLANE
0.1 C
16
1
14X 1.27
2X
8.89
10.5
10.1
NOTE 3
8
9
B
7.6
7.4
NOTE 4
0.51
0.31
0.25
C A
16X
2.65 MAX
B
0.38
TYP
0.25
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 -8
1.27
0.40
(1.4)
DETAIL A
TYPICAL
4221009/A 08/2013
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MO-013, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
16X (2)
1
SYMM
16X (1.65)
SEE
DETAILS
SEE
DETAILS
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
9
8
9
8
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
LAND PATTERN EXAMPLE
SCALE:4X
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
0.07 MAX
ALL AROUND
METAL
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221009/A 08/2013
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
16X (2)
SYMM
16X (1.65)
1
1
16
16X (0.6)
16
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
9
8
9
8
(9.3)
(9.75)
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
4221009/A 08/2013
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
ISO7230CDW
ACTIVE
SOIC
DW
16
40
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7230C
Samples
ISO7230CDWR
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7230C
Samples
ISO7230MDW
ACTIVE
SOIC
DW
16
40
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7230M
Samples
ISO7230MDWR
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7230M
Samples
ISO7231CDW
ACTIVE
SOIC
DW
16
40
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7231C
Samples
ISO7231CDWR
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7231C
Samples
ISO7231CDWRG4
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7231C
Samples
ISO7231MDW
ACTIVE
SOIC
DW
16
40
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7231M
Samples
ISO7231MDWR
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7231M
Samples
ISO7231MDWRG4
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7231M
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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