ISO7240CF-Q1, ISO7240C-Q1
ISO7241C-Q1, ISO7242C-Q1
SLLSE40A – SEPTEMBER 2010 – REVISED SEPTEMBER 2011
www.ti.com
HIGH-SPEED QUAD DIGITAL ISOLATORS
Check for Samples: ISO7240CF-Q1, ISO7241C-Q1
FEATURES
1
•
•
•
•
•
Qualified for Automotive Applications
Selectable Failsafe Output (ISO7240CF)
25 and 150-Mbps Signaling Rate Options
– Low Channel-to-Channel Output Skew;
1 ns Max
– Low Pulse-Width Distortion (PWD);
2 ns Max
– Low Jitter Content; 1 ns Typ at 150 Mbps
Typical 25-Year Life at Rated Working Voltage
(see application note SLLA197 and Figure 17)
4000-Vpeak Isolation, 560-Vpeak VIORM
– UL 1577 , IEC 60747-5-2 (VDE 0884, Rev 2),
IEC 61010-1, IEC 60950-1 and CSA
Approved
•
•
•
•
4 kV ESD Protection
Operate With 3.3-V or 5-V Supplies
High Electromagnetic Immunity
(see application report SLLA181)
–40°C to 125°C Operating Range
DESCRIPTION
The ISO7240, ISO7241 and ISO7242 are quad-channel digital isolators with multiple channel configurations and
output enable functions. These devices have logic input and output buffers separated by TI’s silicon dioxide
(SiO2) isolation barrier. Used in conjunction with isolated power supplies, these devices block high voltage,
isolate grounds, and prevent noise currents from entering the local ground and interfering with or damaging
sensitive circuitry.
The ISO7240 has all four channels in the same direction while the ISO7241 has three channels the same
direction and one channel in opposition. The ISO7242 has two channels in each direction.
The C option devices have TTL input thresholds and a noise-filter at the input that prevents transient pulses from
being passed to the output of the device. The M option devices have CMOS VCC/2 input thresholds and do not
have the input noise-filter or the additional propagation delay.
The ISO7240CF has an input disable function on pin 7, and a selectable high or low failsafe-output function with
the CTRL pin (pin 10). The failsafe-output is a logic high when a logic-high is placed on the CTRL pin or it is left
unconnected. If a logic-low signal is applied to the CTRL pin, the failsafe-output becomes a logic-low output
state. The ISO7240CF input disable function prevents data from being passed across the isolation barrier to the
output. When the inputs are disabled, the outputs are set by the CTRL pin.
These devices may be powered from either 3.3-V or 5-V supplies on either side in any 3.3-V / 3.3-V, 5-V / 5-V,
5-V / 3.3-V, or 3.3-V / 5-V combination. Note that the signal input pins are 5-V tolerant regardless of the voltage
supply level being used.
These devices are characterized for operation over the ambient temperature range of –40°C to 125°C.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2011, Texas Instruments Incorporated
ISO7240CF-Q1, ISO7240C-Q1
ISO7241C-Q1, ISO7242C-Q1
SLLSE40A – SEPTEMBER 2010 – REVISED SEPTEMBER 2011
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION (1)
PACKAGE (2)
TA
–40°C to 125°C
(1)
(2)
SOIC – DW
ORDERABLE PART NUMBER
Reel of 2000
TOP-SIDE MARKING
ISO7240CFQDWRQ1
ISO7240CFQ
ISO7240CQDWRQ1
Product Preview
ISO7241CQDWRQ1
ISO7241CQ
ISO7242CQDWRQ1
ISO7242CQ
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
VCC1
GND1
INA
INB
INC
IND
DISABLE
GND1
1
2
3
4
5
6
7
8
ISO7240CF
16
15
14
13
12
11
10
9
ISO7240
VCC2 VCC1
GND2 GND1
OUTA
INA
INB
OUTB
INC
OUTC
OUTD
IND
CTRL
NC
GND2 GND1
1
2
3
4
5
6
7
8
ISO7241
VCC2
GND2
OUTA
OUTB
OUTC
OUTD
EN
GND2
16
15
14
13
12
11
10
9
VCC1
GND1
INA
INB
INC
OUTD
EN1
GND1
1
2
3
4
5
6
7
8
ISO7242
VCC2
GND2
OUTA
OUTB
OUTC
IND
EN2
GND2
16
15
14
13
12
11
10
9
VCC1
GND1
INA
INB
OUTC
OUTD
EN1
GND1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC2
GND2
OUTA
OUTB
INC
IND
EN2
GND2
Table 1. ISO724xC Function Table (1)
INPUT VCC
OUTPUT VCC
PU
(1)
INPUT
(IN)
OUTPUT ENABLE
(EN)
OUTPUT
(OUT)
H
H or Open
H
L
H or Open
L
X
L
Z
Open
H or Open
H
PU
PD
PU
X
H or Open
H
PD
PU
X
L
Z
PU = Powered Up; PD = Powered Down ; X = Irrelevant; H = High Level; L = Low Level
Table 2. ISO7240CF Function Table
2
VCC1
VCC2
DATA INPUT
(IN)
DISABLE INPUT
(DISABLE)
FAILSAFE CONTROL INPUT
(CTRL)
DATA OUTPUT
(OUT)
PU
PU
H
L or Open
X
H
PU
PU
L
L or Open
X
L
X
PU
X
H
H or Open
H
X
PU
X
H
L
L
PD
PU
X
X
H or Open
H
PD
PU
X
X
L
L
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Copyright © 2010–2011, Texas Instruments Incorporated
Product Folder Link(s): ISO7240CF-Q1 ISO7241C-Q1
ISO7240CF-Q1, ISO7240C-Q1
ISO7241C-Q1, ISO7242C-Q1
SLLSE40A – SEPTEMBER 2010 – REVISED SEPTEMBER 2011
www.ti.com
ABSOLUTE MAXIMUM RATINGS (1)
VALUE
UNIT
VCC
Supply voltage (2), VCC1, VCC2
–0.5 to 6
V
VI
Voltage at IN, OUT, EN, DISABLE, CTRL
–0.5 to 6
V
IO
Output current
±15
mA
ESD
Human-Body Model
Electrostatic
Field-Induced-Charged Device Model
discharge
Machine Model
TJ
(1)
(2)
±4
kV
±1
All pins
Maximum junction temperature
±200
V
150
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal and are peak voltage values.
RECOMMENDED OPERATING CONDITIONS
MIN
VCC
Supply voltage (1), VCC1, VCC2
IOH
High-level output current
IOL
Low-level output current
–4
tui
Input pulse width
40
1/tui
Signaling rate
0
VIH
High-level input voltage (IN, DISABLE, CTRL, EN)
2
VIL
Low-level input voltage (IN, DISABLE, CTRL, EN)
TA
Operating free-air temperature
H
External magnetic field-strength immunity per IEC 61000-4-8 and IEC 61000-4-9
certification
(1)
(2)
TYP
3.15
MAX
UNIT
5.5
V
4
mA
mA
ns
30 (2)
25
Mbps
VCC
V
0
0.8
V
-40
125
°C
1000
A/m
For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V.
Typical value at room temperature and well-regulated power supply.
IEC 60747-5-2 INSULATION CHARACTERISTICS (1)
over recommended operating conditions (unless otherwise noted)
PARAMETER
VIORM
VPR
TEST CONDITIONS
SPECIFICATIONS
UNIT
560
V
After Input/Output Safety Test Subgroup 2/3
VPR = VIORM × 1.2, t = 10 s,
Partial discharge < 5 pC
672
V
Method a, VPR = VIORM × 1.6,
Type and sample test with t = 10 s,
Partial discharge < 5 pC
896
V
Method b1, VPR = VIORM × 1.875,
100 % Production test with t = 1 s,
Partial discharge < 5 pC
1050
V
Maximum working insulation voltage
Input to output test voltage
VIOTM
Transient overvoltage
t = 60 s
4000
V
RS
Insulation resistance
VIO = 500 V at TS
>109
Ω
Pollution degree
(1)
2
Climatic Classification 40/125/21
Copyright © 2010–2011, Texas Instruments Incorporated
Product Folder Link(s): ISO7240CF-Q1 ISO7241C-Q1
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ISO7240CF-Q1, ISO7240C-Q1
ISO7241C-Q1, ISO7242C-Q1
SLLSE40A – SEPTEMBER 2010 – REVISED SEPTEMBER 2011
www.ti.com
ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 5-V (1) OPERATION
, over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
ISO7240C
ICC1
ISO7241C
ISO7242C
ISO7240C
ICC2
ISO7241C
ISO7242C
Quiescent
25 Mbps
Quiescent
25 Mbps
Quiescent
25 Mbps
Quiescent
25 Mbps
Quiescent
25 Mbps
Quiescent
25 Mbps
VI = VCC or 0 V, All channels, no load,
EN2 at 3 V
1
3
7
10.5
VI = VCC or 0 V, All channels, no load,
EN1 at 3 V, EN2 at 3 V
6.5
11
12
18
VI = VCC or 0 V, All channels, no load,
EN1 at 3 V, EN2 at 3 V
10
16
15
24
VI = VCC or 0 V, All channels, no load,
EN2 at 3 V
15
22
17
25
VI = VCC or 0 V, All channels, no load,
EN1 at 3 V, EN2 at 3 V
13
20
18
28
VI = VCC or 0 V, All channels, no load,
EN1 at 3 V, EN2 at 3 V
10
16
15
24
mA
mA
mA
mA
mA
mA
ELECTRICAL CHARACTERISTICS
IOFF
Sleep mode output current
EN at 0 V, Single channel
VCC – 0.8
IOH = –20 μA, See Figure 1
VCC – 0.1
VOH
High-level output voltage
VOL
Low-level output voltage
VI(HYS)
Input voltage hysteresis
IIH
High-level input current
IIL
Low-level input current
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6πt)
CMTI
Common-mode transient immunity
VI = VCC or 0 V, See Figure 5
(1)
4
μA
0
IOH = –4 mA, See Figure 1
V
IOL = 4 mA, See Figure 1
0.4
IOL = 20 μA, See Figure 1
0.1
150
mV
10
IN from 0 V to VCC
–10
25
V
μA
2
pF
50
kV/μs
For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V.
Submit Documentation Feedback
Copyright © 2010–2011, Texas Instruments Incorporated
Product Folder Link(s): ISO7240CF-Q1 ISO7241C-Q1
ISO7240CF-Q1, ISO7240C-Q1
ISO7241C-Q1, ISO7242C-Q1
SLLSE40A – SEPTEMBER 2010 – REVISED SEPTEMBER 2011
www.ti.com
SWITCHING CHARACTERISTICS: VCC1 and VCC2 at 5-V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tPLH, tPHL
Propagation delay
PWD
Pulse-width distortion (1) |tPHL – tPLH|
tsk(pp)
Part-to-part skew
See Figure 1
MIN
TYP
18
MAX
45
5
(2)
8
(3)
ISO7240C, ISO7241C
3
ISO7242C
4
UNIT
ns
ns
tsk(o)
Channel-to-channel output skew
tr
Output signal rise time
tf
Output signal fall time
tPHZ
Propagation delay, high-level-to-high-impedance output
15
25
tPZH
Propagation delay, high-impedance-to-high-level output
15
25
tPLZ
Propagation delay, low-level-to-high-impedance output
15
25
tPZL
Propagation delay, high-impedance-to-low-level output
15
25
tfs
Failsafe output delay time from input power loss
See Figure 3
12
μs
twake
Wake time from input disable
See Figure 4
15
μs
(1)
(2)
(3)
See Figure 1
See Figure 2
2
ns
ns
2
ns
Also referred to as pulse skew.
tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
Copyright © 2010–2011, Texas Instruments Incorporated
Product Folder Link(s): ISO7240CF-Q1 ISO7241C-Q1
Submit Documentation Feedback
5
ISO7240CF-Q1, ISO7240C-Q1
ISO7241C-Q1, ISO7242C-Q1
SLLSE40A – SEPTEMBER 2010 – REVISED SEPTEMBER 2011
www.ti.com
ELECTRICAL CHARACTERISTICS: VCC1 at 5-V, VCC2 at 3.3-V (1) OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
ISO7240C
ICC1
ISO7241C
ISO7242C
ISO7240C
ICC2
ISO7241C
ISO7242C
Quiescent
25 Mbps
Quiescent
25 Mbps
Quiescent
25 Mbps
Quiescent
25 Mbps
Quiescent
25 Mbps
Quiescent
25 Mbps
1
3
7
10.5
VI = VCC or 0 V, All channels, no load, EN1 at 3 V,
EN2 at 3 V
6.5
11
12
18
VI = VCC or 0 V, All channels, no load, EN1 at 3 V,
EN2 at 3 V
10
16
15
24
VI = VCC or 0 V, All channels, no load, EN2 at 3 V
VI = VCC or 0 V, All channels, no load, EN2 at 3 V
VI = VCC or 0 V, All channels, no load, EN1 at 3 V,
EN2 at 3 V
VI = VCC or 0 V, All channels, no load, EN1 at 3 V,
EN2 at 3 V
9.5
15
10.5
17
8
13
11.5
18
6
10
9
14
mA
mA
mA
mA
mA
mA
ELECTRICAL CHARACTERISTICS
IOFF
Sleep mode output current
VOH
High-level output voltage
EN at 0 V, Single channel
IOH = –4 mA, See Figure 1
VCC – 0.4
ISO724x (5-V
side)
VCC – 0.8
IOH = –20 μA, See Figure 1
VCC – 0.1
0.4
IOL = 20 μA, See Figure 1
0.1
Low-level output voltage
VI(HYS)
Input voltage hysteresis
IIH
High-level input current
IIL
Low-level input current
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6πt)
CMTI
Common-mode transient
immunity
VI = VCC or 0 V, See Figure 5
6
V
IOL = 4 mA, See Figure 1
VOL
(1)
μA
0
ISO7240
150
mV
10
IN from 0 V to VCC
–10
25
V
μA
2
pF
50
kV/μs
For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V.
Submit Documentation Feedback
Copyright © 2010–2011, Texas Instruments Incorporated
Product Folder Link(s): ISO7240CF-Q1 ISO7241C-Q1
ISO7240CF-Q1, ISO7240C-Q1
ISO7241C-Q1, ISO7242C-Q1
SLLSE40A – SEPTEMBER 2010 – REVISED SEPTEMBER 2011
www.ti.com
SWITCHING CHARACTERISTICS: VCC1 at 5-V, VCC2 at 3.3-V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
tPLH, tPHL
PWD
TEST CONDITIONS
MIN
TYP
20
MAX
Propagation delay
See Figure 1
Pulse-width distortion (1) |tPHL – tPLH|
ISO7240C, ISO7241C
3
ISO7242C
4
UNIT
50
(2)
tsk(pp)
Part-to-part skew
tsk(o)
Channel-to-channel output skew
tr
Output signal rise time
tf
Output signal fall time
tPHZ
Propagation delay, high-level-to-high-impedance output
15
25
tPZH
Propagation delay, high-impedance-to-high-level output
15
25
tPLZ
Propagation delay, low-level-to-high-impedance output
15
25
tPZL
Propagation delay, high-impedance-to-low-level output
15
25
tfs
Failsafe output delay time from input power loss
See Figure 3
18
μs
twake
Wake time from input disable
See Figure 4
15
μs
(1)
(2)
(3)
10
ns
(3)
ISO7240C, ISO7241C
3
ISO7242C
4
See Figure 1
See Figure 2
2
ns
ns
ns
2
ns
Also known as pulse skew
tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
Copyright © 2010–2011, Texas Instruments Incorporated
Product Folder Link(s): ISO7240CF-Q1 ISO7241C-Q1
Submit Documentation Feedback
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ISO7240CF-Q1, ISO7240C-Q1
ISO7241C-Q1, ISO7242C-Q1
SLLSE40A – SEPTEMBER 2010 – REVISED SEPTEMBER 2011
www.ti.com
ELECTRICAL CHARACTERISTICS: VCC1 at 3.3-V, VCC2 at 5-V (1) OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.5
1
3
5
4
7
6.5
11
6
10
9
14
15
22
17
25
13
20
18
28
10
16
15
24
UNIT
SUPPLY CURRENT
ISO7240C
ISO7241C
ICC1
Quiescent
VI = VCC or 0 V, All channels, no load, EN2 at 3 V
25 Mbps
Quiescent
VI = VCC or 0 V, All channels, no load, EN1 at 3 V,
EN2 at 3 V
25 Mbps
ISO7242C
Quiescent
VI = VCC or 0 V, All channels, no load, EN1 at 3 V,
EN2 at 3 V
25 Mbps
ISO7240C
ISO7241C
ICC2
Quiescent
VI = VCC or 0 V, All channels, no load, EN2 at 3 V
25 Mbps
Quiescent
VI = VCC or 0 V, All channels, no load, EN1 at 3 V,
EN2 at 3 V
25 Mbps
ISO7242C
Quiescent
VI = VCC or 0 V, All channels, no load, EN1 at 3 V,
EN2 at 3 V
25 Mbps
mA
mA
mA
mA
mA
mA
ELECTRICAL CHARACTERISTICS
IOFF
Sleep mode output current
VOH
High-level output voltage
EN at 0 V, Single channel
IOH = –4 mA, See Figure 1
VCC – 0.4
ISO724x (5-V side)
VCC – 0.8
IOH = –20 μA, See Figure 1
VCC – 0.1
0.4
IOL = 20 μA, See Figure 1
0.1
Low-level output voltage
VI(HYS)
Input voltage hysteresis
IIH
High-level input current
IIL
Low-level input current
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6πt)
CMTI
Common-mode transient
immunity
VI = VCC or 0 V, See Figure 5
8
V
IOL = 4 mA, See Figure 1
VOL
(1)
μA
0
ISO7240
150
mV
10
IN from 0 V to VCC
–10
25
V
μA
2
pF
50
kV/μs
For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V.
Submit Documentation Feedback
Copyright © 2010–2011, Texas Instruments Incorporated
Product Folder Link(s): ISO7240CF-Q1 ISO7241C-Q1
ISO7240CF-Q1, ISO7240C-Q1
ISO7241C-Q1, ISO7242C-Q1
SLLSE40A – SEPTEMBER 2010 – REVISED SEPTEMBER 2011
www.ti.com
SWITCHING CHARACTERISTICS: VCC1 at 3.3-V and VCC2 at 5-V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
tPLH,
tPHL
TEST CONDITIONS
Propagation delay
See Figure 1
Pulse-width distortion (1) |tPHL – tPLH|
PWD
See Figure 1
MIN
TYP MA
X
20
51
ISO7240C,
ISO7241C
3
ISO7242C
tsk(pp)
Part-to-part skew
10
(3)
Channel-to-channel output skew
tr
Output signal rise time
tf
Output signal fall time
tPHZ
Propagation delay,
high-level-to-high-impedance output
tPZH
Propagation delay,
high-impedance-to-high-level output
ISO7240C, ISO7241C
3
ISO7242C
4
See Figure 1
ns
4
(2)
tsk(o)
UNIT
2
ns
ns
ns
2
15
25
15
25
15
25
15
25
See Figure 2
ns
tPLZ
Propagation delay, low-level-to-high-impedance
output
tPZL
Propagation delay, high-impedance-to-low-level
output
tfs
Failsafe output delay time from input power loss See Figure 3
12
μs
twake
Wake time from input disable
15
μs
(1)
(2)
(3)
See Figure 4
Also known as pulse skew
tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
Copyright © 2010–2011, Texas Instruments Incorporated
Product Folder Link(s): ISO7240CF-Q1 ISO7241C-Q1
Submit Documentation Feedback
9
ISO7240CF-Q1, ISO7240C-Q1
ISO7241C-Q1, ISO7242C-Q1
SLLSE40A – SEPTEMBER 2010 – REVISED SEPTEMBER 2011
www.ti.com
ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 3.3 V (1) OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
SUPPLY CURRENT
ISO7240C
ISO7241C
ICC1
Quiescent
25 Mbps
Quiescent
25 Mbps
ISO7242C
Quiescent
25 Mbps
ISO7240C
ISO7241C
ICC2
Quiescent
25 Mbps
Quiescent
25 Mbps
ISO7242C
Quiescent
25 Mbps
VI = VCC or 0 V, all channels, no load,
EN2 at 3 V
0.5
1
3
5
VI = VCC or 0 V, all channels, no load,
EN1 at 3 V, EN2 at 3 V
4
7
6.5
11
6
10
9
14
VI = VCC or 0 V, all channels, no load,
EN1 at 3 V, EN2 at 3 V
VI = VCC or 0 V, all channels, no load,
EN2 at 3 V
VI = VCC or 0 V, all channels, no load,
EN1 at 3 V, EN2 at 3 V
VI = VCC or 0 V, all channels, no load,
EN1 at 3 V, EN2 at 3 V
9.5
15
10.5
17
8
13
11.5
18
6
10
9
14
mA
mA
mA
mA
ELECTRICAL CHARACTERISTICS
IOFF
Sleep mode output current
EN at 0 V, single channel
VCC – 0.4
IOH = –20 μA, See Figure 1
VCC – 0.1
VOH
High-level output voltage
VOL
Low-level output voltage
VI(HYS)
Input voltage hysteresis
IIH
High-level input current
IIL
Low-level input current
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6πt)
CMTI
Common-mode transient immunity
VI = VCC or 0 V, See Figure 5
(1)
10
μA
0
IOH = –4 mA, See Figure 1
V
IOL = 4 mA, See Figure 1
0.4
IOL = 20 μA, See Figure 1
0.1
150
mV
10
IN from 0 V or VCC
–10
25
V
μA
2
pF
50
kV/μs
For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V.
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ISO7240CF-Q1, ISO7240C-Q1
ISO7241C-Q1, ISO7242C-Q1
SLLSE40A – SEPTEMBER 2010 – REVISED SEPTEMBER 2011
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SWITCHING CHARACTERISTICS: VCC1 and VCC2 at 3.3-V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tPLH,
tPHL
Propagation delay
PWD
Pulse-width distortion |tPHL – tPLH| (1)
tsk(pp)
Part-to-part skew
See Figure 1
(3)
tr
Output signal rise time
tf
Output signal fall time
tPHZ
Propagation delay,
high-level-to-high-impedance output
tPZH
Propagation delay,
high-impedance-to-high-level output
tPLZ
Propagation delay, low-level-to-high-impedance
output
56
UNIT
ns
4
ISO7240C, ISO7241C
3.5
ISO7242C
4
See Figure 1
See Figure 2
Propagation delay, high-impedance-to-low-level
output
tfs
Failsafe output delay time from input power
loss
See Figure 3
twake
Wake time from input disable
See Figure 4
(3)
25
10
Channel-to-channel output skew
(1)
(2)
TY MAX
P
(2)
tsk(o)
tPZL
MI
N
ns
ns
2
ns
2
ns
ISO7240C,
ISO7241C
15
20
ISO7242C
15
25
ISO7240C,
ISO7241C
15
20
ISO7242C
15
25
ISO7240C,
ISO7241C
15
20
ISO7242C
15
25
ISO7240C,
ISO7241C
15
20
ISO7242C
15
25
18
15
ns
μs
μs
Also referred to as pulse skew.
tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
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ISO7240CF-Q1, ISO7240C-Q1
ISO7241C-Q1, ISO7242C-Q1
SLLSE40A – SEPTEMBER 2010 – REVISED SEPTEMBER 2011
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ISOLATION BARRIER
PARAMETER MEASUREMENT INFORMATION
IN
Input
Generator
VI
50 W
NOTE A
VCC1
VI
VCC1/2
VCC1/2
OUT
0V
tPHL
tPLH
CL
NOTE B
VO
VO
VOH
90%
50%
50%
10%
tr
VOL
tf
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50Ω.
B.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 1. Switching Characteristic Test Circuit and Voltage Waveforms
Vcc
VCC
ISOLATION BARRIER
0V
RL = 1 kW ±1%
IN
Input
Generator
VI
OUT
EN
VCC/2
VI
t PZL
VO
VO
CL
VCC/2
0V
t PLZ
VCC
0.5 V
50%
NOTE
B
50 W
VOL
3V
ISOLATION BARRIER
NOTE A
IN
Input
Generator
VI
OUT
VO
VCC
VCC/2
VI
VCC/2
0V
EN
50 W
t PZH
CL
NOTE
B
VOH
RL = 1 kW ±1%
50%
VO
0.5 V
t PHZ
0V
NOTE A
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50Ω.
B.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 2. Enable/Disable Propagation Delay Time Test Circuit and Waveform
12
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ISO7241C-Q1, ISO7242C-Q1
SLLSE40A – SEPTEMBER 2010 – REVISED SEPTEMBER 2011
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PARAMETER MEASUREMENT INFORMATION (continued)
VI
0V
or
VCC1
IN
VCC
ISOLATION BARRIER
VCC
2.7 V
VI
OUT
0V
VO
tfs
VOH
CL
NOTE A
VO
50%
fs low
VOL
A.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
B.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50Ω.
3V
IN
DISABLE
ISOLATION BARRIER
Figure 3. Failsafe Delay Time Test Circuit and Voltage Waveforms
OUT
VCC
VO
VI
0V
CTRL
t wake
VCC
CL
Input
VI
Generator
0V
( Note B)
50 W
IN
0V
DISABLE
ISOLATION BARRIER
( Note A)
50 %
VO
0V
VCC2
OUT
VO
VI
VCC2/2
0V
t wake
CTRL
VCC2
CL
Input
Generator
VCC2/2
VI
3V
(Note B )
50 W
50 %
VO
( Note A )
0V
NOTE: Which ever test yields the longest time is used in this data sheet
A.
Whichever test yields the longest time is used in this data sheet.
Figure 4. Wake Time From Input Disable Test Circuit and Voltage Waveforms
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ISO7240CF-Q1, ISO7240C-Q1
ISO7241C-Q1, ISO7242C-Q1
SLLSE40A – SEPTEMBER 2010 – REVISED SEPTEMBER 2011
www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
VCC1
VCC2
S1
ISOLATION BARRIER
C = 0.1 mF± 1%
IN
GND1
C = 0.1 mF± 1%
OUT
NOTE B
Pass-fail criteria:
Output must
remain stable
VOH or VOL
GND2
VCM
A.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
B.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50Ω.
Figure 5. Common-Mode Transient Immunity Test Circuit and Voltage Waveform
VCC1
DUT
Tektronix
HFS9009
IN
OUT
0V
Tektronix
784D
PATTERN
GENERATOR
VCC/2
Jitter
NOTE: PRBS bit pattern run length is 216 – 1. Transition time is 800 ps. NRZ data input has no more than five consecutive 1s
or 0s.
Figure 6. Peak-to-Peak Eye-Pattern Jitter Test Circuit and Voltage Waveform
14
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ISO7240CF-Q1, ISO7240C-Q1
ISO7241C-Q1, ISO7242C-Q1
SLLSE40A – SEPTEMBER 2010 – REVISED SEPTEMBER 2011
www.ti.com
DEVICE INFORMATION
PACKAGE CHARACTERISTICS
PARAMETER
L(I01)
TEST CONDITIONS
MIN
TYP MAX
UNIT
Minimum air gap (Clearance)
Shortest terminal-to-terminal distance through air
8.34
mm
L(I02)
Minimum external tracking (Creepage)
Shortest terminal-to-terminal distance across the
package surface
8.1
mm
CTI
Tracking resistance (comparative
tracking index)
DIN IEC 60112/VDE 0303 Part 1
≥ 175
V
Minimum Internal Gap (Internal
Clearance)
Distance through the insulation
0.008
mm
RIO
Isolation resistance
Input to output, VIO = 500 V, all pins on each side of the
barrier tied together creating a two-terminal device
CIO
Barrier capacitance Input to output
CI
Input capacitance to ground
>1012
Ω
VI = 0.4 sin (4E6πt)
2
pF
VI = 0.4 sin (4E6πt)
2
pF
IEC 60664-1 RATINGS TABLE
PARAMETER
TEST CONDITIONS
Basic isolation group
Installation classification
SPECIFICATION
Material group
IIIa
Rated mains voltage ≤150 VRMS
I-IV
Rated mains voltage ≤300 VRMS
I-III
REGULATORY INFORMATION
VDE
CSA
UL
Certified according to IEC 60747-5-2
Approved under CSA Component
Acceptance Notice
Recognized under 1577 Component Recognition
Program (1)
File Number: 40016131
File Number: 1698195
File Number: E181974
(1)
Production tested ≥ 3000 Vrms for 1 second in accordance with UL 1577.
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ISO7240CF-Q1, ISO7240C-Q1
ISO7241C-Q1, ISO7242C-Q1
SLLSE40A – SEPTEMBER 2010 – REVISED SEPTEMBER 2011
www.ti.com
DEVICE I/O SCHEMATICS
Enable
VCC
Output
Input
VCC
VCC
VCC
VCC
VCC
VCC
1 MW
1 MW
500 W
IN
EN
8W
500 W
OUT
13 W
ISO7240CF
Input
VCC
VCC
IN
500 W
1 MW
THERMAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
Low-K Thermal Resistance (1)
168
High-K Thermal Resistance
96.1
UNIT
θJA
Junction-to-air
θJB
Junction-to-Board Thermal Resistance
61
°C/W
θJC
Junction-to-Case Thermal Resistance
48
°C/W
PD
(1)
16
Device Power Dissipation
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
Input a 50% duty cycle square wave
°C/W
220
mW
Tested in accordance with the Low-K or High-K thermal metric definitions of EIA/JESD51-3 for leaded surface mount packages.
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ISO7240CF-Q1, ISO7240C-Q1
ISO7241C-Q1, ISO7242C-Q1
SLLSE40A – SEPTEMBER 2010 – REVISED SEPTEMBER 2011
www.ti.com
TYPICAL CHARACTERISTIC CURVES
ISO7240C RMS SUPPLY CURRENT
vs
SIGNALING RATE
ISO7241C RMS SUPPLY CURRENT
vs
SIGNALING RATE
45
45
TA = 25°C,
Load = 15 pF,
All Channels
40
ICC - Supply Current - mA/RMS
ICC - Supply Current - mA/RMS
40
35
5-V ICC2
30
3.3-V ICC2
25
20
5-V ICC1
15
10
5
35
5-V ICC2
30
20
3.3-V ICC2
15
50
75
100
Signaling Rate - Mbps
125
5
0
0
150
75
100
Figure 8.
ISO7242C RMS SUPPLY CURRENT
vs
SIGNALING RATE
PROPAGATION DELAY
vs
FREE-AIR TEMPERATURE
125
150
45
TA = 25°C,
Load = 15 pF,
All Channels
40
C 3.3-V tpLH, tpHL
35
30
Propagation Delay - ns
ICC - Supply Current - mA/RMS
50
Figure 7.
35
5-V ICC1,ICC2
25
20
15
3.3-V ICC1,ICC2
C 5-V tpLH, tpHL
30
25
M 3.3-V tpLH, tpHL
20
15
M 5-V tpLH, tpHL
10
10
5
5
0
0
25
Signaling Rate - Mbps
45
40
3.3-V ICC1
10
3.3-V ICC1
25
5-V ICC1
25
0
0
TA = 25°C,
Load = 15 pF,
All Channels
TA = 25°C,
Load = 15 pF,
All Channels
0
25
50
75
100
Signaling Rate - Mbps
125
150
-40
-25
-10
5
80
65
35
20
50
TA - Free-Air Temperature - °C
Figure 9.
95
110
125
Figure 10.
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ISO7240CF-Q1, ISO7240C-Q1
ISO7241C-Q1, ISO7242C-Q1
SLLSE40A – SEPTEMBER 2010 – REVISED SEPTEMBER 2011
www.ti.com
TYPICAL CHARACTERISTIC CURVES (continued)
INPUT VOLTAGE THRESHOLD
vs
FREE-AIR TEMPERATURE
VCC1 FAILSAFE THRESHOLD
vs
FREE-AIR TEMPERATURE
1.4
3
5 V Vth+
1.3
2.9
VCC1 - Failsafe Threshold - V
Input Voltage Threshold - V
1.35
3.3 V Vth+
1.25
1.2
Air Flow at 7 cf/m,
Low_K Board
1.15
5 V Vth1.1
2.8
VCC at 5 V or 3.3 V,
Load = 15 pF,
Air Flow at 7/cf/m,
Low-K Board
2.7
Vfs+
2.6
2.5
Vfs-
2.4
2.3
2.2
1.05
1
-40
3.3 V Vth-25
-10
2.1
5
20
35
50
65
80
TA - Free-Air Temperature - °C
95
110
2
-40
125
-10
5
20
35
50
65
80
95
110
125
TA - Free-Air Temperature - °C
Figure 11.
Figure 12.
HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
50
50
Load = 15 pF,
TA = 25°C
VCC = 5 V
Load = 15 pF,
TA = 25°C
45
40
IO - Output Current - mA
40
IO - Output Current - mA
-25
VCC = 3.3 V
30
20
35
VCC = 3.3 V
30
25
VCC = 5 V
20
15
10
10
5
0
0
0
2
4
VO - Output Voltage - V
6
0
1
Figure 13.
18
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2
3
VO - Output Voltage - V
4
5
Figure 14.
Copyright © 2010–2011, Texas Instruments Incorporated
Product Folder Link(s): ISO7240CF-Q1 ISO7241C-Q1
ISO7240CF-Q1, ISO7240C-Q1
ISO7241C-Q1, ISO7242C-Q1
SLLSE40A – SEPTEMBER 2010 – REVISED SEPTEMBER 2011
www.ti.com
APPLICATION INFORMATION
2 mm
max. from
VCC1
VCC1
2 mm
max. from
VCC2
VCC2
0.1 mF
0.1 mF
1
16
2
15
IN A
3
14
OUT A
IN B
4
13
OUT B
IN C
5
12
OUT C
IN D
6
11
GND1
GND2
NC
7
10
8
9
OUT D
EN
GND2
GND1
ISO7240x
Figure 15. Typical ISO7240x Application Circuit
2 mm
max. from
VCC1
VCC1
2 mm
max. from
VCC2
VCC2
0.1 mF
0.1 mF
1
16
2
15
IN A
3
14
OUT A
IN B
4
13
OUT B
IN C
5
12
OUT C
6
11
GND1
IN D
GND2
DISABLE
OUT D
CTRL
7
10
8
9
GND2
GND1
ISO7240CF
Figure 16. Typical ISO7240CF Failsafe-Low Application Circuit
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ISO7240CF-Q1, ISO7240C-Q1
ISO7241C-Q1, ISO7242C-Q1
SLLSE40A – SEPTEMBER 2010 – REVISED SEPTEMBER 2011
www.ti.com
LIFE EXPECTANCY vs WORKING VOLTAGE
WORKING LIFE -- YEARS
100
VIORM at 560-V
28 Years
10
0
120
250
500
750
880
1000
WORKING VOLTAGE (VIORM) -- V
Figure 17. Time-Dependant Dielectric Breakdown Testing Results
20
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
ISO7240CFQDWRQ1
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
ISO7240CFQ
ISO7241CQDWRQ1
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
ISO7241CQ
ISO7242CQDWRQ1
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
ISO7242CQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
