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ISO7310-Q1
SLLSER6 – DECEMBER 2015
ISO7310-Q1 Robust EMC, Low Power, Single Channel Digital Isolator
1 Features
2 Applications
•
•
•
1
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•
•
•
•
•
•
•
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Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to
+125°C Ambient Operating Temperature
Range
– Device HBM Classification Level 3A
– Device CDM Classification Level C6
Signaling Rate: 25 Mbps
Integrated Noise Filter at the Input
Default Output High and Low Options
Low Power Consumption: Typical ICC
– 1.9 mA at 1 Mbps, 3.8 mA at 25 Mbps (5-V
Supplies)
– 1.4 mA at 1 Mbps, 2.6 mA at 25 Mbps (3.3-V
Supplies)
Low Propagation Delay: 32 ns Typical (5-V
Supplies)
65-kV/μs Transient Immunity, Typical (5-V
Supplies)
Robust Electromagnetic Compatibility (EMC)
– System-level ESD, EFT, and Surge Immunity
– Low Emissions
Isolation Barrier Life: > 25 Years
Operates from 3.3-V and 5-V Supplies
3.3-V and 5-V Level Translation
Narrow Body SOIC-8 Package
Safety and Regulatory Approvals:
– 4242-VPK Isolation per DIN V VDE V 0884-10
and DIN EN 61010-1
– 3000-VRMS Isolation for 1 minute per UL 1577
– CSA Component Acceptance Notice 5A,
IEC 60950-1 and IEC 61010-1 End Equipment
Standards
– Planned CQC Certification per GB4943.1-2011
Opto-Coupler Replacement in:
– Industrial FieldBus
– ProfiBus
– ModBus
– DeviceNet™ Data Buses
– Servo Control Interface
– Motor Control
– Power Supplies
– Battery Packs
3 Description
The ISO7310-Q1 device provides galvanic isolation
up to 3000 VRMS for 1 minute per UL 1577 and 4242
VPK per VDE V 0884-10. These devices have one
isolated channel comprised of a logic input and
output buffer separated by a silicon dioxide (SiO2)
insulation barrier. Used in conjunction with isolated
power supplies, the ISO7310-Q1 device prevents
noise currents on a data bus or other circuit from
entering the local ground and interfering with or
damaging sensitive circuitry. The device has
integrated noise filters for harsh industrial
environment where short noise pulses may be
present at the device input pins.
The ISO7310-Q1 device has TTL input thresholds
and operate from 3-V to 5.5-V supply levels. Through
innovative chip design and layout techniques,
electromagnetic compatibility of the ISO7310-Q1
device has been significantly enhanced to enable
system-level ESD, EFT, Surge and Emissions
compliance.
Device Information(1)
PART NUMBER
ISO7310-Q1
PACKAGE
SOIC (8)
BODY SIZE (NOM)
4.90 mm × 3.91 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
VCC1
Isolation
Capacitor
VCC2
IN
OUT
GND1
GND2
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ISO7310-Q1
SLLSER6 – DECEMBER 2015
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
4
4
4
4
5
5
5
5
6
6
6
7
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics—5-V Supply .....................
Supply Current Characteristics—5-V Supply ............
Electrical Characteristics—3.3-V Supply ..................
Supply Current Characteristics—3.3-V Supply .........
Power Dissipation Characteristics ............................
Switching Characteristics—5-V Supply...................
Switching Characteristics ........................................
Typical Characteristics ............................................
8
Detailed Description ............................................ 10
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
10
10
11
14
Applications and Implementation ...................... 15
9.1 Application Information............................................ 15
9.2 Typical Application ................................................. 15
10 Power Supply Recommendations ..................... 17
11 Layout................................................................... 18
11.1 Layout Guidelines ................................................. 18
11.2 Layout Example .................................................... 18
12 Device and Documentation Support ................. 19
12.1
12.2
12.3
12.4
12.5
Documentation Support ........................................
Community Resource............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
19
19
19
19
19
13 Mechanical, Packaging, and Orderable
Information ........................................................... 19
Parameter Measurement Information .................. 9
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
December 2015
*
Initial release.
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5 Pin Configuration and Functions
VCC1
1
IN
2
VCC1
3
GND1
4
Isolation
D Package
8-Pin SOIC
Top View
8
VCC2
7
GND2
6
OUT
5
GND2
Pin Functions
PIN
NAME
NO.
GND1
4
GND2
5
7
I/O
DESCRIPTION
—
Ground connection for VCC1
—
Ground connection for VCC2
IN
2
I
Input
OUT
6
O
Output
—
Power supply, VCC1
—
Power supply, VCC2
VCC1
VCC2
1
3
8
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Supply voltage (2)
Voltage
VCC1 , VCC2
(2)
IN, OUT
MIN
MAX
–0.5
6
–0.5
UNIT
V
VCC+0.5
(3)
V
IO
Output current
±15
mA
TJ
Junction temperature
150
°C
Tstg
Storage temperature
150
°C
(1)
(2)
(3)
–65
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal and are peak voltage values.
Maximum voltage must not exceed 6 V.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1)
±4000
Charged-device model (CDM), per AEC Q100-011
±1500
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
MIN
NOM
Supply voltage
IOH
High-level output current
IOL
Low-level output current
VIH
High-level input voltage
2
5.5
VIL
Low-level input voltage
0
0.8
tui
Input pulse duration
1 / tui
Signaling rate
TJ
Junction temperature (1)
TA
Ambient temperature
(1)
3
MAX
VCC1, VCC2
5.5
–4
UNIT
V
mA
4
40
mA
V
V
ns
0
–40
25
25
Mbps
136
°C
125
°C
To maintain the recommended operating conditions for TJ, see the Thermal Information table.
6.4 Thermal Information
ISO7310-Q1
THERMAL METRIC (1)
D (SOIC)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
119.9
°C/W
RθJCtop
Junction-to-case (top) thermal resistance
65.2
°C/W
RθJB
Junction-to-board thermal resistance
61.3
°C/W
ψJT
Junction-to-top characterization parameter
19.3
°C/W
ψJB
Junction-to-board characterization parameter
60.7
°C/W
RθJCbot
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics—5-V Supply
VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
MIN
TYP
IOH = –4 mA; see Figure 9
TEST CONDITIONS
VCC2 – 0.5
4.7
IOH = –20 μA; see Figure 9
VCC2 – 0.1
5
VOH
High-level output voltage
VOL
Low-level output voltage
VI(HYS)
Input threshold voltage hysteresis
IIH
High-level input current
IN = VCC
IIL
Low-level input current
IN = 0 V
CMTI
Common-mode transient immunity
VI = VCC or 0 V; see Figure 11.
MAX
UNIT
V
IOL = 4 mA; see Figure 9
0.2
0.4
IOL = 20 μA; see Figure 9
0
0.1
V
480
mV
μA
10
μA
–10
25
65
kV/μs
6.6 Supply Current Characteristics—5-V Supply
All inputs switching with square wave clock signal for dynamic ICC measurement. VCC1 and VCC2 at 5 V ± 10% (over
recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
DC to 1 Mbps
Supply current for VCC1 and VCC2
DC Input: VI = VCC or 0 V,
AC Input: CL = 15 pF
10 Mbps
CL = 15 pF
25 Mbps
CL = 15 pF
SUPPLY
CURRENT
MIN
TYP
MAX
ICC1
0.3
0.6
ICC2
1.6
2.4
ICC1
0.5
1
ICC2
2.2
3.2
ICC1
0.8
1.3
ICC2
3
4.2
MAX
UNIT
mA
6.7 Electrical Characteristics—3.3-V Supply
VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
MIN
TYP
IOH = –4 mA; see Figure 9
TEST CONDITIONS
VCC2 – 0.5
3
IOH = –20 μA; see Figure 9
VCC2 – 0.1
3.3
VOH
High-level output voltage
VOL
Low-level output voltage
VI(HYS)
Input threshold voltage hysteresis
IIH
High-level input current
IN = VCC
IIL
Low-level input curre
IN = 0 V
CMTI
Common-mode transient immunity
VI = VCC or 0 V; see Figure 11
V
IOL = 4 mA; see Figure 9
0.2
0.4
IOL = 20 μA; see Figure 9
0
0.1
450
V
mV
10
μA
μA
–10
25
UNIT
50
kV/μs
6.8 Supply Current Characteristics—3.3-V Supply
All inputs switching with square wave clock signal for dynamic ICC measurement. VCC1 and VCC2 at 3.3 V ± 10% (over
recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
DC to 1 Mbps
Supply current for VCC1 and VCC2
DC Input: VI = VCC or 0 V,
AC Input: CL = 15 pF
10 Mbps
CL = 15 pF
25 Mbps
CL = 15 pF
SUPPLY
CURRENT
MIN
TYP
MAX
ICC1
0.2
0.4
ICC2
1.2
1.8
ICC1
0.3
0.5
ICC2
1.6
2.2
ICC1
0.5
0.8
ICC2
2.1
3
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UNIT
mA
5
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SLLSER6 – DECEMBER 2015
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6.9 Power Dissipation Characteristics
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF, Input a 12.5 MHz 50% duty-cycle square wave (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PD
Maximum power dissipation
34
mW
PD1
Power dissipation by Side-1
7.9
mW
PD2
Power dissipation by Side-2
26.1
mW
6.10 Switching Characteristics—5-V Supply
VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
tPLH, tPHL
TEST CONDITIONS
Propagation delay time
See Figure 9
PWD
(1)
Pulse width distortion |tPHL – tPLH|
See Figure 9
tsk(pp)
(2)
Part-to-part skew time
MIN
TYP
MAX
20
32
58
UNIT
ns
4
ns
24
ns
tr
Output signal rise time
See Figure 9
2.5
ns
tf
Output signal fall time
See Figure 9
2
ns
tfs
Fail-safe output delay time from input
power loss
See Figure 10
7.5
μs
(1)
(2)
Also known as pulse skew.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
6.11 Switching Characteristics
VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
tPLH, tPHL
Propagation delay time
See Figure 9
PWD (1)
Pulse width distortion |tPHL – tPLH|
See Figure 9
tsk(pp)
(2)
MIN
TYP
MAX
22
36
67
ns
3.5
ns
28
ns
Part-to-part skew time
UNIT
tr
Output signal rise time
See Figure 9
3.2
ns
tf
Output signal fall time
See Figure 9
2.7
ns
tfs
Fail-safe output delay time from input
power loss
See Figure 10
7.4
μs
(1)
(2)
6
Also known as pulse skew.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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6.12 Typical Characteristics
3.5
2.5
2
1.5
1
0.5
ICC1 atat3.3
ICC2
5 VV
2.5
2
1.5
1
0.5
0
0
0
5
10
15
20
25
Data Rate (Mbps)
TA = 25°C
0
6
10
15
20
25
Data Rate (Mbps)
CL = 15 pF
TA = 25°C
C014
CL = No Load
Figure 2. Supply Current vs Data Rate (With No Load)
0.9
VCC at
VV
VCC
at 53.3
Low-Level Output Voltage (V)
VCC =at3.3
VCC
5 VV
5
5
C014
Figure 1. Supply Current vs Data Rate (With 15-pF Load)
High-Level Output Voltage (V)
ICC1
ICC2 atat53.3
V V
ICC2 atat3.3
ICC1
5 VV
ICC1 atat53.3
V V
ICC2
3
Supply Current (mA)
3
Supply Current (mA)
3.5
ICC1
ICC2 atat53.3
V V
ICC1
5 VV
ICC2 atat3.3
ICC2
ICC1 atat53.3
V V
ICC1 atat3.3
ICC2
5 VV
4
3
2
1
VCC
3.3VV
V
CC atat3.3
0.8
V
VCC
CC atat55VV
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
±15
±10
0
±5
High-Level Output Current (mA)
0
TA = 25°C
15
C014
Figure 4. Low-Level Output Voltage vs Low-Level Output
Current
43
2.5
VCC
Rising
V
CC Rising
tpHL at 3.3 V
tpLH at 3.3 V
tpHL at 5 V
tpLH at 5 V
41
V
VCC
Falling
CC Falling
Propagation Delay Time (ns)
Power Supply Undervoltage Threshold (V)
10
TA = 25°C
Figure 3. High-Level Output Voltage vs High-level Output
Current
2.48
5
Low-Level Output Current (mA)
C014
2.46
2.44
2.42
2.4
2.38
2.36
39
37
35
33
31
29
27
25
2.34
±40
±20
0
20
40
60
80
Free-Air Temperature (oC)
100
120
140
±40
Figure 5. Power Supply Undervoltage Threshold vs Free-Air
Temperature
±5
30
65
100
135
Free-Air Temperature (oC)
C014
C014
Figure 6. Propagation Delay Time vs Free-Air Temperature
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Typical Characteristics (continued)
240
tGS at 5 V
tGS at 3.3 V
27
220
Pk-Pk Output Jitter (ps)
Input Glitch Suppression Time (ns)
29
25
23
21
19
17
200
180
160
140
Output Jitter at 3.3 V
120
15
Output Jitter at 5 V
100
±40
±5
30
65
Free-Air Temperature (oC)
100
135
0
5
10
15
20
Data Rate (Mbps)
C014
25
C014
TA = 25°C
Figure 7. Input Glitch Suppression Time vs Free-Air
Temperature
8
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Figure 8. Output Jitter vs Data Rate
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7 Parameter Measurement Information
Isolation Barrier
IN
Input
Generator(1)
VI
VCC1
50 Ω
VI
OUT
50%
50%
0V
tPLH
VO
tPHL
CL(2)
VOH
90%
50%
VO
50%
10%
VOL
tr
tf
(1)
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle,
tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω. At the input, a 50-Ω resistor is required to terminate the Input Generator signal. It is not
needed in actual application.
(2)
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 9. Switching Characteristic Test Circuit and Voltage Waveforms
VI
VCC
IN = 0 V (ISO7310C)
IN = VCC (ISO7310FC)
(1)
Isolation Barrier
VCC
IN
2.7 V
VI
0V
OUT
tfs
VO
fs high
CL
50%
VO
(1)
VOH
fs low V
OL
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 10. Fail-Safe Output Delay-Time Test Circuit and Voltage Waveforms
S1
C = 0.1 µF ±1%
IN
C = 0.1 µF ±1%
OUT
+
(1)
CL
GND1
GND2
+
(1)
VCC1
Pass-fail criteria:
output must remain
stable.
Isolation Barrier
VCC1
VCM
VOH or VOL
–
–
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 11. Common-Mode Transient Immunity Test Circuit
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8 Detailed Description
8.1 Overview
The isolator in Figure 12 is based on a capacitive isolation barrier technique. The I/O channel of the device
consists of two internal data channels, a high-frequency (HF) channel with a bandwidth from 100 kbps up to
25 Mbps, and a low-frequency (LF) channel covering the range from 100 kbps down to DC.
In principle, a single-ended input signal entering the HF channel is split into a differential signal via the inverter
gate at the input. The following capacitor-resistor networks differentiate the signal into transient pulses, which
then are converted into CMOS levels by a comparator. The transient pulses at the input of the comparator can
be either above or below the common mode voltage VREF depending on whether the input bit transitions from 0
to 1 or 1 to 0. The comparator threshold is adjusted based on the expected bit transition. A decision logic (DCL)
at the output of the HF channel comparator measures the durations between signal transients. If the duration
between two consecutive transients exceeds a certain time limit (as in the case of a low-frequency signal), the
DCL forces the output-multiplexer to switch from the high-frequency to the low-frequency channel.
8.2 Functional Block Diagram
Isolation Barrier
OSC
Low t Frequency
Channel
(DC...100 kbps)
PWM
VREF
LPF
0
Polarity and
Threshold Selection
IN
OUT
1 S
High t Frequency
Channel
(100 kbps...25 Mbps)
VREF
DCL
Polarity and Threshold Selection
Figure 12. Conceptual Block Diagram of a Digital Capacitive Isolator
Because low-frequency input signals require the internal capacitors to assume prohibitively large values, these
signals are pulse-width modulated (PWM) with the carrier frequency of an internal oscillator, thus creating a
sufficiently high frequency, capable of passing the capacitive barrier. As the input is modulated, a low-pass filter
(LPF) is needed to remove the high-frequency carrier from the actual data before passing it on to the output
multiplexer.
10
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8.3 Feature Description
ORDERABLE DEVICE
RATED ISOLATION
ISO7310CQDQ1 and
ISO7310CQDRQ1
DEFAULT OUTPUT
High
3000 VRMS / 4242 VPK
ISO7310FCQDQ1 and
ISO7310FCQDRQ1
(1)
MAX DATA RATE
(1)
25 Mbps
Low
See the Regulatory Information section for detailed Isolation Ratings
8.3.1 High Voltage Feature Description
8.3.1.1 Insulation and Safety-Related Specifications for D-8 Package
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
L(I01)
Minimum air gap (clearance)
Shortest terminal-to-terminal distance through air
4
mm
L(I02)
Minimum external tracking
(creepage)
Shortest terminal-to-terminal distance across the
package surface
4
mm
CTI
Tracking resistance (comparative
tracking index)
DIN EN 60112 (VDE 0303-11); IEC 60112
DTI
Minimum internal gap (internal
clearance)
Distance through the insulation
RIO
Isolation resistance, input to
output (1)
CIO
Isolation capacitance, input to
output (1)
CI
(1)
(2)
Input capacitance
(2)
400
V
13
µm
VIO = 500 V, TA = 25°C
12
>10
Ω
VIO = 500 V, 100°C ≤ TA ≤ 125°C
>1011
Ω
VIO = 0.4 sin (2πft), f = 1 MHz
0.5
pF
VI = VCC/2 + 0.4 sin (2πft), f = 1 MHz, VCC = 5 V
1.6
pF
All pins on each side of the barrier tied together creating a two-terminal device.
Measured from input pin to ground.
NOTE
Creepage and clearance requirements should be applied according to the specific
equipment isolation standards of an application. Care should be taken to maintain the
creepage and clearance distance of a board design to ensure that the mounting pads of
the isolator on the printed-circuit board do not reduce this distance.
Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves and/or ribs on a printed circuit board are used to
help increase these specifications.
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8.3.1.2 Insulation Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER (1)
SPECIFICATION
UNIT
VIOWM
Maximum isolation working voltage
TEST CONDITIONS
400
VRMS
VIORM
Maximum repetitive peak voltage per
DIN V VDE V 0884-10
566
VPK
Input-to-output test voltage per
DIN V VDE V 0884-10
VPR
After Input/Output safety test subgroup 2/3,
VPR = VIORM × 1.2, t = 10 s,
Partial discharge < 5 pC
680
Method a, After environmental tests subgroup 1,
VPR = VIORM × 1.6, t = 10 s,
Partial Discharge < 5 pC
906
Method b1,
VPR = VIORM × 1.875, t = 1 s (100% Production test)
Partial discharge < 5 pC
1062
VPK
VIOTM
Maximum transient overvoltage per
DIN V VDE V 0884-10
VTEST = VIOTM
t = 60 sec (qualification)
t= 1 sec (100% production)
4242
VPK
VIOSM
Maximum surge isolation voltage per
DIN V VDE V 0884-10
Test method per IEC 60065, 1.2/50 µs waveform,
VTEST = 1.3 × VIOSM = 7800 VPK (qualification)
6000
VPK
VISO
Withstand isolation voltage per UL 1577
VTEST = VISO = 3000 VRMS, t = 60 sec
(qualification);
VTEST = 1.2 × VISO = 3600 VRMS, t = 1 sec (100%
production)
3000
VRMS
RS
Insulation resistance
VIO = 500 V at TS = 150°C
>109
Ω
Pollution degree
(1)
2
Climatic Classification 40/125/21
Table 1. IEC 60664-1 Ratings Table
PARAMETER
TEST CONDITIONS
Basic isolation group
SPECIFICATION
Material group
Installation classification
II
Rated mains voltage ≤ 150 VRMS
I–IV
Rated mains voltage ≤ 300 VRMS
I–III
8.3.1.3 Regulatory Information
VDE
CSA
Certified according to DIN V VDE
V 0884-10 (VDE V 088410):2006-12 and DIN EN 610101 (VDE 0411-1):2011-07
Approved under CSA
Component Acceptance Notice
5A, IEC 60950-1, and IEC
61010-1
Basic Insulation
Maximum Transient Overvoltage,
4242 VPK;
Maximum Surge Isolation
Voltage, 6000 VPK;
Maximum Repetitive Peak
Voltage, 566 VPK
400 VRMS Basic Insulation and
200 VRMS Reinforced Insulation
working voltage per CSA
60950-1-07+A1+A2 and IEC
60950-1 2nd Ed.+A1+A2;
Single protection, 3000 VRMS
300 VRMS Basic Insulation
working voltage per CSA
61010-1-12 and IEC 61010-1
3rd Ed.
Certificate number: 40016131
Master contract number:
220991
(1)
12
UL
CQC
Recognized under UL 1577
Component Recognition
Program
File number: E181974
Plan to certify according to
GB4943.1-2011
(1)
Basic Insulation, Altitude ≤ 5000 m,
Tropical Climate, 250 VRMS
maximum working voltage
Certification planned
Production tested ≥ 3600 VRMS for 1 second in accordance with UL 1577.
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8.3.1.4 Safety Limiting Values
Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure of
the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat
the die and damage the isolation barrier, potentially leading to secondary system failures.
PARAMETER
TEST CONDITIONS
IS
Safety input, output, or supply
current
TS
Maximum safety temperature
MIN
TYP
MAX
RθJA = 119.9 °C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C
190
RθJA = 119.9 °C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C
290
150
UNIT
mA
°C
The safety-limiting constraint is the absolute-maximum junction temperature specified in the Absolute Maximum
Ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the
application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the
Thermal Information table is that of a device installed on a High-K Test Board for Leaded Surface-Mount
Packages. The power is the recommended maximum input voltage times the current. The junction temperature is
then the ambient temperature plus the power times the junction-to-air thermal resistance.
350
VCC1 = VCC2 = 3.6 V
VCC1 = VCC2 = 5.5 V
Safety Limiting Current (mA)
300
250
200
150
100
50
0
0
50
100
150
Ambient Temperature (qC)
200
D001
Figure 13. Thermal Derating Curve per VDE
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8.4 Device Functional Modes
Table 2 lists the functional modes for the ISO7310-Q1 device.
Table 2. Function Table (1)
OUT
(1)
(2)
(3)
VCC1
VCC2
PU
PU
IN
ISO7310CQDQ1 AND
ISO7310CQDRQ1
ISO7310FCQDQ1 AND
ISO7310FCQDRQ1
H
H
H
L
L
L
Open
H (2)
L (3)
PD
PU
X
H (2)
L (3)
X
PD
X
Undetermined
Undetermined
PU = Powered up (VCC ≥ 3 V); PD = Powered down (VCC ≤ 2.1 V); X = Irrelevant; H = High level; L = Low level
In fail-safe condition, output defaults to high level
In fail-safe condition, output defaults to low level
8.4.1 Device I/O Schematics
Input (ISO7310C)
VCC1
VCC1
VCC1
VCC1
5 µA
500 Ÿ
IN
Output
VCC2
40 Ÿ
OUT
Input (ISO7310FC)
VCC1
VCC1
VCC1
500 Ÿ
IN
5 µA
Figure 14. Device I/O Schematics
14
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9 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The ISO7310-Q1 device uses single-ended TTL-logic switching technology. The supply voltage range is from 3 V
to 5.5 V for both supplies, VCC1 and VCC2. When designing with digital isolators, keep in mind that due to the
single-ended design structure, digital isolators do not conform to any specific interface standard and are only
intended for isolating single-ended CMOS or TTL digital signal lines. The isolator is typically placed between the
data controller (essentially μC or UART), and a data converter or a line transceiver, regardless of the interface
type or standard.
9.2 Typical Application
The ISO7310-Q1 device can be used with a Texas Instruments’ microcontroller, CAN transceiver, transformer
driver, and low-dropout voltage regulator to create an Isolated CAN Interface as shown in Figure 15.
VS
10 F
3.3 V
2
Vcc
D2
1:1.33
3
MBR0520L
1
GND
4
10 F 0.1 F
3
1
EN
10 F
2
GND
MBR0520L
GND
5
ISO Barrier
5,7
GND2
0.1 F
6
8
29,57
VDDIO
0.1 F
4
GND1
OUT ISO7310-Q1 IN
VCC2
0.1 F
VCC1
0.1 F
1,3
TMS320F28
035PAGQ CANTXA
VSS
6,28
4
1
26
25
3
2
CANRXA
(1)
ISO 3.3V
5
OUT
TPS76333-Q1
SN6501-Q1
D1
IN
1,3
0.1 F
0.1 F
VCC1
VCC2
VCC
R
RS 8
CANH
SN65HVD231Q
D
CANL
GND
8
IN ISO7310-Q1 OUT
6
GND1
GND2
4
5,7
2
10
(optional)
10
(optional)
7
6
Vref 5
SM712
2
4.7 nF /
2 kV
Multiple pins and capacitors omitted for clarity purpose.
Figure 15. Isolated CAN Interface
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Typical Application (continued)
9.2.1 Design Requirements
9.2.1.1 Typical Supply Current Equations
For the equations in this section, the following is true:
• ICC1 and ICC2 are typical supply currents measured in mA
• f is the data rate measured in Mbps
• CL is the capacitive load measured in pF
At VCC1 = VCC2 = 5 V
ICC1 = 0.30517 + (0.01983 × f)
ICC2 = 1.40021 + (0.02879 × f) + (0.0021 × f × CL)
(1)
(2)
At VCC1 = VCC2 = 3.3 V
ICC1 = 0.18133 + (0.01166 × f)
ICC2 = 1.053 + (0.01607 × f) + (0.001488 × f × CL)
(3)
(4)
9.2.2 Detailed Design Procedure
Unlike optocouplers, which require external components to improve performance, provide bias, or limit current,
the ISO7310-Q1 device only requires two external bypass capacitors to operate.
VCC1
VCC1
0.1 µF
2 mm
maximum
from
VCC1
1
2
INPUT
3
4
8
2 mm
maximum
from
VCC2
0.1 µF
7
IN
OUT
6
OUTPUT
5
GND1
GND2
Figure 16. Typical ISO7310-Q1 Circuit Hook-up
9.2.2.1 Electromagnetic Compatibility (EMC) Considerations
Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge
(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances
are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level
performance and reliability depends, to a large extent, on the application board design and layout, the ISO7310Q1 device incorporates many chip-level design improvements for overall system robustness. Some of these
improvements include:
• Robust ESD protection cells for input and output signal pins and inter-chip bond pads.
• Low-resistance connectivity of ESD cells to supply and ground pins.
• Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.
• Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance
path.
• PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic
SCRs.
• Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.
16
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Typical Application (continued)
9.2.3 Application Curves
The following typical eye diagrams of the ISO7310-Q1 device indicate low jitter and wide open eye at the
maximum data rate of 25 Mbps.
Figure 17. Eye Diagram at 25 Mbps, 5 V and 25°C
Figure 18. Eye Diagram at 25 Mbps, 3.3 V and 25°C
10 Power Supply Recommendations
To help ensure reliable operation at data rates and supply voltages, a 0.1-µF bypass capacitor is recommended
at input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins as
possible. If only a single primary-side power supply is available in an application, isolated power can be
generated for the secondary-side with the help of a transformer driver such as Texas Instruments' SN6501-Q1
device. For such applications, detailed power supply design and transformer selection recommendations are
available in SN6501-Q1 datasheet (SLLSEF3).
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11 Layout
11.1 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 19). Layer stacking should
be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency
signal layer.
• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/in2.
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to
the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the
power and ground plane of each power system can be placed closer together, thus increasing the high-frequency
bypass capacitance significantly.
For detailed layout recommendations, see the application note SLLA284, Digital Isolator Design Guide.
11.1.1 PCB Material
For digital circuit boards operating at less than 150 Mbps, (or rise and fall times greater than 1 ns), and trace
lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper
alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater strength and
stiffness, and the self-extinguishing flammability-characteristics.
11.2 Layout Example
High-speed traces
10 mils
Ground plane
40 mils
Keep this
space free
from planes,
traces, pads,
and vias
FR-4
0r ~ 4.5
Power plane
10 mils
Low-speed traces
Figure 19. Recommended Layer Stack
18
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Digital Isolator Design Guide, SLLA284
• ISO7310 Evaluation Module User's Guide, SLLU206
• Isolation Glossary, SLLA353
• SN6501-Q1 Transformer Driver for Isolated Power Supplies, SLLSEF3
• SN65HVD231Q 3.3-V CAN Transceivers, SGLS398
• TMS320F28035 Piccolo™ Microcontrollers, SPRS584
• TPS76333-Q1 Low-Power 150-mA Low-Dropout Linear Regulators, SGLS247
12.2 Community Resource
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
DeviceNet, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OUTLINE
D0008B
SOIC - 1.75 mm max height
SCALE 2.800
SOIC
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4
5
B
.150-.157
[3.81-3.98]
NOTE 4
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A
B
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
SEE DETAIL A
.010
[0.25]
.004-.010
[ 0.11 -0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
.041
[1.04]
TYPICAL
4221445/B 04/2014
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15], per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008B
SOIC - 1.75 mm max height
SOIC
8X (.061 )
[1.55]
SEE
DETAILS
SYMM
8X (.055)
[1.4]
SEE
DETAILS
SYMM
1
1
8
8X (.024)
[0.6]
8
SYMM
8X (.024)
[0.6]
5
4
6X (.050 )
[1.27]
SYMM
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
(.217)
[5.5]
HV / ISOLATION OPTION
.162 [4.1] CLEARANCE / CREEPAGE
IPC-7351 NOMINAL
.150 [3.85] CLEARANCE / CREEPAGE
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
.0028 MAX
[0.07]
ALL AROUND
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221445/B 04/2014
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
D0008B
SOIC - 1.75 mm max height
SOIC
8X (.061 )
[1.55]
8X (.055)
[1.4]
SYMM
SYMM
1
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
8
SYMM
8X (.024)
[0.6]
SYMM
5
4
5
4
6X (.050 )
[1.27]
(.217)
[5.5]
(.213)
[5.4]
HV / ISOLATION OPTION
.162 [4.1] CLEARANCE / CREEPAGE
IPC-7351 NOMINAL
.150 [3.85] CLEARANCE / CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.127 MM] THICK STENCIL
SCALE:6X
4221445/B 04/2014
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
ISO7310CQDQ1
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7310Q
ISO7310CQDRQ1
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7310Q
ISO7310FCQDQ1
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7310FQ
ISO7310FCQDRQ1
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7310FQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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