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ISO7631FM, ISO7631FC, ISO7641FC
SLLSEC3F – SEPTEMBER 2012 – REVISED APRIL 2016
ISO76x1 Low-Power Triple and Quad-Channels Digital Isolators
1 Features
3 Description
•
The ISO7631F and ISO7641F devices provide
galvanic isolation up to 4242 VPK per VDE. The
ISO7631F device has three channels, two of which
operate in the forward direction and one which
operates in the reverse direction. The ISO7641F
device has 4 channels, three of which operate in the
forward direction and one of which operates in the
reverse direction. Suffix F indicates that output
defaults to low-state in fail-safe conditions (see ). MGrade devices are high-speed isolators capable of up
to150-Mbps data rates with fast propagation delays,
whereas C-Grade devices are capable of up to 25Mbps data rates with low power consumption and
integrated filters for noise-prone applications. CGrade devices are recommended for lower-speed
applications where input noise pulses of less than 6
ns duration must be suppressed, or when low-power
consumption is critical.
1
•
•
•
•
•
•
•
•
•
•
•
•
Signaling Rate: 150 Mbps (M-Grade), 25 Mbps
(C-Grade)
Robust Design with Integrated Noise Filter
(C-Grade)
Low Power Consumption, Typical ICC per Channel
(3.3-V Supplies):
– ISO7631FM: 2 mA at 10 Mbps
– ISO7631FC: 1.5 mA at 10 Mbps
– ISO7641FC: 1.3 mA at 10 Mbps
Extremely-Low ICC_disable (C-Grade)
Low Propagation Delay: 7 ns Typical (M-Grade)
Output Defaults to Low-State in Fail-Safe Mode
Wide Temperature Range: –40°C to 125°C
50 KV/µs Transient Immunity, Typical
Long Life With SiO2 Isolation Barrier
Operates From 2.7-V (M-Grade), 3.3-V and 5-V
Supply and Logic Levels
2.7-V (M-Grade), 3.3-V and 5-V Level Translation
Wide Body SOIC-16 Package
Safety and Regulatory Approvals
– 2500 VRMS Isolation for 1 Minute per UL 1577
– 4242 VPK Basic Insulation per DIN V VDE V
0884-10 and DIN EN 61010-1
– CSA Component Acceptance Notice 5A, IEC
60950-1 and IEC 61010-1 End Equipment
Standards
– CQC Certification per GB4943.1-2011
– TUV 3000 VRMS Reinforced Insulation
according to EN/UL/CSA 60950-1 and
EN/UL/CSA 61010-1
Each isolation channel has a logic input and output
buffer separated by a silicon dioxide (SiO2) insulation
barrier. Used in conjunction with isolated power
supplies, these devices prevent noise currents on a
data bus or other circuits from entering the local
ground and interfering with or damaging sensitive
circuitry. The devices have TTL input thresholds and
can operate from 2.7-V (M-Grade), 3.3-V and 5-V
supplies. All inputs are 5-V tolerant when supplied
from 3.3-V or 2.7-V supplies.
Device Information(1)
PART NUMBER
ISO7631FC
Optocoupler Replacement in:
– Industrial Fieldbus
– Profibus
– Modbus
– DeviceNet™ Data Buses
– Servo Control Interface
– Motor Control
– Power Supplies
– Battery Packs
BODY SIZE (NOM)
SOIC (16)
10.30 mm × 7.50 mm
ISO7641FC
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
2 Applications
•
PACKAGE
ISO7631FM
Simplified Schematic
VCCI
Isolation
Capacitor
VCCO
INx
OUTx
ENx
GNDI
GNDO
Copyright © 2016, Texas Instruments Incorporated
(1)
VCCI and GNDI are supply and ground
connections respectively for the input
channels.
(2)
VCCO and GNDO are supply and ground
connections respectively for the output
channels.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ISO7631FM, ISO7631FC, ISO7641FC
SLLSEC3F – SEPTEMBER 2012 – REVISED APRIL 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Available Options...................................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.17 Switching Characteristics: VCC1 at 5 V ± 10% and
VCC2 at 3.3 V ± 10% ................................................ 11
7.18 Switching Characteristics: VCC1 at 3.3 V ± 10% and
VCC2 at 5 V ± 10% ................................................... 12
7.19 Switching Characteristics: VCC1 and VCC2 at 3.3 V ±
10% .......................................................................... 12
7.20 Switching Characteristics: VCC1 and VCC2 at 2.7 V
................................................................................. 13
7.21 Typical Characteristics .......................................... 14
1
1
1
2
4
4
5
7.1
7.2
7.3
7.4
7.5
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information ................................................. 6
Electrical Characteristics: VCC1 and VCC2 at 5 V ±
10% ............................................................................ 6
7.6 Electrical Characteristics: VCC1 at 5 V ± 10% and
VCC2 at 3.3 V ± 10% .................................................. 6
7.7 Electrical Characteristics: VCC1 at 3.3 V ± 10% and
VCC2 at 5 V ± 10% ..................................................... 7
7.8 Electrical Characteristics: VCC1 and VCC2 at 3.3 V ±
10% ............................................................................ 7
7.9 Electrical Characteristics: VCC1 and VCC2 at 2.7 V
(ISO7631FM Only)..................................................... 7
7.10 Power Dissipation Characteristics .......................... 7
7.11 Supply Current Characteristics: VCC1 and VCC2 at 5
V ± 10% ..................................................................... 8
7.12 Supply Current Characteristics: VCC1 at 5 V ± 10%
and VCC2 at 3.3 V ± 10% ........................................... 9
7.13 Supply Current Characteristics: VCC1 at 3.3 V ± 10%
and VCC2 at 5 V ± 10% .............................................. 9
7.14 Supply Current Characteristics: VCC1 and VCC2 at
3.3 V ± 10% ............................................................. 10
7.15 Supply Current Characteristics: VCC1 and VCC2 at
2.7 V (ISO7631FM Only) ........................................ 10
7.16 Switching Characteristics: VCC1 and VCC2 at 5 V ±
10% .......................................................................... 11
8
9
Parameter Measurement Information ................ 17
Detailed Description ............................................ 19
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
19
19
20
23
10 Application and Implementation........................ 24
10.1 Application Information.......................................... 24
10.2 Typical Application ............................................... 24
11 Power Supply Recommendations ..................... 27
12 Layout................................................................... 27
12.1 Layout Guidelines ................................................. 27
12.2 Layout Example .................................................... 27
13 Device and Documentation Support ................. 28
13.1
13.2
13.3
13.4
13.5
13.6
Documentation Support ........................................
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
28
28
28
28
28
28
14 Mechanical, Packaging, and Orderable
Information ........................................................... 28
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (August 2015) to Revision F
•
Page
Changed the ISO7631 pin image in the Pin Configuration and Functions section ............................................................... 4
Changes from Revision D (September 2013) to Revision E
Page
•
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. ............................. 1
•
Added 2.7-V (M-Grade), 3.3-V and 5-V Level Translation to Features section ..................................................................... 1
•
Deleted marked as column from Available Options table....................................................................................................... 4
•
Added Footnote 3 to Absolute Maximum Ratings table. ........................................................................................................ 5
•
Changed thermal metric values in the Thermal Information table. ........................................................................................ 6
•
Changed VCCX to VCCOin Electrical Characteristics: VCC1 and VCC2 at 5 V ± 10% table. ........................................................ 6
•
Added cross-reference to VI = VCCI in the Electrical Characteristics: VCC1 and VCC2 at 5 V ± 10% table. ....................... 6
•
Changed Footnote 1 of the Electrical Characteristics: VCC1 and VCC2 at 5 V ± 10% table for clarification. ..................... 6
2
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SLLSEC3F – SEPTEMBER 2012 – REVISED APRIL 2016
•
Added cross-reference to VI = VCCI in the Electrical Characteristics: VCC1 at 5 V ± 10% and VCC2 at 3.3 V ± 10%
table. ....................................................................................................................................................................................... 6
•
Added footnote to the Electrical Characteristics: VCC1 at 3.3 V ± 10% and VCC2 at 5 V ± 10% table. .............................. 7
•
Changed VCCX to VCCO in the Electrical Characteristics: VCC1 and VCC2 at 3.3 V ± 10% table. ........................................ 7
•
Changed footnote 1 in the Electrical Characteristics: VCC1 and VCC2 at 3.3 V ± 10% table for clarification. ..................... 7
•
Changed VCCX to VCCO in the Electrical Characteristics: VCC1 and VCC2 at 2.7 V table. ................................................... 7
•
Deleted IEC and for DW-16 Package from IEC Package Insulation and Safety-Related Specifications for DW-16
Package section. .................................................................................................................................................................. 20
•
Changed L(I01) MIN from 8.3 mm to 8 mm, L(IO2) MIN from 8.1 mm to 8 mm, and DIN IEC 60112 / VDE 0303 Part
1 to DIN EN 60112 (VDE 0303-11); IEC 60112 in the Package Insulation and Safety-Related Specifications table. ....... 20
•
Deleted footnote 2 from Package Insulation and Safety-Related Specifications IEC and for DW-16 Package from
IEC Package Insulation and Safety-Related Specifications for DW-16 Package section.. .................................................. 20
•
Changed VDE Standard to DIN V VDE V 0884-10 (VDE V 0084-10): 2006-12. ................................................................ 21
•
Changed the value for θJA from 72 °C/W to 77.5 °C/W for the Test Conditions and the values for Safety input,
output, or supply current max from 316, 482, and 643 to 293, 448 and 597 in the Safety Limiting Values table. ............. 22
•
Changed safety temperature to case temperature in Safety Limiting Values. ..................................................................... 22
•
Changed name of DW-16 θJC Thermal Derating Curve per IEC 64747-5-2 to Thermal Derating Curve for Safety
Limiting Current per VDE...................................................................................................................................................... 22
•
Changed Figure 22 in the Safety Limiting Values section. .................................................................................................. 22
•
Changed I/O schematics figure in Feature Description section. ......................................................................................... 23
Changes from Revision C (August 2013) to Revision D
Page
•
Deleted 2500 VRMS from Rated Isolation Data ....................................................................................................................... 4
•
Changed the Table 3, TUV column From: Certificate Number: U8V 13 07 77311 009 To: Certificate Number: U8V
13 09 77311 010................................................................................................................................................................... 21
Changes from Revision B (April 2013) to Revision C
Page
•
Changed the Description ........................................................................................................................................................ 1
•
Deleted ISO7640FC from the Available Options table ........................................................................................................... 4
•
Changed The ISO7631FC Rated Isolation values in the Available Options table ................................................................. 4
•
Deleted Graph ISO7640FC Supply Current Per Channel vs Data Rate .............................................................................. 14
•
Deleted Graph ISO7640FC Supply Current For All Channels vs Data Rate ....................................................................... 14
•
Added the TUV column to Table 3 ....................................................................................................................................... 21
•
Deleted ISO7640FC from the TYPICAL SUPPLY CURRENT EQUATIONS section .......................................................... 25
•
Deleted the ISO7640 circuit from the APPLICATION INFORMATION section.................................................................... 27
Changes from Revision A (September 2012) to Revision B
Page
•
Changed the VIOTM SPECIFICATION From: 4000 VPEAK to 4242 VPEAK............................................................................... 21
•
Changed Table 3: 4242 VPK To: 4000 VPK .......................................................................................................................... 21
Changes from Original (September 2012) to Revision A
Page
•
Changed Description text From: "applications where input noise pulses of less than 10 ns duration..."
To:"applications where input noise pulses of less than 6 ns duration..."................................................................................ 1
•
Added note Product Preview to ISO7640FC in the Available Options table.......................................................................... 4
•
Changed Input PU in the Function table From: Z To: 'Undetermined .................................................................................. 23
Copyright © 2012–2016, Texas Instruments Incorporated
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SLLSEC3F – SEPTEMBER 2012 – REVISED APRIL 2016
www.ti.com
5 Available Options
PRODUCT
RATED ISOLATION (1)
PACKAGE
INPUT
THRESHOLD
DATA RATE
INTEGRATED NOISE
FILTER
CHANNEL
DIRECTION
ISO631FM
4242 VPK
DW-16
~1.5 V TTL
150 Mbps
No
2 Forward,
1 Reverse
ISO7631FC
4242 VPK
DW-16
~1.5 V TTL
25 Mbps
Yes
2 Forward,
1 Reverse
ISO7641FC
4242 VPK
DW-16
~1.5 V TTL
25 Mbps
Yes
3 Forward,
1 Reverse
(1)
See the Table 3 table for detailed isolation ratings.
6 Pin Configuration and Functions
ISO7641 DW Package
16-Pin SOIC
Top View
ISO7631 DW Package
16-Pin SOIC
Top View
VCC1
GND1
1
16
VCC1
GND1
16
15
VCC2
GND2
1
2
2
15
VCC2
GND2
INA
3
14
OUTA
INA
3
14
OUTA
INB
4
13
OUTB
INB
4
13
OUTB
INC
OUTD
5
12
OUTC
5
12
INC
6
11
IND
OUTC
NC
6
11
NC
EN1
GND1
7
10
10
9
EN1
GND1
7
8
EN2
GND2
8
9
EN2
GND2
Pin Functions
PIN
NAME
I/O
DESCRIPTION
7
I
Enables (when input is High or Open) or Disables (when input is Low) OUTD of ISO7641 and
OUTC of ISO7631
10
I
Enables (when input is High or Open) or Disables (when input is Low) OUTA, OUTB, and
OUTC of ISO7641
Enables (when input is High or Open) or Disables (when input is Low) OUTA and OUTB of
ISO7631
ISO7641
ISO7631
EN1
7
EN2
10
GND1
2, 8
2, 8
–
Ground connection for VCC1
GND2
9, 15
9, 15
–
Ground connection for VCC2
INA
3
3
I
Input, channel A
INB
4
4
I
Input, channel B
INC
5
12
I
Input, channel C
IND
11
–
I
Input, channel D
NC
–
6,11
–
No Connect pins are floating with no internal connection
OUTA
14
14
O
Output, channel A
OUTB
13
13
O
Output, channel B
OUTC
12
5
O
Output, channel C
OUTD
6
–
O
Output, channel D
VCC1
1
1
–
Power supply, VCC1
VCC2
16
16
–
Power supply, VCC2
4
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SLLSEC3F – SEPTEMBER 2012 – REVISED APRIL 2016
7 Specifications
7.1 Absolute Maximum Ratings
See
(1)
VCC1
VCC2 (2)
Supply voltage
Voltage
INx, OUTx, ENx
IO
Output current
TJ
Maximum junction temperature
TSTG
Storage temperature
(1)
(2)
(3)
MIN
MAX
UNIT
–0.5
6
V
–0.5
(3)
6
–65
V
±15
mA
150
°C
150
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak
voltage values.
Maximum voltage must not exceed 6 V.
7.2 ESD Ratings
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
±4000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1500
Machine model (MM), JEDEC JESD22-A115-A
±200
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN
VCC1, VCC2
Supply voltage
IOH
High-level output current
IOL
Low-level output current
VIH
High-level input voltage
VIL
Low-level input voltage
tui
Input pulse duration
NOM
MAX
M-Grade
2.7
5.5
C-Grade
3
5.5
–4
UNIT
V
mA
4
mA
2
5.5
V
0
0.8
V
M-Grade: ≥3-V Operation
6.67
M-Grade: 1011
VIO = 500 V at TS = 150°C
>109
VI = 0.4 sin (2πft), f = 1MHz
VPEAK
VPEAK
Ω
2
Pollution degree
(1)
(2)
SPECIFICATION
pF
2
Climatic Classification 40/125/21
All pins on each side of the barrier tied together creating a two-terminal device.
Table 2. IEC 60664-1 Ratings Table
PARAMETER
TEST CONDITIONS
SPECIFICATION
Material Group
II
Installation classification / Overvoltage
category for basic insulation
Rated mains voltage ≤ 300 VRMS
I–IV
Rated mains voltage ≤ 600 VRMS
I–III
Rated mains voltage ≤ 1000 VRMS
I–II
Table 3. Regulatory Information
VDE
TUV
CSA
Certified according to
DIN V VDE V 0884-10
(VDE V 0884-10):200612 and DIN EN 610101 (VDE 0411-1):201107
Certified according to
EN/UL/CSA 60950-1 and 610101
Approved under CSA
Component Acceptance Notice
5A, IEC 60950-1 and IEC
61010-1
Basic Insulation
Maximum Transient
Overvoltage, 4242 VPK
Maximum Working
Voltage, 1414 VPK
3000 VRMS Reinforced Insulation,
400 VRMS maximum working
voltage
3000 VRMS Basic Insulation, 600
VRMS maximum working voltage
3000 VRMS Isolation Rating
Certificate number:
40016131
Certificate number:
U8V 13 09 77311 010
Master contract number:
220991
(1)
UL
CQC
Recognized under 1577
Component Recognition
Program
Single Protection, 2500
VRMS (1)
File number: E181974
Certified according to
GB4943.1-2011
Reinforced Insulation, Altitude ≤
5000 m, Tropical Climate, 250
VRMS Maximum Working
Voltage
Certificate number:
CQC14001109542
Production tested ≥ 3000 VRMS for 1 second in accordance with UL 1577.
Copyright © 2012–2016, Texas Instruments Incorporated
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9.3.1.1 Safety Limiting Values
Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry.
A failure of the IO can allow low resistance to ground or the supply and, without current limiting, dissipate
sufficient power to overheat the die and damage the isolation barrier potentially leading to secondary system
failures.
PARAMETER
IS
Safety input, output, or supply
current
TS
Maximum safety temperature
TEST CONDITIONS
DW-16
MIN
TYP MAX
θJA = 77.5 °C/W, VI = 5.5V, TJ = 150°C, TA = 25°C
293
θJA = 77.5 °C/W, VI = 3.6V, TJ = 150°C, TA = 25°C
448
θJA = 77.5 °C/W, VI = 2.7V, TJ = 150°C, TA = 25°C
597
150
UNIT
mA
°C
The safety-limiting constraint is the absolute maximum junction temperature specified in the absolute maximum
ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the
application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the
Thermal Information table is that of a device installed on a High-K Test Board for Leaded Surface Mount
Packages. The power is the recommended maximum input voltage times the current. The junction temperature is
then the ambient temperature plus the power times the junction-to-air thermal resistance.
700
VCC1 = VCC2 = 2.7 V
VCC1 = VCC2 = 3.6 V
VCC1 = VCC2 = 5.5 V
Safety Limiting Current - mA
600
500
400
300
200
100
0
0
50
100
Ambient Temperature - (qC)
150
200
D001
D001
Figure 22. Thermal Derating Curve for Safety Limiting Current per VDE
22
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SLLSEC3F – SEPTEMBER 2012 – REVISED APRIL 2016
9.4 Device Functional Modes
Table 4. Function Table (1)
INPUT
VCC
OUTPUT
VCC
PU
(1)
PU
INPUT
(INx)
OUTPUT ENABLE
(ENx)
OUTPUT
(OUTx)
H
H or Open
H
L
H or Open
L
X
L
Z
Open
H or Open
L
H or Open
L
PD
PU
X
PD
PU
X
L
Z
PU
PD
X
X
Undetermined
PU = Powered Up(VCC ≥ 2.7 V); PD = Powered Down (VCC ≤ 2.1 V); X = Irrelevant; H = High Level; L
= Low Level; Z = High Impedance
Input
VCCI
VCCI
Enable
Output
VCCO
VCCO VCCO
VCCO
1 MW
8W
500 W
IN
500 W
OUT
EN
13 W
7.5 µA
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Figure 23. Device I/O Schematics
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
ISO7641FC uses single-ended TTL-logic switching technology. It has a supply voltage range from 3 V to 5.5
V for both supplies, VCC1 and VCC2. When designing with digital isolators, it is important to note that due to
the single-ended design structure, digital isolators do not conform to any specific interface standard and are
only intended for isolating single-ended CMOS or TTL digital signal lines. The isolator is typically placed
between the data controller (that is, μC or UART), and a data converter or a line transceiver, regardless of
the interface type or standard.
10.2 Typical Application
ISO-BARRIER
5VISO 5VISO
0.1 F
RTD
Bridge
Thermo
couple
Current
shunt
0.1 F
5VISO
22 1
0.1 F
AVDD DVDD
11
8
AIN1+
A0
12
7
AIN1A1
27
SCLK
18
28
AIN2+
DOUT
ADS1234
17
5VISO
5VISO
AIN220
REF+
0.1 F
13
19
AIN3+
REF0.1 F
14
23
AIN3GAIN0
24
GAIN1
16
25
AIN4+
SPEED
15
26
PWDN
AIN4AGND DGND
2
21
3.3V
16
10
VCC2
VCC1
3.3V
0.1 F
1
7
EN2
EN1
3
INA
OUTA
13
4
ISO7641
INB
OUTB
5
12
OUTC
INC
11
6
IND
OUTD
9,15
2,8
GND2
GND1
14
16
10
14
VCC2
EN
VCC1
NC
11
12
14
P3.0
DVcc
5
XOUT
P3.1
6
MSP430
XIN
F2132
18
13
SOMI
P3.7
17
P3.6
15
16
P3.4
P3.5
DVss
3.3V
1
7
2
0.1 F
CLK
0.1 F
4
3
OUTA
INA
4
ISO7640
OUTB
INB
12
5
OUTC
INC
11
6
OUTD
IND
9,15
2,8
GND2
GND1
13
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Figure 24. Isolated Data Acquisition System for Process Control
10.2.1 Design Requirements
Unlike optocouplers, which require external components to improve performance, provide bias, or limit current,
the ISO76xx device only requires two external bypass capacitors to operate.
24
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SLLSEC3F – SEPTEMBER 2012 – REVISED APRIL 2016
Typical Application (continued)
10.2.2 Detailed Design Procedure
ISO7641
0.1 µF
VCC1
0.1 µF
VCC2
1
16
2
15
INA
3
14
OUTA
INB
4
13
OUTB
INC
5
12
OUTD
6
11
7
10
8
9
GND1
GND2
OUTC
IND
EN2
EN1
GND2
GND1
Copyright © 2016, Texas Instruments Incorporated
Figure 25. Typical ISO7641FC Circuit Hookup
10.2.2.1 Typical Supply Current Equations
(Calculated based on room temperature and typical Silicon process)
ISO7631FM:
At VCC1 = VCC2 = 3.3 V
ICC1 = 1.8072 + 0.0244 × f + 0.0016 × f × CL
ICC2 = 2.4625 + 0.0252 × f + 0.0033 × f × CL
(1)
(2)
At VCC1 = VCC2 = 5 V
ICC1 = 2.3183 + 0.04 × f + 0.0025 × f × CL
ICC2 = 3.2582 + 0.0403 × f + 0.0049 × f × CL
(3)
(4)
ISO7631FC:
At VCC1 = VCC2 = 3.3 V
ICC1 = 1.1762 + 0.0325 × f + 0.0017 × f × CL
ICC2 = 1.5285 + 0.0299 × f + 0.0033 × f × CL
(5)
(6)
At VCC1 = VCC2 = 5 V
ICC1 = 1.6001 + 0.0528 × f + 0.0025 × f × CL
ICC2 = 2.2032 + 0.0475 × f + 0.005 × f × CL
(7)
(8)
ISO7641FC:
At VCC1 = VCC2 = 3.3 V
ICC1 = 1.2162 + 0.0462 × f + 0.0017 × f × CL
Copyright © 2012–2016, Texas Instruments Incorporated
(9)
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Typical Application (continued)
(Calculated based on room temperature and typical Silicon process)
ICC2 = 1.8054 + 0.0411 × f + 0.005 × f × CL
(10)
At VCC1 = VCC2 = 5 V
ICC1 = 1.6583 + 0.0757 × f + 0.0025 × f × CL
ICC2 = 2.5008 + 0.0655 × f + 0.0076 × f × CL
(11)
(12)
ICC1 and ICC2 are typical supply currents measured in mA; f is data rate measured in Mbps; CL is the capacitive
load on each channel measured in pF.
10.2.3 Application Curves
TA = 25 oC, CL = 15 pF
TA = 25 oC, CL = 15 pF
VCC1 = V CC2 = 5 V
Pattern: NRZ 216-1
VCC1 = V CC2 = 3.3 V
Pattern: NRZ 216-1
Figure 26. M-Grade Typical Eye Diagram at 150 Mbps,
5 V Operation
Figure 27. M-Grade Typical Eye Diagram at 150 Mbps,
3.3 V Operation
TA = 25 oC, CL = 15 pF
VCC1 = V CC2 = 5 V
Pattern: NRZ 216-1
TA = 25 oC, CL = 15 pF
VCC1 = V CC2 = 3.3 V
Pattern: NRZ 216-1
Figure 28. C-Grade Typical Eye Diagram at 25 Mbps, 5 V
Operation
26
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Figure 29. C-Grade Typical Eye Diagram at 25 Mbps, 3.3 V
Operation
Copyright © 2012–2016, Texas Instruments Incorporated
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ISO7631FM, ISO7631FC, ISO7641FC
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SLLSEC3F – SEPTEMBER 2012 – REVISED APRIL 2016
11 Power Supply Recommendations
To ensure reliable operation at all data rates and supply voltages, a 0.1-μF bypass capacitor is recommended at
input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins as
possible. If only a single primary-side power supply is available in an application, isolated power can be
generated for the secondary-side with the help of a transformer driver such as Texas Instruments' SN6501. For
such applications, detailed power supply design and transformer selection recommendations are available in
SN6501 data sheet (SLLSEA0).
12 Layout
12.1 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 30). Layer stacking should
be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency
signal layer.
• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/in2.
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power and ground plane system to
the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the
power and ground plane of each power system can be placed closer together, thus increasing the high-frequency
bypass capacitance significantly.
NOTE
For detailed layout recommendations, see Digital Isolator Design Guide, SLLA284.
12.2 Layout Example
High-speed traces
10 mils
Ground plane
40 mils
Keep this
space free
from planes,
traces, pads,
and vias
FR-4
0r ~ 4.5
Power plane
10 mils
Low-speed traces
Figure 30. Recommended Layer Stack
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13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
For related documentation, see the following:
• Digital Isolator Design Guide, SLLA284
• Transformer Driver for Isolated Power Supplies, SLLSEA0
• Isolation Glossary, SLLA353
13.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 5. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
ISO7631FM
Click here
Click here
Click here
Click here
Click here
ISO7631FC
Click here
Click here
Click here
Click here
Click here
ISO7641FC
Click here
Click here
Click here
Click here
Click here
13.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.4 Trademarks
DeviceNet, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
13.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
28
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ISO7631FM, ISO7631FC, ISO7641FC
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SLLSEC3F – SEPTEMBER 2012 – REVISED APRIL 2016
PACKAGE OUTLINE
DW0016B
SOIC - 2.65 mm max height
SCALE 1.500
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
14X 1.27
16
1
2X
8.89
10.5
10.1
NOTE 3
8
9
0.51
0.31
0.25
C A
16X
B
7.6
7.4
NOTE 4
2.65 MAX
B
0.38
TYP
0.25
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 -8
1.27
0.40
DETAIL A
TYPICAL
(1.4)
4221009/A 08/2013
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MO-013, variation AA.
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SLLSEC3F – SEPTEMBER 2012 – REVISED APRIL 2016
www.ti.com
EXAMPLE BOARD LAYOUT
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (2)
16X (1.65)
SEE
DETAILS
1
SEE
DETAILS
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
9
8
9
8
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
LAND PATTERN EXAMPLE
SCALE:4X
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
0.07 MAX
ALL AROUND
METAL
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221009/A 08/2013
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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ISO7631FM, ISO7631FC, ISO7641FC
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SLLSEC3F – SEPTEMBER 2012 – REVISED APRIL 2016
EXAMPLE STENCIL DESIGN
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (1.65)
16X (2)
1
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
9
8
9
8
(9.3)
(9.75)
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
4221009/A 08/2013
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
ISO7631FCDW
ACTIVE
SOIC
DW
16
40
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
ISO7631FC
ISO7631FCDWR
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
ISO7631FC
ISO7631FMDW
ACTIVE
SOIC
DW
16
40
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
ISO7631FM
ISO7631FMDWR
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
ISO7631FM
ISO7641FCDW
ACTIVE
SOIC
DW
16
40
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
ISO7641FC
ISO7641FCDWR
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
ISO7641FC
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
