ISO7720-Q1, ISO7721-Q1
ISO7720-Q1,
ISO7721-Q1
SLLSEU1B – MARCH 2017
– REVISED OCTOBER
2020
SLLSEU1B – MARCH 2017 – REVISED OCTOBER 2020
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ISO772x-Q1 High-Speed, Robust EMC, Reinforced Dual-Channel Digital Isolators
1 Features
3 Description
•
•
The ISO772x-Q1 devices are high-performance, dualchannel digital isolators with 5000 V RMS (DW
package) and 3000 V RMS (D package) isolation
ratings per UL 1577. This family includes devices with
reinforced insulation ratings according to VDE, CSA,
TUV and CQC.
•
•
•
•
•
•
•
•
•
•
•
Qualified for automotive applications
AEC-Q100 qualified With the following results:
– Device temperature grade 1: –40°C to +125°C
ambient operating temperature range
– Device HBM ESD classification level 3A
– Device CDM ESD classification level C6
Functional Safety-Capable
– Documentation available to aid functional safety
system design: ISO7720-Q1, ISO7721-Q1
100 Mbps data rate
Robust isolation barrier:
– >100-Year projected lifetime at 1.5 kVRMS
working voltage
– Up to 5000 VRMS Isolation Rating
– Up to 12.8 kV surge capability
– ±100 kV/μs Typical CMTI
Wide supply range: 2.25 V to 5.5 V
2.25-V to 5.5-V level translation
Default output High (ISO772x) and Low
(ISO772xF) Options
Low power consumption, typical 1.7 mA per
channel at 1 Mbps
Low propagation delay: 11 ns typical
Robust electromagnetic compatibility (EMC)
– System-Level ESD, EFT, and surge immunity
– ±8 kV IEC 61000-4-2 contact discharge
protection across isolation barrier
– Low emissions
Wide-SOIC (DW-16) and Narrow-SOIC (D-8)
package options
Section 6.7
– DIN VDE V 0884-11:2017-01
– UL 1577 component recognition program
– IEC 60950-1, IEC 62368-1, IEC 61010-1, IEC
60601-1 and GB 4943.1-2011 certifications
The
ISO772x-Q1
devices
provide
high
electromagnetic immunity and low emissions at low
power consumption, while isolating CMOS or
LVCMOS digital I/Os. Each isolation channel has a
logic input and output buffer separated by a double
capacitive silicon dioxide (SiO2) insulation barrier. The
ISO7720-Q1 device has both channels in the same
direction while the ISO7721-Q1 device has both
channels in the opposite direction. In the event of
input power or signal loss, the default output is high
for devices without suffix F and low for devices with
suffix F. See the Device Functional Modes section for
further details.
Used in conjunction with isolated power supplies,
these devices help prevent noise currents on data
buses, such as CAN and LIN, from damaging
sensitive circuitry. Through innovative chip design and
layout techniques, the electromagnetic compatibility of
the ISO772x-Q1 devices has been significantly
enhanced to ease system-level ESD, EFT, surge, and
emissions compliance. The ISO772x-Q1 family of
devices is available in 16-pin SOIC wide-body (DW)
and 8-pin SOIC narrow-body (D) packages.
Device Information
PART NUMBER (1)
ISO7720-Q1
ISO7721-Q1
(1)
D (8)
4.90 mm × 3.91 mm
DW (16)
10.30 mm × 7.50 mm
VCCO
VCCI
Hybrid, electric and power train system (EV/HEV)
– Battery management system (BMS)
– On-board charger
– Traction inverter
– DC/DC converter
– Inverter and motor control
BODY SIZE (NOM)
For all available packages, see the orderable addendum at
the end of the datasheet.
2 Applications
•
PACKAGE
Series Isolation
Capacitors
INx
OUTx
GNDI
GNDO
Copyright © 2016, Texas Instruments Incorporated
VCCI=Input supply, VCCO=Output supply
GNDI=Input ground, GNDO=Output ground
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
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© 2020 Texas
Instruments
Incorporated
intellectual
property
matters
and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................4
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings .............................................................. 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................6
6.5 Power Ratings.............................................................6
6.6 Insulation Specifications............................................. 7
6.7 Safety-Related Certifications...................................... 8
6.8 Safety Limiting Values.................................................9
6.9 Electrical Characteristics—5-V Supply..................... 10
6.10 Supply Current Characteristics—5-V Supply.......... 10
6.11 Electrical Characteristics—3.3-V Supply................. 11
6.12 Supply Current Characteristics—3.3-V Supply....... 11
6.13 Electrical Characteristics—2.5-V Supply................ 12
6.14 Supply Current Characteristics—2.5-V Supply....... 12
6.15 Switching Characteristics—5-V Supply...................13
6.16 Switching Characteristics—3.3-V Supply................13
6.17 Switching Characteristics—2.5-V Supply................13
6.18 Insulation Characteristics Curves........................... 14
6.19 Typical Characteristics............................................ 15
7 Parameter Measurement Information.......................... 17
8 Detailed Description......................................................18
8.1 Overview................................................................... 18
8.2 Functional Block Diagram......................................... 18
8.3 Feature Description...................................................19
8.4 Device Functional Modes..........................................20
9 Application and Implementation.................................. 21
9.1 Application Information............................................. 21
9.2 Typical Application.................................................... 22
10 Power Supply Recommendations..............................26
11 Layout........................................................................... 27
11.1 Layout Guidelines................................................... 27
11.2 Layout Example...................................................... 27
12 Device and Documentation Support..........................28
12.1 Device Support....................................................... 28
12.2 Documentation Support.......................................... 28
12.3 Related Links.......................................................... 28
12.4 Receiving Notification of Documentation Updates..28
12.5 Support Resources................................................. 28
12.6 Trademarks............................................................. 28
12.7 Electrostatic Discharge Caution..............................29
12.8 Glossary..................................................................29
13 Mechanical, Packaging, and Orderable
Information.................................................................... 29
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (April 2020) to Revision B (October 2020)
Page
• Added Functional Safety bullets......................................................................................................................... 1
Changes from Revision * (March 2016) to Revision A (April 2020)
Page
• Made editorial and cosmetic changes throughout the document ...................................................................... 1
• Changed From: "Isolation Barrier Life: >40 Years" To:">100-Year Projected Lifetime at 1.5 kVRMS Working
Voltage" in Section 1 ..........................................................................................................................................1
• Added "Up to 5000 VRMS Isolation Rating" in Section 1 .................................................................................... 1
• Added "Up to 12.8 kV Surge Capability" in Section 1 ........................................................................................1
• Added "±8 kV IEC 61000-4-2 Contact Discharge Protection across Isolation Barrier" in Section 1 .................. 1
• Updated certification-related bullets in Section 1 and changed VDE standard name From: DIN V VDE V
0884-10 (VDE V 0884-10):2006-12 To: DIN VDE V 0884-11:2017-01 throughout the document...................... 1
• Updated Section 2 list.........................................................................................................................................1
• Updated Figure 3-1 to show two isolation capacitors in series per channel instead of a single isolation
capacitor ............................................................................................................................................................ 1
• Added "Contact discharge per IEC 61000-4-2" specification of ±8000 V in Section 6.2 table .......................... 5
• Changed 'Signaling' rate to 'Data' rate and added table note to Data rate specification in Section 6.3 table ....5
• Changed VIORM Value for DW-16 package From: "1414 VPK" To: "2121 VPK" in Section 6.6 table ................... 7
• Changed VIOWM value for DW-16 package From: "1000 VRMS" and "1414 VDC" To: "1500 VRMS" and "2121 V
DC" in Section 6.6 table ...................................................................................................................................... 7
• Added 'see Figure 9-6" to TEST CONDITIONS of VIOWM specification .............................................................7
• Changed VIOTM TEST CONDITIONS for 100% production test From: "VTEST = VIOTM" To: "VTEST = 1.2 x V
IOTM" in Section 6.6 table ................................................................................................................................... 7
2
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•
•
•
•
•
•
•
•
•
ISO7720-Q1, ISO7721-Q1
SLLSEU1B – MARCH 2017 – REVISED OCTOBER 2020
Changed VIOSM TEST CONDITIONS From: "Test method per IEC 60065" To: "Test method per IEC 62368-1"
in Section 6.6 table ............................................................................................................................................ 7
Changed qpd TEST CONDITIONS for method b1 test From: "Vini = VIOTM" To: "Vini = 1.2 x VIOTM" in Section
6.6 table ............................................................................................................................................................. 7
Changed the climatic category for the D package from 5/125/21 to 55/125/21 .................................................7
Updated certification information in Section 6.7 table ........................................................................................8
Switched the line colors for VCC at 2.5 V and VCC at 3.3 V in the Low-Level Output Voltage vs Low-Level
Output Current graph........................................................................................................................................15
Deleted EN from the Common-Mode Transient Immunity Test Circuit figure................................................... 17
Corrected ground symbols for "Input (Devices with F suffix)" in Section 8.4.1 ................................................ 20
Added Section 9.2.3.1 sub-section under Section 9.2.3 section ..................................................................... 24
Added 'How to use isolation to improve ESD, EFT and Surge immunity in industrial systems' application
report to Section 12.2 section .......................................................................................................................... 28
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5 Pin Configuration and Functions
GND1 1
16 GND2
NC
2
15
14 VCC2
VCC1
3
14 VCC2
13 OUTA
OUTA 4
NC
2
15
VCC1
3
INA
4
INB
5
NC
ISOLATION
16 GND2
NC
ISOLATION
GND1 1
13
NC
INA
12 OUTB
INB
5
6
11
NC
NC
6
11
NC
GND1 7
10
NC
GND1 7
10
NC
8
NC
9 GND2
INA
2
INB
3
ISOLATION
1
8 VCC2
VCC1
7 OUTA
OUTA 2
6 OUTB
GND1 4
9 GND2
Figure 5-2. ISO7721-Q1 DW Package 16-Pin SOIC
Top View
Figure 5-1. ISO7720-Q1 DW Package 16-Pin SOIC
Top View
VCC1
8
INB
5 GND2
1
3
8 VCC2
ISOLATION
NC
12 OUTB
GND1 4
Figure 5-3. ISO7720-Q1 D Package 8-Pin SOIC Top
View
7
INA
6 OUTB
5 GND2
Figure 5-4. ISO7721-Q1 D Package 8-Pin SOIC Top
View
Table 5-1. Pin Functions
PIN
NAME
D PACKAGE
I/O
DESCRIPTION
ISO7721-Q1
ISO7720-Q1
ISO7721-Q1
1, 7
1, 7
4
4
—
Ground connection for VCC1
9
9
16
16
5
5
—
Ground connection for VCC2
INA
4
13
2
7
I
Input, channel A
INB
5
5
3
3
I
Input, channel B
NC
2, 6, 8, 10, 11,
15
2, 6, 8, 10, 11,
15
—
—
—
Not connected
GND1
GND2
4
DW PACKAGE
ISO7720-Q1
OUTA
13
4
7
2
O
Output, channel A
OUTB
12
12
6
6
O
Output, channel B
VCC1
3
3
1
1
—
Power supply, VCC1
VCC2
14
14
8
8
—
Power supply, VCC2
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6 Specifications
6.1 Absolute Maximum Ratings
See (1).
Supply voltage(2)
VCC1, VCC2
MIN
MAX
UNIT
–0.5
6
V
V
Voltage at INx, OUTx
–0.5
IO
Output current
–15
15
mA
TJ
Junction temperature
150
°C
Tstg
Storage temperature
–65
150
°C
(1)
(2)
(3)
VCC +
0.5(3)
V
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak
voltage values.
Maximum voltage must not exceed 6 V.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per AEC
V(ESD)
Q100-002(1)
±6000
Electrostatic discharge Charged-device model (CDM), per AEC Q100-011
±1500
Contact discharge per IEC 61000-4-2; Isolation barrier withstand
(1)
(2)
(3)
UNIT
test(2) (3)
V
±8000
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
IEC ESD strike is applied across the barrier with all pins on each side tied together creating a two-terminal device.
Testing is carried out in air or oil to determine the intrinsic contact discharge capability of the device.
6.3 Recommended Operating Conditions
MIN
VCC1, VCC2
Supply voltage
NOM
2.25
MAX
5.5
2
V
VCC(UVLO+)
UVLO threshold when supply voltage is rising
VCC(UVLO-)
UVLO threshold when supply voltage is falling
1.7
1.8
V
VHYS(UVLO)
Supply voltage UVLO hysteresis
100
200
mV
VCCO (1) = 5 V
IOH
High-level output current
IOL
Low-level output current
VIH
High-level input voltage
2.25
UNIT
V
–4
VCCO = 3.3 V
–2
VCCO = 2.5 V
–1
mA
VCCO = 5 V
4
VCCO = 3.3 V
2
VCCO = 2.5 V
mA
1
0.7 × VCC I (1)
VCCI
V
VIL
Low-level input voltage
0
0.3 × VCCI
DR(2)
Data rate
0
100
Mbps
TA
Ambient temperature
125
°C
(1)
(2)
–40
25
V
VCCI = Input-side VCC; VCCO = Output-side VCC.
100 Mbps is the maximum specified data rate, although higher data rates are possible.
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6.4 Thermal Information
ISO772x-Q1
THERMAL
METRIC(1)
DW (SOIC)
D (SOIC)
16 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
86.5
137.7
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
49.6
54.9
°C/W
RθJB
Junction-to-board thermal resistance
49.7
71.7
°C/W
ψJT
Junction-to-top characterization parameter
32.3
7.1
°C/W
ψJB
Junction-to-board characterization parameter
49.2
70.7
°C/W
RθJC(bottom)
Junction-to-case(bottom) thermal resistance
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Power Ratings
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ISO7720-Q1
PD
Maximum power dissipation
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
input a 50 MHz 50% duty cycle square wave
100
mW
PD1
Maximum power dissipation by side-1
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
input a 50 MHz 50% duty cycle square wave
20
mW
PD2
Maximum power dissipation by side-2
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
input a 50 MHz 50% duty cycle square wave
80
mW
ISO7721-Q1
6
PD
Maximum power dissipation
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
input a 50 MHz 50% duty cycle square wave
100
mW
PD1
Maximum power dissipation by side-1
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
input a 50 MHz 50% duty cycle square wave
50
mW
PD2
Maximum power dissipation by side-2
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
input a 50 MHz 50% duty cycle square wave
50
mW
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6.6 Insulation Specifications
PARAMETER
TEST CONDITIONS
VALUE
DW-16
D-8
UNIT
CLR
External clearance (1)
Shortest terminal-to-terminal distance through air
8
4
mm
CPG
External creepage (1)
Shortest terminal-to-terminal distance across the
package surface
8
4
mm
21
21
μm
>600
>600
V
DTI
Distance through the insulation
Minimum internal gap (internal clearance)
CTI
Comparative tracking index
DIN EN 60112 (VDE 0303-11); IEC 60112; UL 746A
Material group
According to IEC 60664-1
Overvoltage category per IEC 60664-1
I
I
Rated mains voltage ≤ 150 VRMS
I–IV
I–IV
Rated mains voltage ≤ 300 VRMS
I–IV
I–III
Rated mains voltage ≤ 600 VRMS
I–IV
n/a
Rated mains voltage ≤ 1000 VRMS
I–III
n/a
AC voltage (bipolar)
2121
637
VPK
AC voltage; Time dependent dielectric breakdown
(TDDB) test; see Figure 9-6
1500
450
VRMS
DC voltage
2121
637
VDC
DIN VDE V 0884-11:2017-01(2)
VIORM
Maximum repetitive peak isolation
voltage
VIOWM
Maximum working isolation voltage
VIOTM
Maximum transient isolation voltage
VTEST = VIOTM, t = 60 s (qualification);
VTEST = 1.2 x VIOTM, t = 1 s (100% production)
8000
4242
VPK
VIOSM
Maximum surge isolation voltage(3)
Test method per IEC 62368-1, 1.2/50 µs waveform,
VTEST = 1.6 × VIOSM (qualification)
8000
5000
VPK
Method a, After Input/Output safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.2 × VIORM, tm = 10 s
≤5
≤5
Method a, After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.6 × VIORM, tm = 10 s
≤5
≤5
Method b1; At routine test (100% production) and
preconditioning (type test),
Vini = 1.2 x VIOTM, tini = 1 s;
Vpd(m) = 1.875 × VIORM, tm = 1 s
≤5
≤5
qpd
Apparent
charge(4)
Barrier capacitance, input to output(5)
CIO
Isolation resistance(5)
RIO
VIO = 0.4 × sin (2πft), f = 1 MHz
~0.5
~0.5
VIO = 500 V, TA = 25°C
>1012
>1012
VIO = 500 V, 100°C ≤ TA ≤ 125°C
>1011
>1011
VIO = 500 V at TS = 150°C
>109
>109
Pollution degree
2
2
Climatic category
55/125/21
55/125/21
5000
3000
pC
pF
Ω
UL 1577
VISO
(1)
(2)
(3)
(4)
(5)
Withstanding isolation voltage
VTEST = VISO, t = 60 s(qualification);
VTEST = 1.2 × VISO, t = 1 s (100% production)
VRMS
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application.
Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the
isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in
certain cases. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these
specifications.
This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured
by means of suitable protective circuits.
Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
Apparent charge is electrical discharge caused by a partial discharge (pd).
All pins on each side of the barrier tied together creating a two-terminal device.
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6.7 Safety-Related Certifications
VDE
Certified according to DIN
VDE V 0884-11:2017-01
CSA
UL
Certified according to IEC
60950-1, IEC 62368-1 and
IEC 60601-1
800 VRMS (DW-16)
reinforced insulation and
400 VRMS (D-8) basic
insulation working voltage
per CSA
60950-1-07+A1+A2, IEC
60950-1 2nd Ed.+A1+A2,
CSA 62368-1-14 and IEC
62368-1:2014, (pollution
degree 2, material group I);
Maximum transient
isolation voltage, 8000 VPK
(DW-16) and 4242 VPK
(D-8);
Maximum repetitive peak
isolation voltage, 2121 VPK
(DW-16) and 637 VPK
(D-8);
2 MOPP (Means of Patient
Maximum surge isolation
voltage, 8000 VPK (DW-16) Protection) per CSA
60601-1:14 and IEC
and 5000 VPK (D-8)
60601-1 Ed. 3.1, 250 VRMS
(DW-16) max working
voltage
Certificate number:
40040142
8
Master contract number:
220991
Recognized under UL
1577 Component
Recognition Program
CQC
Certified according to
GB4943.1-2011
TUV
Certified according to EN
61010-1:2010/A1:2019,
EN 60950-1:2006/
A2:2013 and EN
62368-1:2014
5000 VRMS (DW-16) and
3000 VRMS (D-8)
Reinforced insulation per
EN 61010-1:2010/
A1:2019 up to working
DW-16: Reinforced
voltage of 600 VRMS
Insulation, Altitude ≤ 5000 m, (DW-16) and 300 V
RMS
Tropical Climate,700 VRMS
DW-16: Single
(D-8)
protection, 5000 VRMS; maximum working voltage;
D-8: Single protection, D-8: Basic Insulation, Altitude
5000 VRMS (DW-16) and
≤ 5000 m, Tropical Climate,
3000 VRMS
400 VRMS maximum working 3000 VRMS (D-8)
Reinforced insulation per
voltage
EN 60950-1:2006/
A2:2013 and EN
62368-1:2014 up to
working voltage of 800 V
RMS (DW-16) and 400 V
RMS (D-8)
Certificate numbers:
File number: E181974 CQC15001121716 (DW-16)
CQC15001121656 (D-8)
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6.8 Safety Limiting Values
Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
DW-16 PACKAGE
IS
RθJA = 86.5 °C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C, see Figure 6-1
Safety input, output, or supply
RθJA = 86.5 °C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C, see Figure 6-1
current(1)
RθJA = 86.5 °C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C, see Figure 6-1
PS
Safety input, output, or total
power(1)
TS
Maximum safety
temperature(1)
RθJA = 86.5 °C/W, TJ = 150°C, TA = 25°C, see Figure 6-2
263
401
mA
525
1445
mW
150
°C
D-8 PACKAGE
IS
RθJA = 137.7 °C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C, see Figure 6-3
165
Safety input, output, or supply RθJA = 137.7 °C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C, see Figure 6-3
current(1)
RθJA = 137.7 °C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C, see Figure
6-3
252
PS
Safety input, output, or total
power(1)
TS
Maximum safety
temperature(1)
(1)
RθJA = 137.7 °C/W, TJ = 150°C, TA = 25°C, see Figure 6-4
mA
330
908
mW
150
°C
The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS
and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be
exceeded. These limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the Section 6.4 table is that of a device installed on a high-K test board for leaded
surface-mount packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum allowed junction temperature.
PS = IS × VI, where VI is the maximum input voltage.
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6.9 Electrical Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
VCCO (1) – 0.4
4.8
VOH
High-level output voltage
IOH = –4 mA; see Figure 7-1
VOL
Low-level output voltage
IOL = 4 mA; see Figure 7-1
VIT+(IN)
Rising input threshold voltage
VIT-(IN)
Falling input threshold voltage
0.3 x VCCI
0.4 x VCCI
VI(HYS)
Input threshold voltage hysteresis
0.1 × VCCI
0.2 × VCCI
IIH
High-level input current
VIH = VCCI (1) at INx
IIL
Low-level input current
VIL = 0 V at INx
CMTI
Common-mode transient immunity VI = VCCI or 0 V, VCM = 1200 V; see Figure 7-3
CI
Input Capacitance(2)
(1)
(2)
MAX
V
0.2
0.4
V
0.6 x VCCI
0.7 x VCCI
V
V
V
10
–10
85
VI = VCC/ 2 + 0.4×sin(2πft), f = 1 MHz, VCC = 5 V
UNIT
μA
µA
100
kV/μs
2
pF
VCCI = Input-side VCC; VCCO = Output-side VCC.
Measured from input pin to ground.
6.10 Supply Current Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
SUPPLY CURRENT
MIN
TYP
MAX
ICC1
0.8
1.1
ICC2
1.1
1.7
ICC1
2.9
4.2
ICC2
1.2
1.9
ICC1
1.8
2.7
ICC2
1.3
1.9
2.7
UNIT
ISO7720-Q1
VI = VCCI (ISO7720-Q1), VI = 0 V (ISO7720-Q1 with F suffix)
Supply current - DC signal
VI = 0 V (ISO7720-Q1), VI = VCCI (ISO7720-Q1 with F suffix)
1 Mbps
Supply current - AC signal
All channels switching with square
wave clock input; CL = 15 pF
10 Mbps
100 Mbps
ICC1
1.9
ICC2
2.2
3
ICC1
2.5
3.2
ICC2
11.6
14
mA
ISO7721-Q1
Supply current - DC signal
Supply current - AC signal
10
VI = VCCI (ISO7721-Q1),
VI = 0 V (ISO7721-Q1 with F suffix)
ICC1, ICC2
1
1.6
VI = 0 V (ISO7721-Q1),
VI = VCCI (ISO7721-Q1 with F suffix)
ICC1, ICC2
2.2
3.2
1 Mbps
ICC1, ICC2
1.7
2.4
10 Mbps
ICC1, ICC2
2.2
3
100 Mbps
ICC1, ICC2
7.3
9
All channels switching with square
wave clock input; CL = 15 pF
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6.11 Electrical Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
IOH = –2 mA; see Figure 7-1
VOL
Low-level output voltage
IOL = 2 mA; see Figure 7-1
VIT+(IN)
Rising input voltage threshold
MIN
TYP
VCCO (1) – 0.3
3.2
MAX
UNIT
V
0.1
0.3
V
0.6 x VCCI
0.7 x VCCI
V
VIT-(IN)
Falling input voltage threshold
0.3 x VCCI
0.4 x VCCI
V
VI(HYS)
Input threshold voltage hysteresis
0.1 × VCCI
0.2 × VCCI
V
IIH
High-level input current
VIH = VCCI (1) at INx
IIL
Low-level input current
VIL = 0 V at INx
CMTI
Common-mode transient immunity VI = VCCI or 0 V, VCM = 1200 V; see Figure 7-3
(1)
10
–10
μA
µA
85
100
kV/μs
MIN
TYP
MAX
ICC1
0.8
1.1
ICC2
1.1
1.7
ICC1
2.9
4.2
ICC2
1.2
1.9
ICC1
1.8
2.7
ICC2
1.2
1.9
ICC1
1.9
2.7
ICC2
1.9
2.6
ICC1
2.2
3.1
ICC2
8.6
11
VCCI = Input-side VCC; VCCO = Output-side VCC.
6.12 Supply Current Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
SUPPLY
CURRENT
TEST CONDITIONS
UNIT
ISO7720-Q1
VI = VCCI (ISO7720-Q1), VI = 0 V (ISO7720-Q1 with F suffix)
Supply current - DC signal
VI = 0 V (ISO7720-Q1), VI = VCCI (ISO7720-Q1 with F suffix)
1 Mbps
Supply current - AC signal
All channels switching with square wave
clock input; CL = 15 pF
10 Mbps
100 Mbps
mA
ISO7721-Q1
Supply current - DC signal
Supply current - AC signal
VI = VCCI (ISO7721-Q1), VI = 0 V (ISO7721-Q1 with F suffix)
ICC1, ICC2
1
1.6
VI = 0 V (ISO7721-Q1), VI = VCCI (ISO7721-Q1 with F suffix)
ICC1, ICC2
2.2
3.2
1 Mbps
ICC1, ICC2
1.6
2.4
10 Mbps
ICC1, ICC2
2
2.8
100 Mbps
ICC1, ICC2
5.6
7
All channels switching with square wave
clock input; CL = 15 pF
mA
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6.13 Electrical Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
VCCO (1) – 0.2
2.45
VOH
High-level output voltage
IOH = –1 mA; see Figure 7-1
VOL
Low-level output voltage
IOL = 1 mA; see Figure 7-1
VIT+(IN)
Rising input voltage threshold
VIT-(IN)
Falling input voltage threshold
0.3 x VCCI
0.4 x VCCI
VI(HYS)
Input threshold voltage hysteresis
0.1 × VCCI
0.2 × VCCI
IIH
High-level input current
VIH = VCCI (1) at INx
IIL
Low-level input current
VIL = 0 V at INx
CMTI
Common-mode transient immunity VI = VCCI or 0 V, VCM = 1200 V; see Figure 7-3
(1)
MAX
UNIT
V
0.05
0.2
V
0.6 x VCCI
0.7 x VCCI
V
V
V
10
–10
μA
μA
85
100
kV/μs
MIN
TYP
MAX
VCCI = Input-side VCC; VCCO = Output-side VCC.
6.14 Supply Current Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
SUPPLY CURRENT
UNIT
ISO7720-Q1
VI = VCCI (ISO7720-Q1), VI = 0 V (ISO7720-Q1 with F
suffix)
Supply current - DC signal
VI = 0 V (ISO7720-Q1), VI = VCCI (ISO7720-Q1 with F
suffix)
1 Mbps
Supply current - AC signal
All channels switching with square
wave clock input; CL = 15 pF
10 Mbps
100 Mbps
ICC1
0.8
1.1
ICC2
1.1
1.7
ICC1
2.9
4.2
ICC2
1.2
1.9
ICC1
1.8
2.7
ICC2
1.3
1.9
ICC1
1.9
2.7
ICC2
1.7
2.4
ICC1
2.2
3
ICC2
6.8
9
mA
ISO7721-Q1
Supply current - DC signal
Supply current - AC signal
12
VI = VCCI (ISO7721-Q1), VI = 0 V (ISO7721-Q1 with F
suffix)
ICC1, ICC2
1
1.6
VI = 0 V (ISO7721-Q1), VI = VCCI (ISO7721-Q1 with F
suffix)
ICC1, ICC2
2.2
3.2
1 Mbps
ICC1, ICC2
1.6
2.4
10 Mbps
ICC1, ICC2
1.9
2.7
100 Mbps
ICC1, ICC2
4.6
6
All channels switching with square
wave clock input; CL = 15 pF
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6.15 Switching Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
tPLH, tPHL
Propagation delay time
PWD
Pulse width distortion(1) |tPHL – tPLH|
tsk(o)
Channel-to-channel output skew time(2)
TEST CONDITIONS
See Figure 7-1
MAX
11
16
ns
0.5
4.9
ns
4
ns
4.5
ns
time(3)
Part-to-part skew
tr
Output signal rise time
tf
Output signal fall time
tDO
Default output delay time from input power loss
Measured from the time VCC goes below 1.7
V. See Figure 7-2
tie
Time interval error
216 – 1 PRBS data at 100 Mbps
(3)
TYP
6
Same direction channels
tsk(pp)
(1)
(2)
MIN
See Figure 7-1
UNIT
1.8
3.9
ns
1.9
3.9
ns
0.1
0.3
μs
1
ns
Also known as pulse skew.
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
6.16 Switching Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
tPLH, tPHL
Propagation delay time
PWD
Pulse width distortion(1) |tPHL – tPLH|
tsk(o)
Channel-to-channel output skew time(2)
tsk(pp)
Part-to-part skew time(3)
See Figure 7-1
Output signal rise time
tf
Output signal fall time
tDO
Default output delay time from input power loss
Measured from the time VCC goes
below 1.7 V. See Figure 7-2
tie
Time interval error
216 – 1 PRBS data at 100 Mbps
(3)
TYP
MAX
6
11
16
ns
0.5
5
ns
4.1
ns
4.5
ns
Same direction channels
tr
(1)
(2)
MIN
See Figure 7-1
UNIT
0.7
3
ns
0.7
3
ns
0.1
0.3
μs
1
ns
Also known as pulse skew.
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
6.17 Switching Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
tPLH, tPHL
Propagation delay time
PWD
Pulse width distortion(1) |tPHL – tPLH|
tsk(o)
Channel-to-channel output skew time(2)
tsk(pp)
Part-to-part skew time(3)
tr
Output signal rise time
tf
Output signal fall time
See Figure 7-1
See Figure 7-1
tDO
Default output delay time from input power loss
tie
Time interval error
216 – 1 PRBS data at 100 Mbps
(3)
TYP
MAX
UNIT
7.5
12
18.5
ns
0.5
5.1
ns
4.1
ns
4.6
ns
1
3.5
ns
1
3.5
ns
0.1
0.3
μs
Same direction channels
Measured from the time VCC goes
below 1.7 V. See Figure 7-2
(1)
(2)
MIN
1
ns
Also known as pulse skew.
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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6.18 Insulation Characteristics Curves
1600
VCC1 = VCC2 = 2.75 V
VCC1 = VCC2 = 3.6 V
VCC1 = VCC2 = 5.5 V
500
1400
Safety Limiting Current (mA)
Safety Limiting Current (mA)
600
400
300
200
100
800
600
400
0
0
50
100
150
Ambient Temperature (qC)
0
200
D001
Figure 6-1. Thermal Derating Curve for Limiting
Current per VDE for DW-16 Package
50
100
150
Ambient Temperature (qC)
200
D002
Figure 6-2. Thermal Derating Curve for Limiting
Power per VDE for DW-16 Package
350
1000
VCC1 = VCC2 = 2.75 V
VCC1 = VCC2 = 3.6 V
VCC1 = VCC2 = 5.5 V
900
Safety Limiting Current (mA)
300
Safety Limiting Current (mA)
1000
200
0
250
200
150
100
50
800
700
600
500
400
300
200
100
0
0
0
50
100
150
Ambient Temperature (qC)
200
0
50
D003
Figure 6-3. Thermal Derating Curve for Limiting
Current per VDE for D-8 Package
14
1200
100
150
Ambient Temperature (qC)
200
D004
Figure 6-4. Thermal Derating Curve for Limiting
Power per VDE for D-8 Package
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6.19 Typical Characteristics
14
5
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
4.5
4
10
Supply Current (mA)
Supply Current (mA)
12
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
8
6
4
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
3.5
3
2.5
2
1.5
1
2
0.5
0
0
0
25
50
Data Rate (Mbps)
TA = 25°C
75
0
100
TA = 25°C
CL = 15 pF
Figure 6-5. ISO7720-Q1 Supply Current vs Data
Rate
(With 15-pF Load)
50
Data Rate (Mbps)
75
100
D006
CL = No Load
Figure 6-6. ISO7720-Q1 Supply Current vs Data
Rate
(With No Load)
9
4
ICC1, ICC2 at 2.5 V
ICC1, ICC2 at 3.3 V
ICC1, ICC2 at 5 V
8
ICC1, ICC2 at 2.5 V
ICC1, ICC2 at 3.3 V
ICC1, ICC2 at 5 V
3.5
Supply Current (mA)
7
Supply Current (mA)
25
D005
6
5
4
3
2
3
2.5
2
1.5
1
0.5
1
0
0
0
25
TA = 25°C
50
Data Rate (Mbps)
75
100
0
25
D007
TA = 25°C
CL = 15 pF
Figure 6-7. ISO7721-Q1 Supply Current vs Data
Rate
(With 15-pF Load)
50
Data Rate (Mbps)
75
100
D008
CL = No Load
Figure 6-8. ISO7721-Q1 Supply Current vs Data
Rate
(With No Load)
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0.9
6
Low-Level Output Voltage (V)
High-Level Output Voltage (V)
0.8
5
4
3
2
VCC at 2.5 V
VCC at 3.3 V
VCC at 5 V
1
0
-15
-10
-5
High-Level Output Current (mA)
0.7
0.6
0.5
0.4
0.3
0.2
VCC at 2.5 V
VCC at 3.3 V
VCC at 5 V
0.1
0
0
0
Figure 6-9. High-Level Output Voltage vs High-level
Output Current
D012
Figure 6-10. Low-Level Output Voltage vs LowLevel
Output Current
14
2.1
2.05
Propagation Delay Time (ns)
Power Supply UVLO Threshold (V)
15
TA = 25°C
TA = 25°C
2
1.95
1.9
1.85
1.8
1.75
1.7
VCC1+
VCC1-
1.65
1.6
-55
-25
5
35
65
Free-Air Temperature (qC)
VCC2+
VCC295
125
13
12
11
10
tPLH at 2.5 V
tPHL at 2.5 V
tPLH at 3.3 V
9
8
-55
-25
D011
Figure 6-11. Power Supply Undervoltage Threshold
vs
Free-Air Temperature
16
5
10
Low-Level Output Current (mA)
D011
5
35
65
Free Air Temperature (qC)
tPHL at 3.3 V
tPLH at 5 V
tPHL at 5 V
95
125
D012
Figure 6-12. Propagation Delay Time vs Free-Air
Temperature
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7 Parameter Measurement Information
Isolation Barrier
IN
Input Generator
(See Note A)
VI
VCCI
VI
OUT
50%
50%
0V
tPLH
CL
See Note B
VO
50
tPHL
VOH
90%
50%
VO
50%
10%
VOL
tf
tr
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO =
50 Ω. At the input, 50 Ω resistor is required to terminate Input Generator signal. It is not needed in actual application.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 7-1. Switching Characteristics Test Circuit and Voltage Waveforms
VI
See Note B
VCC
VCC
Isolation Barrier
IN = 0 V (Devices without suffix F)
IN = VCC (Devices with suffix F)
VI
IN
1.7 V
0V
OUT
VO
tDO
CL
See Note A
default high
VOH
50%
VO
VOL
default low
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
B. Power Supply Ramp Rate = 10 mV/ns
Figure 7-2. Default Output Delay Time Test Circuit and Voltage Waveforms
VCCI
VCCO
C = 0.1 µF ±1%
Pass-fail criteria:
The output must
remain stable.
Isolation Barrier
S1
C = 0.1 µF ±1%
IN
OUT
+
VOH or VOL
CL
See Note A
GNDI
+
VCM ±
±
GNDO
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 7-3. Common-Mode Transient Immunity Test Circuit
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8 Detailed Description
8.1 Overview
The ISO772x-Q1 family of devices has an ON-OFF keying (OOK) modulation scheme to transmit the digital data
across a silicon dioxide based isolation barrier. The transmitter sends a high frequency carrier across the barrier
to represent one digital state and sends no signal to represent the other digital state. The receiver demodulates
the signal after advanced signal conditioning and produces the output through a buffer stage. These devices
also incorporate advanced circuit techniques to maximize the CMTI performance and minimize the radiated
emissions due the high frequency carrier and IO buffer switching. The conceptual block diagram of a digital
capacitive isolator, Figure 8-1, shows a functional block diagram of a typical channel.
8.2 Functional Block Diagram
Receiver
Transmitter
TX IN
OOK
Modulation
TX Signal
Conditioning
Oscillator
SiO2 based
Capacitive
Isolation
Barrier
RX Signal
Conditioning
Envelope
Detection
RX OUT
Emissions
Reduction
Techniques
Figure 8-1. Conceptual Block Diagram of a Digital Capacitive Isolator
Figure 8-2 shows a conceptual detail of how the OOK scheme works.
TX IN
Carrier signal through
isolation barrier
RX OUT
Figure 8-2. On-Off Keying (OOK) Based Modulation Scheme
18
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8.3 Feature Description
The ISO772x-Q1 family of devices is available in two channel configurations and default output state options to
enable a variety of application uses. Table 8-1 lists the device features of the ISO772x-Q1 devices.
Table 8-1. Device Features
PART NUMBER
MAXIMUM DATA
RATE
CHANNEL DIRECTION
DEFAULT OUTPUT
STATE
ISO7720-Q1
100 Mbps
2 Forward, 0 Reverse
High
ISO7720-Q1 with F
suffix
100 Mbps
2 Forward, 0 Reverse
Low
ISO7721-Q1
100 Mbps
1 Forward, 1 Reverse
High
ISO7721-Q1 with F
suffix
100 Mbps
1 Forward, 1 Reverse
Low
(1)
PACKAGE
RATED ISOLATION(1)
DW-16
5000 VRMS / 8000 VPK
D-8
3000 VRMS / 4242 VPK
DW-16
5000 VRMS / 8000 VPK
D-8
3000 VRMS / 4242 VPK
DW-16
5000 VRMS / 8000 VPK
D-8
3000 VRMS / 4242 VPK
DW-16
5000 VRMS / 8000 VPK
D-8
3000 VRMS / 4242 VPK
See the Section 6.7 section for detailed isolation ratings.
8.3.1 Electromagnetic Compatibility (EMC) Considerations
Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge
(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances
are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level
performance and reliability depends, to a large extent, on the application board design and layout, the ISO772xQ1 family of devices incorporates many chip-level design improvements for overall system robustness. Some of
these improvements include:
• Robust ESD protection cells for input and output signal pins and inter-chip bond pads.
• Low-resistance connectivity of ESD cells to supply and ground pins.
• Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.
• Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance
path.
• PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic
SCRs.
• Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.
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8.4 Device Functional Modes
Table 8-2 lists the functional modes for the ISO772x-Q1 devices.
Table 8-2. Function Table
VCCI
(1)
VCCO
PU
(1)
(2)
(3)
INPUT
(INx)(3)
OUTPUT
(OUTx)
H
H
L
L
Open
Default
Default mode: When INx is open, the corresponding channel output goes to
the default logic state. The default is High for ISO772x-Q1 and Low for
ISO772x-Q1 with F suffix.
Default mode: When VCCI is unpowered, a channel output assumes the logic
state based on the selected default option. The default is High for ISO772x-Q1
and Low for ISO772x-Q1 with F suffix.
When VCCI transitions from unpowered to powered-up, a channel output
assumes the logic state of the input.
When VCCI transitions from powered-up to unpowered, channel output
assumes the selected default state.
COMMENTS
Normal Operation:
A channel output assumes the logic state of the input.
PU
PD
PU
X
Default
X
PD
X
Undetermined
When VCCO is unpowered, a channel output is undetermined(2).
When VCCO transitions from unpowered to powered-up, a channel output
assumes the logic state of the input
VCCI = Input-side VCC; VCCO = Output-side VCC; PU = Powered up (VCC ≥ 2.25 V); PD = Powered down (VCC ≤ 1.7 V); X = Irrelevant; H
= High level; L = Low level
The outputs are in undetermined state when 1.7 V < VCCI, VCCO < 2.25 V.
A strongly driven input signal can weakly power the floating VCC via an internal protection diode and cause undetermined output.
8.4.1 Device I/O Schematics
Input (Devices with F suffix)
Input (Devices without F suffix)
VCCI
VCCI
VCCI
VCCI
VCCI
VCCI
VCCI
1.5 M
985
985
INx
INx
1.5 M
Output
VCCO
~20
OUTx
Copyright © 2016, Texas Instruments Incorporated
Figure 8-3. Device I/O Schematics
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The ISO772x-Q1 devices are high-performance, dual-channel digital isolators. The devices use single-ended
CMOS-logic switching technology. The supply voltage range is from 2.25 V to 5.5 V for both supplies, V CC1 and
V CC2. When designing with digital isolators, keep in mind that because of the single-ended design structure,
digital isolators do not conform to any specific interface standard and are only intended for isolating single-ended
CMOS or TTL digital signal lines. The isolator is typically placed between the data controller (that is, μC or
UART), and a data converter or a line transceiver, regardless of the interface type or standard.
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9.2 Typical Application
The ISO7721-Q1 device can be used with Texas Instruments' Piccolo™ microcontroller, CAN transceiver,
transformer driver, and voltage regulator to create an isolated CAN interface.
VS
3.3 V
0.1 F
2
VCC D2 3
1:1.33
MBR0520L
1
SN6501-Q1
GND D1
10 F
0.1 F
IN
OUT
5
10 F
TPS76333-Q1
3
1
EN
GND
3.3VISO
2
10 F
MBR0520L
4, 5
ISO Barrier
0.1 F
0.1 F
0.1 F
1
29,57
VCC1
VDDIO
CANRXA 26
TMS320F28035PAGQ
CANTXA
25
VSS
6,28
2
8
4
3
VCC2
VCC
INA 7
4
6
1
OUTA
ISO7721-Q1
3
OUTB
INB
GND1
0.1 F
GND2
5
RS 8
R
D
CANH
SN65HVD231Q
CANL
10
(optional)
10
(optional)
7
6
Vref 5
GND
SM712
2
4.7 nF /
2 kV
Copyright © 2017, Texas Instruments Incorporated
Figure 9-1. Isolated 4-mA to 20-mA Current Loop
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9.2.1 Design Requirements
To design with these devices, use the parameters listed in Table 9-1.
Table 9-1. Design Parameters
PARAMETER
VALUE
Supply voltage, VCC1 and VCC2
2.25 V to 5.5 V
Decoupling capacitor between VCC1 and GND1
0.1 µF
Decoupling capacitor from VCC2 and GND2
0.1 µF
9.2.2 Detailed Design Procedure
Unlike optocouplers, which require external components to improve performance, provide bias, or limit current,
the ISO772x-Q1 devices only require two external bypass capacitors to operate.
VCC1
VCC2
GND1 1
16 GND2
0.1 µF
0.1 µF
GND2
GND1
OUTA
NC
2
15
VCC1
3
14 VCC2
OUTA 4
INB
GND1
ISOLATION
GND1
13
NC
5
NC
6
11
NC
GND1 7
10
NC
8
INA
INA
INB
NC
GND2
12 OUTB
OUTB
9 GND2
GND2
Figure 9-2. Typical ISO7721-Q1 Circuit Hook-up
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9.2.3 Application Curve
1 V/ div
1 V/ div
The following typical eye diagrams of the ISO772x-Q1 family of devices indicate low jitter and wide open eye at
the maximum data rate of 100 Mbps.
Time = 3.5 ns / div
Time = 3.5 ns / div
Figure 9-3. ISO7720-Q1 Eye Diagram at 100 Mbps
PRBS,
5-V Supplies and 25°C
Figure 9-4. ISO7721-Q1 Eye Diagram at 100 Mbps
PRBS,
5-V Supplies and 25°C
9.2.3.1 Insulation Lifetime
Insulation lifetime projection data is collected by using industry-standard Time Dependent Dielectric Breakdown
(TDDB) test method. In this test, all pins on each side of the barrier are tied together creating a two-terminal
device and high voltage applied between the two sides; See Figure 9-5 for TDDB test setup. The insulation
breakdown data is collected at various high voltages switching at 60 Hz over temperature. For reinforced
insulation, VDE standard requires the use of TDDB projection line with failure rate of less than 1 part per million
(ppm). Even though the expected minimum insulation lifetime is 20 years at the specified working isolation
voltage, VDE reinforced certification requires additional safety margin of 20% for working voltage and 87.5% for
lifetime which translates into minimum required insulation lifetime of 37.5 years at a working voltage that's 20%
higher than the specified value.
Figure 9-6 shows the intrinsic capability of the isolation barrier to withstand high voltage stress over its lifetime.
Based on the TDDB data, the intrinsic capability of the insulation is 1500 VRMS with a lifetime of 135 years. Other
factors, such as package size, pollution degree, material group, etc. can further limit the working voltage of the
component. The working voltage of DW-16 package is specified up to 1500 V RMS and D-8 package up to 450 V
RMS. At the lower working voltages, the corresponding insulation lifetime is much longer than 135 years.
A
Vcc 1
Vcc 2
Time Counter
> 1 mA
DUT
GND 1
GND 2
VS
Oven at 150 °C
Figure 9-5. Test Setup for Insulation Lifetime Measurement
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Figure 9-6. Insulation Lifetime Projection Data
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10 Power Supply Recommendations
To help ensure reliable operation at data rates and supply voltages, a 0.1-μF bypass capacitor is recommended
at the input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins
as possible. If only a single primary-side power supply is available in an application, isolated power can be
generated for the secondary-side with the help of a transformer driver such as Texas Instruments' SN6501-Q1 .
For such applications, detailed power supply design and transformer selection recommendations are available in
SN6501-Q1 Transformer Driver for Isolated Power Supplies .
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11 Layout
11.1 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 11-1). Layer stacking
should be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and lowfrequency signal layer.
•
•
•
•
Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/in2.
Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to
the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also
the power and ground plane of each power system can be placed closer together, thus increasing the highfrequency bypass capacitance significantly.
For detailed layout recommendations, refer to the Digital Isolator Design Guide.
11.1.1 PCB Material
For digital circuit boards operating at less than 150 Mbps, (or rise and fall times greater than 1 ns), and trace
lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper
alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater strength
and stiffness, and the self-extinguishing flammability-characteristics.
11.2 Layout Example
High-speed traces
10 mils
Ground plane
40 mils
Keep this
space free
from planes,
traces, pads,
and vias
FR-4
0r ~ 4.5
Power plane
10 mils
Low-speed traces
Figure 11-1. Layout Example
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
For development support, refer to:
•
•
•
•
Isolated CAN Flexible Data (FD) Rate Repeater Reference Design
Isolated 16-Channel AC Analog Input Module Reference Design Using Dual Simultaneously Sampled ADCs
Polyphase Shunt Metrology with Isolated AFE Reference Design
Reference Design for Power-Isolated Ultra-Compact Analog Output Module
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, Digital Isolator Design Guide
• Texas Instruments, How to use isolation to improve ESD, EFT and Surge immunity in industrial systems
application report
• Texas Instruments, Isolation Glossary
• Texas Instruments, SN6501-Q1 Transformer Driver for Isolated Power Supplies data sheet
• Texas Instruments, SN65HVD231Q 3.3-V CAN Transceivers data sheet
• Texas Instruments, TPS763xx-Q1 Low-Power, 150-mA, Low-Dropout Linear Regulators data sheet
• Texas Instruments, TMS320F2803x Piccolo™ Microcontrollers data sheet
12.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 12-1. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
ISO7720-Q1
Click here
Click here
Click here
Click here
Click here
ISO7721-Q1
Click here
Click here
Click here
Click here
Click here
12.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.5 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.6 Trademarks
Piccolo™ is a trademark of Texas Instruments.
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
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12.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.8 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OUTLINE
D0008B
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4X (0 -15 )
4
5
B
8X .012-.020
[0.31-0.51]
.150-.157
[3.81-3.98]
NOTE 4
.010 [0.25]
C A B
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
.041
[1.04]
TYPICAL
4221445/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15], per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008B
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
8X (.055)
[1.4]
SEE
DETAILS
SYMM
SEE
DETAILS
SYMM
1
1
8
8X (.024)
[0.6]
8
SYMM
5
4
6X (.050 )
[1.27]
8X (.024)
[0.6]
(R.002 ) TYP
[0.05]
SYMM
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
(R.002 )
[0.05]
TYP
(.217)
[5.5]
HV / ISOLATION OPTION
.162 [4.1] CLEARANCE / CREEPAGE
IPC-7351 NOMINAL
.150 [3.85] CLEARANCE / CREEPAGE
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:6X
SOLDER MASK
OPENING
METAL
EXPOSDE
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221445/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
D0008B
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
8X (.055)
[1.4]
SYMM
SYMM
1
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
8
SYMM
5
4
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
6X (.050 )
[1.27]
5
4
(R.002 )
[0.05]
TYP
(.217)
[5.5]
(.213)
[5.4]
HV / ISOLATION OPTION
.162 [4.1] CLEARANCE / CREEPAGE
IPC-7351 NOMINAL
.150 [3.85] CLEARANCE / CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.127 MM] THICK STENCIL
SCALE:6X
4221445/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
ISO7720FQDQ1
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7720FQ
ISO7720FQDRQ1
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7720FQ
ISO7720FQDWQ1
ACTIVE
SOIC
DW
16
40
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7720FQ
ISO7720FQDWRQ1
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7720FQ
ISO7720QDQ1
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7720Q
ISO7720QDRQ1
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7720Q
ISO7720QDWQ1
ACTIVE
SOIC
DW
16
40
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7720Q
ISO7720QDWRQ1
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7720Q
ISO7721FQDQ1
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7721FQ
ISO7721FQDRQ1
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7721FQ
ISO7721FQDWQ1
ACTIVE
SOIC
DW
16
40
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7721FQ
ISO7721FQDWRQ1
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7721FQ
ISO7721QDQ1
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7721Q
ISO7721QDRQ1
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7721Q
ISO7721QDWQ1
ACTIVE
SOIC
DW
16
40
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7721Q
ISO7721QDWRQ1
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7721Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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