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ISO7720, ISO7721
ZHCSFQ6C – NOVEMBER 2016 – REVISED JULY 2018
EMC 性能优异的 ISO772x 高速双通道增强型数字隔离器
1 特性
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1
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信号传输速率：高达 100Mbps
宽电源电压范围：2.25V 至 5.5V
2.25V 至 5.5V 电平转换
默认输出高电平 和低电平 选项
宽温度范围：–55°C 至 +125°C
低功耗，1Mbps 时每通道的电流典型值为 1.7mA
低传播延迟：典型值为 11ns
（由 5V 电源供电）
高 CMTI：±100kV/μs（典型值）
优异的电磁兼容性 (EMC)
– 系统级 ESD、EFT 和浪涌抗扰性
– 低辐射
隔离栅寿命：> 40 年
宽体 SOIC（DW-16 和 DWV-8）和窄体 SOIC (D8) 封装选项
安全相关认证：
– 符合 DIN V VDE V 0884-11:2017-01 标准的
VDE 增强型绝缘
– 符合 UL 1577 的 5000VRMS（DW 和 DWV）和
3000VRMS (D) 隔离额定值
– 符合 IEC 60950-1、IEC 62368-1、IEC 610101 和 IEC 60601-1 终端设备标准的 CSA 认证
– 符合 GB4943.1-2011 的 CQC 认证
– 符合 EN 60950-1 和 EN 61010-1 的 TUV 认证
– DWV 封装认证已提上日程，所有其他认证均已
完成
2 应用
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•
•
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•
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工业自动化
混合动力电动汽车
电机控制
电源
光伏逆变器
医疗设备
3 说明
ISO772x 器件是一款高性能双通道数字隔离器，可提
供符合 UL 1577 标准的 5000VRMS（DW 和 DWV 封
装）和 3000VRMS（D 封装）隔离额定值。这些器件还
通过了 VDE、TUV、CSA 和 CQC 认证。
在隔离互补金属氧化物半导体 (CMOS) 或者低电压互
补金属氧化物半导体 (LVCMOS) 数字 I/O 的同
时，ISO772x 器件还可提供高电磁抗扰度和低辐射，
同时具备低功耗特性。每个隔离通道都有一个由二氧化
硅 (SiO2) 绝缘隔栅分开的逻辑输入和输出缓冲器。
ISO7720 器件具有两条同向通道，而 ISO7721 器件具
有两条反向通道。如果输入功率或信号出现损失，不带
后缀 F 的器件默认输出高电平，带后缀 F 的器件默认
输出低电平。更多详细信息，请参见 器件功能模式 部
分。
与隔离式电源一起使用时，这些器件有助于防止数据总
线或者其他电路上的噪声电流进入本地接地并且干扰或
损坏敏感电路。凭借创新型芯片设计和布线技
术，ISO772x 器件的电磁兼容性得到了显著增强，可
缓解系统级 ESD、EFT 和浪涌问题并符合辐射标准。
ISO772x 系列器件可提供 16 引脚 SOIC 宽体 (DW)、
8 引脚 SOIC 宽体 (DWV) 和 8 引脚 SOIC 窄体 (D) 封
装。
器件信息(1)
器件型号
封装
ISO7720，ISO7721
，ISO7721F，ISO7721F
封装尺寸（标称值）
D (8)
4.90 mm × 3.91 mm
DWV (8)
5.85mm × 7.50mm
DW (16)
10.30mm × 7.50mm
(1) 要了解所有可用封装，请参见数据表末尾的可订购产品附录。
简化原理图
VCCI
Isolation
Capacitor
VCCO
INx
OUTx
GNDI
GNDO
Copyright © 2016, Texas Instruments Incorporated
VCCI 和 GNDI 分别是输入通道的电源和接地
连接引脚。
VCCO 和 GNDO 分别是输出通道的电源和接
地连接引脚。
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。 TI 不保证翻译的准确性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLLSEP3
ISO7720, ISO7721
ZHCSFQ6C – NOVEMBER 2016 – REVISED JULY 2018
www.ti.com.cn
目录
1
2
3
4
5
6
特性 ..........................................................................
应用 ..........................................................................
说明 ..........................................................................
修订历史记录 ...........................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.14
6.15
6.16
6.17
6.18
1
1
1
2
4
5
Absolute Maximum Ratings ..................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 6
Power Ratings........................................................... 6
Insulation Specifications............................................ 7
Safety-Related Certifications..................................... 8
Safety Limiting Values .............................................. 9
Electrical Characteristics—5-V Supply ................... 10
Supply Current Characteristics—5-V Supply ........ 10
Electrical Characteristics—3.3-V Supply .............. 11
Supply Current Characteristics—3.3-V Supply ..... 11
Electrical Characteristics—2.5-V Supply .............. 12
Supply Current Characteristics—2.5-V Supply ..... 12
Switching Characteristics—5-V Supply................. 13
Switching Characteristics—3.3-V Supply.............. 13
Switching Characteristics—2.5-V Supply.............. 13
Insulation Characteristics Curves ......................... 14
6.19 Typical Characteristics .......................................... 15
7
8
Parameter Measurement Information ................ 17
Detailed Description ............................................ 18
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
18
18
19
20
Application and Implementation ........................ 21
9.1 Application Information............................................ 21
9.2 Typical Application .................................................. 21
10 Power Supply Recommendations ..................... 23
11 Layout................................................................... 23
11.1 Layout Guidelines ................................................. 23
11.2 Layout Example .................................................... 23
12 器件和文档支持 ..................................................... 24
12.1
12.2
12.3
12.4
12.5
12.6
12.7
12.8
器件支持................................................................
文档支持................................................................
相关链接................................................................
接收文档更新通知 .................................................
社区资源................................................................
商标 .......................................................................
静电放电警告.........................................................
术语表 ...................................................................
24
24
24
24
24
24
24
25
13 机械、封装和可订购信息 ....................................... 26
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision B (March 2017) to Revision C
Page
•
已添加 在数据表中添加了 8 引脚 SOIC 封装 (DWV).............................................................................................................. 1
•
通篇更新了 VDE 和 CSA 认证 说明........................................................................................................................................ 1
•
已更改 在特性 部分中，更改了所有需要为 DW 和 D 封装完成的认证 ................................................................................... 1
•
Changed the climatic category for the D package from 5/125/21 to 55/125/21 .................................................................... 7
•
Changed the maximum working voltages for DW-16 and D-8 from 400 to 700 VRMS and 250 to 400 VRMS
(respectively) in the Safety-Related Certifications table......................................................................................................... 8
•
Switched the line colors for VCC at 2.5 V and VCC at 3.3 V in the Low-Level Output Voltage vs Low-Level Output
Current graph........................................................................................................................................................................ 15
•
Deleted EN from the Common-Mode Transient Immunity Test Circuit figure ...................................................................... 17
•
已添加 器件支持 部分 ........................................................................................................................................................... 24
Changes from Revision A (December 2016) to Revision B
Page
•
Added D-8 values for TUV in the Safety-Related Certifications table ................................................................................... 8
•
Changed the minimum CMTI value from 40 kV/μs to 85 kV/μs in all Electrical Characteristics tables................................ 10
•
已添加 接收文档更新通知 部分 ............................................................................................................................................. 24
•
已更改 静电放电注意事项 声明 ............................................................................................................................................ 24
2
版权 © 2016–2018, Texas Instruments Incorporated
ISO7720, ISO7721
www.ti.com.cn
Changes from Original (November 2016) to Revision A
ZHCSFQ6C – NOVEMBER 2016 – REVISED JULY 2018
Page
•
将特性 从“IEC 60950-1、IEC 60601-1 和 IEC 61010-1 终端设备标准”更改为“IEC 60950-1 和 IEC 60601-1 终端设备
标准” ....................................................................................................................................................................................... 1
•
Added Climatic category to the Insulation Specifications....................................................................................................... 7
•
Changed the CSA column of Regulatory Information ........................................................................................................... 8
•
Changed DW package) To: (DW-16) in the TUV column of Regulatory Information ............................................................ 8
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Changed tie TYP value From: 1.5 To 1 in Switching Characteristics—5-V Supply .............................................................. 13
•
Changed tie TYP value From: 1.5 To 1 in Switching Characteristics—3.3-V Supply ........................................................... 13
•
Changed tie TYP value From: 1.5 To 1 in Switching Characteristics—2.5-V Supply ........................................................... 13
Copyright © 2016–2018, Texas Instruments Incorporated
3
ISO7720, ISO7721
ZHCSFQ6C – NOVEMBER 2016 – REVISED JULY 2018
www.ti.com.cn
5 Pin Configuration and Functions
ISO7720 DW Package
16-Pin SOIC
Top View
16 GND2
2
15
VCC1
3
INA
4
INB
5
NC
ISOLATION
NC
GND1 1
NC
16 GND2
NC
2
15
14 VCC2
VCC1
3
14 VCC2
13 OUTA
OUTA 4
ISOLATION
GND1 1
ISO7721 DW Package
16-Pin SOIC
Top View
13
NC
INA
12 OUTB
INB
5
6
11
NC
NC
6
11
NC
GND1 7
10
NC
GND1 7
10
NC
8
9 GND2
NC
8
9 GND2
VCC1
1
INA
2
INB
3
ISOLATION
ISO7720 D and DWV Package
8-Pin SOIC
Top View
ISO7721 D and DWV Package
8-Pin SOIC
Top View
8 VCC2
VCC1
7 OUTA
OUTA 2
6 OUTB
GND1 4
INB
5 GND2
1
8 VCC2
ISOLATION
NC
12 OUTB
3
GND1 4
7
INA
6 OUTB
5 GND2
Pin Functions
PIN
NAME
DW PACKAGE
D, DWV PACKAGE
I/O
DESCRIPTION
ISO7720
ISO7721
ISO7720
ISO7721
1, 7
1, 7
4
4
—
Ground connection for VCC1
9
9
16
16
5
5
—
Ground connection for VCC2
INA
4
13
2
7
I
Input, channel A
INB
5
5
3
3
I
Input, channel B
NC
2, 6, 8, 10, 11,
15
2, 6, 8, 10,
11, 15
—
—
—
Not connected
GND1
GND2
OUTA
13
4
7
2
O
Output, channel A
OUTB
12
12
6
6
O
Output, channel B
VCC1
3
3
1
1
—
Power supply, VCC1
VCC2
14
14
8
8
—
Power supply, VCC2
4
Copyright © 2016–2018, Texas Instruments Incorporated
ISO7720, ISO7721
www.ti.com.cn
ZHCSFQ6C – NOVEMBER 2016 – REVISED JULY 2018
6 Specifications
6.1 Absolute Maximum Ratings
See
(1)
.
Supply voltage (2)
VCC1, VCC2
MIN
MAX
–0.5
6
V
Voltage at INx, OUTx
–0.5
IO
Output current
–15
TJ
Junction temperature
Tstg
Storage temperature
(1)
(2)
(3)
VCC + 0.5
–65
UNIT
V
(3)
V
15
mA
150
°C
150
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak
voltage values.
Maximum voltage must not exceed 6 V.
6.2 ESD Ratings
VALUE
UNIT
(1)
±6000
V
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins (2)
±1500
V
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins
VESD
(1)
(2)
Electrostatic discharge
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
NOM
MAX
5.5
V
2
2.25
V
VCC1, VCC2
Supply voltage
VCC(UVLO+)
UVLO threshold when supply voltage is rising
VCC(UVLO-)
UVLO threshold when supply voltage is falling
1.7
1.8
V
VHYS(UVLO)
Supply voltage UVLO hysteresis
100
200
mV
IOH
IOL
High-level output current
Low-level output current
2.25
UNIT
VCCO (1) = 5 V
–4
VCCO = 3.3 V
–2
VCCO = 2.5 V
–1
mA
VCCO = 5 V
4
VCCO = 3.3 V
2
VCCO = 2.5 V
1
mA
VIH
High-level input voltage
0.7 × VCCI (1)
VCCI
VIL
Low-level input voltage
0
0.3 × VCCI
DR
Signaling rate
0
100
Mbps
TA
Ambient temperature
125
°C
(1)
–55
25
V
V
VCCI = Input-side VCC; VCCO = Output-side VCC.
Copyright © 2016–2018, Texas Instruments Incorporated
5
ISO7720, ISO7721
ZHCSFQ6C – NOVEMBER 2016 – REVISED JULY 2018
www.ti.com.cn
6.4 Thermal Information
ISO772x
THERMAL METRIC (1)
DW (SOIC)
DWV (SOIC)
D (SOIC)
16 PINS
16 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
86.5
84.3
137.7
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
49.6
36.3
54.9
°C/W
RθJB
Junction-to-board thermal resistance
49.7
47.0
71.7
°C/W
ψJT
Junction-to-top characterization parameter
32.3
7.4
7.1
°C/W
ψJB
Junction-to-board characterization parameter
49.2
45.1
70.7
°C/W
RθJC(botto
Junction-to-case(bottom) thermal resistance
N/A
N/A
N/A
°C/W
m)
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Power Ratings
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ISO7720
PD
Maximum power dissipation
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
input a 50 MHz 50% duty cycle square wave
100
mW
PD1
Maximum power dissipation by side-1
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
input a 50 MHz 50% duty cycle square wave
20
mW
PD2
Maximum power dissipation by side-2
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
input a 50 MHz 50% duty cycle square wave
80
mW
PD
Maximum power dissipation
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
input a 50 MHz 50% duty cycle square wave
100
mW
PD1
Maximum power dissipation by side-1
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
input a 50 MHz 50% duty cycle square wave
50
mW
PD2
Maximum power dissipation by side-2
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
input a 50 MHz 50% duty cycle square wave
50
mW
ISO7721
6
Copyright © 2016–2018, Texas Instruments Incorporated
ISO7720, ISO7721
www.ti.com.cn
ZHCSFQ6C – NOVEMBER 2016 – REVISED JULY 2018
6.6 Insulation Specifications
PARAMETER
CLR
External clearance
TEST CONDITIONS
DWV
D
UNIT
(1)
Shortest terminal-to-terminal distance through air
8
8.5
4
mm
(1)
Shortest terminal-to-terminal distance across the
package surface
8
8.5
4
mm
21
21
21
μm
>600
>600
>600
V
CPG
External creepage
DTI
Distance through the insulation
Minimum internal gap (internal clearance)
Comparative tracking index
DIN EN 60112 (VDE 0303-11); IEC 60112; UL
746A
Material group
According to IEC 60664-1
CTI
VALUE
DW
Overvoltage category per IEC
60664-1
I
I
I
Rated mains voltage ≤ 150 VRMS
I–IV
I–IV
I–IV
Rated mains voltage ≤ 300 VRMS
I–IV
I–IV
I–III
Rated mains voltage ≤ 600 VRMS
I–IV
I–IV
n/a
Rated mains voltage ≤ 1000 VRMS
I–III
I–III
n/a
AC voltage (bipolar)
1414
1414
637
VPK
AC voltage; Time dependent dielectric breakdown
(TDDB) test
1000
1000
450
VRMS
DIN V VDE V 0884-11:2017-01 (2)
VIORM
Maximum repetitive peak
isolation voltage
VIOWM
Maximum working isolation
voltage
DC voltage
1414
1414
637
VDC
VIOTM
Maximum transient isolation
voltage
VTEST = VIOTM, t = 60 s (qualification);
t = 1 s (100% production)
8000
7071
4242
VPK
VIOSM
Maximum surge isolation
voltage (3)
Test method per IEC 60065, 1.2/50 µs waveform,
VTEST = 1.6 × VIOSM (qualification)
8000
8000
5000
VPK
Method a, After Input/Output safety test subgroup
2/3, Vini = VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM,
tm = 10 s
≤5
≤5
≤5
Method a, After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s; Vpd(m) = 1.6 × VIORM, tm =
10 s
≤5
≤5
≤5
Method b1; At routine test (100% production) and
preconditioning (type test), Vini = VIOTM, tini = 1 s;
Vpd(m) = 1.875 × VIORM, tm = 1 s
≤5
≤5
≤5
~0.5
~0.5
~0.5
Apparent charge (4)
qpd
Barrier capacitance, input to
output (5)
CIO
Isolation resistance (5)
RIO
VIO = 0.4 × sin (2πft), f = 1 MHz
12
12
pC
VIO = 500 V, TA = 25°C
>10
>10
VIO = 500 V, 100°C ≤ TA ≤ 125°C
>1011
>1011
>1011
9
9
9
VIO = 500 V at TS = 150°C
pF
12
>10
>10
>10
Pollution degree
2
2
2
Climatic category
55/125/21
55/125/21
55/125/21
5000
5000
3000
Ω
>10
UL 1577
VISO
(1)
(2)
(3)
(4)
(5)
Withstanding isolation voltage
VTEST = VISO, t = 60 s(qualification);
VTEST = 1.2 × VISO, t = 1 s (100% production)
VRMS
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care
should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on
the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.
This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by
means of suitable protective circuits.
Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
Apparent charge is electrical discharge caused by a partial discharge (pd).
All pins on each side of the barrier tied together creating a two-terminal device.
Copyright © 2016–2018, Texas Instruments Incorporated
7
ISO7720, ISO7721
ZHCSFQ6C – NOVEMBER 2016 – REVISED JULY 2018
www.ti.com.cn
6.7 Safety-Related Certifications
DWV package certifications are planned; all other certifications are complete.
VDE
Certified according to DIN V
VDE V 0884-11:2017-01
Maximum transient isolation
voltage, 8000 VPK (DW-16,
Reinforced) and 4242 VPK
(D-8);
Maximum repetitive peak
isolation voltage, 1414 VPK
(DW-16, Reinforced) and
637 VPK (D-8);
Maximum surge isolation
voltage, 8000 VPK (DW-16,
Reinforced) and 5000 VPK
(D-8)
Certificate number:
40040142
8
CSA
Certified according to
IEC 60950-1, IEC
62368-1, IEC 61010-1,
and IEC 60601-1
Reinforced insulation
per CSA 60950-107+A1+A2 and IEC
60950-1 2nd Ed.,
800 VRMS (DW-16) and
400 VRMS (D-8) max
working voltage
(pollution degree 2,
material group I);
UL
CQC
Certified according to UL
Certified according to
1577 Component
GB4943.1-2011
Recognition Program
DW-16: Single
protection, 5000 VRMS;
D-8: Single protection,
3000 VRMS
DW-16: Reinforced
Insulation, Altitude ≤ 5000
m, Tropical Climate, 700
VRMS maximum working
voltage;
D-8: Basic Insulation,
Altitude ≤ 5000 m, Tropical
Climate, 400 VRMS maximum
working voltage
Master contract number:
File number: E181974
220991
Certificate number:
CQC15001121716 (DW-16),
CQC15001121656 (D-8)
2 MOPP (Means of
Patient Protection) per
CSA 60601-1:14 and
IEC 60601-1 Ed. 3.1,
250 VRMS (DW-16) max
working voltage
TUV
Certified according to
EN 61010-1:2010 (3rd
Ed) and EN 609501:2006/A11:2009/A1:201
0/A12:2011/A2:2013
5000 VRMS (DW-16) and
3000 VRMS (D-8)
Reinforced insulation
per EN 61010-1:2010
(3rd Ed) up to working
voltage of 600 VRMS
(DW-16) and 300 VRMS
(D-8)
5000 VRMS (DW-16) and
3000 VRMS (D-8)
Reinforced insulation
per EN 609501:2006/A11:2009/A1:201
0/A12:2011/A2:2013 up
to working voltage of
800 VRMS (DW-16) and
400 VRMS (D-8)
Client ID number: 77311
Copyright © 2016–2018, Texas Instruments Incorporated
ISO7720, ISO7721
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ZHCSFQ6C – NOVEMBER 2016 – REVISED JULY 2018
6.8 Safety Limiting Values
Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
DW-16 PACKAGE
IS
Safety input, output, or supply
current (1)
PS
Safety input, output, or total
power (1)
TS
Maximum safety
temperature (1)
RθJA = 86.5 °C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C, see Figure 1
263
RθJA = 86.5 °C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C, see Figure 1
401
RθJA = 86.5 °C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C, see Figure 1
525
RθJA = 86.5 °C/W, TJ = 150°C, TA = 25°C, see Figure 2
mA
1445
mW
150
°C
DWV-8 PACKAGE
IS
Safety input, output, or supply
current (1)
PS
Safety input, output, or total
power (1)
TS
Maximum safety
temperature (1)
RθJA = 84.3 °C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C, see Figure 3
270
RθJA = 84.3 °C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C, see Figure 3
412
RθJA = 84.3 °C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C, see Figure 3
539
RθJA = 84.3 °C/W, TJ = 150°C, TA = 25°C, see Figure 4
mA
1483
mW
150
°C
D-8 PACKAGE
IS
Safety input, output, or supply
current (1)
PS
Safety input, output, or total
power (1)
TS
Maximum safety
temperature (1)
(1)
RθJA = 137.7 °C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C, see Figure 5
165
RθJA = 137.7 °C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C, see Figure 5
252
RθJA = 137.7 °C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C, see Figure 5
330
RθJA = 137.7 °C/W, TJ = 150°C, TA = 25°C, see Figure 6
908
mW
150
°C
mA
The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS
and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be
exceeded. These limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the Thermal Information table is that of a device installed on a high-K test board for
leaded surface-mount packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum allowed junction temperature.
PS = IS × VI, where VI is the maximum input voltage.
Copyright © 2016–2018, Texas Instruments Incorporated
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6.9 Electrical Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
VCCO (1) –
0.4
4.8
VOH
High-level output voltage
IOH = –4 mA; see Figure 15
VOL
Low-level output voltage
IOL = 4 mA; see Figure 15
VIT+(IN)
Rising input threshold voltage
VIT-(IN)
Falling input threshold voltage
0.3 x VCCI
0.4 x VCCI
VI(HYS)
Input threshold voltage hysteresis
0.1 × VCCI
0.2 × VCCI
IIH
High-level input current
VIH = VCCI (1) at INx
IIL
Low-level input current
VIL = 0 V at INx
CMTI
Common-mode transient
immunity
VI = VCCI or 0 V, VCM = 1200 V; see Figure 17
CI
Input Capacitance (2)
VI = VCC/ 2 + 0.4×sin(2πft), f = 1 MHz, VCC = 5 V
(1)
(2)
MAX
V
0.2
0.4
V
0.6 x VCCI
0.7 x VCCI
V
V
V
10
–10
85
UNIT
μA
µA
100
kV/μs
2
pF
VCCI = Input-side VCC; VCCO = Output-side VCC.
Measured from input pin to ground.
6.10 Supply Current Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
SUPPLY
CURRENT
TEST CONDITIONS
MIN
TYP
MAX
ICC1
0.8
1.1
ICC2
1.1
1.7
ICC1
2.9
4.2
ICC2
1.2
1.9
ICC1
1.8
2.7
ICC2
1.3
1.9
ICC1
1.9
2.7
ICC2
2.2
3
ICC1
2.5
3.2
ICC2
11.6
14
UNIT
ISO7720
VI = VCCI (ISO7720), VI = 0 V (ISO7720 with F suffix)
Supply current - DC signal
VI = 0 V (ISO7720), VI = VCCI (ISO7720 with F suffix)
1 Mbps
Supply current - AC signal
All channels switching with square
wave clock input; CL = 15 pF
10 Mbps
100 Mbps
mA
ISO7721
Supply current - DC signal
Supply current - AC signal
10
VI = VCCI (ISO7721),
VI = 0 V (ISO7721 with F suffix)
ICC1, ICC2
1
1.6
VI = 0 V (ISO7721),
VI = VCCI (ISO7721 with F suffix)
ICC1, ICC2
2.2
3.2
1 Mbps
ICC1, ICC2
1.7
2.4
10 Mbps
ICC1, ICC2
2.2
3
100 Mbps
ICC1, ICC2
7.3
9
All channels switching with square
wave clock input; CL = 15 pF
mA
Copyright © 2016–2018, Texas Instruments Incorporated
ISO7720, ISO7721
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6.11 Electrical Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
VCCO (1) – 0.3
3.2
VOH
High-level output voltage
IOH = –2 mA; see Figure 15
VOL
Low-level output voltage
IOL = 2 mA; see Figure 15
VIT+(IN)
Rising input voltage threshold
VIT-(IN)
Falling input voltage threshold
0.3 x VCCI
0.4 x VCCI
VI(HYS)
Input threshold voltage hysteresis
0.1 × VCCI
0.2 × VCCI
IIH
High-level input current
VIH = VCCI (1) at INx
IIL
Low-level input current
VIL = 0 V at INx
CMTI
Common-mode transient immunity
VI = VCCI or 0 V, VCM = 1200 V; see Figure 17
(1)
MAX
UNIT
V
0.1
0.3
V
0.6 x VCCI
0.7 x VCCI
V
V
V
10
–10
μA
µA
85
100
kV/μs
MIN
TYP
MAX
ICC1
0.8
1.1
ICC2
1.1
1.7
ICC1
2.9
4.2
ICC2
1.2
1.9
ICC1
1.8
2.7
ICC2
1.2
1.9
ICC1
1.9
2.7
ICC2
1.9
2.6
ICC1
2.2
3.1
ICC2
8.6
11
VCCI = Input-side VCC; VCCO = Output-side VCC.
6.12 Supply Current Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
SUPPLY
CURRENT
TEST CONDITIONS
UNIT
ISO7720
VI = VCCI (ISO7720), VI = 0 V (ISO7720 with F suffix)
Supply current - DC signal
VI = 0 V (ISO7720), VI = VCCI (ISO7720 with F suffix)
1 Mbps
Supply current - AC signal
All channels switching with square wave
clock input; CL = 15 pF
10 Mbps
100 Mbps
mA
ISO7721
Supply current - DC signal
Supply current - AC signal
VI = VCCI (ISO7721), VI = 0 V (ISO7721 with F suffix)
ICC1, ICC2
1
1.6
VI = 0 V (ISO7721), VI = VCCI (ISO7721 with F suffix)
ICC1, ICC2
2.2
3.2
1 Mbps
ICC1, ICC2
1.6
2.4
10 Mbps
ICC1, ICC2
2
2.8
100 Mbps
ICC1, ICC2
5.6
7
All channels switching with square wave
clock input; CL = 15 pF
Copyright © 2016–2018, Texas Instruments Incorporated
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6.13 Electrical Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
VCCO (1) – 0.2
2.45
VOH
High-level output voltage
IOH = –1 mA; see Figure 15
VOL
Low-level output voltage
IOL = 1 mA; see Figure 15
VIT+(IN)
Rising input voltage threshold
VIT-(IN)
Falling input voltage threshold
0.3 x VCCI
0.4 x VCCI
VI(HYS)
Input threshold voltage hysteresis
0.1 × VCCI
0.2 × VCCI
IIH
High-level input current
VIH = VCCI (1) at INx
IIL
Low-level input current
VIL = 0 V at INx
CMTI
Common-mode transient immunity
VI = VCCI or 0 V, VCM = 1200 V; see Figure 17
(1)
MAX
V
0.05
0.2
V
0.6 x VCCI
0.7 x VCCI
V
V
V
10
–10
85
UNIT
μA
μA
100
kV/μs
VCCI = Input-side VCC; VCCO = Output-side VCC.
6.14 Supply Current Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
SUPPLY CURRENT
MIN
TYP
MAX
ICC1
0.8
1.1
ICC2
1.1
1.7
ICC1
2.9
4.2
ICC2
1.2
1.9
ICC1
1.8
2.7
ICC2
1.3
1.9
ICC1
1.9
2.7
ICC2
1.7
2.4
ICC1
2.2
3
ICC2
6.8
9
UNIT
ISO7720
VI = VCCI (ISO7720), VI = 0 V (ISO7720 with F suffix)
Supply current - DC signal
VI = 0 V (ISO7720), VI = VCCI (ISO7720 with F suffix)
1 Mbps
Supply current - AC signal
All channels switching with square
wave clock input; CL = 15 pF
10 Mbps
100 Mbps
mA
ISO7721
Supply current - DC signal
Supply current - AC signal
12
VI = VCCI (ISO7721), VI = 0 V (ISO7721 with F suffix)
ICC1, ICC2
1
1.6
VI = 0 V (ISO7721), VI = VCCI (ISO7721 with F suffix)
ICC1, ICC2
2.2
3.2
1 Mbps
ICC1, ICC2
1.6
2.4
10 Mbps
ICC1, ICC2
1.9
2.7
100 Mbps
ICC1, ICC2
4.6
6
All channels switching with square
wave clock input; CL = 15 pF
mA
Copyright © 2016–2018, Texas Instruments Incorporated
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6.15 Switching Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
tPLH, tPHL
Propagation delay time
PWD
Pulse width distortion (1) |tPHL – tPLH|
tsk(o)
Channel-to-channel output skew time (2)
tsk(pp)
Part-to-part skew time (3)
tr
Output signal rise time
tf
Output signal fall time
TEST CONDITIONS
MAX
11
16
ns
0.5
4.9
ns
4
ns
4.5
ns
1.8
3.9
ns
1.9
3.9
ns
0.1
0.3
μs
Same direction channels
See Figure 15
tDO
Default output delay time from input power loss
tie
Time interval error
216 – 1 PRBS data at 100 Mbps
(3)
TYP
6
See Figure 15
Measured from the time VCC goes below 1.7
V. See Figure 16
(1)
(2)
MIN
1
UNIT
ns
Also known as pulse skew.
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
6.16 Switching Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
tPLH, tPHL
Propagation delay time
PWD
Pulse width distortion (1) |tPHL – tPLH|
tsk(o)
Channel-to-channel output skew time (2)
tsk(pp)
Part-to-part skew time (3)
tr
Output signal rise time
tf
Output signal fall time
See Figure 15
MAX
11
16
ns
0.5
5
ns
4.1
ns
4.5
ns
0.7
3
ns
0.7
3
ns
0.1
0.3
μs
See Figure 15
tDO
Default output delay time from input power loss
tie
Time interval error
216 – 1 PRBS data at 100 Mbps
(3)
TYP
6
Same direction channels
Measured from the time VCC goes
below 1.7 V. See Figure 16
(1)
(2)
MIN
1
UNIT
ns
Also known as pulse skew.
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
6.17 Switching Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
tPLH, tPHL
Propagation delay time
PWD
Pulse width distortion (1) |tPHL – tPLH|
tsk(o)
Channel-to-channel output skew time
tsk(pp)
Part-to-part skew time (3)
tr
Output signal rise time
tf
Output signal fall time
tDO
tie
(1)
(2)
(3)
TEST CONDITIONS
See Figure 15
(2)
Default output delay time from input power loss
Time interval error
MIN
TYP
MAX
UNIT
7.5
12
18.5
ns
0.5
5.1
ns
4.1
ns
4.6
ns
1
3.5
ns
1
3.5
ns
0.1
0.3
μs
Same direction channels
See Figure 15
Measured from the time VCC goes
below 1.7 V. See Figure 16
16
2
– 1 PRBS data at 100 Mbps
1
ns
Also known as pulse skew.
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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6.18 Insulation Characteristics Curves
1600
VCC1 = VCC2 = 2.75 V
VCC1 = VCC2 = 3.6 V
VCC1 = VCC2 = 5.5 V
500
1400
Safety Limiting Current (mA)
Safety Limiting Current (mA)
600
400
300
200
100
50
100
150
Ambient Temperature (qC)
600
400
0
200
50
D001
Figure 1. Thermal Derating Curve for Limiting Current per
VDE for DW-16 Package
100
150
Ambient Temperature (qC)
200
D002
Figure 2. Thermal Derating Curve for Limiting Power per
VDE for DW-16 Package
600
1600
VCC1 = VCC2 = 2.75 V
VCC1 = VCC2 = 3.6 V
VCC1 = VCC2 = 5.5 V
500
1400
Safety Limiting Current (mA)
Safety Limiting Current (mA)
800
0
0
400
300
200
100
1200
1000
800
600
400
200
0
0
0
50
100
150
Ambient Temperature (qC)
200
0
50
D013
Figure 3. Thermal Derating Curve for Limiting Current per
VDE for DWV-8 Package
100
150
Ambient Temperature (qC)
200
D014
Figure 4. Thermal Derating Curve for Limiting Power per
VDE for DWV-8 Package
350
1000
VCC1 = VCC2 = 2.75 V
VCC1 = VCC2 = 3.6 V
VCC1 = VCC2 = 5.5 V
900
Safety Limiting Current (mA)
300
Safety Limiting Current (mA)
1000
200
0
250
200
150
100
50
800
700
600
500
400
300
200
100
0
0
0
50
100
150
Ambient Temperature (qC)
200
D003
Figure 5. Thermal Derating Curve for Limiting Current per
VDE for D-8 Package
14
1200
0
50
100
150
Ambient Temperature (qC)
200
D004
Figure 6. Thermal Derating Curve for Limiting Power per
VDE for D-8 Package
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ISO7720, ISO7721
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ZHCSFQ6C – NOVEMBER 2016 – REVISED JULY 2018
6.19 Typical Characteristics
5
14
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
4.5
4
10
Supply Current (mA)
Supply Current (mA)
12
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
8
6
4
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
3.5
3
2.5
2
1.5
1
2
0.5
0
0
0
25
50
Data Rate (Mbps)
TA = 25°C
75
0
100
CL = 15 pF
50
Data Rate (Mbps)
TA = 25°C
Figure 7. ISO7720 Supply Current vs Data Rate
(With 15-pF Load)
75
100
D006
CL = No Load
Figure 8. ISO7720 Supply Current vs Data Rate
(With No Load)
4
9
ICC1, ICC2 at 2.5 V
ICC1, ICC2 at 3.3 V
ICC1, ICC2 at 5 V
8
ICC1, ICC2 at 2.5 V
ICC1, ICC2 at 3.3 V
ICC1, ICC2 at 5 V
3.5
Supply Current (mA)
7
Supply Current (mA)
25
D005
6
5
4
3
2
3
2.5
2
1.5
1
0.5
1
0
0
0
25
TA = 25°C
50
Data Rate (Mbps)
75
0
100
25
D007
CL = 15 pF
TA = 25°C
Figure 9. ISO7721 Supply Current vs Data Rate
(With 15-pF Load)
50
Data Rate (Mbps)
75
100
D008
CL = No Load
Figure 10. ISO7721 Supply Current vs Data Rate
(With No Load)
6
0.9
Low-Level Output Voltage (V)
High-Level Output Voltage (V)
0.8
5
4
3
2
VCC at 2.5 V
VCC at 3.3 V
VCC at 5 V
1
0
-15
0.7
0.6
0.5
0.4
0.3
0.2
VCC at 2.5 V
VCC at 3.3 V
VCC at 5 V
0.1
0
-10
-5
High-Level Output Current (mA)
0
TA = 25°C
Figure 11. High-Level Output Voltage vs High-level
Output Current
Copyright © 2016–2018, Texas Instruments Incorporated
0
5
10
Low-Level Output Current (mA)
D011
15
D012
TA = 25°C
Figure 12. Low-Level Output Voltage vs Low-Level
Output Current
15
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Typical Characteristics (continued)
14
Propagation Delay Time (ns)
Power Supply UVLO Threshold (V)
2.1
2.05
2
1.95
1.9
1.85
1.8
1.75
1.7
VCC1+
VCC1-
1.65
1.6
-55
-25
5
35
65
Free-Air Temperature (qC)
12
11
10
tPLH at 2.5 V
tPHL at 2.5 V
tPLH at 3.3 V
9
VCC2+
VCC295
125
D011
Figure 13. Power Supply Undervoltage Threshold vs
Free-Air Temperature
16
13
8
-55
-25
5
35
65
Free Air Temperature (qC)
tPHL at 3.3 V
tPLH at 5 V
tPHL at 5 V
95
125
D012
Figure 14. Propagation Delay Time vs Free-Air Temperature
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ISO7720, ISO7721
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ZHCSFQ6C – NOVEMBER 2016 – REVISED JULY 2018
7 Parameter Measurement Information
Isolation Barrier
IN
Input Generator
(See Note A)
VI
VCCI
VI
OUT
50%
50%
0V
tPLH
CL
See Note B
VO
50
tPHL
VOH
90%
50%
VO
50%
10%
VOL
tf
tr
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50 Ω. At the input, 50 Ω resistor is required to terminate Input Generator signal. It is not needed in
actual application.
B.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 15. Switching Characteristics Test Circuit and Voltage Waveforms
VI
See Note B
VCC
VCC
Isolation Barrier
IN = 0 V (Devices without suffix F)
IN = VCC (Devices with suffix F)
VI
IN
1.7 V
0V
OUT
VO
tDO
CL
See Note A
default high
VOH
50%
VO
VOL
default low
A.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
B.
Power Supply Ramp Rate = 10 mV/ns
Figure 16. Default Output Delay Time Test Circuit and Voltage Waveforms
VCCI
VCCO
C = 0.1 µF ±1%
Pass-fail criteria:
The output must
remain stable.
Isolation Barrier
S1
C = 0.1 µF ±1%
IN
OUT
+
VOH or VOL
CL
See Note A
GNDI
A.
+
VCM ±
±
GNDO
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 17. Common-Mode Transient Immunity Test Circuit
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8 Detailed Description
8.1 Overview
The ISO772x family of devices has an ON-OFF keying (OOK) modulation scheme to transmit the digital data
across a silicon dioxide based isolation barrier. The transmitter sends a high frequency carrier across the barrier
to represent one digital state and sends no signal to represent the other digital state. The receiver demodulates
the signal after advanced signal conditioning and produces the output through a buffer stage. These devices also
incorporate advanced circuit techniques to maximize the CMTI performance and minimize the radiated emissions
due the high frequency carrier and IO buffer switching. The conceptual block diagram of a digital capacitive
isolator, Figure 18, shows a functional block diagram of a typical channel.
8.2 Functional Block Diagram
Transmitter
TX IN
Receiver
OOK
Modulation
TX Signal
Conditioning
Oscillator
SiO2 based
Capacitive
Isolation
Barrier
RX Signal
Conditioning
Envelope
Detection
RX OUT
Emissions
Reduction
Techniques
Copyright © 2017, Texas Instruments Incorporated
Figure 18. Conceptual Block Diagram of a Digital Capacitive Isolator
Figure 19 shows a conceptual detail of how the OOK scheme works.
TX IN
Carrier signal through
isolation barrier
RX OUT
Figure 19. On-Off Keying (OOK) Based Modulation Scheme
18
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ZHCSFQ6C – NOVEMBER 2016 – REVISED JULY 2018
8.3 Feature Description
The ISO772x family of devices is available in two channel configurations and default output state options to
enable a variety of application uses. Table 1 lists the device features of the ISO772x devices.
Table 1. Device Features
PART NUMBER
MAXIMUM DATA
RATE
CHANNEL
DIRECTION
DEFAULT OUTPUT
STATE
PACKAGE
RATED ISOLATION (1)
DW-16
5000 VRMS / 8000 VPK
ISO7720
100 Mbps
2 Forward, 0 Reverse
High
DWV-8
5000 VRMS / 7071 VPK
ISO7720F
ISO7721
ISO7721F
(1)
100 Mbps
100 Mbps
100 Mbps
2 Forward, 0 Reverse
1 Forward, 1 Reverse
1 Forward, 1 Reverse
Low
High
Low
D-8
3000 VRMS / 4242 VPK
DW-16
5000 VRMS / 8000 VPK
DWV-8
5000 VRMS / 7071 VPK
D-8
3000 VRMS / 4242 VPK
DW-16
5000 VRMS / 8000 VPK
DWV-8
5000 VRMS / 7071 VPK
D-8
3000 VRMS / 4242 VPK
DW-16
5000 VRMS / 8000 VPK
DWV-8
5000 VRMS / 7071 VPK
D-8
3000 VRMS / 4242 VPK
See the Safety-Related Certifications section for detailed isolation ratings.
8.3.1 Electromagnetic Compatibility (EMC) Considerations
Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge
(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances
are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level
performance and reliability depends, to a large extent, on the application board design and layout, the ISO772x
family of devices incorporates many chip-level design improvements for overall system robustness. Some of
these improvements include:
• Robust ESD protection cells for input and output signal pins and inter-chip bond pads.
• Low-resistance connectivity of ESD cells to supply and ground pins.
• Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.
• Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance
path.
• PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic
SCRs.
• Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.
Copyright © 2016–2018, Texas Instruments Incorporated
19
ISO7720, ISO7721
ZHCSFQ6C – NOVEMBER 2016 – REVISED JULY 2018
www.ti.com.cn
8.4 Device Functional Modes
Table 2 lists the functional modes for the ISO772x devices.
Table 2. Function Table (1)
VCCI
VCCO
PU
(1)
(2)
(3)
INPUT
(INx) (2)
OUTPUT
(OUTx)
H
H
L
L
Open
Default
Default mode: When INx is open, the corresponding channel output goes to the
default high logic state. The default is High for ISO772x and Low for ISO772x
with F suffix.
Default mode: When VCCI is unpowered, a channel output assumes the logic
state based on the selected default option. The default is High for ISO772x and
Low for ISO772x with F suffix.
When VCCI transitions from unpowered to powered-up, a channel output
assumes the logic state of the input.
When VCCI transitions from powered-up to unpowered, channel output assumes
the selected default state.
COMMENTS
Normal Operation:
A channel output assumes the logic state of the input.
PU
PD
PU
X
Default
X
PD
X
Undetermined
When VCCO is unpowered, a channel output is undetermined (3).
When VCCO transitions from unpowered to powered-up, a channel output
assumes the logic state of the input
VCCI = Input-side VCC; VCCO = Output-side VCC; PU = Powered up (VCC ≥ 2.25 V); PD = Powered down (VCC ≤ 1.7 V); X = Irrelevant; H
= High level; L = Low level
A strongly driven input signal can weakly power the floating VCC via an internal protection diode and cause undetermined output.
The outputs are in undetermined state when 1.7 V < VCCI, VCCO < 2.25 V.
8.4.1 Device I/O Schematics
Input (Devices without F suffix)
VCCI
VCCI
VCCI
Input (Devices with F suffix)
VCCI
VCCI
VCCI
VCCI
1.5 M
985
985
INx
INx
1.5 M
Output
VCCO
~20
OUTx
Figure 20. Device I/O Schematics
20
Copyright © 2016–2018, Texas Instruments Incorporated
ISO7720, ISO7721
www.ti.com.cn
ZHCSFQ6C – NOVEMBER 2016 – REVISED JULY 2018
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant the accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The ISO772x devices are high-performance, dual-channel digital isolators. The devices use single-ended CMOSlogic switching technology. The supply voltage range is from 2.25 V to 5.5 V for both supplies, VCC1 and VCC2.
When designing with digital isolators, keep in mind that because of the single-ended design structure, digital
isolators do not conform to any specific interface standard and are only intended for isolating single-ended
CMOS or TTL digital signal lines. The isolator is typically placed between the data controller (that is, μC or
UART), and a data converter or a line transceiver, regardless of the interface type or standard.
9.2 Typical Application
The ISO7721 device can be used with Texas Instruments' mixed signal microcontroller, digital-to-analog
converter, transformer driver, and voltage regulator to create an isolated 4-mA to 20-mA current loop.
VS
0.1 F
3.3 V
2
VCC D2 3
1:1.33
MBR0520L
1
SN6501
10 F
GND D1
0.1 F
IN
OUT
5 3.3VISO
10 F
TPS76333
3
1
EN
GND
2
10 F
MBR0520L
4, 5
ISO Barrier
0.1 F
0.1 F
20
LOOP+
0.1 F
0.1 F
15
0.1 F
10
3
8
2
5
6
VCC1
DVCC
XOUT
MSP430G2132
XIN
DVSS
4
14
P3.0 11
12
P3.1
4
5
VCC2
OUTA ISO7721
INB
GND1
1, 7
INA
OUTB
GND2
9, 16
13
12
5
4
3
VA
VD
LOW
BASE
ERRLVL
16
0.1 F
DAC161P997
22
DBACK
DIN
C1
14
3 × 2.2 nF
1 F
C2
13
C3 COMA
12
1
OUT
COMD
9
LOOP±
2
Copyright © 2017, Texas Instruments Incorporated
Figure 21. Isolated 4-mA to 20-mA Current Loop
Copyright © 2016–2018, Texas Instruments Incorporated
21
ISO7720, ISO7721
ZHCSFQ6C – NOVEMBER 2016 – REVISED JULY 2018
www.ti.com.cn
Typical Application (continued)
9.2.1 Design Requirements
To design with these devices, use the parameters listed in Table 3.
Table 3. Design Parameters
PARAMETER
VALUE
Supply voltage, VCC1 and VCC2
2.25 V to 5.5 V
Decoupling capacitor between VCC1 and GND1
0.1 µF
Decoupling capacitor from VCC2 and GND2
0.1 µF
9.2.2 Detailed Design Procedure
Unlike optocouplers, which require external components to improve performance, provide bias, or limit current,
the ISO772x devices only require two external bypass capacitors to operate.
VCC1
VCC2
GND1 1
GND1
16 GND2
GND2
0.1 µF
0.1 µF
NC
2
15
NC
VCC1
3
14 VCC2
GND2
OUTA
OUTA 4
INB
ISOLATION
GND1
13
INA
INA
INB
5
12 OUTB
NC
6
11
NC
GND1 7
10
NC
OUTB
GND1
NC
8
9 GND2
GND2
Figure 22. Typical ISO7721 Circuit Hook-up
9.2.3 Application Curve
1 V/ div
1 V/ div
The following typical eye diagrams of the ISO772x family of devices indicate low jitter and wide open eye at the
maximum data rate of 100 Mbps.
Time = 3.5 ns / div
Figure 23. ISO7720 Eye Diagram at 100 Mbps PRBS,
5-V Supplies and 25°C
22
Time = 3.5 ns / div
Figure 24. ISO7721 Eye Diagram at 100 Mbps PRBS,
5-V Supplies and 25°C
Copyright © 2016–2018, Texas Instruments Incorporated
ISO7720, ISO7721
www.ti.com.cn
ZHCSFQ6C – NOVEMBER 2016 – REVISED JULY 2018
10 Power Supply Recommendations
To help ensure reliable operation at data rates and supply voltages, a 0.1-μF bypass capacitor is recommended
at the input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins
as possible. If only a single primary-side power supply is available in an application, isolated power can be
generated for the secondary-side with the help of a transformer driver such as Texas Instruments' SN6501 or
SN6505A. For such applications, detailed power supply design and transformer selection recommendations are
available in SN6501 Transformer Driver for Isolated Power Supplies or SN6505 Low-Noise 1-A Transformer
Drivers for Isolated Power Supplies.
11 Layout
11.1 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 25). Layer stacking should
be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency
signal layer.
• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/in2.
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to
the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the
power and ground plane of each power system can be placed closer together, thus increasing the high-frequency
bypass capacitance significantly.
For detailed layout recommendations, refer to the Digital Isolator Design Guide.
11.1.1 PCB Material
For digital circuit boards operating at less than 150 Mbps, (or rise and fall times greater than 1 ns), and trace
lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper
alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater strength and
stiffness, and the self-extinguishing flammability-characteristics.
11.2 Layout Example
High-speed traces
10 mils
Ground plane
40 mils
Keep this
space free
from planes,
traces, pads,
and vias
FR-4
0r ~ 4.5
Power plane
10 mils
Low-speed traces
Figure 25. Layout Example
版权 © 2016–2018, Texas Instruments Incorporated
23
ISO7720, ISO7721
ZHCSFQ6C – NOVEMBER 2016 – REVISED JULY 2018
www.ti.com.cn
12 器件和文档支持
12.1 器件支持
12.1.1 开发支持
有关开发支持，请参阅：
• 隔离式 CAN 灵活数据 (FD) 速率中继器参考设计
• 采用双同步采样 ADC 的隔离式 16 通道交流模拟输入模块参考设计
• 具有隔离式 AFE 的多相分流计量参考设计
• 电源隔离型超紧凑模拟输出模块参考设计
12.2 文档支持
12.2.1 相关文档
请参阅如下相关文档：
• 德州仪器 (TI)，《适用于 4mA 至 20mA 回路的 DAC161P997 单线 16 位 DAC》数据表
• 德州仪器 (TI)，《数字隔离器设计指南》
• 德州仪器 (TI)，《隔离相关术语》
• 德州仪器 (TI)，MSP430G2132《混合信号微控制器》数据表
• 德州仪器 (TI)，《SN6501 用于隔离式电源的变压器驱动器》数据表
• 德州仪器 (TI)，《TPS76333 低功耗 150mA 低压降线性稳压器》数据表
12.3 相关链接
下表列出了快速访问链接。类别包括技术文档、支持与社区资源、工具和软件，以及申请样片或购买产品的快速链
接。
表 4. 相关链接
器件
产品文件夹
立即订购
技术文档
工具与软件
支持和社区
ISO7720
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
ISO7721
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
12.4 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.5 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
12.6 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.7 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
24
版权 © 2016–2018, Texas Instruments Incorporated
ISO7720, ISO7721
www.ti.com.cn
ZHCSFQ6C – NOVEMBER 2016 – REVISED JULY 2018
12.8 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
版权 © 2016–2018, Texas Instruments Incorporated
25
ISO7720, ISO7721
ZHCSFQ6C – NOVEMBER 2016 – REVISED JULY 2018
www.ti.com.cn
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
26
版权 © 2016–2018, Texas Instruments Incorporated
ISO7720, ISO7721
www.ti.com.cn
ZHCSFQ6C – NOVEMBER 2016 – REVISED JULY 2018
PACKAGE OUTLINE
D0008B
SOIC - 1.75 mm max height
SCALE 2.800
SOIC
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
A
.004 [0.1] C
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.150
[3.81]
.189-.197
[4.81-5.00]
NOTE 3
4
5
B
.150-.157
[3.81-3.98]
NOTE 4
8X .012-.020
[0.31-0.51]
.010 [0.25]
C A
B
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
SEE DETAIL A
.010
[0.25]
.004-.010
[ 0.11 -0.25]
0 -8
.016-.050
[0.41-1.27]
DETAIL A
.041
[1.04]
TYPICAL
4221445/B 04/2014
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15], per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
版权 © 2016–2018, Texas Instruments Incorporated
27
ISO7720, ISO7721
ZHCSFQ6C – NOVEMBER 2016 – REVISED JULY 2018
www.ti.com.cn
EXAMPLE BOARD LAYOUT
D0008B
SOIC - 1.75 mm max height
SOIC
8X (.061 )
[1.55]
SEE
DETAILS
SYMM
8X (.055)
[1.4]
SEE
DETAILS
SYMM
1
1
8
8X (.024)
[0.6]
8
SYMM
8X (.024)
[0.6]
5
4
6X (.050 )
[1.27]
SYMM
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
(.217)
[5.5]
HV / ISOLATION OPTION
.162 [4.1] CLEARANCE / CREEPAGE
IPC-7351 NOMINAL
.150 [3.85] CLEARANCE / CREEPAGE
LAND PATTERN EXAMPLE
SCALE:6X
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
.0028 MAX
[0.07]
ALL AROUND
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221445/B 04/2014
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
28
版权 © 2016–2018, Texas Instruments Incorporated
ISO7720, ISO7721
www.ti.com.cn
ZHCSFQ6C – NOVEMBER 2016 – REVISED JULY 2018
EXAMPLE STENCIL DESIGN
D0008B
SOIC - 1.75 mm max height
SOIC
8X (.061 )
[1.55]
8X (.055)
[1.4]
SYMM
SYMM
1
1
8
8X (.024)
[0.6]
6X (.050 )
[1.27]
8
SYMM
8X (.024)
[0.6]
5
4
6X (.050 )
[1.27]
SYMM
5
4
(.217)
[5.5]
(.213)
[5.4]
HV / ISOLATION OPTION
.162 [4.1] CLEARANCE / CREEPAGE
IPC-7351 NOMINAL
.150 [3.85] CLEARANCE / CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.127 MM] THICK STENCIL
SCALE:6X
4221445/B 04/2014
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
版权 © 2016–2018, Texas Instruments Incorporated
29
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
ISO7720D
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
7720
ISO7720DR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
7720
ISO7720DW
ACTIVE
SOIC
DW
16
40
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
ISO7720
ISO7720DWR
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
ISO7720
ISO7720DWV
ACTIVE
SOIC
DWV
8
64
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
7720
ISO7720DWVR
ACTIVE
SOIC
DWV
8
1000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
7720
ISO7720FD
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
7720F
ISO7720FDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
7720F
ISO7720FDW
ACTIVE
SOIC
DW
16
40
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
ISO7720F
ISO7720FDWR
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
ISO7720F
ISO7720FDWV
ACTIVE
SOIC
DWV
8
64
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
7720F
ISO7720FDWVR
ACTIVE
SOIC
DWV
8
1000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
7720F
ISO7721BDW
ACTIVE
SOIC
DW
16
40
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
ISO7721B
ISO7721BDWR
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
ISO7721B
ISO7721D
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
7721
ISO7721DR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
7721
ISO7721DW
ACTIVE
SOIC
DW
16
40
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
ISO7721
ISO7721DWR
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
ISO7721
ISO7721DWV
ACTIVE
SOIC
DWV
8
64
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
7721
ISO7721DWVR
ACTIVE
SOIC
DWV
8
1000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
7721
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
ISO7721FBDW
ACTIVE
SOIC
DW
16
40
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
ISO7721FB
ISO7721FBDWR
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
ISO7721FB
ISO7721FD
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
7721F
ISO7721FDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
7721F
ISO7721FDW
ACTIVE
SOIC
DW
16
40
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
ISO7721F
ISO7721FDWR
ACTIVE
SOIC
DW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
ISO7721F
ISO7721FDWV
ACTIVE
SOIC
DWV
8
64
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
7721F
ISO7721FDWVR
ACTIVE
SOIC
DWV
8
1000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
7721F
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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