ISO7740DBQR

Product Folder Order Now Support & Community Tools & Software Technical Documents ISO7740, ISO7741, ISO7742 SLLSEP4F – MARCH 2016 – REVISED MAY 2019 ISO774x High-Speed, Robust-EMC Reinforced Quad-Channel Digital Isolators 1 Features 3 Description • • The ISO774x devices are high-performance, quadchannel digital isolators with 5000 VRMS (DW package) and 3000 VRMS (DBQ package) isolation ratings per UL 1577. This family of devices has reinforced insulation ratings according to VDE, CSA, TUV and CQC. 1 • • • • • • • • • • 100 Mbps data rate Robust isolation barrier: – >100-year projected lifetime at 1500 VRMS working voltage – Up to 5000 VRMS isolation rating – Up to 12.8 kV surge capability – ±100 kV/μs typical CMTI Wide supply range: 2.25 V to 5.5 V 2.25-V to 5.5-V level translation Default output high (ISO774x) and low (ISO774xF) options Wide temperature range: –55°C to 125°C Low power consumption, typical 1.5 mA per channel at 1 Mbps Low propagation delay: 10.7 ns typical (5-V Supplies) Robust electromagnetic compatibility (EMC) – System-level ESD, EFT, and surge immunity – ±8 kV IEC 61000-4-2 contact discharge protection across isolation barrier – Low emissions Wide-SOIC (DW-16) and QSOP (DBQ-16) Package Options Automotive version available: ISO774x-Q1 Safety-related certifications: – DIN V VDE V 0884-11:2017-01 – UL 1577 component recognition program – CSA component acceptance notice 5A, IEC 60950-1 and IEC 60601-1 end equipment standards – CQC approval per GB4943.1-2011 – TUV certification according to EN 60950-1 and EN 61010-1 – All certifications complete The ISO774x devices provide high electromagnetic immunity and low emissions at low power consumption, while isolating CMOS or LVCMOS digital I/Os. Each isolation channel has a logic input and output buffer separated by a double capacitive silicon dioxide (SiO2) insulation barrier. This device comes with enable pins which can be used to put the respective outputs in high impedance for multi-master driving applications and to reduce power consumption. The ISO7740 device has all four channels in the same direction, the ISO7741 device has three forward and one reverse-direction channels, and the ISO7742 device has two forward and two reverse-direction channels. If the input power or signal is lost, default output is high for devices without suffix F and low for devices with suffix F. See the Device Functional Modes section for further details. Device Information(1) PART NUMBER ISO7740 ISO7741 ISO7742 PACKAGE BODY SIZE (NOM) SOIC (DW) 10.30 mm × 7.50 mm SSOP (DBQ) 4.90 mm × 3.90 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic VCCO VCCI Series Isolation Capacitors INx OUTx ENx 2 Applications • • • • • Industrial automation Motor control Power supplies Solar inverters Medical equipment GNDI GNDO Copyright © 2016, Texas Instruments Incorporated VCCI=Input supply, VCCO=Output supply GNDI=Input ground, GNDO=Output ground 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. ISO7740, ISO7741, ISO7742 SLLSEP4F – MARCH 2016 – REVISED MAY 2019 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Description Continued .......................................... Pin Configuration and Functions ......................... Specifications......................................................... 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17 1 1 1 2 5 6 8 Absolute Maximum Ratings ...................................... 8 ESD Ratings.............................................................. 8 Recommended Operating Conditions....................... 8 Thermal Information .................................................. 9 Power Rating............................................................. 9 Insulation Specifications.......................................... 10 Safety-Related Certifications................................... 11 Safety Limiting Values ............................................ 11 Electrical Characteristics—5-V Supply ................... 12 Supply Current Characteristics—5-V Supply ........ 13 Electrical Characteristics—3.3-V Supply .............. 14 Supply Current Characteristics—3.3-V Supply ..... 15 Electrical Characteristics—2.5-V Supply .............. 16 Supply Current Characteristics—2.5-V Supply ..... 17 Switching Characteristics—5-V Supply................. 18 Switching Characteristics—3.3-V Supply.............. 18 Switching Characteristics—2.5-V Supply.............. 19 7.18 Insulation Characteristics Curves ......................... 20 7.19 Typical Characteristics .......................................... 21 8 9 Parameter Measurement Information ................ 23 Detailed Description ............................................ 25 9.1 9.2 9.3 9.4 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 25 25 26 27 10 Application and Implementation........................ 29 10.1 Application Information.......................................... 29 10.2 Typical Application ................................................ 29 11 Power Supply Recommendations ..................... 32 12 Layout................................................................... 33 12.1 Layout Guidelines ................................................. 33 12.2 Layout Example .................................................... 33 13 Device and Documentation Support ................. 34 13.1 13.2 13.3 13.4 13.5 13.6 13.7 Documentation Support ........................................ Related Links ........................................................ Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 34 34 34 34 34 35 35 14 Mechanical, Packaging, and Orderable Information ........................................................... 35 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (January 2018) to Revision F Page • Made editorial and cosmetic changes throughout the document .......................................................................................... 1 • Changed From: "Isolation Barrier Life: >40 Years" To: " >100-year projected lifetime at 1500 VRMS working voltage" in Features.............................................................................................................................................................................. 1 • Added "Up to 5000 VRMS isolation rating" in Features............................................................................................................ 1 • Added "Up to 12.8 kV surge capability" in Features .............................................................................................................. 1 • Added "±8 kV IEC 61000-4-2 contact discharge protection across isolation barrier" in Features ......................................... 1 • Added "Automotive version available: ISO774x-Q1" in Features........................................................................................... 1 • Changed From: "All Certifications Complete except CQC Approval of DBQ-16 Package Devices" To: "All certifications complete" in Features ....................................................................................................................................... 1 • Updated Simplified Schematic to show two isolation capacitors in series per channel instead of a single isolation capacitor ................................................................................................................................................................................. 1 • Added "Contact discharge per IEC 61000-4-2" specification of ±8000 V in ESD Ratings..................................................... 8 • Added the following table note to Data rate specification: "100 Mbps is the maximum specified data rate, although higher data rates are possible." ............................................................................................................................................. 8 • Changed VIORM value for DW-16 package From: "1414 VPK" To: "2121 VPK" in Insulation Specifications table.................. 10 • Changed VIOWM values for DW-16 package From: "1000 VRMS" and "1414 VDC" To: "1500 VRMS" and "2121 VDC" in Insulation Specifications table ............................................................................................................................................. 10 • Added 'see Figure 28' to TEST CONDITIONS of VIOWM specification in Insulation Specifications ...................................... 10 • Changed VIOSM TEST CONDITIONS From: "Test method per IEC 60065" To: "Test method per IEC 62368-1" in Insulation Specifications table .............................................................................................................................................. 10 • Updated certification information in Safety-Related Certifications table .............................................................................. 11 2 Submit Documentation Feedback Copyright © 2016–2019, Texas Instruments Incorporated Product Folder Links: ISO7740 ISO7741 ISO7742 ISO7740, ISO7741, ISO7742 www.ti.com SLLSEP4F – MARCH 2016 – REVISED MAY 2019 Revision History (continued) • Switched the line colors for VCC at 2.5 V and VCC at 3.3 V in Figure 12 .............................................................................. 21 • Added Insulation Lifetime sub-section under Application Curve section.............................................................................. 31 • Added 'How to use isolation to improve ESD, EFT, and Surge immunity in industrial systems' application report to Documentation Support section ........................................................................................................................................... 34 Changes from Revision D (May 2017) to Revision E Page • Changed the DIN certification number and certification status throughout the document ..................................................... 1 • Changed the isolation rating of the DBQ package from 2500 VRMS to 3000 VRMS ................................................................. 1 • Added VTEST to the conditions for the maximum transient isolation voltage parameter in the Insulation Specifications table ...................................................................................................................................................................................... 10 • Changed the value for the DBQ package from 3600 VPK to 4242 VPK throughout the document...................................... 10 • Changed the method b1 Vini condition for apparent charge in the Insulation Specifications table ...................................... 10 • Switched the labels for VCC1 falling and VCC2 rising in the graph legend of Power Supply Undervoltage Threshold vs Free-Air Temperature ........................................................................................................................................................... 21 Changes from Revision C (December 2016) to Revision D Page • Updated the Safety-Related Certifications table................................................................................................................... 11 • Changed the minimum CMTI from 40 to 85 in all Electrical Characteristics tables ............................................................ 12 Changes from Revision B (October 2016) to Revision C Page • Changed the Regulatory Information table to Safety-Related Certifications and updated content...................................... 11 • Changed the certifications from planned to certified in the Safety-Related Certifications table........................................... 11 Changes from Revision A (June 2016) to Revision B Page • Changed Feature From: High CMTI: ±75 kV/μs Typical To: High CMTI: ±100 kV/μs Typical ............................................... 1 • Changed Feature From: All Certifications are Planned To: 'VDE, UL, and TUV Certifications for DW Package Complete; All Other Certifications are Planned...................................................................................................................... 1 • Changed the unit value of CLR and CPG From: μm To: mm in Insulation Specifications................................................... 10 • Changed From: "Plan to certify" To: "Certified" in column VDE of Safety-Related Certifications ........................................ 11 • Added a conditions statement to Safety-Related Certifications .......................................................................................... 11 • Changed From: "Plan to certify" To: "Certified" in column UL of Safety-Related Certifications ........................................... 11 • Changed From: "Plan to certify" To: "Certified" in column TUV of Safety-Related Certifications ........................................ 11 • Changed From: "Certification Planned" To: 'Certificate number: 40040142" in column VDE of Safety-Related Certifications ......................................................................................................................................................................... 11 • Changed From: "Certification Planned" To: "File number: E181974" in column VDE of Safety-Related Certifications....... 11 • Changed From: "Certification Planned" To: "Client ID number: 77311" in column TUV of Safety-Related Certifications ... 11 • Changed the CMTI TYP value From: 75 kV/μs To: 100 kV/μs in the Electrical Characteristics—5-V Supply..................... 12 • Changed the CMTI TYP value From: 75 kV/μs To: 100 kV/μs in the Electrical Characteristics—3.3-V Supply .................. 14 • Changed the CMTI TYP value From: 75 kV/μs To: 100 kV/μs in the Electrical Characteristics—2.5-V Supply .................. 16 • Changed the tDO TYP value From: 6 μs To: 0.1 μs and the MAX value From: 9 µs To: 0.3 µs in the Switching Characteristics—5-V Supply................................................................................................................................................. 18 • Changed the tDO TYP value From: 6 μs To: 0.1 μs and the MAX value From: 9 µs To: 0.3 µs in the Switching Characteristics—3.3-V Supply.............................................................................................................................................. 18 • Changed the tDO TYP value From: 6 μs To: 0.1 μs and the MAX value From: 9 µs To: 0.3 µs in the Switching Copyright © 2016–2019, Texas Instruments Incorporated Product Folder Links: ISO7740 ISO7741 ISO7742 Submit Documentation Feedback 3 ISO7740, ISO7741, ISO7742 SLLSEP4F – MARCH 2016 – REVISED MAY 2019 www.ti.com Characteristics—2.5-V Supply.............................................................................................................................................. 19 • Added Note B to Figure 17................................................................................................................................................... 24 • Changed the Design Requirements paragraph ................................................................................................................... 30 • Replaced the Power Supply Recommendations section ..................................................................................................... 32 Changes from Original (March 2016) to Revision A • 4 Page Changed the device status From: Preview To; Production. ................................................................................................... 1 Submit Documentation Feedback Copyright © 2016–2019, Texas Instruments Incorporated Product Folder Links: ISO7740 ISO7741 ISO7742 ISO7740, ISO7741, ISO7742 www.ti.com SLLSEP4F – MARCH 2016 – REVISED MAY 2019 5 Description Continued Used in conjunction with isolated power supplies, these devices help prevent noise currents on data buses, such as RS-485, RS-232, and CAN, or other circuits from entering the local ground and interfering with or damaging sensitive circuitry. Through innovative chip design and layout techniques, electromagnetic compatibility of the ISO774x devices have been significantly enhanced to ease system-level ESD, EFT, surge, and emissions compliance. The ISO774x devices are available in 16-pin SOIC and QSOP packages. Copyright © 2016–2019, Texas Instruments Incorporated Product Folder Links: ISO7740 ISO7741 ISO7742 Submit Documentation Feedback 5 ISO7740, ISO7741, ISO7742 SLLSEP4F – MARCH 2016 – REVISED MAY 2019 www.ti.com 6 Pin Configuration and Functions ISO7740 DW and DBQ Packages 16-Pin SOIC-WB and QSOP Top View ISO7741 DW and DBQ Packages 16-Pin SOIC-WB and QSOP Top View 1 16 VCC2 VCC1 1 16 VCC2 GND1 2 15 GND2 GND1 2 15 GND2 3 INB 4 INC 5 IND 6 11 OUTD NC 7 10 ISOLATION INA 14 OUTA INA 3 13 OUTB INB 4 12 OUTC INC 5 GND1 8 14 OUTA ISOLATION VCC1 OUTD 6 EN2 EN1 9 GND2 7 GND1 8 13 OUTB 12 OUTC 11 IND 10 EN2 9 GND2 ISO7742 DW and DBQ Packages 16-Pin SOIC-WB and QSOP Top View 1 16 VCC2 GND1 2 15 GND2 INA 3 INB 4 OUTC 5 OUTD 6 EN1 7 GND1 8 6 Submit Documentation Feedback 14 OUTA ISOLATION VCC1 13 OUTB 12 INC 11 IND 10 EN2 9 GND2 Copyright © 2016–2019, Texas Instruments Incorporated Product Folder Links: ISO7740 ISO7741 ISO7742 ISO7740, ISO7741, ISO7742 www.ti.com SLLSEP4F – MARCH 2016 – REVISED MAY 2019 Pin Functions PIN NAME I/O DESCRIPTION 7 I Output enable 1. Output pins on side 1 are enabled when EN1 is high or open and in high-impedance state when EN1 is low. 10 10 I Output enable 2. Output pins on side 2 are enabled when EN2 is high or open and in high-impedance state when EN2 is low. 2 2 2 8 8 8 ISO7740 ISO7741 ISO7742 EN1 — 7 EN2 10 GND1 — Ground connection for VCC1 — Ground connection for VCC2 9 9 9 15 15 15 INA 3 3 3 I Input, channel A INB 4 4 4 I Input, channel B INC 5 5 12 I Input, channel C IND 6 11 11 I Input, channel D NC 7 — — — Not connected OUTA 14 14 14 O Output, channel A OUTB 13 13 13 O Output, channel B OUTC 12 12 5 O Output, channel C OUTD 11 6 6 O Output, channel D VCC1 1 1 1 — Power supply, side 1 VCC2 16 16 16 — Power supply, side 2 GND2 Copyright © 2016–2019, Texas Instruments Incorporated Product Folder Links: ISO7740 ISO7741 ISO7742 Submit Documentation Feedback 7 ISO7740, ISO7741, ISO7742 SLLSEP4F – MARCH 2016 – REVISED MAY 2019 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings See (1) VCC1, VCC2 Supply voltage (2) MIN MAX –0.5 6 V Voltage at INx, OUTx, ENx –0.5 IO Output current –15 TJ Junction temperature Tstg Storage temperature (1) (2) (3) UNIT V VCCX + 0.5 –65 (3) V 15 mA 150 °C 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak voltage values. Maximum voltage must not exceed 6 V. 7.2 ESD Ratings VALUE V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) ±6000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) ±1500 Contact discharge per IEC 61000-4-2; Isolation barrier withstand test (1) (2) (3) (4) (3) (4) UNIT V ±8000 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. IEC ESD strike is applied across the barrier with all pins on each side tied together creating a two-terminal device. Testing is carried out in air or oil to determine the intrinsic contact discharge capability of the device. 7.3 Recommended Operating Conditions MIN NOM UNIT Supply voltage VCC(UVLO+) UVLO threshold when supply voltage is rising VCC(UVLO-) UVLO threshold when supply voltage is falling 1.7 1.8 V VHYS(UVLO) Supply voltage UVLO hysteresis 100 200 mV IOH IOL High-level output current Low-level output current VCCO (1) = 5 V –4 VCCO = 3.3 V –2 VCCO = 2.5 V –1 V 2.25 V mA VCCO = 5 V 4 VCCO = 3.3 V 2 VCCO = 2.5 V 1 mA VCCI Low-level input voltage 0 0.3 × VCCI Data rate (2) 0 100 Mbps 125 °C High-level input voltage VIL DR TA Ambient temperature 8 2 5.5 (1) VIH (1) (2) 2.25 MAX VCC1, VCC2 0.7 × VCCI –55 25 V V VCCI = Input-side VCC; VCCO = Output-side VCC. 100 Mbps is the maximum specified data rate, although higher data rates are possible. Submit Documentation Feedback Copyright © 2016–2019, Texas Instruments Incorporated Product Folder Links: ISO7740 ISO7741 ISO7742 ISO7740, ISO7741, ISO7742 www.ti.com SLLSEP4F – MARCH 2016 – REVISED MAY 2019 7.4 Thermal Information ISO774x THERMAL METRIC (1) DW (SOIC) DBQ (QSOP) 16 Pins 16 Pins UNIT 83.4 109 °C/W RθJA Junction-to-ambient thermal resistance RθJC(top) Junction-to-case(top) thermal resistance 46 54.4 °C/W RθJB Junction-to-board thermal resistance 48 51.9 °C/W ψJT Junction-to-top characterization parameter 19.1 14.2 °C/W ψJB Junction-to-board characterization parameter 47.5 51.4 °C/W RθJC(bottom) Junction-to-case(bottom) thermal resistance — — °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 7.5 Power Rating PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 200 mW 40 mW 160 mW 200 mW 75 mW 125 mW 200 mW 100 mW 100 mW ISO7740 PD Maximum power dissipation PD1 Maximum power dissipation by side-1 PD2 Maximum power dissipation by side-2 VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF, Input a 50-MHz 50% duty cycle square wave ISO7741 PD Maximum power dissipation PD1 Maximum power dissipation by side-1 PD2 Maximum power dissipation by side-2 VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF, Input a 50-MHz 50% duty cycle square wave ISO7742 PD Maximum power dissipation PD1 Maximum power dissipation by side-1 PD2 Maximum power dissipation by side-2 VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF, Input a 50-MHz 50% duty cycle square wave Copyright © 2016–2019, Texas Instruments Incorporated Product Folder Links: ISO7740 ISO7741 ISO7742 Submit Documentation Feedback 9 ISO7740, ISO7741, ISO7742 SLLSEP4F – MARCH 2016 – REVISED MAY 2019 www.ti.com 7.6 Insulation Specifications PARAMETER VALUE TEST CONDITIONS DW-16 DBQ-16 UNIT External clearance (1) Shortest terminal-to-terminal distance through air >8 >3.7 mm CPG External creepage (1) Shortest terminal-to-terminal distance across the package surface >8 >3.7 mm DTI Distance through the insulation Minimum internal gap (internal clearance) >21 >21 μm CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112 >600 >600 V Material group According to IEC 60664-1 I I Rated mains voltage ≤ 300 VRMS I-IV I-III Rated mains voltage ≤ 600 VRMS I-IV n/a Rated mains voltage ≤ 1000 VRMS I-III n/a CLR Overvoltage category per IEC 60664-1 DIN V VDE V 0884-11:2017-01 (2) VIORM VIOWM Maximum repetitive peak isolation voltage AC voltage (bipolar) 2121 566 VPK Maximum working isolation voltage AC voltage; Time dependent dielectric breakdown (TDDB) Test; see Figure 28 1500 400 VRMS DC voltage 2121 566 VDC 8000 4242 VPK 8000 4000 VPK Method a, After Input/Output safety test subgroup 2/3, Vini = VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM, tm = 10 s ≤5 ≤5 Method a, After environmental tests subgroup 1, Vini = VIOTM, tini = 60 s; Vpd(m) = 1.6 × VIORM, tm = 10 s ≤5 ≤5 Method b1; At routine test (100% production) and preconditioning (type test) Vini = 1.2 × VIOTM, tini = 1 s; Vpd(m) = 1.875 × VIORM, tm = 1 s ≤5 ≤5 VIOTM Maximum transient isolation voltage VTEST = VIOTM, t = 60 s (qualification); VTEST = 1.2 × VIOTM, t= 1 s (100% production) VIOSM Maximum surge isolation voltage (3) Test method per IEC 62368-1, 1.2/50 µs waveform, VTEST = 1.6 × VIOSM (qualification) Apparent charge (4) qpd Barrier capacitance, input to output (5) CIO VIO = 0.4 × sin (2πft), f = 1 MHz ~1 ~1 VIO = 500 V, TA = 25°C >1012 >1012 VIO = 500 V, 100°C ≤ TA ≤ 125°C >1011 >1011 VIO = 500 V at TS = 150°C >109 >109 Pollution degree 2 2 Climatic category 55/125/21 55/125/21 5000 3000 Isolation resistance (5) RIO pC pF Ω UL 1577 VISO (1) (2) (3) (4) (5) 10 Maximum withstanding isolation voltage VTEST = VISO , t = 60 s (qualification), VTEST = 1.2 × VISO , t = 1 s (100% production) VRMS Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications. This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits. Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier. Apparent charge is electrical discharge caused by a partial discharge (pd). All pins on each side of the barrier tied together creating a two-terminal device. Submit Documentation Feedback Copyright © 2016–2019, Texas Instruments Incorporated Product Folder Links: ISO7740 ISO7741 ISO7742 ISO7740, ISO7741, ISO7742 www.ti.com SLLSEP4F – MARCH 2016 – REVISED MAY 2019 7.7 Safety-Related Certifications VDE CSA UL Certified according to IEC Certified according to DIN 60950-1, IEC 62368-1 and IEC V VDE V 0884-11:2017-01 60601-1 Certified according to UL 1577 Component Recognition Program CQC Certified according to GB 4943.1-2011 Maximum transient isolation voltage, 8000 VPK (DW-16) and 4242 VPK (DBQ-16); Maximum repetitive peak isolation voltage, 2121 VPK (DW-16, Reinforced) and 566 VPK (DBQ-16); Maximum surge isolation voltage, 8000 VPK (DW16) and 4000 VPK (DBQ16) Reinforced insulation per CSA 60950-1-07+A1+A2 and IEC 60950-1 2nd Ed., 800 VRMS (DW-16) and 370 VRMS (DBQ-16) max working voltage (pollution degree 2, material group I); 2 MOPP (Means of Patient Protection) per CSA 60601-1:14 and IEC 60601-1 Ed. 3.1, 250 VRMS (DW-16) max working voltage DW-16: Reinforced Insulation, Altitude ≤ 5000 m, Tropical DW-16: Single protection, 5000 Climate, 700 VRMS maximum VRMS; working voltage; DBQ-16: Single protection, DBQ-16: Basic Insulation, 3000 VRMS Altitude ≤ 5000 m, Tropical Climate, 400 VRMS maximum working voltage Certificate number: 40040142 Master contract number: 220991 File number: E181974 Certificate numbers: CQC15001121716 (DW-16) CQC18001199097 (DBQ-16) TUV Certified according to EN 61010-1:2010 (3rd Ed) and EN 60950-1:2006/A2:2013 5000 VRMS (DW-16) and 3000 VRMS (DBQ-16) Reinforced insulation per EN 61010-1:2010 (3rd Ed) up to working voltage of 600 VRMS (DW-16) and 300 VRMS (DBQ-16) 5000 VRMS (DW-16) and3000 VRMS (DBQ-16) Reinforced insulation per EN 60950-1:2006/A2:2013 up to working voltage of 800 VRMS (DW-16) and 370 VRMS (DBQ-16) Client ID number: 77311 7.8 Safety Limiting Values Safety limiting (1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier potentially leading to secondary system failures. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DW-16 PACKAGE IS Safety input, output, or supply current RθJA = 83.4 °C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C, see Figure 1 273 RθJA = 83.4 °C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C, see Figure 1 416 RθJA = 83.4 °C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C, see Figure 1 545 PS Safety input, output, or total power RθJA = 83.4 °C/W, TJ = 150°C, TA = 25°C, see Figure 3 TS Maximum safety temperature mA 1499 mW 150 °C DBQ-16 PACKAGE IS Safety input, output, or supply current RθJA = 109 °C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C, see Figure 2 209 RθJA = 109 °C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C, see Figure 2 319 RθJA = 109 °C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C, see Figure 2 417 PS Safety input, output, or total power RθJA = 109 °C/W, TJ = 150°C, TA = 25°C, see Figure 4 TS Maximum safety temperature (1) mA 1147 mW 150 °C The maximum safety temperature is the maximum junction temperature specified for the device. The power dissipation and junction-toair thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-toair thermal resistance in the Thermal Information is that of a device installed on a High-K test board for leaded Surface Mount Packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance Copyright © 2016–2019, Texas Instruments Incorporated Product Folder Links: ISO7740 ISO7741 ISO7742 Submit Documentation Feedback 11 ISO7740, ISO7741, ISO7742 SLLSEP4F – MARCH 2016 – REVISED MAY 2019 www.ti.com 7.9 Electrical Characteristics—5-V Supply VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted) PARAMETER TEST CONDITIONS VOH High-level output voltage IOH = –4 mA; see Figure 15 VOL Low-level output voltage IOL = 4 mA; see Figure 15 VCCO (1) MIN TYP – 0.4 4.8 VIT+(IN) Rising input voltage threshold VIT-(IN) Falling input voltage threshold VI(HYS) Input threshold voltage hysteresis (1) IIH High-level input current VIH = VCCI IIL Low-level input current VIL = 0 V at INx or ENx CMTI Common-mode transient immunity VI = VCCI or 0 V, VCM = 1200 V; see Figure 18 CI Input Capacitance (2) VI = VCC/ 2 + 0.4×sin(2πft), f = 1 MHz, VCC = 5 V (1) (2) 12 MAX UNIT V 0.2 0.4 V 0.6 × VCCI 0.7 × VCCI V 0.3 × VCCI 0.4 × VCCI V 0.1 × VCCI 0.2 × VCCI V 10 at INx or ENx –10 85 μA μA 100 2 kV/μs pF VCCI = Input-side VCC; VCCO = Output-side VCC. Measured from input pin to ground. Submit Documentation Feedback Copyright © 2016–2019, Texas Instruments Incorporated Product Folder Links: ISO7740 ISO7741 ISO7742 ISO7740, ISO7741, ISO7742 www.ti.com SLLSEP4F – MARCH 2016 – REVISED MAY 2019 7.10 Supply Current Characteristics—5-V Supply VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted). PARAMETER SUPPLY CURRENT TEST CONDITIONS MIN TYP MAX UNIT ISO7740 EN2 = 0 V; VI = VCC1 (ISO7740); VI = 0 V (ISO7740 with F suffix) ICC1 1.2 1.6 ICC2 0.3 0.5 EN2 = 0 V; VI = 0 V (ISO7740); VI = VCC1 (ISO7740 with F suffix) ICC1 5.5 7.8 ICC2 0.3 0.5 EN2 = VCC2; VI = VCC1 (ISO7740); VI = 0 V (ISO7740 with F suffix) ICC1 1.2 1.6 ICC2 2 3.2 EN2 = VCC2; VI = 0 V (ISO7740); VI = VCC1 (ISO7740 with F suffix) ICC1 5.5 7.8 ICC2 2.2 3.6 ICC1 3.3 4.7 ICC2 2.3 3.6 ICC1 3.4 4.8 ICC2 4.2 5.8 ICC1 3.8 5.7 ICC2 22.7 28 Supply current - Disable Supply current - DC signal 1 Mbps Supply current - AC signal All channels switching with square wave clock input; CL = 15 pF 10 Mbps 100 Mbps mA ISO7741 EN1 = EN2 = 0 V; VI = VCCI (1) (ISO7741); VI = 0 V (ISO7741 with F suffix) ICC1 1 1.5 ICC2 0.8 1.1 EN1 = EN2 = 0 V; VI = 0 V (ISO7741); VI = VCCI (ISO7741 with F suffix) ICC1 4.3 6.3 ICC2 1.8 2.7 EN1 = EN2 = VCCI; VI = VCCI (ISO7741); VI = 0 V (ISO7741 with F suffix) ICC1 1.5 2.3 ICC2 2 3 EN1 = EN2 = VCCI; VI = 0 V (ISO7741); VI = VCCI (ISO7741 with F suffix) ICC1 4.8 6.8 ICC2 3.2 4.9 ICC1 3.2 4.6 ICC2 2.8 4.1 ICC1 3.7 5.2 ICC2 4.2 5.7 ICC1 8.6 11.3 ICC2 18 22 EN1 = EN2 = 0 V; VI = VCCI (ISO7742); VI = 0 V (ISO7742 with F suffix) ICC1, ICC2 0.9 1.3 EN1 = EN2 = 0 V; VI = 0 V (ISO7742); VI = VCCI (ISO7742 with F suffix) ICC1, ICC2 3 4.6 EN1 = EN2 = VCCI; VI = VCCI (ISO7742); VI = 0 V (ISO7742 with F suffix) ICC1, ICC2 1.7 2.7 EN1 = EN2 = VCCI; VI = 0 V (ISO7742); VI = VCCI (ISO7742 with F suffix) ICC1, ICC2 4 5.9 1 Mbps ICC1, ICC2 3 4.4 10 Mbps ICC1, ICC2 4 5.5 100 Mbps ICC1, ICC2 13.4 17 Supply current - Disable Supply current - DC signal 1 Mbps Supply current - AC signal All channels switching with square wave clock input; CL = 15 pF 10 Mbps 100 Mbps mA ISO7742 Supply current - Disable Supply current - DC signal Supply current - AC signal (1) All channels switching with square wave clock input; CL = 15 pF mA VCCI = Input-side VCC Copyright © 2016–2019, Texas Instruments Incorporated Product Folder Links: ISO7740 ISO7741 ISO7742 Submit Documentation Feedback 13 ISO7740, ISO7741, ISO7742 SLLSEP4F – MARCH 2016 – REVISED MAY 2019 www.ti.com 7.11 Electrical Characteristics—3.3-V Supply VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP VCCO (1) – 0.3 3.2 VOH High-level output voltage IOH = –2 mA; see Figure 15 VOL Low-level output voltage IOL = 2 mA; see Figure 15 VIT+(IN) Rising input voltage threshold VIT-(IN) Falling input voltage threshold 0.3 × VCCI 0.4 × VCCI VI(HYS) Input threshold voltage hysteresis 0.1 × VCCI 0.2 × VCCI IIH High-level input current VIH = VCCI (1) at INx or ENx IIL Low-level input current VIL = 0 V at INx or ENx CMTI Common-mode transient immunity VI = VCCI or 0 V, VCM = 1200 V; see Figure 18 (1) 14 MAX V 0.1 0.3 V 0.6 × VCCI 0.7 × VCCI V V V 10 –10 85 UNIT μA μA 100 kV/μs VCCI = Input-side VCC; VCCO = Output-side VCC. Submit Documentation Feedback Copyright © 2016–2019, Texas Instruments Incorporated Product Folder Links: ISO7740 ISO7741 ISO7742 ISO7740, ISO7741, ISO7742 www.ti.com SLLSEP4F – MARCH 2016 – REVISED MAY 2019 7.12 Supply Current Characteristics—3.3-V Supply VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted). PARAMETER SUPPLY CURRENT TEST CONDITIONS MIN TYP MAX UNIT ISO7740 EN2 = 0 V; VI = VCC1 (ISO7740); VI = 0 V (ISO7740 with F suffix) ICC1 1.2 1.6 ICC2 0.3 0.5 EN2 = 0 V; VI = 0 V (ISO7740); VI = VCC1 (ISO7740 with F suffix) ICC1 5.5 7.8 ICC2 0.3 0.5 EN2 = VCC2; VI = VCC1 (ISO7740); VI = 0 V (ISO7740 with F suffix) ICC1 1.2 1.6 ICC2 1.9 3.2 EN2 = VCC2; VI = 0 V (ISO7740); VI = VCC1 (ISO7740 with F suffix) ICC1 5.5 7.8 ICC2 2.2 3.6 ICC1 3.3 4.7 ICC2 2.2 3.6 ICC1 3.4 4.8 ICC2 3.6 5 ICC1 3.3 5.5 ICC2 17 20 Supply current - Disable Supply current - DC signal 1 Mbps Supply current - AC signal All channels switching with square wave clock input; CL = 15 pF 10 Mbps 100 Mbps mA ISO7741 EN1 = EN2 = 0 V; VI = VCCI (1) (ISO7741); VI = 0 V (ISO7741 with F suffix) ICC1 1 1.5 ICC2 0.8 1.1 EN1 = EN2 = 0 V; VI = 0 V (ISO7741); VI = VCCI (ISO7741 with F suffix) ICC1 4.3 6.3 ICC2 1.9 2.7 EN1 = EN2 = VCCI; VI = VCCI (ISO7741); VI = 0 V (ISO7741 with F suffix) ICC1 1.5 2.3 ICC2 2 3 EN1 = EN2 = VCCI; VI = 0 V (ISO7741); VI = VCCI (ISO7741 with F suffix) ICC1 4.8 6.8 ICC2 3.2 4.9 ICC1 3.2 4.6 ICC2 2.7 4.1 ICC1 3.5 5 ICC2 3.7 5.2 Supply current - Disable Supply current - DC signal 1 Mbps Supply current - AC signal All channels switching with square wave clock input; CL = 15 pF 10 Mbps ICC1 6.8 9.3 ICC2 13.7 16.4 EN1 = EN2 = 0 V; VI = VCCI (ISO7742); VI = 0 V (ISO7742 with F suffix) ICC1, ICC2 0.9 1.3 EN1 = EN2 = 0 V; VI = 0 V (ISO7742); VI = VCCI (ISO7742 with F suffix) ICC1, ICC2 3 4.6 EN1 = EN2 = VCCI; VI = VCCI (ISO7742); VI = 0 V (ISO7742 with F suffix) ICC1, ICC2 1.7 2.7 EN1 = EN2 = VCCI; VI = 0 V (ISO7742); VI = VCCI (ISO7742 with F suffix) ICC1, ICC2 4 5.9 1 Mbps ICC1, ICC2 2.9 4.3 10 Mbps ICC1, ICC2 3.6 5.1 100 Mbps ICC1, ICC2 10.3 13 100 Mbps mA ISO7742 Supply current - Disable Supply current - DC signal Supply current - AC signal (1) All channels switching with square wave clock input; CL = 15 pF mA VCCI = Input-side VCC Copyright © 2016–2019, Texas Instruments Incorporated Product Folder Links: ISO7740 ISO7741 ISO7742 Submit Documentation Feedback 15 ISO7740, ISO7741, ISO7742 SLLSEP4F – MARCH 2016 – REVISED MAY 2019 www.ti.com 7.13 Electrical Characteristics—2.5-V Supply VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP VCCO (1) – 0.2 2.45 VOH High-level output voltage IOH = –1 mA; see Figure 15 VOL Low-level output voltage IOL = 1 mA; see Figure 15 VIT+(IN) Rising input voltage threshold VIT-(IN) Falling input voltage threshold 0.3 × VCCI 0.4 × VCCI VI(HYS) Input threshold voltage hysteresis 0.1 × VCCI 0.2 × VCCI IIH High-level input current VIH = VCCI (1) at INx or ENx IIL Low-level input current VIL = 0 V at INx or ENx CMTI Common-mode transient immunity VI = VCCI or 0 V, VCM = 1200 V; see Figure 18 (1) 16 MAX V 0.05 0.2 V 0.6 × VCCI 0.7 × VCCI V V V 10 –10 85 UNIT μA μA 100 kV/μs VCCI = Input-side VCC; VCCO = Output-side VCC. Submit Documentation Feedback Copyright © 2016–2019, Texas Instruments Incorporated Product Folder Links: ISO7740 ISO7741 ISO7742 ISO7740, ISO7741, ISO7742 www.ti.com SLLSEP4F – MARCH 2016 – REVISED MAY 2019 7.14 Supply Current Characteristics—2.5-V Supply VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted). PARAMETER TEST CONDITIONS SUPPLY CURRENT MIN TYP MAX UNIT ISO7740 EN2 = 0 V; VI = VCC1 (ISO7740); VI = 0 V (ISO7740 with F suffix) ICC1 1.2 1.6 ICC2 0.3 0.5 EN2 = 0 V; VI = 0 V (ISO7740); VI = VCC1 (ISO7740 with F suffix) ICC1 5.5 7.8 ICC2 0.3 0.5 EN2 = VCC2; VI = VCC1 (ISO7740); VI = 0 V (ISO7740 with F suffix) ICC1 1.2 1.6 ICC2 1.9 3.2 EN2 = VCC2; VI = 0 V (ISO7740); VI = VCC1 (ISO7740 with F suffix) ICC1 5.4 7.8 ICC2 2.2 3.6 ICC1 3.3 4.7 ICC2 2.2 3.5 ICC1 3.4 4.8 ICC2 3.2 4.7 ICC1 3.2 5.4 ICC2 13 17 Supply current - Disable Supply current - DC signal 1 Mbps Supply current - AC signal All channels switching with square wave clock input; CL = 15 pF 10 Mbps 100 Mbps mA ISO7741 EN1 = EN2 = 0 V; VI = VCCI (1) (ISO7741); VI = 0 V (ISO7741 with F suffix) ICC1 1 1.5 ICC2 0.8 1.1 EN1 = EN2 = 0 V; VI = 0 V (ISO7741); VI = VCCI (ISO7741 with F suffix) ICC1 4.3 6.3 ICC2 1.8 2.7 EN1 = EN2 = VCCI; VI = VCCI (ISO7741); VI = 0 V (ISO7741 with F suffix) ICC1 1.4 2.3 ICC2 2 3 EN1 = EN2 = VCCI; VI = 0 V (ISO7741); VI = VCCI (ISO7741 with F suffix) ICC1 4.7 6.8 ICC2 3.2 4.9 ICC1 3.1 4.6 ICC2 2.7 4 ICC1 3.4 4.9 ICC2 3.5 4.9 ICC1 5.6 8.3 ICC2 10.8 13.8 EN1 = EN2 = 0 V; VI = VCCI (ISO7742); VI = 0 V (ISO7742 with F suffix) ICC1, ICC2 0.9 1.3 EN1 = EN2 = 0 V; VI = 0 V (ISO7742); VI = VCCI (ISO7742 with F suffix) ICC1, ICC2 3 4.6 EN1 = EN2 = VCCI; VI = VCCI (ISO7742); VI = 0 V (ISO7742 with F suffix) ICC1, ICC2 1.7 2.7 EN1 = EN2 = VCCI; VI = 0 V (ISO7742); VI = VCCI (ISO7742 with F suffix) ICC1, ICC2 4 5.9 1 Mbps ICC1, ICC2 2.9 4.3 10 Mbps ICC1, ICC2 3.4 4.9 100 Mbps ICC1, ICC2 8.3 11.5 Supply current - Disable Supply current - DC signal 1 Mbps Supply current - AC signal All channels switching with square wave clock input; CL = 15 pF 10 Mbps 100 Mbps mA ISO7742 Supply current - Disable Supply current - DC signal Supply current - AC signal (1) All channels switching with square wave clock input; CL = 15 pF mA VCCI = Input-side VCC Copyright © 2016–2019, Texas Instruments Incorporated Product Folder Links: ISO7740 ISO7741 ISO7742 Submit Documentation Feedback 17 ISO7740, ISO7741, ISO7742 SLLSEP4F – MARCH 2016 – REVISED MAY 2019 www.ti.com 7.15 Switching Characteristics—5-V Supply VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 6 10.7 16 ns 0 4.9 ns 4 ns 4.4 ns 2.4 3.9 ns 2.4 3.9 ns Disable propagation delay, high-to-high impedance output 9 20 ns Disable propagation delay, low-to-high impedance output 9 20 ns Enable propagation delay, high impedance-to-high output for ISO774x 7 20 ns 3 8.5 μs Enable propagation delay, high impedance-to-low output for ISO774x 3 8.5 μs Enable propagation delay, high impedance-to-low output for ISO774x with F suffix 7 20 ns 0.1 0.3 μs tPLH, tPHL Propagation delay time PWD Pulse width distortion (1) |tPHL – tPLH| tsk(o) Channel-to-channel output skew time (2) tsk(pp) Part-to-part skew time (3) tr Output signal rise time tf Output signal fall time tPHZ tPLZ tPZH tDO See Figure 15 See Figure 16 Measured from the time VCC goes below 1.7 V. See Figure 18 Default output delay time from input power loss tie (3) Same-direction channels Enable propagation delay, high impedance-to-high output for ISO774x with F suffix tPZL (1) (2) See Figure 15 16 Time interval error 2 0.8 – 1 PRBS data at 100 Mbps UNIT ns Also known as pulse skew. tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads. tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads. 7.16 Switching Characteristics—3.3-V Supply VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 6 11 16 ns 0.1 5 ns 4.1 ns 4.5 ns 1.3 3 ns 1.3 3 ns Disable propagation delay, high-to-high impedance output 17 30 ns Disable propagation delay, low-to-high impedance output 17 30 ns Enable propagation delay, high impedance-to-high output for ISO774x 17 30 ns 3.2 8.5 μs Enable propagation delay, high impedance-to-low output for ISO774x 3.2 8.5 μs Enable propagation delay, high impedance-to-low output for ISO774x with F suffix 17 30 ns 0.1 0.3 μs tPLH, tPHL Propagation delay time PWD Pulse width distortion (1) |tPHL – tPLH| tsk(o) Channel-to-channel output skew time (2) tsk(pp) Part-to-part skew time (3) tr Output signal rise time tf Output signal fall time tPHZ tPLZ tPZH tPZL tDO tie (1) (2) (3) 18 Same-direction channels See Figure 15 Enable propagation delay, high impedance-to-high output for ISO774x with F suffix Default output delay time from input power loss Time interval error See Figure 15 See Figure 16 Measured from the time VCC goes below 1.7 V. See Figure 18 16 2 – 1 PRBS data at 100 Mbps 0.9 UNIT ns Also known as pulse skew. tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads. tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads. Submit Documentation Feedback Copyright © 2016–2019, Texas Instruments Incorporated Product Folder Links: ISO7740 ISO7741 ISO7742 ISO7740, ISO7741, ISO7742 www.ti.com SLLSEP4F – MARCH 2016 – REVISED MAY 2019 7.17 Switching Characteristics—2.5-V Supply VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted) PARAMETER TEST CONDITIONS tPLH, tPHL Propagation delay time PWD Pulse width distortion (1) |tPHL – tPLH| tsk(o) Channel-to-channel output skew time (2) tsk(pp) Part-to-part skew time (3) tr Output signal rise time tf Output signal fall time tPHZ tPLZ tPZH tPZL tDO tie (1) (2) (3) MIN TYP MAX UNIT 12 18.5 ns 0.2 5.1 ns 4.1 ns 4.6 ns 1 3.5 ns 1 3.5 ns Disable propagation delay, high-to-high impedance output 22 40 ns Disable propagation delay, low-to-high impedance output 22 40 ns Enable propagation delay, high impedance-to-high output for ISO774x 18 40 ns 3.3 8.5 μs Enable propagation delay, high impedance-to-low output for ISO774x 3.3 8.5 μs Enable propagation delay, high impedance-to-low output for ISO774x with F suffix 18 40 ns 0.1 0.3 μs See Figure 15 Same-direction Channels See Figure 15 Enable propagation delay, high impedance-to-high output for ISO774x with F suffix Default output delay time from input power loss See Figure 16 Measured from the time VCC goes below 1.7 V. See Figure 18 16 Time interval error 7.5 2 – 1 PRBS data at 100 Mbps 0.7 ns Also known as pulse skew. tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads. tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads. Copyright © 2016–2019, Texas Instruments Incorporated Product Folder Links: ISO7740 ISO7741 ISO7742 Submit Documentation Feedback 19 ISO7740, ISO7741, ISO7742 SLLSEP4F – MARCH 2016 – REVISED MAY 2019 www.ti.com 7.18 Insulation Characteristics Curves 450 VCC1 = VCC2 = 2.75 V VCC1 = VCC2 = 3.6 V VCC1 = VCC2 = 5.5 V 500 VCC1 = VCC2 = 2.75 V VCC1 = VCC2 = 3.6 V VCC1 = VCC2 = 5.5 V 400 Safety Limiting Current (mA) Safety Limiting Current (mA) 600 400 300 200 100 350 300 250 200 150 100 50 0 0 0 50 100 150 Ambient Temperature (qC) 0 200 1600 1400 1400 1200 1200 1000 800 600 400 100 150 Ambient Temperature (qC) 200 D002 Figure 2. Thermal Derating Curve for Safety Limiting Current for DBQ-16 Package Safety Limiting Power (mW) Safety Limiting Power (mW) Figure 1. Thermal Derating Curve for Safety Limiting Current for DW-16 Package 1000 800 600 400 200 200 0 0 0 50 100 150 Ambient Temperature (qC) 200 Submit Documentation Feedback 0 50 D003 Figure 3. Thermal Derating Curve for Safety Limiting Power for DW-16 Package 20 50 D001 100 150 Ambient Temperature (qC) 200 D004 Figure 4. Thermal Derating Curve for Safety Limiting Power for DBQ-16 Package Copyright © 2016–2019, Texas Instruments Incorporated Product Folder Links: ISO7740 ISO7741 ISO7742 ISO7740, ISO7741, ISO7742 www.ti.com SLLSEP4F – MARCH 2016 – REVISED MAY 2019 7.19 Typical Characteristics 9 25 ICC1 at 2.5 V ICC2 at 2.5 V ICC1 at 3.3 V ICC2 at 3.3 V ICC1 at 5 V ICC2 at 5 V 15 7 Supply Current (mA) Supply Current (mA) 20 ICC1 at 2.5 V ICC2 at 2.5 V ICC1 at 3.3 V ICC2 at 3.3 V ICC1 at 5 V ICC2 at 5 V 8 10 6 5 4 3 2 5 1 0 0 0 25 TA = 25°C 50 Data Rate (Mbps) 75 0 100 CL = 15 pF TA = 25°C Figure 5. ISO7740 Supply Current vs Data Rate (With 15-pF Load) 75 100 D006 CL = No Load 9 ICC1 at 2.5 V ICC2 at 2.5 V ICC1 at 3.3 V ICC2 at 3.3 V ICC1 at 5 V ICC2 at 5 V 16 14 12 ICC1 at 2.5 V ICC2 at 2.5 V ICC1 at 3.3 V ICC2 at 3.3 V ICC1 at 5 V ICC2 at 5 V 8 7 Supply Current (mA) 18 Supply Current (mA) 50 Data Rate (Mbps) Figure 6. ISO7740 Supply Current vs Data Rate (With No Load) 20 10 8 6 6 5 4 3 4 2 2 1 0 0 0 25 TA = 25°C 50 Data Rate (Mbps) 75 100 0 25 D007 CL = 15 pF TA = 25°C Figure 7. ISO7741 Supply Current vs Data Rate (With 15-pF Load) 50 Data Rate (Mbps) 75 100 D008 CL = No Load Figure 8. ISO7741 Supply Current vs Data Rate (With No Load) 8 16 ICC1 at 2.5 V ICC2 at 2.5 V ICC1 at 3.3 V ICC2 at 3.3 V ICC1 at 5 V ICC2 at 5 V 12 10 ICC1 at 2.5 V ICC2 at 2.5 V ICC1 at 3.3 V ICC2 at 3.3 V ICC1 at 5 V ICC2 at 5 V 7 Supply Current (mA) 14 Supply Current (mA) 25 D005 8 6 4 6 5 4 3 2 1 2 0 0 0 25 TA = 25°C 50 Data Rate (Mbps) 75 100 0 25 D009 CL = 15 pF Figure 9. ISO7742 Supply Current vs Data Rate (With 15-pF Load) TA = 25°C 50 Data Rate (Mbps) 75 100 D010 CL = No Load Figure 10. ISO7742 Supply Current vs Data Rate (With No Load) Copyright © 2016–2019, Texas Instruments Incorporated Product Folder Links: ISO7740 ISO7741 ISO7742 Submit Documentation Feedback 21 ISO7740, ISO7741, ISO7742 SLLSEP4F – MARCH 2016 – REVISED MAY 2019 www.ti.com Typical Characteristics (continued) 6 0.9 Low-Level Output Voltage (V) High-Level Output Voltage (V) 0.8 5 4 3 2 VCC at 2.5 V VCC at 3.3 V VCC at 5 V 1 0 -15 0.7 0.6 0.5 0.4 0.3 0.2 VCC at 2.5 V VCC at 3.3 V VCC at 5 V 0.1 0 -10 -5 High-Level Output Current (mA) 0 0 15 D012 TA = 25°C Figure 11. High-Level Output Voltage vs High-level Output Current Figure 12. Low-Level Output Voltage vs Low-Level Output Current 2.10 14 2.05 Propagation Delay Time (ns) Power Supply UVLO Threshold (V) TA = 25°C 2.00 1.95 1.90 1.85 1.80 VCC1 Rising VCC2 Rising VCC1 Falling VCC2 Falling 1.75 1.70 1.65 -55 -5 45 Free-Air Temperature (qC) 95 125 Submit Documentation Feedback 13 12 11 10 tPHL at 2.5 V tPLH at 2.5 V tPHL at 3.3 V 9 8 -55 -25 D013 Figure 13. Power Supply Undervoltage Threshold vs FreeAir Temperature 22 5 10 Low-Level Output Current (mA) D011 5 35 65 Free-Air Temperature (qC) tPLH at 3.3 V tPHL at 5 V tPLH at 5 V 95 125 D014 Figure 14. Propagation Delay Time vs Free-Air Temperature Copyright © 2016–2019, Texas Instruments Incorporated Product Folder Links: ISO7740 ISO7741 ISO7742 ISO7740, ISO7741, ISO7742 www.ti.com SLLSEP4F – MARCH 2016 – REVISED MAY 2019 8 Parameter Measurement Information Isolation Barrier IN Input Generator (See Note A) VI VCCI VI OUT 50% 50% 0V tPLH CL See Note B VO 50 tPHL VO VOH 90% 50% 50% 10% VOL tf tr Copyright © 2016, Texas Instruments Incorporated A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3ns, ZO = 50 Ω. At the input, 50 Ω resistor is required to terminate Input Generator signal. It is not needed in actual application. B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 15. Switching Characteristics Test Circuit and Voltage Waveforms VCCO VCC Isolation Barrier IN 0V VO VI tPZL 0V tPLZ VOH EN 0.5 V VO 50% VOL 50 OUT VCC VO VCC / 2 VCC / 2 VI 0V tPZH EN CL See Note B VI VCC / 2 VCC / 2 VI CL See Note B IN Input Generator (See Note A) ±1% OUT Isolation Barrier Input Generator (See Note A) 3V RL = 1 k RL = 1 k ±1% VOH 50% VO 0.5 V tPHZ 50 0V Copyright © 2016, Texas Instruments Incorporated A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 10 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω. B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 16. Enable/Disable Propagation Delay Time Test Circuit and Waveform Copyright © 2016–2019, Texas Instruments Incorporated Product Folder Links: ISO7740 ISO7741 ISO7742 Submit Documentation Feedback 23 ISO7740, ISO7741, ISO7742 SLLSEP4F – MARCH 2016 – REVISED MAY 2019 www.ti.com Parameter Measurement Information (continued) VI See Note B VCC VCC Isolation Barrier IN = 0 V (Devices without suffix F) IN = VCC (Devices with suffix F) VI IN 1.7 V 0V OUT VO tDO CL See Note A default high VOH 50% VO VOL default low A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. B. Power Supply Ramp Rate = 10 mV/ns Figure 17. Default Output Delay Time Test Circuit and Voltage Waveforms VCCI VCCO C = 0.1 µF ±1% S1 Isolation Barrier C = 0.1 µF ±1% IN Pass-fail criteria: The output must remain stable. OUT + CL See Note A VOH or VOL ± GNDI A. + VCM ± GNDO CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 18. Common-Mode Transient Immunity Test Circuit 24 Submit Documentation Feedback Copyright © 2016–2019, Texas Instruments Incorporated Product Folder Links: ISO7740 ISO7741 ISO7742 ISO7740, ISO7741, ISO7742 www.ti.com SLLSEP4F – MARCH 2016 – REVISED MAY 2019 9 Detailed Description 9.1 Overview The ISO774x family of devices an ON-OFF keying (OOK) modulation scheme to transmit the digital data across a silicon dioxide based isolation barrier. The transmitter sends a high frequency carrier across the barrier to represent one digital state and sends no signal to represent the other digital state. The receiver demodulates the signal after advanced signal conditioning and produces the output through a buffer stage. If the ENx pin is low then the output goes to high impedance. The ISO774x devices also incorporate advanced circuit techniques to maximize the CMTI performance and minimize the radiated emissions due to the high frequency carrier and IO buffer switching. The conceptual block diagram of a digital capacitive isolator, Figure 19, shows a functional block diagram of a typical channel. 9.2 Functional Block Diagram Transmitter Receiver EN TX IN OOK Modulation TX Signal Conditioning Oscillator SiO2 based Capacitive Isolation Barrier RX Signal Conditioning Envelope Detection RX OUT Emissions Reduction Techniques Copyright © 2016, Texas Instruments Incorporated Figure 19. Conceptual Block Diagram of a Digital Capacitive Isolator Figure 20 shows a conceptual detail of how the ON-OFF keying scheme works. TX IN Carrier signal through isolation barrier RX OUT Figure 20. On-Off Keying (OOK) Based Modulation Scheme Copyright © 2016–2019, Texas Instruments Incorporated Product Folder Links: ISO7740 ISO7741 ISO7742 Submit Documentation Feedback 25 ISO7740, ISO7741, ISO7742 SLLSEP4F – MARCH 2016 – REVISED MAY 2019 www.ti.com 9.3 Feature Description Table 1 provides an overview of the device features. Table 1. Device Features PART NUMBER CHANNEL DIRECTION MAXIMUM DATA RATE DEFAULT OUTPUT ISO7740 4 Forward, 0 Reverse 100 Mbps High ISO7740 with F suffix 4 Forward, 0 Reverse 100 Mbps Low ISO7741 3 Forward, 1 Reverse 100 Mbps High ISO7741 with F suffix 3 Forward, 1 Reverse ISO7742 2 Forward, 2 Reverse ISO7742 with F suffix (1) 2 Forward, 2 Reverse 100 Mbps 100 Mbps 100 Mbps Low High Low PACKAGE RATED ISOLATION (1) DW-16 5000 VRMS / 8000 VPK DBQ-16 3000 VRMS / 4242 VPK DW-16 5000 VRMS / 8000 VPK DBQ-16 3000 VRMS / 4242 VPK DW-16 5000 VRMS / 8000 VPK DBQ-16 3000 VRMS / 4242 VPK DW-16 5000 VRMS / 8000 VPK DBQ-16 3000 VRMS / 4242 VPK DW-16 5000 VRMS / 8000 VPK DBQ-16 3000 VRMS / 4242 VPK DW-16 5000 VRMS / 8000 VPK DBQ-16 3000 VRMS / 4242 VPK See Safety-Related Certifications for detailed isolation ratings. 9.3.1 Electromagnetic Compatibility (EMC) Considerations Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge (ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level performance and reliability depends, to a large extent, on the application board design and layout, the ISO774x family of devices incorporates many chip-level design improvements for overall system robustness. Some of these improvements include: • Robust ESD protection cells for input and output signal pins and inter-chip bond pads. • Low-resistance connectivity of ESD cells to supply and ground pins. • Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events. • Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance path. • PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic SCRs. • Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation. 26 Submit Documentation Feedback Copyright © 2016–2019, Texas Instruments Incorporated Product Folder Links: ISO7740 ISO7741 ISO7742 ISO7740, ISO7741, ISO7742 www.ti.com SLLSEP4F – MARCH 2016 – REVISED MAY 2019 9.4 Device Functional Modes Table 2 lists the functional modes for the ISO774x devices. Table 2. Function Table (1) VCCI PU X (1) (2) (3) VCCO INPUT (INx) (2) OUTPUT ENABLE (ENx) OUTPUT (OUTx) H H or open H L H or open L Open H or open Default X L Z PU PU PD PU X H or open Default X PD X X Undetermined COMMENTS Normal Operation: A channel output assumes the logic state of its input. Default mode: When INx is open, the corresponding channel output goes to its default logic state. Default is High for ISO774x and Low for ISO774x with F suffix. A low value of output enable causes the outputs to be highimpedance. Default mode: When VCCI is unpowered, a channel output assumes the logic state based on the selected default option. Default is High for ISO774x and Low for ISO774x with F suffix. When VCCI transitions from unpowered to powered-up, a channel output assumes the logic state of the input. When VCCI transitions from powered-up to unpowered, channel output assumes the selected default state. When VCCO is unpowered, a channel output is undetermined (3). When VCCO transitions from unpowered to powered-up, a channel output assumes the logic state of the input. VCCI = Input-side VCC; VCCO = Output-side VCC; PU = Powered up (VCC ≥ 2.25 V); PD = Powered down (VCC ≤ 1.7 V); X = Irrelevant; H = High level; L = Low level ; Z = High Impedance A strongly driven input signal can weakly power the floating VCC through an internal protection diode and cause undetermined output. The outputs are in undetermined state when 1.7 V < VCCI, VCCO < 2.25 V. Copyright © 2016–2019, Texas Instruments Incorporated Product Folder Links: ISO7740 ISO7741 ISO7742 Submit Documentation Feedback 27 ISO7740, ISO7741, ISO7742 SLLSEP4F – MARCH 2016 – REVISED MAY 2019 www.ti.com 9.4.1 Device I/O Schematics Input (ISO774x) VCCI VCCI Input (ISO774xF) VCCI VCCI VCCI VCCI VCCI 1.5 MW 985 W 985 W INx INx 1.5 MW Enable Output VCCO VCCO VCCO VCCO VCCO 2 MW ~20 W OUTx 1970 W ENx Copyright © 2016, Texas Instruments Incorporated Figure 21. Device I/O Schematics 28 Submit Documentation Feedback Copyright © 2016–2019, Texas Instruments Incorporated Product Folder Links: ISO7740 ISO7741 ISO7742 ISO7740, ISO7741, ISO7742 www.ti.com SLLSEP4F – MARCH 2016 – REVISED MAY 2019 10 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 10.1 Application Information The ISO774x devices are high-performance, quad-channel digital isolators. These devices come with enable pins on each side which can be used to put the respective outputs in high impedance for multi master driving applications and reduce power consumption. The ISO774x devices use single-ended CMOS-logic switching technology. The voltage range is from 2.25 V to 5.5 V for both supplies, VCC1 and VCC2. When designing with digital isolators, keep in mind that because of the single-ended design structure, digital isolators do not conform to any specific interface standard and are only intended for isolating single-ended CMOS or TTL digital signal lines. The isolator is typically placed between the data controller (that is, μC or UART), and a data converter or a line transceiver, regardless of the interface type or standard. 10.2 Typical Application Figure 22 shows the isolated serial peripheral interface (SPI). VS 3.3 V 0.1 F 2 Vcc D2 3 1:1.33 MBR0520L 4 SN6501 GND D1 10 F 0.1 F 3 1 OUT 1 3.3 VISO TLV70733 EN GND 10 F 2 2 10 F 4,5 IN MBR0520L 1 F VIN VOUT 6 22 F REF5025 4 GND ISO-BARRIER 0.1 F 0.1 F 0.1 F 0.1 F 1 4.7 k 2 DVcc 7 6 P1.4 XOUT MSP430 SCLK 7 G2132 8 6 (14-PW) SDO XIN 9 SDI DVss 5 4 3 Vcc1 EN1 16 Vcc2 EN2 4.7 k 14 OUTA ISO7741 13 OUTB 5 12 INC OUTC 6 11 OUTD IND 4 INA INB GND1 2,8 3 10 GND2 23 24 25 26 2 28 32 31 AINP MXO VBD VA REFP 20 CS CH0 SCLK ADS7953 SDI SDO CH15 BDGND AGND REFM 27 9,15 1,22 5 16 Analog Inputs 30 Copyright © 2016, Texas Instruments Incorporated Figure 22. Isolated SPI for an Analog Input Module With 16 Input Copyright © 2016–2019, Texas Instruments Incorporated Product Folder Links: ISO7740 ISO7741 ISO7742 Submit Documentation Feedback 29 ISO7740, ISO7741, ISO7742 SLLSEP4F – MARCH 2016 – REVISED MAY 2019 www.ti.com Typical Application (continued) 10.2.1 Design Requirements To design with these devices, use the parameters listed in Table 3. Table 3. Design Parameters PARAMETER VALUE Supply voltage, VCC1 and VCC2 2.25 to 5.5 V Decoupling capacitor between VCC1 and GND1 0.1 µF Decoupling capacitor from VCC2 and GND2 0.1 µF 10.2.2 Detailed Design Procedure Unlike optocouplers, which require external components to improve performance, provide bias, or limit current, the ISO774x family of devices only require two external bypass capacitors to operate. 2 mm maximum from VCC2 2 mm maximum from VCC1 0.1 µF 0.1 µF VCC2 VCC1 1 16 2 15 INA 3 14 OUTA INB 4 13 OUTB INC 5 12 OUTC OUTD 6 11 IND 7 10 8 9 GND1 GND2 EN2 EN1 GND2 GND1 Figure 23. Typical ISO774x Circuit Hook-up 30 Submit Documentation Feedback Copyright © 2016–2019, Texas Instruments Incorporated Product Folder Links: ISO7740 ISO7741 ISO7742 ISO7740, ISO7741, ISO7742 www.ti.com SLLSEP4F – MARCH 2016 – REVISED MAY 2019 10.2.3 Application Curve Ch4 = 1 V / div Ch4 = 1 V / div The following typical eye diagrams of the ISO774x family of devices indicates low jitter and wide open eye at the maximum data rate of 100 Mbps. Time = 2.5 ns / div Time = 2.5 ns / div Figure 25. Eye Diagram at 100 Mbps PRBS 216 – 1, 3.3 V and 25°C Ch4 = 500 mV / div Figure 24. Eye Diagram at 100 Mbps PRBS 216 – 1, 5 V and 25°C Time = 2.5 ns / div Figure 26. Eye Diagram at 100 Mbps PRBS 216 – 1, 2.5 V and 25°C 10.2.3.1 Insulation Lifetime Insulation lifetime projection data is collected by using industry-standard Time Dependent Dielectric Breakdown (TDDB) test method. In this test, all pins on each side of the barrier are tied together creating a two-terminal device and high voltage applied between the two sides; See Figure 27 for TDDB test setup. The insulation breakdown data is collected at various high voltages switching at 60 Hz over temperature. For reinforced insulation, VDE standard requires the use of TDDB projection line with failure rate of less than 1 part per million (ppm). Even though the expected minimum insulation lifetime is 20 years at the specified working isolation voltage, VDE reinforced certification requires additional safety margin of 20% for working voltage and 87.5% for lifetime which translates into minimum required insulation lifetime of 37.5 years at a working voltage that's 20% higher than the specified value. Figure 28 shows the intrinsic capability of the isolation barrier to withstand high voltage stress over its lifetime. Based on the TDDB data, the intrinsic capability of the insulation is 1500 VRMS with a lifetime of 135 years. Other factors, such as package size, pollution degree, material group, etc. can further limit the working voltage of the component. The working voltage of DW-16 package is specified upto 1500 VRMS and DBQ-16 package up to 400 VRMS. At the lower working voltages, the corresponding insulation lifetime is much longer than 135 years. Copyright © 2016–2019, Texas Instruments Incorporated Product Folder Links: ISO7740 ISO7741 ISO7742 Submit Documentation Feedback 31 ISO7740, ISO7741, ISO7742 SLLSEP4F – MARCH 2016 – REVISED MAY 2019 www.ti.com A Vcc 1 Vcc 2 Time Counter > 1 mA DUT GND 1 GND 2 VS Oven at 150 °C Figure 27. Test Setup for Insulation Lifetime Measurement Figure 28. Insulation Lifetime Projection Data 11 Power Supply Recommendations To help ensure reliable operation at data rates and supply voltages, a 0.1-μF bypass capacitor is recommended at the input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins as possible. If only a single primary-side power supply is available in an application, isolated power can be generated for the secondary-side with the help of a transformer driver such as Texas Instruments' SN6501 or SN6505A. For such applications, detailed power supply design and transformer selection recommendations are available in SN6501 Transformer Driver for Isolated Power Supplies data sheet or SN6505A Low-Noise 1-A Transformer Drivers for Isolated Power Supplies data sheet. 32 Submit Documentation Feedback Copyright © 2016–2019, Texas Instruments Incorporated Product Folder Links: ISO7740 ISO7741 ISO7742 ISO7740, ISO7741, ISO7742 www.ti.com SLLSEP4F – MARCH 2016 – REVISED MAY 2019 12 Layout 12.1 Layout Guidelines A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 29). Layer stacking should be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency signal layer. • Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits of the data link. • Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for transmission line interconnects and provides an excellent low-inductance path for the return current flow. • Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of approximately 100 pF/inch2. • Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links usually have margin to tolerate discontinuities such as vias. If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the power and ground plane of each power system can be placed closer together, thus increasing the high-frequency bypass capacitance significantly. For detailed layout recommendations, refer to the Digital Isolator Design Guide. 12.1.1 PCB Material For digital circuit boards operating below 150 Mbps, (or rise and fall times higher than 1 ns), and trace lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit boards. This PCB is preferred over cheaper alternatives due to its lower dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and self-extinguishing flammability-characteristics. 12.2 Layout Example High-speed traces 10 mils Ground plane 40 mils Keep this space free from planes, traces, pads, and vias FR-4 0r ~ 4.5 Power plane 10 mils Low-speed traces Figure 29. Layout Example Schematic Copyright © 2016–2019, Texas Instruments Incorporated Product Folder Links: ISO7740 ISO7741 ISO7742 Submit Documentation Feedback 33 ISO7740, ISO7741, ISO7742 SLLSEP4F – MARCH 2016 – REVISED MAY 2019 www.ti.com 13 Device and Documentation Support 13.1 Documentation Support 13.1.1 Related Documentation For related documentation, see the following: • Texas Instruments, ADS79xx 12/10/8-Bit, 1 MSPS, 16/12/8/4-Channel, Single-Ended, MicroPower, Serial Interface ADCs data sheet • Texas Instruments, Digital Isolator Design Guide • Texas Instruments, Isolation Glossary • Texas Instruments, How to use isolation to improve ESD, EFT, and Surge immunity in industrial systems application report • Texas Instruments, MSP430G2132 Mixed Signal Microcontroller data sheet • Texas Instruments, REF50xx Low-Noise, Very Low Drift, Precision Voltage Reference data sheet • Texas Instruments, SN6501 Transformer Driver for Isolated Power Supplies data sheet • Texas Instruments, SN6505A Low-Noise 1-A Transformer Drivers for Isolated Power Supplies data sheet • Texas Instruments, TLV707, TLV707P 200-mA, Low-IQ, Low-Noise, Low-Dropout Regulator for Portable Devices data sheet 13.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 4. Related Links PARTS PRODUCT FOLDER ORDER NOW TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY ISO7740 Click here Click here Click here Click here Click here ISO7741 Click here Click here Click here Click here Click here ISO7742 Click here Click here Click here Click here Click here 13.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 13.4 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 13.5 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 34 Submit Documentation Feedback Copyright © 2016–2019, Texas Instruments Incorporated Product Folder Links: ISO7740 ISO7741 ISO7742 ISO7740, ISO7741, ISO7742 www.ti.com SLLSEP4F – MARCH 2016 – REVISED MAY 2019 13.6 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 13.7 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 2016–2019, Texas Instruments Incorporated Product Folder Links: ISO7740 ISO7741 ISO7742 Submit Documentation Feedback 35 PACKAGE OPTION ADDENDUM www.ti.com 26-Feb-2019 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) ISO7740DBQ ACTIVE SSOP DBQ 16 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -55 to 125 7740 ISO7740DBQR ACTIVE SSOP DBQ 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -55 to 125 7740 ISO7740DW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -55 to 125 ISO7740 ISO7740DWR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -55 to 125 ISO7740 ISO7740FDBQ ACTIVE SSOP DBQ 16 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -55 to 125 7740F ISO7740FDBQR ACTIVE SSOP DBQ 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -55 to 125 7740F ISO7740FDW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -55 to 125 ISO7740F ISO7740FDWR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -55 to 125 ISO7740F ISO7741DBQ ACTIVE SSOP DBQ 16 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -55 to 125 7741 ISO7741DBQR ACTIVE SSOP DBQ 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -55 to 125 7741 ISO7741DW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -55 to 125 ISO7741 ISO7741DWR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -55 to 125 ISO7741 ISO7741FDBQ ACTIVE SSOP DBQ 16 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -55 to 125 7741F ISO7741FDBQR ACTIVE SSOP DBQ 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -55 to 125 7741F ISO7741FDW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -55 to 125 ISO7741F ISO7741FDWR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -55 to 125 ISO7741F ISO7742DBQ ACTIVE SSOP DBQ 16 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -55 to 125 7742 Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 26-Feb-2019 Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) ISO7742DBQR ACTIVE SSOP DBQ 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -55 to 125 7742 ISO7742DW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -55 to 125 ISO7742 ISO7742DWR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -55 to 125 ISO7742 ISO7742FDBQ ACTIVE SSOP DBQ 16 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -55 to 125 7742F ISO7742FDBQR ACTIVE SSOP DBQ 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -55 to 125 7742F ISO7742FDW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -55 to 125 ISO7742F ISO7742FDWR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -55 to 125 ISO7742F (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of