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ISO7740-Q1, ISO7741-Q1, ISO7742-Q1
SLLSEU0C – NOVEMBER 2016 – REVISED FEBRUARY 2020
ISO774x-Q1 Automotive, High-Speed, Reinforced Quad-Channel Digital Isolators
1 Features
2 Applications
•
•
•
1
•
•
•
•
•
•
•
•
•
•
Qualified for automotive applications
AEC-Q100 qualified with the following results:
– Device temperature Grade 1: –40°C to 125°C
ambient operating temperature
100 Mbps data rate
Robust isolation barrier:
– >100-year projected lifetime at 1500 VRMS
working voltage
– Up to 5700 VRMS isolation rating
– Up to 12.8 kV surge capability
– ±100 kV/μs typical CMTI
Wide supply range: 2.25 V to 5.5 V
2.25-V to 5.5-V level translation
Default output high (ISO774x) and low
(ISO774xF) options
Low power consumption, typical 1.5 mA per
channel at 1 Mbps
Low propagation delay: 10.7 ns typical
(5-V Supplies)
Robust electromagnetic compatibility (EMC)
– System-level ESD, EFT, and surge immunity
– ±8 kV IEC 61000-4-2 contact discharge
protection across isolation barrier
– Low emissions
Extra-wide SOIC (DWW-16), wide-SOIC (DW-16)
and QSOP (DBQ-16) package options
Safety-related certifications:
– DIN VDE V 0884-11:2017-01
– UL 1577 component recognition program
– CSA certification according to IEC 60950-1,
IEC 62368-1, IEC 61010-1 and IEC 60601-1
end equipment standards
– CQC approval per GB4943.1-2011
– TUV certification according to EN 60950-1, EN
62368-1 and EN 61010-1
Hybrid, electric and powertrain system (EV/HEV)
– Battery management system (BMS)
– On-board charger
– Traction inverter
– DC/DC converter
– Inverter and motor control
3 Description
The ISO774x-Q1 automotive devices are highperformance, quad-channel digital isolators with 5700
VRMS (DWW package), 5000 VRMS (DW package) and
3000 VRMS (DBQ package) isolation ratings per UL
1577. This family of devices has reinforced insulation
ratings according to VDE, CSA, TUV and CQC.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
ISO7741-Q1
SOIC (DWW)
10.30 mm × 14.0 mm
ISO7740-Q1
ISO7741-Q1
ISO7742-Q1
SOIC (DW)
10.30 mm × 7.50 mm
SSOP (DBQ)
4.90 mm × 3.90 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
VCCO
VCCI
Series Isolation
Capacitors
INx
OUTx
ENx
GNDI
GNDO
Copyright © 2016, Texas Instruments Incorporated
VCCI=Input supply, VCCO=Output supply
GNDI=Input ground, GNDO=Output ground
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ISO7740-Q1, ISO7741-Q1, ISO7742-Q1
SLLSEU0C – NOVEMBER 2016 – REVISED FEBRUARY 2020
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description Continued ..........................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
7.14
7.15
7.16
7.17
1
1
1
2
4
5
7
Absolute Maximum Ratings ...................................... 7
ESD Ratings ............................................................ 7
Recommended Operating Conditions....................... 7
Thermal Information .................................................. 8
Power Rating............................................................. 8
Insulation Specifications............................................ 9
Safety-Related Certifications................................... 10
Safety Limiting Values ............................................ 10
Electrical Characteristics—5-V Supply ................... 11
Supply Current Characteristics—5-V Supply ........ 12
Electrical Characteristics—3.3-V Supply .............. 13
Supply Current Characteristics—3.3-V Supply ..... 14
Electrical Characteristics—2.5-V Supply .............. 15
Supply Current Characteristics—2.5-V Supply ..... 16
Switching Characteristics—5-V Supply................. 17
Switching Characteristics—3.3-V Supply.............. 17
Switching Characteristics—2.5-V Supply.............. 18
7.18 Insulation Characteristics Curves ......................... 19
7.19 Typical Characteristics .......................................... 20
8
9
Parameter Measurement Information ................ 22
Detailed Description ............................................ 24
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
24
24
25
26
10 Application and Implementation........................ 28
10.1 Application Information.......................................... 28
10.2 Typical Application ................................................ 28
11 Power Supply Recommendations ..................... 31
12 Layout................................................................... 32
12.1 Layout Guidelines ................................................. 32
12.2 Layout Example .................................................... 32
13 Device and Documentation Support ................. 33
13.1
13.2
13.3
13.4
13.5
13.6
13.7
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
33
33
33
33
33
33
33
14 Mechanical, Packaging, and Orderable
Information ........................................................... 34
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (June 2018) to Revision C
Page
•
Made editorial and cosmetic changes throughout the document .......................................................................................... 1
•
Changed From: "Isolation Barrier Life: >40 Years" To: " >100-year projected lifetime at 1500 VRMS working voltage"
in Features ............................................................................................................................................................................. 1
•
Added "Up to 5700 VRMS isolation rating" in Features ........................................................................................................... 1
•
Added "Up to 12.8 kV surge capability" in Features ............................................................................................................. 1
•
Added "±8 kV IEC 61000-4-2 contact discharge protection across isolation barrier" in Features ........................................ 1
•
Changed VDE standard name From: DIN V VDE V 0884-11:2017-01 To: DIN VDE V 0884-11:2017-01 throughout
the document ......................................................................................................................................................................... 1
•
Updated list of applications in Applications section................................................................................................................ 1
•
Updated Simplified Schematic to show two isolation capacitors in series per channel instead of a single isolation
capacitor ................................................................................................................................................................................ 1
•
Added extra-wide SOIC (DWW-16) package information for ISO7741-Q1 in the datasheet ................................................ 4
•
Added "Contact discharge per IEC 61000-4-2" specification of ±8000 V in ESD Ratings .................................................... 7
•
Added the following table note to Data rate specification: "100 Mbps is the maximum specified data rate, although
higher data rates are possible." ............................................................................................................................................. 7
•
Changed ISO7741-Q1 PD1 or Maximum power dissipation by side-1 From: 50 mW To: 75 mW and PD2 or Maximum
power dissipation by side-2 From: 150 mW To: 125 mW in Power Rating table................................................................... 8
•
Changed VIORM value for DW-16 package From: "1414 VPK" To: "2121 VPK" in Insulation Specifications table ................... 9
•
Changed VIOWM values for DW-16 package From: "1000 VRMS" and "1414 VDC" To: "1500 VRMS" and "2121 VDC" in
Insulation Specifications table ............................................................................................................................................... 9
•
Added 'see Figure 30' to TEST CONDITIONS of VIOWM specification in Insulation Specifications ........................................ 9
2
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SLLSEU0C – NOVEMBER 2016 – REVISED FEBRUARY 2020
Revision History (continued)
•
Changed VIOSM TEST CONDITIONS From: "Test method per IEC 60065" To: "Test method per IEC 62368-1" in
Insulation Specifications table ................................................................................................................................................ 9
•
Updated certification information in Safety-Related Certifications table .............................................................................. 10
•
Corrected ground symbol for 'Input (ISO774xF)' schematic in Device I/O Schematics ...................................................... 27
•
Updated Figure 24 by changing CAN transceiver From: SN65HVD231Q To: TCAN1042-Q1 and transformer driver
From: SN6501-Q1 To: SN6505x-Q1 .................................................................................................................................... 28
•
Added Insulation Lifetime sub-section under Application Curve section.............................................................................. 30
•
Added SN6505x-Q1 reference in Power Supply Recommendations section ..................................................................... 31
•
Added 'How to use isolation to improve ESD, EFT, and Surge immunity in industrial systems' application report to
Documentation Support section .......................................................................................................................................... 33
•
Added SN6505x-Q1 data sheet reference in Documentation Support section .................................................................... 33
Changes from Revision A (May 2018) to Revision B
Page
•
Changed the isolation rating of the DBQ package from 2500 VRMS to 3000 VRMS ................................................................. 1
•
Moved the HBM and CDM values from the Features section to the ESD Ratings table ....................................................... 7
•
Added VTEST to the conditions for the maximum transient isolation voltage parameter in the Insulation Specifications
table ........................................................................................................................................................................................ 9
•
Changed the value for the DBQ package from 3600 VPK to 4242 VPK throughout the document ......................................... 9
•
Changed the method b1 Vini condition for apparent charge in the Insulation Specifications table ........................................ 9
•
Switched the line colors for VCC at 2.5 V and VCC at 3.3 V in Figure 14 .............................................................................. 20
•
Switched the labels for VCC1 falling and VCC2 rising in the graph legend of Power Supply Undervoltage Threshold vs
Free-Air Temperature ........................................................................................................................................................... 20
Changes from Original (November 2016) to Revision A
Page
•
Updated the Safety-Related Certifications table................................................................................................................... 10
•
Changed the minimum CMTI from 40 to 85 in all Electrical Characteristics tables ............................................................ 11
Copyright © 2016–2020, Texas Instruments Incorporated
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SLLSEU0C – NOVEMBER 2016 – REVISED FEBRUARY 2020
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5 Description Continued
The ISO774x-Q1 devices provide high electromagnetic immunity and low emissions at low power consumption,
while isolating CMOS or LVCMOS digital I/Os. Each isolation channel has a logic input and output buffer
separated by a double capacitive silicon dioxide (SiO2) insulation barrier. These devices come with enable pins
which can be used to put the respective outputs in high impedance for multi-master driving applications and to
reduce power consumption. The ISO7740-Q1 device has all four channels in the same direction, the ISO7741Q1 device has three forward and one reverse-direction channels, and the ISO7742-Q1 device has two forward
and two reverse-direction channels. If the input power or signal is lost, default output is high for devices without
suffix F and low for devices with suffix F. See the Device Functional Modes section for further details.
Used in conjunction with isolated power supplies, these devices help prevent noise currents on data buses, such
as CAN and LIN, or other circuits from entering the local ground and interfering with or damaging sensitive
circuitry. Through innovative chip design and layout techniques, electromagnetic compatibility of the ISO774x-Q1
devices have been significantly enhanced to ease system-level ESD, EFT, surge, and emissions compliance.
The ISO774x-Q1 devices are available in 16-pin wide SOIC (DW) and QSOP (DBQ) packages. ISO7741-Q1 is
also available in extra-wide SOIC (DWW) package.
4
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SLLSEU0C – NOVEMBER 2016 – REVISED FEBRUARY 2020
6 Pin Configuration and Functions
ISO7740-Q1 DW and DBQ Packages
16-Pin SOIC-WB and QSOP
Top View
ISO7741-Q1 DWW, DW and DBQ Packages
16-Pin SOIC-Extra-WB, SOIC-WB and QSOP
Top View
1
16 VCC2
VCC1
1
16 VCC2
GND1 2
15 GND2
GND1 2
15 GND2
3
INB
4
INC
5
IND
6
11 OUTD
NC
7
10
ISOLATION
INA
14 OUTA
INA
3
13 OUTB
INB
4
12 OUTC
INC
5
GND1 8
14 OUTA
ISOLATION
VCC1
OUTD 6
EN2
EN1
9 GND2
7
GND1 8
13 OUTB
12 OUTC
11
IND
10
EN2
9 GND2
ISO7742-Q1 DW and DBQ Packages
16-Pin SOIC-WB and QSOP
Top View
1
16 VCC2
GND1 2
15 GND2
INA
3
INB
4
OUTC 5
OUTD 6
EN1
7
GND1 8
Copyright © 2016–2020, Texas Instruments Incorporated
14 OUTA
ISOLATION
VCC1
13 OUTB
12
INC
11
IND
10
EN2
9 GND2
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SLLSEU0C – NOVEMBER 2016 – REVISED FEBRUARY 2020
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Pin Functions
PIN
NAME
I/O
DESCRIPTION
7
I
Output enable 1. Output pins on side 1 are enabled when EN1 is high
or open and in high-impedance state when EN1 is low.
10
10
I
Output enable 2. Output pins on side 2 are enabled when EN2 is high
or open and in high-impedance state when EN2 is low.
2
2
2
8
8
8
ISO7740-Q1
ISO7741-Q1
ISO7742-Q1
EN1
—
7
EN2
10
GND1
—
Ground connection for VCC1
—
Ground connection for VCC2
9
9
9
15
15
15
INA
3
3
3
I
Input, channel A
INB
4
4
4
I
Input, channel B
INC
5
5
12
I
Input, channel C
IND
6
11
11
I
Input, channel D
NC
7
—
—
—
Not connected
OUTA
14
14
14
O
Output, channel A
OUTB
13
13
13
O
Output, channel B
OUTC
12
12
5
O
Output, channel C
OUTD
11
6
6
O
Output, channel D
VCC1
1
1
1
—
Power supply, side 1
VCC2
16
16
16
—
Power supply, side 2
GND2
6
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SLLSEU0C – NOVEMBER 2016 – REVISED FEBRUARY 2020
7 Specifications
7.1 Absolute Maximum Ratings
See
(1)
VCC1, VCC2
Supply voltage (2)
MIN
MAX
–0.5
6
V
Voltage at INx, OUTx, ENx
–0.5
IO
Output current
–15
TJ
Junction temperature
Tstg
Storage temperature
(1)
(2)
(3)
UNIT
V
VCCX + 0.5
–65
(3)
V
15
mA
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak
voltage values.
Maximum voltage must not exceed 6 V.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
(3)
Electrostatic
discharge
Human-body model (HBM), per AEC Q100-002 (1)
HBM ESD Classification Level 3A
±6000
Charged-device model (CDM), per AEC Q100-011
CDM ESD Classification Level C6
±1500
Contact discharge per IEC 61000-4-2; Isolation barrier withstand test (2) (3)
±8000
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
IEC ESD strike is applied across the barrier with all pins on each side tied together creating a two-terminal device.
Testing is carried out in air or oil to determine the intrinsic contact discharge capability of the device.
7.3 Recommended Operating Conditions
MIN
NOM
UNIT
Supply voltage
VCC(UVLO+)
UVLO threshold when supply voltage is rising
VCC(UVLO-)
UVLO threshold when supply voltage is falling
1.7
1.8
V
VHYS(UVLO)
Supply voltage UVLO hysteresis
100
200
mV
IOH
2.25
MAX
VCC1, VCC2
High-level output current
IOL
Low-level output current
VIH
High-level input voltage
VIL
Low-level input voltage
2
VCCO (1) = 5 V
–4
VCCO = 3.3 V
–2
VCCO = 2.5 V
–1
Data rate
Ambient temperature
(1)
(2)
V
VCCO = 5 V
4
VCCO = 3.3 V
2
mA
1
0.7 × VCCI
(2)
TA
V
2.25
mA
VCCO = 2.5 V
DR
5.5
(1)
VCCI
V
0
0.3 × VCCI
V
0
-40
25
100
Mbps
125
°C
VCCI = Input-side VCC; VCCO = Output-side VCC.
100 Mbps is the maximum specified data rate, although higher data rates are possible.
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7.4 Thermal Information
ISO774x-Q1
THERMAL METRIC
(1)
DWW (SOIC)
DW (SOIC)
DBQ
(QSOP)
16 Pins
16 Pins
16 Pins
UNIT
RθJA
Junction-to-ambient thermal resistance
58.3
83.4
109
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
21.4
46
54.4
°C/W
RθJB
Junction-to-board thermal resistance
30.5
48
51.9
°C/W
ψJT
Junction-to-top characterization parameter
7.1
19.1
14.2
°C/W
ψJB
Junction-to-board characterization parameter
29.8
47.5
51.4
°C/W
RθJC(bottom)
Junction-to-case(bottom) thermal resistance
—
—
—
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Power Rating
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
200
mW
ISO7740-Q1
PD
Maximum power dissipation
PD1
Maximum power dissipation by side-1
PD2
Maximum power dissipation by side-2
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
Input a 50-MHz 50% duty cycle square wave
40
mW
160
mW
200
mW
ISO7741-Q1
PD
Maximum power dissipation
PD1
Maximum power dissipation by side-1
PD2
Maximum power dissipation by side-2
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
Input a 50-MHz 50% duty cycle square wave
75
mW
125
mW
200
mW
100
mW
100
mW
ISO7742-Q1
PD
Maximum power dissipation
PD1
Maximum power dissipation by side-1
PD2
Maximum power dissipation by side-2
8
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VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
Input a 50-MHz 50% duty cycle square wave
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7.6 Insulation Specifications
PARAMETER
VALUE
TEST CONDITIONS
DWW-16
DW-16
DBQ-16
UNIT
CLR
External clearance (1)
Shortest terminal-to-terminal distance through air
>14.5
>8
>3.7
mm
CPG
External creepage (1)
Shortest terminal-to-terminal distance across the package surface
>14.5
>8
>3.7
mm
DTI
Distance through the insulation
Minimum internal gap (internal clearance)
>21
>21
>21
μm
CTI
Comparative tracking index
DIN EN 60112 (VDE 0303-11); IEC 60112
>600
>600
>600
V
Material group
According to IEC 60664-1
I
I
I
Rated mains voltage ≤ 300 VRMS
I-IV
I-IV
I-III
Rated mains voltage ≤ 600 VRMS
I-IV
I-IV
n/a
Rated mains voltage ≤ 1000 VRMS
I-IV
I-III
n/a
AC voltage (bipolar)
2828
2121
566
VPK
AC voltage; Time dependent dielectric breakdown (TDDB) Test;
see Figure 30
2000
1500
400
VRMS
DC voltage
2828
2121
566
VDC
8000
8000
4242
VPK
8000
8000
4000
VPK
Method a, After Input/Output safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.2 × VIORM, tm = 10 s
≤5
≤5
≤5
Method a, After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.6 × VIORM, tm = 10 s
≤5
≤5
≤5
Method b1; At routine test (100% production) and preconditioning
(type test)
Vini = 1.2 × VIOTM, tini = 1 s;
Vpd(m) = 1.875 × VIORM, tm = 1 s
≤5
≤5
≤5
Overvoltage category per IEC 606641
DIN VDE V 0884-11:2017-01 (2)
VIORM
Maximum repetitive peak isolation
voltage
VIOWM
Maximum working isolation voltage
VIOTM
Maximum transient isolation voltage
VTEST = VIOTM,
t = 60 s (qualification);
VTEST = 1.2 × VIOTM,
t= 1 s (100% production)
VIOSM
Maximum surge isolation voltage (3)
Test method per IEC 62368-1, 1.2/50 µs waveform,
VTEST = 1.6 × VIOSM (qualification)
Apparent charge (4)
qpd
Barrier capacitance, input to output (5)
CIO
~1
~1
~1
VIO = 500 V, TA = 25°C
>1012
>1012
>1012
VIO = 500 V, 100°C ≤ TA ≤ 125°C
>1011
>1011
>1011
VIO = 500 V at TS = 150°C
>109
>109
>109
Pollution degree
2
2
2
Climatic category
55/125/
21
55/125/
21
55/125/
21
5700
5000
3000
Isolation resistance (5)
RIO
VIO = 0.4 × sin (2πft), f = 1 MHz
pC
pF
Ω
UL 1577
VISO
(1)
(2)
(3)
(4)
(5)
Maximum withstanding isolation
voltage
VTEST = VISO , t = 60 s (qualification),
VTEST = 1.2 × VISO , t = 1 s (100% production)
VRMS
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care
should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on
the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.
This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by
means of suitable protective circuits.
Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
Apparent charge is electrical discharge caused by a partial discharge (pd).
All pins on each side of the barrier tied together creating a two-terminal device.
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7.7 Safety-Related Certifications
VDE
Certified according to DIN
VDE V 0884-11:2017-01
CSA
UL
Certified according to IEC
60950-1, IEC 62368-1 and IEC
60601-1
Certified according to UL 1577
Component Recognition
Program
CQC
Certified according to GB
4943.1-2011
Maximum transient
isolation voltage, 8000 VPK
(DWW-16, DW-16) and
4242 VPK (DBQ-16);
Maximum repetitive peak
isolation voltage, 2828 VPK
(DWW-16, Reinforced),
2121 VPK (DW-16,
Reinforced) and 566 VPK
(DBQ-16);
Maximum surge isolation
voltage, 8000 VPK (DWW16, DW-16) and 4000 VPK
(DBQ-16)
Reinforced insulation per CSA
60950-1-07+A1+A2, IEC 609501 2nd Ed.+A1+A2, CSA 623681-14 and IEC 62368-1 2nd Ed.
1450 VRMS (DWW-16), 800 VRMS
(DW-16) and 370 VRMS (DBQ16) max working voltage
(pollution degree 2, material
group I);
2 MOPP (Means of Patient
Protection) per CSA 60601-1:14
and IEC 60601-1 Ed. 3.1, 400
VRMS (DWW-16) and 250 VRMS
(DW-16) max working voltage
DWW-16: Reinforced
Insulation, Altitude ≤ 5000 m,
Tropical Climate, 1450 VRMS
maximum working voltage;
DW-16: Single protection, 5000 DW-16: Reinforced Insulation,
VRMS;
Altitude ≤ 5000 m, Tropical
DBQ-16: Single protection,
Climate, 700 VRMS maximum
3000 VRMS
working voltage;
DBQ-16: Basic Insulation,
Altitude ≤ 5000 m, Tropical
Climate, 400 VRMS maximum
working voltage
Certificate number:
40040142
Master contract number: 220991
File number: E181974
Certificate numbers:
CQC15001121716 (DWx-16)
CQC18001199097 (DBQ-16)
TUV
Certified according to EN
61010-1:2010/A1:2019, EN
60950-1:2006/A2:2013 and
EN 62368-1:2014
5700 VRMS (DWW-16), 5000
VRMS (DW-16) and 3000
VRMS (DBQ-16) Reinforced
insulation per EN 610101:2010/A1:2019 up to
working voltage of 1000
VRMS (DWW-16), 600 VRMS
(DW-16) and 300 VRMS
(DBQ-16)
5700 VRMS (DWW-16), 5000
VRMS (DW-16) and 3000
VRMS (DBQ-16) Reinforced
insulation per EN 609501:2006/A2:2013 and EN
62368-1:2014 up to working
voltage of 1450 VRMS
(DWW-16), 800 VRMS (DW16) and 370 VRMS (DBQ-16)
Client ID number: 77311
7.8 Safety Limiting Values
Safety limiting (1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure
of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat
the die and damage the isolation barrier potentially leading to secondary system failures.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
DWW-16 PACKAGE
IS
Safety input, output, or supply
current
RθJA = 58.3 °C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C, see Figure 1
390
RθJA = 58.3 °C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C, see Figure 1
596
RθJA = 58.3 °C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C, see
Figure 1
780
PS
Safety input, output, or total power RθJA = 58.3 °C/W, TJ = 150°C, TA = 25°C, see Figure 4
TS
Maximum safety temperature
mA
2144
mW
150
°C
DW-16 PACKAGE
IS
Safety input, output, or supply
current
RθJA = 83.4 °C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C, see Figure 2
273
RθJA = 83.4 °C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C, see Figure 2
416
RθJA = 83.4 °C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C, see
Figure 2
545
PS
Safety input, output, or total power RθJA = 83.4 °C/W, TJ = 150°C, TA = 25°C, see Figure 5
TS
Maximum safety temperature
mA
1499
mW
150
°C
DBQ-16 PACKAGE
IS
Safety input, output, or supply
current
RθJA = 109 °C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C, see Figure 3
209
RθJA = 109 °C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C, see Figure 3
319
RθJA = 109 °C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C, see
Figure 3
417
PS
Safety input, output, or total power RθJA = 109 °C/W, TJ = 150°C, TA = 25°C, see Figure 6
TS
Maximum safety temperature
(1)
10
mA
1147
mW
150
°C
The maximum safety temperature is the maximum junction temperature specified for the device. The power dissipation and junction-toair thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-toair thermal resistance in the Thermal Information is that of a device installed on a High-K test board for leaded Surface Mount Packages.
The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature
plus the power times the junction-to-air thermal resistance
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7.9 Electrical Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
IOH = –4 mA; see Figure 17
VOL
Low-level output voltage
IOL = 4 mA; see Figure 17
VCCO
(1)
MIN
TYP
– 0.4
4.8
VIT+(IN) Rising input voltage threshold
VIT-(IN) Falling input voltage threshold
VI(HYS)
Input threshold voltage
hysteresis
(1)
IIH
High-level input current
VIH = VCCI
IIL
Low-level input current
VIL = 0 V at INx or ENx
CMTI
Common-mode transient
immunity
VI = VCCI or 0 V, VCM = 1200 V; see
Figure 20
CI
Input Capacitance (2)
VI = VCC/ 2 + 0.4×sin(2πft), f = 1 MHz,
VCC = 5 V
(1)
(2)
MAX
UNIT
V
0.2
0.4
V
0.6 × VCCI
0.7 × VCCI
V
0.3 × VCCI
0.4 × VCCI
V
0.1 × VCCI
0.2 × VCCI
V
10
at INx or ENx
–10
85
μA
μA
100
2
kV/μs
pF
VCCI = Input-side VCC; VCCO = Output-side VCC.
Measured from input pin to ground.
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7.10 Supply Current Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted).
PARAMETER
SUPPLY
CURRENT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ISO7740-Q1
EN2 = 0 V; VI = VCC1 (ISO7740-Q1);
VI = 0 V (ISO7740-Q1 with F suffix)
ICC1
1.2
1.6
ICC2
0.3
0.5
EN2 = 0 V; VI = 0 V (ISO7740-Q1);
VI = VCC1 (ISO7740-Q1 with F suffix)
ICC1
5.5
7.8
ICC2
0.3
0.5
EN2 = VCC2; VI = VCC1 (ISO7740-Q1);
VI = 0 V (ISO7740-Q1 with F suffix)
ICC1
1.2
1.6
ICC2
2
3.2
EN2 = VCC2; VI = 0 V (ISO7740-Q1);
VI = VCC1 (ISO7740-Q1 with F suffix)
ICC1
5.5
7.8
ICC2
2.2
3.6
ICC1
3.3
4.7
ICC2
2.3
3.6
ICC1
3.4
4.8
ICC2
4.2
5.8
ICC1
3.8
5.7
ICC2
22.7
28
Supply current - Disable
Supply current - DC signal
1 Mbps
Supply current - AC signal
All channels switching with square
wave clock input; CL = 15 pF
10 Mbps
100 Mbps
mA
ISO7741-Q1
EN1 = EN2 = 0 V; VI = VCCI (1) (ISO7741-Q1);
VI = 0 V (ISO7741-Q1 with F suffix)
ICC1
1
1.5
ICC2
0.8
1.1
EN1 = EN2 = 0 V; VI = 0 V (ISO7741-Q1);
VI = VCCI (ISO7741-Q1 with F suffix)
ICC1
4.3
6.3
ICC2
1.8
2.7
EN1 = EN2 = VCCI; VI = VCCI (ISO7741-Q1);
VI = 0 V (ISO7741-Q1 with F suffix)
ICC1
1.5
2.3
ICC2
2
3
EN1 = EN2 = VCCI; VI = 0 V (ISO7741-Q1);
VI = VCCI (ISO7741-Q1 with F suffix)
ICC1
4.8
6.8
ICC2
3.2
4.9
ICC1
3.2
4.6
ICC2
2.8
4.1
ICC1
3.7
5.2
ICC2
4.2
5.7
ICC1
8.6
11.3
ICC2
18
22
EN1 = EN2 = 0 V; VI = VCCI (ISO7742-Q1);
VI = 0 V (ISO7742-Q1 with F suffix)
ICC1, ICC2
0.9
1.3
EN1 = EN2 = 0 V; VI = 0 V (ISO7742-Q1);
VI = VCCI (ISO7742-Q1 with F suffix)
ICC1, ICC2
3
4.6
EN1 = EN2 = VCCI; VI = VCCI (ISO7742-Q1);
VI = 0 V (ISO7742-Q1 with F suffix)
ICC1, ICC2
1.7
2.7
EN1 = EN2 = VCCI; VI = 0 V (ISO7742-Q1);
VI = VCCI (ISO7742-Q1 with F suffix)
ICC1, ICC2
4
5.9
1 Mbps
ICC1, ICC2
3
4.4
10 Mbps
ICC1, ICC2
4
5.5
100 Mbps
ICC1, ICC2
13.4
17
Supply current - Disable
Supply current - DC signal
1 Mbps
Supply current - AC signal
All channels switching with square
wave clock input; CL = 15 pF
10 Mbps
100 Mbps
mA
ISO7742-Q1
Supply current - Disable
Supply current - DC signal
Supply current - AC signal
(1)
12
All channels switching with square
wave clock input; CL = 15 pF
mA
VCCI = Input-side VCC
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7.11 Electrical Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
VCCO (1) – 0.3
3.2
VOH
High-level output voltage
IOH = –2 mA; see Figure 17
VOL
Low-level output voltage
IOL = 2 mA; see Figure 17
VIT+(IN)
Rising input voltage threshold
VIT-(IN)
Falling input voltage threshold
0.3 × VCCI
0.4 × VCCI
VI(HYS)
Input threshold voltage hysteresis
0.1 × VCCI
0.2 × VCCI
IIH
High-level input current
VIH = VCCI (1) at INx or ENx
IIL
Low-level input current
VIL = 0 V at INx or ENx
CMTI
Common-mode transient
immunity
VI = VCCI or 0 V, VCM = 1200 V; see Figure 20
(1)
MAX
V
0.1
0.3
V
0.6 × VCCI
0.7 × VCCI
V
V
V
10
–10
85
UNIT
μA
μA
100
kV/μs
VCCI = Input-side VCC; VCCO = Output-side VCC.
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7.12 Supply Current Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted).
PARAMETER
SUPPLY
CURRENT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ISO7740-Q1
EN2 = 0 V; VI = VCC1 (ISO7740-Q1);
VI = 0 V (ISO7740-Q1 with F suffix)
ICC1
1.2
1.6
ICC2
0.3
0.5
EN2 = 0 V; VI = 0 V (ISO7740-Q1);
VI = VCC1 (ISO7740-Q1 with F suffix)
ICC1
5.5
7.8
ICC2
0.3
0.5
EN2 = VCC2; VI = VCC1 (ISO7740-Q1);
VI = 0 V (ISO7740-Q1 with F suffix)
ICC1
1.2
1.6
ICC2
1.9
3.2
EN2 = VCC2; VI = 0 V (ISO7740-Q1);
VI = VCC1 (ISO7740-Q1 with F suffix)
ICC1
5.5
7.8
ICC2
2.2
3.6
ICC1
3.3
4.7
ICC2
2.2
3.6
ICC1
3.4
4.8
ICC2
3.6
5
ICC1
3.3
5.5
ICC2
17
20
Supply current - Disable
Supply current - DC signal
1 Mbps
Supply current - AC signal
All channels switching with square
wave clock input; CL = 15 pF
10 Mbps
100 Mbps
mA
ISO7741-Q1
EN1 = EN2 = 0 V; VI = VCCI (1) (ISO7741-Q1);
VI = 0 V (ISO7741-Q1 with F suffix)
ICC1
1
1.5
ICC2
0.8
1.1
EN1 = EN2 = 0 V; VI = 0 V (ISO7741-Q1);
VI = VCCI (ISO7741-Q1 with F suffix)
ICC1
4.3
6.3
ICC2
1.9
2.7
EN1 = EN2 = VCCI; VI = VCCI (ISO7741-Q1);
VI = 0 V (ISO7741-Q1 with F suffix)
ICC1
1.5
2.3
ICC2
2
3
EN1 = EN2 = VCCI; VI = 0 V (ISO7741-Q1);
VI = VCCI (ISO7741-Q1 with F suffix)
ICC1
4.8
6.8
ICC2
3.2
4.9
ICC1
3.2
4.6
ICC2
2.7
4.1
ICC1
3.5
5
ICC2
3.7
5.2
Supply current - Disable
Supply current - DC signal
1 Mbps
Supply current - AC signal
All channels switching with square
wave clock input; CL = 15 pF
10 Mbps
ICC1
6.8
9.3
ICC2
13.7
16.4
EN1 = EN2 = 0 V; VI = VCCI (ISO7742-Q1);
VI = 0 V (ISO7742-Q1 with F suffix)
ICC1, ICC2
0.9
1.3
EN1 = EN2 = 0 V; VI = 0 V (ISO7742-Q1);
VI = VCCI (ISO7742-Q1 with F suffix)
ICC1, ICC2
3
4.6
EN1 = EN2 = VCCI; VI = VCCI (ISO7742-Q1);
VI = 0 V (ISO7742-Q1 with F suffix)
ICC1, ICC2
1.7
2.7
EN1 = EN2 = VCCI; VI = 0 V (ISO7742-Q1);
VI = VCCI (ISO7742-Q1 with F suffix)
ICC1, ICC2
4
5.9
1 Mbps
ICC1, ICC2
2.9
4.3
10 Mbps
ICC1, ICC2
3.6
5.1
100 Mbps
ICC1, ICC2
10.3
13
100 Mbps
mA
ISO7742-Q1
Supply current - Disable
Supply current - DC signal
Supply current - AC signal
(1)
14
All channels switching with square
wave clock input; CL = 15 pF
mA
VCCI = Input-side VCC
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7.13 Electrical Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
VCCO (1) – 0.2
2.45
VOH
High-level output voltage
IOH = –1 mA; see Figure 17
VOL
Low-level output voltage
IOL = 1 mA; see Figure 17
VIT+(IN)
Rising input voltage threshold
VIT-(IN)
Falling input voltage threshold
0.3 × VCCI
0.4 × VCCI
VI(HYS)
Input threshold voltage hysteresis
0.1 × VCCI
0.2 × VCCI
IIH
High-level input current
VIH = VCCI (1) at INx or ENx
IIL
Low-level input current
VIL = 0 V at INx or ENx
CMTI
Common-mode transient
immunity
VI = VCCI or 0 V, VCM = 1200 V; see Figure 20
(1)
MAX
UNIT
V
0.05
0.2
V
0.6 × VCCI
0.7 × VCCI
V
V
V
10
μA
–10
μA
85
100
kV/μs
VCCI = Input-side VCC; VCCO = Output-side VCC.
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7.14 Supply Current Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted).
PARAMETER
TEST CONDITIONS
SUPPLY
CURRENT
MIN
TYP
MAX
UNIT
ISO7740-Q1
EN2 = 0 V; VI = VCC1 (ISO7740-Q1);
VI = 0 V (ISO7740-Q1 with F suffix)
ICC1
1.2
1.6
ICC2
0.3
0.5
EN2 = 0 V; VI = 0 V (ISO7740-Q1);
VI = VCC1 (ISO7740-Q1 with F suffix)
ICC1
5.5
7.8
ICC2
0.3
0.5
EN2 = VCC2; VI = VCC1 (ISO7740-Q1);
VI = 0 V (ISO7740-Q1 with F suffix)
ICC1
1.2
1.6
ICC2
1.9
3.2
EN2 = VCC2; VI = 0 V (ISO7740-Q1);
VI = VCC1 (ISO7740-Q1 with F suffix)
ICC1
5.4
7.8
ICC2
2.2
3.6
ICC1
3.3
4.7
ICC2
2.2
3.5
ICC1
3.4
4.8
ICC2
3.2
4.7
ICC1
3.2
5.4
ICC2
13
17
Supply current - Disable
Supply current - DC signal
1 Mbps
Supply current - AC signal
All channels switching with square
wave clock input; CL = 15 pF
10 Mbps
100 Mbps
mA
ISO7741-Q1
EN1 = EN2 = 0 V; VI = VCCI (1) (ISO7741-Q1);
VI = 0 V (ISO7741-Q1 with F suffix)
ICC1
1
1.5
ICC2
0.8
1.1
EN1 = EN2 = 0 V; VI = 0 V (ISO7741-Q1);
VI = VCCI (ISO7741-Q1 with F suffix)
ICC1
4.3
6.3
ICC2
1.8
2.7
EN1 = EN2 = VCCI; VI = VCCI (ISO7741-Q1);
VI = 0 V (ISO7741-Q1 with F suffix)
ICC1
1.4
2.3
ICC2
2
3
EN1 = EN2 = VCCI; VI = 0 V (ISO7741-Q1);
VI = VCCI (ISO7741-Q1 with F suffix)
ICC1
4.7
6.8
ICC2
3.2
4.9
ICC1
3.1
4.6
ICC2
2.7
4
ICC1
3.4
4.9
ICC2
3.5
4.9
ICC1
5.6
8.3
ICC2
10.8
13.8
EN1 = EN2 = 0 V; VI = VCCI (ISO7742-Q1);
VI = 0 V (ISO7742-Q1 with F suffix)
ICC1, ICC2
0.9
1.3
EN1 = EN2 = 0 V; VI = 0 V (ISO7742-Q1);
VI = VCCI (ISO7742-Q1 with F suffix)
ICC1, ICC2
3
4.6
EN1 = EN2 = VCCI; VI = VCCI (ISO7742-Q1);
VI = 0 V (ISO7742-Q1 with F suffix)
ICC1, ICC2
1.7
2.7
EN1 = EN2 = VCCI; VI = 0 V (ISO7742-Q1);
VI = VCCI (ISO7742-Q1 with F suffix)
ICC1, ICC2
4
5.9
1 Mbps
ICC1, ICC2
2.9
4.3
10 Mbps
ICC1, ICC2
3.4
4.9
100 Mbps
ICC1, ICC2
8.3
11.5
Supply current - Disable
Supply current - DC signal
1 Mbps
Supply current - AC signal
All channels switching with square
wave clock input; CL = 15 pF
10 Mbps
100 Mbps
mA
ISO7742-Q1
Supply current - Disable
Supply current - DC signal
Supply current - AC signal
(1)
16
All channels switching with square
wave clock input; CL = 15 pF
mA
VCCI = Input-side VCC
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7.15 Switching Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
MIN
TYP
MAX
6
10.7
16
ns
0
4.9
ns
4
ns
4.4
ns
2.4
3.9
ns
2.4
3.9
ns
Disable propagation delay, high-to-high impedance output
9
20
ns
Disable propagation delay, low-to-high impedance output
9
20
ns
Enable propagation delay, high impedance-to-high output
for ISO774x-Q1
7
20
ns
3
8.5
μs
Enable propagation delay, high impedance-to-low output for
ISO774x-Q1
3
8.5
μs
Enable propagation delay, high impedance-to-low output for
ISO774x-Q1 with F suffix
7
20
ns
0.1
0.3
μs
tPLH, tPHL
Propagation delay time
PWD
Pulse width distortion (1) |tPHL – tPLH|
tsk(o)
Channel-to-channel output skew time (2)
tsk(pp)
Part-to-part skew time (3)
tr
Output signal rise time
tf
Output signal fall time
tPHZ
tPLZ
tPZH
tDO
Same-direction channels
See Figure 17
See Figure 18
Measured from the time VCC goes
below 1.7 V. See Figure 20
Default output delay time from input power loss
tie
(3)
See Figure 17
Enable propagation delay, high impedance-to-high output
for ISO774x-Q1 with F suffix
tPZL
(1)
(2)
TEST CONDITIONS
16
Time interval error
2
0.8
– 1 PRBS data at 100 Mbps
UNIT
ns
Also known as pulse skew.
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
7.16 Switching Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
MIN
TYP
MAX
6
11
16
ns
0.1
5
ns
4.1
ns
4.5
ns
1.3
3
ns
1.3
3
ns
Disable propagation delay, high-to-high impedance output
17
30
ns
Disable propagation delay, low-to-high impedance output
17
30
ns
Enable propagation delay, high impedance-to-high output
for ISO774x-Q1
17
30
ns
3.2
8.5
μs
Enable propagation delay, high impedance-to-low output
for ISO774x-Q1
3.2
8.5
μs
Enable propagation delay, high impedance-to-low output
for ISO774x-Q1 with F suffix
17
30
ns
0.1
0.3
μs
tPLH, tPHL
Propagation delay time
PWD
Pulse width distortion (1) |tPHL – tPLH|
tsk(o)
Channel-to-channel output skew time (2)
tsk(pp)
Part-to-part skew time (3)
tr
Output signal rise time
tf
Output signal fall time
tPHZ
tPLZ
tPZH
tPZL
tDO
tie
(1)
(2)
(3)
TEST CONDITIONS
See Figure 17
Same-direction channels
See Figure 17
Enable propagation delay, high impedance-to-high output
for ISO774x-Q1 with F suffix
Default output delay time from input power loss
See Figure 18
Measured from the time VCC goes
below 1.7 V. See Figure 20
16
Time interval error
2
0.9
– 1 PRBS data at 100 Mbps
UNIT
ns
Also known as pulse skew.
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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7.17 Switching Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
tPLH, tPHL
Propagation delay time
PWD
Pulse width distortion (1) |tPHL – tPLH|
tsk(o)
Channel-to-channel output skew time (2)
tsk(pp)
Part-to-part skew time (3)
tr
Output signal rise time
tf
Output signal fall time
tPHZ
tPLZ
tPZH
tPZL
tDO
tie
(1)
(2)
(3)
18
TEST CONDITIONS
MIN
7.5
TYP
MAX
UNIT
12
18.5
ns
0.2
5.1
ns
4.1
ns
4.6
ns
1
3.5
ns
1
3.5
ns
Disable propagation delay, high-to-high impedance output
22
40
ns
Disable propagation delay, low-to-high impedance output
22
40
ns
Enable propagation delay, high impedance-to-high output
for ISO774x-Q1
18
40
ns
3.3
8.5
μs
Enable propagation delay, high impedance-to-low output
for ISO774x-Q1
3.3
8.5
μs
Enable propagation delay, high impedance-to-low output
for ISO774x-Q1 with F suffix
18
40
ns
0.1
0.3
μs
See Figure 17
Same-direction Channels
See Figure 17
Enable propagation delay, high impedance-to-high output
for ISO774x-Q1 with F suffix
Default output delay time from input power loss
See Figure 18
Measured from the time VCC goes
below 1.7 V. See Figure 20
16
Time interval error
2
– 1 PRBS data at 100 Mbps
0.7
ns
Also known as pulse skew.
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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7.18 Insulation Characteristics Curves
600
VCC1 = VCC2 = 2.75 V
VCC1 = VCC2 = 3.6 V
VCC1 = VCC2 = 5.5 V
Safety Limiting Current (mA)
Safety Limiting Current (mA)
800
600
400
200
0
50
100
150
Ambient Temperature (oC)
400
300
200
100
0
200
50
D017
Figure 1. Thermal Derating Curve for Safety Limiting
Current for DWW-16 Package
100
150
Ambient Temperature (qC)
200
D001
Figure 2. Thermal Derating Curve for Safety Limiting
Current for DW-16 Package
2250
450
VCC1 = VCC2 = 2.75 V
VCC1 = VCC2 = 3.6 V
VCC1 = VCC2 = 5.5 V
350
2000
Safety Limiting Power (mW)
400
Safety Limiting Current (mA)
500
0
0
300
250
200
150
100
1750
1500
1250
1000
750
500
250
50
0
0
0
50
100
150
Ambient Temperature (qC)
0
200
20
40
D002
Figure 3. Thermal Derating Curve for Safety Limiting
Current for DBQ-16 Package
1600
1400
1400
1200
1200
1000
800
600
400
60
80
100
120
Ambient Temperature (oC)
140
160
D018
Figure 4. Thermal Derating Curve for Safety Limiting Power
for DWW-16 Package
Safety Limiting Power (mW)
Safety Limiting Power (mW)
VCC1 = VCC2 = 2.75 V
VCC1 = VCC2 = 3.6 V
VCC1 = VCC2 = 5.5 V
1000
800
600
400
200
200
0
0
0
50
100
150
Ambient Temperature (qC)
200
D003
Figure 5. Thermal Derating Curve for Safety Limiting Power
for DW-16 Package
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0
50
100
150
Ambient Temperature (qC)
200
D004
Figure 6. Thermal Derating Curve for Safety Limiting Power
for DBQ-16 Package
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7.19 Typical Characteristics
9
25
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
15
7
Supply Current (mA)
Supply Current (mA)
20
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
8
10
6
5
4
3
2
5
1
0
0
0
25
TA = 25°C
50
Data Rate (Mbps)
75
0
100
CL = 15 pF
100
D006
CL = No Load
9
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
16
14
12
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
8
7
Supply Current (mA)
18
Supply Current (mA)
75
Figure 8. ISO7740-Q1 Supply Current vs Data Rate
(With No Load)
20
10
8
6
6
5
4
3
4
2
2
1
0
0
0
25
TA = 25°C
50
Data Rate (Mbps)
75
100
0
25
D007
CL = 15 pF
50
Data Rate (Mbps)
TA = 25°C
Figure 9. ISO7741-Q1 Supply Current vs Data Rate
(With 15-pF Load)
75
100
D008
CL = No Load
Figure 10. ISO7741-Q1 Supply Current vs Data Rate
(With No Load)
8
16
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
12
10
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5 V
ICC2 at 5 V
7
Supply Current (mA)
14
Supply Current (mA)
50
Data Rate (Mbps)
TA = 25°C
Figure 7. ISO7740-Q1 Supply Current vs Data Rate
(With 15-pF Load)
8
6
4
6
5
4
3
2
1
2
0
0
0
25
TA = 25°C
50
Data Rate (Mbps)
75
100
CL = 15 pF
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0
25
D009
Figure 11. ISO7742-Q1 Supply Current vs Data Rate
(With 15-pF Load)
20
25
D005
50
Data Rate (Mbps)
TA = 25°C
75
100
D010
CL = No Load
Figure 12. ISO7742-Q1 Supply Current vs Data Rate
(With No Load)
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Typical Characteristics (continued)
6
0.9
Low-Level Output Voltage (V)
High-Level Output Voltage (V)
0.8
5
4
3
2
VCC at 2.5 V
VCC at 3.3 V
VCC at 5 V
1
0
-15
0.7
0.6
0.5
0.4
0.3
0.2
VCC at 2.5 V
VCC at 3.3 V
VCC at 5 V
0.1
0
-10
-5
High-Level Output Current (mA)
0
0
TA = 25°C
15
D012
TA = 25°C
Figure 13. High-Level Output Voltage vs High-level Output
Current
Figure 14. Low-Level Output Voltage vs Low-Level Output
Current
2.10
14
2.05
Propagation Delay Time (ns)
Power Supply UVLO Threshold (V)
5
10
Low-Level Output Current (mA)
D011
2.00
1.95
1.90
1.85
1.80
VCC1 Rising
VCC2 Rising
VCC1 Falling
VCC2 Falling
1.75
1.70
1.65
-55
-5
45
Free-Air Temperature (qC)
95
125
D013
Figure 15. Power Supply Undervoltage Threshold vs FreeAir Temperature
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13
12
11
10
tPHL at 2.5 V
tPLH at 2.5 V
tPHL at 3.3 V
9
8
-55
-25
5
35
65
Free-Air Temperature (qC)
tPLH at 3.3 V
tPHL at 5 V
tPLH at 5 V
95
125
D014
Figure 16. Propagation Delay Time vs Free-Air Temperature
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8 Parameter Measurement Information
Isolation Barrier
IN
Input
Generator
(See Note A)
VI
VCCI
VI
OUT
50%
50%
0V
tPLH
CL
See Note B
VO
50
tPHL
VO
VOH
90%
50%
50%
10%
VOL
tf
tr
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A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3ns, ZO = 50 Ω. At the input, 50 Ω resistor is required to terminate Input Generator signal. It is not needed in
actual application.
B.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 17. Switching Characteristics Test Circuit and Voltage Waveforms
VCCO
VCC
Isolation Barrier
IN
0V
VO
VI
tPZL
0V
tPLZ
VOH
EN
0.5 V
VO
50%
VOL
50
OUT
VCC
VO
VCC / 2
VCC / 2
VI
0V
EN
CL
See Note B
VI
VCC / 2
VCC / 2
VI
CL
See Note B
IN
Input
Generator
(See Note A)
±1%
OUT
Isolation Barrier
Input
Generator
(See Note A)
3V
RL = 1 k
tPZH
RL = 1 k
±1%
VOH
50%
VO
0.5 V
tPHZ
50
0V
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A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 10 kHz, 50% duty cycle,
tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω.
B.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 18. Enable/Disable Propagation Delay Time Test Circuit and Waveform
22
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Parameter Measurement Information (continued)
VI
See Note B
VCC
VCC
Isolation Barrier
IN = 0 V (Devices without suffix F)
IN = VCC (Devices with suffix F)
VI
IN
1.7 V
0V
OUT
VO
tDO
CL
See Note A
default high
VOH
50%
VO
VOL
default low
A.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
B.
Power Supply Ramp Rate = 10 mV/ns
Figure 19. Default Output Delay Time Test Circuit and Voltage Waveforms
VCCI
VCCO
C = 0.1 µF ±1%
S1
Isolation Barrier
C = 0.1 µF ±1%
IN
Pass-fail criteria:
The output must
remain stable.
OUT
+
CL
See Note A
VOH or VOL
±
GNDI
A.
+
VCM ±
GNDO
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 20. Common-Mode Transient Immunity Test Circuit
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9 Detailed Description
9.1 Overview
The ISO774x-Q1 family of devices an ON-OFF keying (OOK) modulation scheme to transmit the digital data
across a silicon dioxide based isolation barrier. The transmitter sends a high frequency carrier across the barrier
to represent one digital state and sends no signal to represent the other digital state. The receiver demodulates
the signal after advanced signal conditioning and produces the output through a buffer stage. If the ENx pin is
low then the output goes to high impedance. The ISO774x-Q1 devices also incorporate advanced circuit
techniques to maximize the CMTI performance and minimize the radiated emissions due to the high frequency
carrier and IO buffer switching. The conceptual block diagram of a digital capacitive isolator, Figure 21, shows a
functional block diagram of a typical channel.
9.2 Functional Block Diagram
Transmitter
Receiver
EN
TX IN
OOK
Modulation
TX Signal
Conditioning
Oscillator
SiO2 based
Capacitive
Isolation
Barrier
RX Signal
Conditioning
Envelope
Detection
RX OUT
Emissions
Reduction
Techniques
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Figure 21. Conceptual Block Diagram of a Digital Capacitive Isolator
Figure 22 shows a conceptual detail of how the ON-OFF keying scheme works.
TX IN
Carrier signal through
isolation barrier
RX OUT
Figure 22. On-Off Keying (OOK) Based Modulation Scheme
24
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9.3 Feature Description
Table 1 provides an overview of the device features.
Table 1. Device Features
PART NUMBER
CHANNEL DIRECTION
MAXIMUM DATA
RATE
DEFAULT
OUTPUT
ISO7740-Q1
4 Forward,
0 Reverse
100 Mbps
High
ISO7740-Q1 with F
suffix
4 Forward,
0 Reverse
100 Mbps
Low
ISO7741-Q1
3 Forward,
1 Reverse
100 Mbps
High
ISO7741-Q1 with F
suffix
ISO7742-Q1
ISO7742-Q1 with F
suffix
(1)
3 Forward,
1 Reverse
2 Forward,
2 Reverse
2 Forward,
2 Reverse
100 Mbps
100 Mbps
100 Mbps
Low
High
Low
PACKAGE
RATED ISOLATION (1)
DW-16
5000 VRMS / 8000 VPK
DBQ-16
3000 VRMS / 4242 VPK
DW-16
5000 VRMS / 8000 VPK
DBQ-16
3000 VRMS / 4242 VPK
DWW-16
5700 VRMS / 8000 VPK
DW-16
5000 VRMS / 8000 VPK
DBQ-16
3000 VRMS / 4242 VPK
DWW-16
5700 VRMS / 8000 VPK
DW-16
5000 VRMS / 8000 VPK
DBQ-16
3000 VRMS / 4242 VPK
DW-16
5000 VRMS / 8000 VPK
DBQ-16
3000 VRMS / 4242 VPK
DW-16
5000 VRMS / 8000 VPK
DBQ-16
3000 VRMS / 4242 VPK
See Safety-Related Certifications for detailed isolation ratings.
9.3.1 Electromagnetic Compatibility (EMC) Considerations
Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge
(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances
are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level
performance and reliability depends, to a large extent, on the application board design and layout, the ISO774xQ1 family of devices incorporates many chip-level design improvements for overall system robustness. Some of
these improvements include:
• Robust ESD protection cells for input and output signal pins and inter-chip bond pads.
• Low-resistance connectivity of ESD cells to supply and ground pins.
• Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.
• Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance
path.
• PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic
SCRs.
• Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.
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9.4 Device Functional Modes
Table 2 lists the functional modes for the ISO774x-Q1 devices.
Table 2. Function Table (1)
VCCI
PU
X
(1)
(2)
(3)
26
VCCO
INPUT
(INx) (2)
OUTPUT
ENABLE
(ENx)
OUTPUT
(OUTx)
H
H or open
H
L
H or open
L
Open
H or open
Default
X
L
Z
PU
PU
PD
PU
X
H or open
Default
X
PD
X
X
Undetermined
COMMENTS
Normal Operation:
A channel output assumes the logic state of its input.
Default mode: When INx is open, the corresponding channel output
goes to its default logic state. Default is High for ISO774x-Q1 and
Low for ISO774x-Q1 with F suffix.
A low value of output enable causes the outputs to be highimpedance.
Default mode: When VCCI is unpowered, a channel output assumes
the logic state based on the selected default option. Default is High
for ISO774x-Q1 and Low for ISO774x-Q1 with F suffix.
When VCCI transitions from unpowered to powered-up, a channel
output assumes the logic state of the input.
When VCCI transitions from powered-up to unpowered, channel output
assumes the selected default state.
When VCCO is unpowered, a channel output is undetermined (3).
When VCCO transitions from unpowered to powered-up, a channel
output assumes the logic state of the input.
VCCI = Input-side VCC; VCCO = Output-side VCC; PU = Powered up (VCC ≥ 2.25 V); PD = Powered down (VCC ≤ 1.7 V); X = Irrelevant; H
= High level; L = Low level ; Z = High Impedance
A strongly driven input signal can weakly power the floating VCC through an internal protection diode and cause undetermined output.
The outputs are in undetermined state when 1.7 V < VCCI, VCCO < 2.25 V.
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9.4.1 Device I/O Schematics
Input (ISO774x)
VCCI
VCCI
Input (ISO774xF)
VCCI
VCCI
VCCI
VCCI
VCCI
1.5 MW
985 W
985 W
INx
INx
1.5 MW
Enable
Output
VCCO
VCCO
VCCO VCCO
VCCO
2 MW
~20 W
OUTx
1970 W
ENx
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Figure 23. Device I/O Schematics
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The ISO774x-Q1 devices are high-performance, quad-channel digital isolators. These devices come with enable
pins on each side which can be used to put the respective outputs in high impedance for multi master driving
applications and reduce power consumption. The ISO774x-Q1 devices use single-ended CMOS-logic switching
technology. The voltage range is from 2.25 V to 5.5 V for both supplies, VCC1 and VCC2. When designing with
digital isolators, keep in mind that because of the single-ended design structure, digital isolators do not conform
to any specific interface standard and are only intended for isolating single-ended CMOS or TTL digital signal
lines. The isolator is typically placed between the data controller (that is, μC or UART), and a data converter or a
line transceiver, regardless of the interface type or standard.
10.2 Typical Application
Figure 24 shows the typical isolated CAN interface implementation.
VS
3.3 V
10 F
2
Vcc
D2
1:1.33
3
MBR0520L
1
D1
4
ISO 3.3V
5
OUT
TPS76333-Q1
SN6505x-Q1
GND
IN
10 F 0.1 F
3
1
EN
10 F
2
GND
MBR0520L
GND
5
ISO Barrier
0.1 F
0.1 F
0.1 F
0.1 F 29,57
VDDIO
TMS320F28
035PAGQ
CANRXA
CANTXA
26
1
5
25
3
VCC1
VCC2
OUTC
INC
INA
OUTA
VSS
6,28
16
12
14
3
VCC
CANH 7
4 RXDTCAN1042-Q1
TXD
CANL 6
1
GND
2
ISO7742-Q1
0.1 F
0.1 F 29,57
6
VDDIO
TMS320F28
035PAGQ
CANRXA
26
4
2,8
CANTXA
25
OUTD
INB
GND1
IND
OUTB
GND2
11
13
9,15
3
VCC
4 RXD
CANH 7
6
CANL
TCAN1042-Q1
1 TXD
GND
2
VSS
6,28
Copyright © 2020, Texas Instruments Incorporated
Figure 24. Typical Isolated CAN Application Circuit
28
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Typical Application (continued)
10.2.1 Design Requirements
To design with these devices, use the parameters listed in Table 3.
Table 3. Design Parameters
PARAMETER
VALUE
Supply voltage, VCC1 and VCC2
2.25 to 5.5 V
Decoupling capacitor between VCC1 and GND1
0.1 µF
Decoupling capacitor from VCC2 and GND2
0.1 µF
10.2.2 Detailed Design Procedure
Unlike optocouplers, which require external components to improve performance, provide bias, or limit current,
the ISO774x-Q1 family of devices only require two external bypass capacitors to operate.
2 mm maximum
from VCC2
2 mm maximum
from VCC1
0.1 µF
0.1 µF
VCC2
VCC1
1
16
2
15
INA
3
14
OUTA
INB
4
13
OUTB
INC
5
12
OUTC
OUTD
6
11
IND
7
10
8
9
GND1
GND2
EN2
EN1
GND2
GND1
Figure 25. Typical ISO774x-Q1 Circuit Hook-up
The DWW package provides wider creepage and clearance without the need for two isolators in series or an
extra isolated power supply, saving design cost and board space. For more details, please refer to the technical
document How to Meet the Higher Isolation Creepage & Clearance Needs in Automotive Applications.
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10.2.3 Application Curve
Ch4 = 1 V / div
Ch4 = 1 V / div
The following typical eye diagrams of the ISO774x-Q1 family of devices indicates low jitter and wide open eye at
the maximum data rate of 100 Mbps.
Time = 2.5 ns / div
Time = 2.5 ns / div
Figure 27. Eye Diagram at 100 Mbps PRBS 216 – 1, 3.3 V
and 25°C
Ch4 = 500 mV / div
Figure 26. Eye Diagram at 100 Mbps PRBS 216 – 1, 5 V and
25°C
Time = 2.5 ns / div
Figure 28. Eye Diagram at 100 Mbps PRBS 216 – 1, 2.5 V and 25°C
10.2.3.1 Insulation Lifetime
Insulation lifetime projection data is collected by using industry-standard Time Dependent Dielectric Breakdown
(TDDB) test method. In this test, all pins on each side of the barrier are tied together creating a two-terminal
device and high voltage applied between the two sides; See Figure 29 for TDDB test setup. The insulation
breakdown data is collected at various high voltages switching at 60 Hz over temperature. For reinforced
insulation, VDE standard requires the use of TDDB projection line with failure rate of less than 1 part per million
(ppm). Even though the expected minimum insulation lifetime is 20 years at the specified working isolation
voltage, VDE reinforced certification requires additional safety margin of 20% for working voltage and 87.5% for
lifetime which translates into minimum required insulation lifetime of 37.5 years at a working voltage that's 20%
higher than the specified value.
Figure 30 shows the intrinsic capability of the isolation barrier to withstand high voltage stress over its lifetime.
Based on the TDDB data, the insulation withstand capability of DW-16 package is 1500 VRMS with a lifetime of
135 years as illustrated in Figure 30. Similarly, the insulation withstand capability of DWW-16 package is 2000
VRMS with a corresponding lifetime of 34 years. DBQ-16 package at 400 VRMS working voltage has a much longer
lifetime than both DW-16 and DWW-16 packages. Factors, such as package size, pollution degree, and material
group can limit the working voltage of a component.
30
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www.ti.com
SLLSEU0C – NOVEMBER 2016 – REVISED FEBRUARY 2020
A
Vcc 1
Vcc 2
Time Counter
> 1 mA
DUT
GND 1
GND 2
VS
Oven at 150 °C
Figure 29. Test Setup for Insulation Lifetime Measurement
Figure 30. Insulation Lifetime Projection Data
11 Power Supply Recommendations
To help ensure reliable operation at data rates and supply voltages, a 0.1-μF bypass capacitor is recommended
at the input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins
as possible. If only a single primary-side power supply is available in an application, isolated power can be
generated for the secondary-side with the help of a transformer driver such as Texas Instruments' SN6501-Q1 or
SN6505B-Q1. For such applications, detailed power supply design and transformer selection recommendations
are available in SN6501-Q1 Transformer Driver for Isolated Power Supplies and SN6505x-Q1 Low-Noise 1-A
Transformer Drivers for Isolated Power Supplies data sheets.
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www.ti.com
12 Layout
12.1 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 31). Layer stacking should
be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency
signal layer.
• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/inch2.
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to
the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the
power and ground plane of each power system can be placed closer together, thus increasing the high-frequency
bypass capacitance significantly.
For detailed layout recommendations, refer to the Digital Isolator Design Guide.
12.1.1 PCB Material
For digital circuit boards operating below 150 Mbps, (or rise and fall times higher than 1 ns), and trace lengths of
up to 10 inches, use standard FR-4 UL94V-0 printed circuit boards. This PCB is preferred over cheaper
alternatives due to its lower dielectric losses at high frequencies, less moisture absorption, greater strength and
stiffness, and self-extinguishing flammability-characteristics.
12.2 Layout Example
High-speed traces
10 mils
Ground plane
40 mils
Keep this
space free
from planes,
traces, pads,
and vias
FR-4
0r ~ 4.5
Power plane
10 mils
Low-speed traces
Figure 31. Layout Example Schematic
32
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ISO7740-Q1, ISO7741-Q1, ISO7742-Q1
www.ti.com
SLLSEU0C – NOVEMBER 2016 – REVISED FEBRUARY 2020
13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, Digital Isolator Design Guide
• Texas Instruments, Isolation Glossary
• Texas Instruments, How to use isolation to improve ESD, EFT, and Surge immunity in industrial systems
application report
• Texas Instruments, SN6501-Q1 Transformer Driver for Isolated Power Supplies data sheet
• Texas Instruments, SN6505x-Q1 Low-Noise 1-A Transformer Drivers for Isolated Power Supplies data sheet
• Texas Instruments, TCAN1042-Q1 Automotive fault protected CAN transceiver with CAN FD data sheet
• Texas Instruments, TMS320F28035 Piccolo™ Microcontrollers data sheet
• Texas Instruments, TPS76333-Q1 Low-Power 150-mA Low-Dropout Linear Regulators data sheet
13.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 4. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
ISO7740-Q1
Click here
Click here
Click here
Click here
Click here
ISO7741-Q1
Click here
Click here
Click here
Click here
Click here
ISO7742-Q1
Click here
Click here
Click here
Click here
Click here
13.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.4 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.5 Trademarks
Piccolo, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
13.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
13.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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SLLSEU0C – NOVEMBER 2016 – REVISED FEBRUARY 2020
www.ti.com
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
34
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PACKAGE OPTION ADDENDUM
www.ti.com
6-Feb-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ISO7740FQDBQQ1
ACTIVE
SSOP
DBQ
16
75
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7740FQ
ISO7740FQDBQRQ1
ACTIVE
SSOP
DBQ
16
2500
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7740FQ
ISO7740FQDWQ1
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7740FQ
ISO7740FQDWRQ1
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7740FQ
ISO7740QDBQQ1
ACTIVE
SSOP
DBQ
16
75
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7740Q
ISO7740QDBQRQ1
ACTIVE
SSOP
DBQ
16
2500
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7740Q
ISO7740QDWQ1
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7740Q
ISO7740QDWRQ1
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7740Q
ISO7741FQDBQQ1
ACTIVE
SSOP
DBQ
16
75
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7741FQ
ISO7741FQDBQRQ1
ACTIVE
SSOP
DBQ
16
2500
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7741FQ
ISO7741FQDWQ1
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7741FQ
ISO7741FQDWRQ1
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7741FQ
ISO7741FQDWWQ1
ACTIVE
SOIC
DWW
16
45
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7741FQ
ISO7741FQDWWRQ1
ACTIVE
SOIC
DWW
16
1000
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7741FQ
ISO7741QDBQQ1
ACTIVE
SSOP
DBQ
16
75
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7741Q
ISO7741QDBQRQ1
ACTIVE
SSOP
DBQ
16
2500
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7741Q
ISO7741QDWQ1
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7741Q
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
6-Feb-2020
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ISO7741QDWRQ1
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7741Q
ISO7741QDWWQ1
ACTIVE
SOIC
DWW
16
45
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7741Q
ISO7741QDWWRQ1
ACTIVE
SOIC
DWW
16
1000
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7741Q
ISO7742FQDBQQ1
ACTIVE
SSOP
DBQ
16
75
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7742FQ
ISO7742FQDBQRQ1
ACTIVE
SSOP
DBQ
16
2500
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7742FQ
ISO7742FQDWQ1
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7742FQ
ISO7742FQDWRQ1
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7742FQ
ISO7742QDBQQ1
ACTIVE
SSOP
DBQ
16
75
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7742Q
ISO7742QDBQRQ1
ACTIVE
SSOP
DBQ
16
2500
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
7742Q
ISO7742QDWQ1
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7742Q
ISO7742QDWRQ1
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ISO7742Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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