ISO7821DWW

Product Folder Order Now Support & Community Tools & Software Technical Documents ISO7821, ISO7821F SLLSEM2F – NOVEMBER 2014 – REVISED MARCH 2016 ISO7821x High-Performance, 8000 VPK Reinforced Dual Channel Digital Isolator 1 Features 3 Description • • • • • The ISO7821 is a high-performance, dual-channel digital isolator with 8000 VPK isolation voltage. This device has reinforced isolation certifications according to VDE, CSA, CQC, and TUV. The isolator provides high electromagnetic immunity and low emissions at low power consumption, while isolating CMOS or LVCMOS digital I/O’s. Each isolation channel has a logic input and output buffer separated by silicon dioxide (SiO2) insulation barrier. ISO7821 has one forward and one reverse-direction channel. If the input power or signal is lost, default output is 'high' for the ISO7821 and 'low' for the ISO7821F device. Used in conjunction with isolated power supplies, this device prevents noise currents on a data bus or other circuits from entering the local ground and interfering with or damaging sensitive circuitry. Through innovative chip design and layout techniques, electromagnetic compatibility of ISO7821 has been significantly enhanced to ease system-level ESD, EFT, Surge and Emissions compliance. ISO7821 is available in 16-pin SOIC wide-body (DW) and extra-wide body (DWW) packages. The DWW package option comes with enable pins which can be used to put the respective outputs in high impedance for multi-master driving applications and to reduce power consumption. 1 • • • • • • • • Signaling Rate: Up to 100 Mbps Wide Supply Range: 2.25 V to 5.5 V 2.25 V to 5.5 V Level Translation Wide Temperature Range: –55°C to 125°C Low Power Consumption, Typical 1.8 mA per Channel at 1 Mbps Low Propagation Delay: 11 ns Typical (5 V Supplies) Industry leading CMTI(Min): ±100 kV/μs Robust Electromagnetic Compatibility (EMC) System-Level ESD, EFT, and Surge Immunity Low Emissions Isolation Barrier Life: > 25 Years SOIC-16 Wide Body (DW) and Extra-Wide Body (DWW) Package Options Safety and Regulatory Approvals: – 8000 VPK Reinforced Isolation per DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 – 5.7 kVRMS Isolation for 1 minute per UL 1577 – CSA Component Acceptance Notice 5A, IEC 60950-1 and IEC 60601-1 End Equipment Standards – CQC Certification per GB4943.1-2011 – TUV Certification per EN 61010-1 and EN 60950-1 – All DW Package Certifications Complete; DWW Package Certifications Complete per UL, TUV and Planned for VDE, CSA, and CQC Device Information(1) PART NUMBER ISO7821, ISO7821F Industrial Automation Motor Control Power Supplies Solar Inverters Medical Equipment Hybrid Electric Vehicles BODY SIZE (NOM) 10.30 mm x 7.50 mm Extra wide SOIC, 10.30 mm × 14.0 mm DWW (16) (1) For all available packages, see the orderable addendum at the end of the datasheet. spacer 2 Applications • • • • • • PACKAGE SOIC, DW (16) Simplified Schematic VCCI Isolation Capacitor VCCO INx OUTx ENx (DWW package only) GNDI GNDO (1) VCCI and GNDI are supply and ground connections respectively for the input channels. (2) VCCO and GNDO are supply and ground connections respectively for the output channels. 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. ISO7821, ISO7821F SLLSEM2F – NOVEMBER 2014 – REVISED MARCH 2016 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 7 8 1 1 1 2 5 6 Absolute Maximum Ratings ..................................... 6 ESD Ratings.............................................................. 6 Recommended Operating Conditions....................... 6 Thermal Information .................................................. 7 Power Dissipation Characteristics ............................ 7 Electrical Characteristics, 5 V ................................... 8 Electrical Characteristics, 3.3 V ................................ 9 Electrical Characteristics, 2.5 V .............................. 10 Switching Characteristics, 5 V ................................ 11 Switching Characteristics, 3.3 V ........................... 11 Switching Characteristics, 2.5 V ........................... 12 Typical Characteristics .......................................... 13 Parameter Measurement Information ................ 14 Detailed Description ............................................ 16 8.1 8.2 8.3 8.4 9 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 16 16 17 21 Application and Implementation ........................ 23 9.1 Application Information............................................ 23 9.2 Typical Application .................................................. 23 10 Power Supply Recommendations ..................... 25 11 Layout................................................................... 26 11.1 PCB Material ......................................................... 26 11.2 Layout Guidelines ................................................. 26 11.3 Layout Example .................................................... 26 12 Device and Documentation Support ................. 27 12.1 12.2 12.3 12.4 12.5 12.6 Documentation Support ........................................ Related Links ........................................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 27 27 27 27 27 27 13 Mechanical, Packaging, and Orderable Information ........................................................... 27 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (December 2015) to Revision F Page • Changed the Safety and Regulatory Approvals list of Features ........................................................................................... 1 • Added Features "TUV Certification per EN 61010-1 and EN 60950-1" ................................................................................ 1 • Changed text in the first paragraph of the Description From: "certifications according to VDE, CSA, and CQC". To: "certifications according to VDE, CSA, CQC, and TUV." ...................................................................................................... 1 • Added Note 1 to Table 2 ..................................................................................................................................................... 18 • Added TUV to the Regulatory Information section and Table 4. Deleted Note 1 in Table 4 .............................................. 19 • Changed Figure 15 .............................................................................................................................................................. 22 Changes from Revision D (July 2015) to Revision E Page • Changed Features From: 8000 VPK VIOTM and 2121 VPK VIORM Reinforced..To: 8000 VPK Reinforced.................................. 1 • Added Features: DW Package Certifications Complete; DWW Certifications Planned ........................................................ 1 • Added text to the Description: and extra-wide body (DWW) packages... .............................................................................. 1 • Added package: Extra wide SOIC, DWW (16) to the Device Information table .................................................................... 1 • Added the DWW pinout image .............................................................................................................................................. 5 • Added the DWW package to the Thermal Information .......................................................................................................... 7 • Changed the MIN value of CMTI in Electrical Characteristics, 5 V table From: 70 To: 100 kV/µs, deleted the TYP value of 100 kV/µs ................................................................................................................................................................. 8 • Added the DW package value to the Supply Current section of the Electrical Characteristics, 5 V ...................................... 8 • Added the DWW package value to the Supply Current section of the Electrical Characteristics, 5 V .................................. 8 • Changed the MIN value of CMTI in Electrical Characteristics, 3.3 V table From: 70 To: 100 kV/µs, deleted the TYP value of 100 kV/µs ................................................................................................................................................................. 9 • Added the DW package value to the Supply Current section of the Electrical Characteristics, 3.3 V ................................... 9 • Added the DWW package value to the Supply Current section of the Electrical Characteristics, 3.3 V .............................. 9 2 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ISO7821 ISO7821F ISO7821, ISO7821F www.ti.com SLLSEM2F – NOVEMBER 2014 – REVISED MARCH 2016 • Changed the MIN value of CMTI in Electrical Characteristics, 2.5 V table From: 70 To: 100 kV/µs, deleted the TYP value of 100 kV/µs ............................................................................................................................................................... 10 • Added the DW package value to the Supply Current section of the Electrical Characteristics, 2.5 V ................................. 10 • Added the DWW package value to the Supply Current section of the Electrical Characteristics, 2.5 V ............................ 10 • Added tPHZ, tPLZ, tPZH, and tPZL to Switching Characteristics, 3.3 V....................................................................................... 11 • Added tPHZ, tPLZ, tPZH, and tPZL to Switching Characteristics, 2.5 V....................................................................................... 12 • Added Figure 8 .................................................................................................................................................................... 14 • Added the DWW package to Table 1 ................................................................................................................................... 17 • Changed CIO typ value From: 2 To 1 pF in Table 1 ............................................................................................................ 17 • Added the DWW package to Table 2 ................................................................................................................................... 18 • Changed Parameter information and added the DWW package information in Table 3 .................................................... 18 • Added the DWW package information to Table 4 ................................................................................................................ 19 • added DWW-16 package options to Table 5 ...................................................................................................................... 20 • Changed Table 6 ................................................................................................................................................................. 21 • Added text to the Application Information section: "isolation voltage per UL 1577." ........................................................... 23 Changes from Revision C (May 2015) to Revision D Page • Added device ISO7821F to the datasheet ............................................................................................................................ 1 • Changed the Description to include: "default output is 'high' for the ISO7821 device and 'low' for the ISO7821F device. ................................................................................................................................................................................... 1 • Changed the Simplified Schematic ........................................................................................................................................ 1 • Changed tPLH and tPHL From: 5.5 V to 5 V in Figure 6 ......................................................................................................... 13 • Changed Figure 9 ................................................................................................................................................................ 15 • Changed the Functional Block Diagram .............................................................................................................................. 16 • Changed Table 1 title From: IEC Insulation and Safety-Related Specifications for DW-16 Package To: Package Insulation and Safety-Related Specifications ...................................................................................................................... 17 • Changed Figure 13 , Added Figure 14 ................................................................................................................................. 20 Changes from Revision B (April 2015) to Revision C Page • Changed From: VCC1 and VCC2 To: VCCI and VCCO, GND1 and GND2 To: GNDI and GNDO and added Notes 1 and 2 in the Simplified Schematic ................................................................................................................................................ 1 • Changed the MIN value of CMTI in Electrical Characteristics, 5 V table From: 50 To: 70 kV/µs ......................................... 8 • Changed the MIN value of CMTI in Electrical Characteristics, 3.3 V table From: 50 To: 70 kV/µs ...................................... 9 • Changed the MIN value of CMTI in Electrical Characteristics, 2.5 V table From: 50 To: 70 kV/µs .................................... 10 • Added sentence "If the EN pin is available and low then the output goes to high impedance." to the Overview section ................................................................................................................................................................................. 16 • Changed the Functional Block Diagram to include the EN pin on the Receiver side .......................................................... 16 • Changed the Installation classification of the Table 3 to include DW package information ................................................. 18 • Changed "ISO782W functional modes" To: "ISO7821DW functional modes" in Device Functional Modes........................ 21 • Changed Table 6 title From: "Functional Table" To: "ISO7821DW Function Table"............................................................ 21 • Added the Device I/O Schematics section .......................................................................................................................... 22 • Changed device number ISO7821 To: ISO7821DW in Figure 17 ....................................................................................... 24 Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ISO7821 ISO7821F Submit Documentation Feedback 3 ISO7821, ISO7821F SLLSEM2F – NOVEMBER 2014 – REVISED MARCH 2016 www.ti.com Changes from Revision A (December 2014) to Revision B Page • Changed the document title From: "Channel Digital Isolator" To: "Channel 1/1 Digital Isolator" .......................................... 1 • Added Features: 2.25 V to 5.5 V Level Translation ............................................................................................................... 1 • Changed the Safety and Regulatory Approvals list of Features ........................................................................................... 1 • Changed text in the Description From: "This device is being reviewed for reinforced isolation certification by VDE and CSA. To: "This device has reinforced isolation certifications according to VDE, CSA, and CQC." ................................ 1 • Added Note (3) to the Absolute Maximum Ratings (1) table .................................................................................................... 6 • Changed From: VCCX To: VCCO In IOH and IOL of the Recommended Operating Conditions table ........................................ 6 • Changed From: VCCX To: VCCI In VIH and VIL of the Recommended Operating Conditions table ......................................... 6 • Changed Note (1) of the Recommended Operating Conditions table ................................................................................... 6 • Added the Power Dissipation Characteristics table ............................................................................................................... 7 • Changed From: VCCX To: VCCO In VOH of the Electrical Characteristics, 5 V table ................................................................ 8 • Changed From: VCCX To: VCCO In VI(HYS) of the Electrical Characteristics, 5 V table ............................................................ 8 • Changed From: VCCX To: VCCI In IIH of the Electrical Characteristics, 5 V table .................................................................... 8 • Changed From: VCCX To: VCCI In CMTI of the Electrical Characteristics, 5 V table .............................................................. 8 • Changed From: VCCX To: VCCI In Supply Current, DC Signal of the Electrical Characteristics, 5 V table.............................. 8 • Changed Note (1) of the Electrical Characteristics, 5 V table ............................................................................................... 9 • Changed From: VCCX To: VCCO In VOH of the Electrical Characteristics, 3.3 V table ............................................................. 9 • Changed From: VCCX To: VCCO In VI(HYS) of the Electrical Characteristics, 3.3 V table ......................................................... 9 • Changed From: VCCX To: VCCI In IIH of the Electrical Characteristics, 3.3 V table.................................................................. 9 • Changed From: VCCX To: VCCI In CMTI of the Electrical Characteristics, 3.3 V table ........................................................... 9 • Changed From: VCCX To: VCCI In Supply Current, DC Signal of the Electrical Characteristics, 3.3 V table .......................... 9 • Changed Note (1) of the Electrical Characteristics, 3.3 V table .......................................................................................... 10 • Changed From: VCCX To: VCCO In VOH of the Electrical Characteristics, 2.5 V table ........................................................... 10 • Changed From: VCCX To: VCCI In IIH of the Electrical Characteristics, 2.5 V table ............................................................... 10 • Changed From: VCCX To: VCCI In Supply Current, DC Signal of the Electrical Characteristics, 2.5 V table ........................ 10 • Changed Note (1) of the Electrical Characteristics, 2.5 V table .......................................................................................... 11 • Changed Figure 7 ................................................................................................................................................................ 14 • Changed From: VCC1 To: VCCI in Figure 9 ........................................................................................................................... 15 • Changed Figure 10 .............................................................................................................................................................. 15 • Changed the Test Condition of CTI in Table 1 .................................................................................................................... 17 • Changed the MIN value of CTI From" > 600 V To: 600 V.................................................................................................... 17 • Changed Table 2 title From: DIN V VDE 0884-10 (VDE V 0884-10) and UL 1577 Insulation Characteristics To: Added the DWW package to ................................................................................................................................................ 18 • Changed Table 2 ................................................................................................................................................................. 18 • Changed columns VDE and CSA to Table 4 ....................................................................................................................... 19 • Changed title From: IEC Safety Limiting Values To: Safety Limiting Values ....................................................................... 20 • Changed the table in Safety Limiting Values, added IS DW-16 package options ................................................................ 20 • Changed Figure 13 .............................................................................................................................................................. 20 • Deleted INPUT-SIDE and OUTPUT-SIDE from columns 1 and 2 of Table 6 ..................................................................... 21 • Changed Note (1) of Table 6 ............................................................................................................................................... 21 • Changed the Application Information section ....................................................................................................................... 23 • Changed the Typical Application section and Figure 16 ...................................................................................................... 23 • Added text and Figure 17 to the Detailed Design Procedure section ................................................................................. 24 4 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ISO7821 ISO7821F ISO7821, ISO7821F www.ti.com SLLSEM2F – NOVEMBER 2014 – REVISED MARCH 2016 Changes from Original (November 2014) to Revision A Page • Changed From: A product preview that included only page 1 and the pinout section To: A complete data sheet .............. 1 • Added Note: "This coupler..." to the High Voltage Feature Description section ................................................................. 17 Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ISO7821 ISO7821F Submit Documentation Feedback 5 ISO7821, ISO7821F SLLSEM2F – NOVEMBER 2014 – REVISED MARCH 2016 www.ti.com 5 Pin Configuration and Functions DW Package 16-Pin (SOIC) Top View GND1 1 DWW Package 16-Pin (SOIC) Top View 16 GND2 VCC1 NC 2 15 VCC1 3 14 VCC2 1 16 VCC2 NC INB 5 NC 6 13 3 EN1 4 INA 12 OUTB OUTA 5 11 GND1 7 NC NC 10 8 15 GND2 ISOLATION OUTA 4 ISOLATION GND1 2 14 NC 13 EN2 12 INA NC INB 6 11 OUTB NC 7 10 NC NC 9 GND2 GND1 8 9 GND2 Pin Functions PIN NAME NO. NO. DW DWW I/O DESCRIPTION GND1 1, 7 2,8 – Ground connection for VCC1 GND2 9, 16 9,15 – Ground connection for VCC2 INA 13 12 I Input, channel A INB 5 6 I Input, channel B NC 2, 6, 8, 10 ,11, 15 3,7,10,14 – Not connected OUTA 4 5 O Output, channel A OUTB 12 11 O Output, channel B VCC1 3 1 – Power supply, VCC1 VCC2 14 16 – Power supply, VCC2 EN1 – 4 I Output enable 1. Output pins on side 1 are enabled when EN1 is high or open and in high-impedance state when EN1 is low. EN2 – 13 I Output enable 2. Output pins on side 2 are enabled when EN2 is high or open and in high-impedance state when EN2 is low. 6 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ISO7821 ISO7821F ISO7821, ISO7821F www.ti.com SLLSEM2F – NOVEMBER 2014 – REVISED MARCH 2016 6 Specifications 6.1 Absolute Maximum Ratings (1) MIN MAX Supply voltage (2) VCC1, VCC2 –0.5 6 Voltage INx, OUTx –0.5 VCC + 0.5 (3) Output Current IO -15 15 mA 12.8 kV 150 °C Surge Immunity Storage temperature, Tstg (1) (2) (3) –65 UNIT V V Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak voltage values. Maximum voltage must not exceed 6 V. 6.2 ESD Ratings VESD (1) (2) Electrostatic discharge VALUE UNIT Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) ±6000 V Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) ±1500 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions MIN VCC1, VCC2 Supply voltage VCCO IOH IOL TYP 2.25 High-level output current Low-level output current (1) =5V -4 VCCO = 3.3 V -2 VCCO = 2.5 V -1 MAX UNIT 5.5 V mA VCCO = 5 V 4 VCCO = 3.3 V 2 VCCO = 2.5 V 1 mA VIH High-level input voltage 0.7 x VCCI (1) VCCI VIL Low-level input voltage 0 0.3 x VCCI DR Signaling rate 0 100 Mbps TJ Junction temperature (2) -55 150 °C TA Ambient temperature -55 125 °C (1) (2) 25 V V VCCI = Input-side VCC; VCCO = Output-side VCC. To maintain the recommended operating conditions for TJ, see the Thermal Information table. Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ISO7821 ISO7821F Submit Documentation Feedback 7 ISO7821, ISO7821F SLLSEM2F – NOVEMBER 2014 – REVISED MARCH 2016 www.ti.com 6.4 Thermal Information ISO7821 THERMAL METRIC (1) DW (SOIC) DWW (SOIC) 16 PINS 16-PINS UNIT RθJA Junction-to-ambient thermal resistance 84.7 84.7 °C/W RθJC(top) Junction-to-case(top) thermal resistance 47.3 46.0 °C/W RθJB Junction-to-board thermal resistance 49.4 54.5 °C/W ψJT Junction-to-top characterization parameter 19.1 18.5 °C/W ψJB Junction-to-board characterization parameter 48.8 53.8 °C/W RθJC(bottom) Junction-to-case(bottom) thermal resistance n/a n/a °C/W (1) For more information about trdational and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 6.5 Power Dissipation Characteristics VALUE PD Maximum power dissipation by ISO7821x PD1 Maximum power dissipation by side-1 of ISO7821x PD2 Maximum power dissipation by side-2 of ISO7821x 8 Submit Documentation Feedback UNIT 100 VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF, input a 50 MHz 50% duty cycle square wave 50 mW 50 Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ISO7821 ISO7821F ISO7821, ISO7821F www.ti.com SLLSEM2F – NOVEMBER 2014 – REVISED MARCH 2016 6.6 Electrical Characteristics, 5 V VCC1 = VCC2 = 5 V ± 10% (over recommended operating conditions unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP VCCO (1) – 0.4 VCCO – 0.2 VOH High-level output voltage IOH = –4 mA; see Figure 7 VOL Low-level output voltage IOL = 4 mA; see Figure 7 VI(HYS) Input threshold voltage hysteresis IIH High-level input current VIH = VCCI (1) at INx or ENx IIL Low-level input current VIL = 0 V at INx or ENx -10 CMTI Common-mode transient immunity VI = VCCI or 0 V; see Figure 10 100 0.2 MAX UNIT V 0.4 0.1 x VCCO (1) V V 10 μA kV/μs Supply Current - ISO7821DW and ISO7821FDW ICC1, ICC2 DC Signal VI = 0 V (ISO7821F) , VI = VCCI (1)(ISO7821) 1.2 1.7 mA ICC1, ICC2 DC Signal VI = VCCI (1) (ISO7821F) , VI = 0 V (ISO7821) 2.4 3.4 mA ICC1, ICC2 1 Mbps 1.8 2.6 mA ICC1, ICC2 10 Mbps 2.4 3.2 mA ICC1, ICC2 100 Mbps 7.5 9.3 mA 0.7 1.1 mA All channels switching with square wave clock input; CL = 15 pF Supply Current - ISO7821DWW and ISO7821FDWW ICC1, ICC2 EN1 = EN2 = 0V, VI = 0 V (ISO7821F) , VI = VCCI (1)(ISO7821) Disable (1) ICC1, ICC2 Disable EN1 = EN2 = 0V, VI = VCCI (ISO7821F) , VI = 0 V (ISO7821) 1.8 2.9 mA ICC1, ICC2 DC Signal VI = 0 V (ISO7821F) , VI = VCCI (1)(ISO7821) 1.2 1.7 mA 2.4 3.5 mA 1.9 2.7 mA 2.5 3.2 mA 7.7 9.3 mA (1) ICC1, ICC2 DC Signal ICC1, ICC2 1 Mbps ICC1, ICC2 10 Mbps ICC1, ICC2 100 Mbps (1) VI = VCCI (ISO7821F) , VI = 0 V (ISO7821) All channels switching with square wave clock input; CL = 15 pF VCCI = Input-side VCC; VCCO = Output-side VCC. Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ISO7821 ISO7821F Submit Documentation Feedback 9 ISO7821, ISO7821F SLLSEM2F – NOVEMBER 2014 – REVISED MARCH 2016 www.ti.com 6.7 Electrical Characteristics, 3.3 V VCC1 = VCC2 = 3.3 V ± 10% (over recommended operating conditions unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP VCCO (1) – 0.4 VCCO – 0.2 VOH High-level output voltage IOH = –2 mA; see Figure 7 VOL Low-level output voltage IOL = 2 mA; see Figure 7 VI(HYS) Input threshold voltage hysteresis IIH High-level input current VIH = VCCI (1) at INx or ENx IIL Low-level input current VIL = 0 V at INx or ENx -10 CMTI Common-mode transient immunity VI = VCCI or 0 V; see Figure 10 100 0.2 MAX UNIT V 0.4 0.1 x VCCO V V 10 μA kV/μs Supply Current - ISO7821DW and ISO7821FDW ICC1, ICC2 DC Signal VI = 0 V (ISO7821F) , VI = VCCI (1)(ISO7821) 1.2 1.7 mA ICC1, ICC2 DC Signal VI = VCCI (1) (ISO7821F) , VI = 0 V (ISO7821) 2.4 3.4 mA ICC1, ICC2 1 Mbps 1.8 2.6 mA 2.2 3 mA 5.8 7.1 mA 0.7 1.1 mA ICC1, ICC2 10 Mbps ICC1, ICC2 100 Mbps All channels switching with square wave clock input; CL = 15 pF Supply Current - ISO7821DWW and ISO7821FDWW ICC1, ICC2 Disable EN1 = EN2 = 0V, VI = 0 V (ISO7821F) , VI = VCCI (1)(ISO7821) (1) ICC1, ICC2 Disable EN1 = EN2 = 0V, VI = VCCI (ISO7821F) , VI = 0 V (ISO7821) 1.8 2.9 mA ICC1, ICC2 DC Signal VI = 0 V (ISO7821F) , VI = VCCI (1)(ISO7821) 1.2 1.7 mA 2.4 3.5 mA 1.9 2.6 mA 2.3 3 mA 5.9 7.1 mA (1) ICC1, ICC2 DC Signal ICC1, ICC2 1 Mbps ICC1, ICC2 10 Mbps ICC1, ICC2 100 Mbps (1) 10 VI = VCCI (ISO7821F) , VI = 0 V (ISO7821) All channels switching with square wave clock input; CL = 15 pF VCCI = Input-side VCC; VCCO = Output-side VCC. Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ISO7821 ISO7821F ISO7821, ISO7821F www.ti.com SLLSEM2F – NOVEMBER 2014 – REVISED MARCH 2016 6.8 Electrical Characteristics, 2.5 V VCC1 = VCC2 = 2.5 V ± 10% (over recommended operating conditions unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP VCCO (1) – 0.4 VCCO – 0.2 VOH High-level output voltage IOH = –1 mA; see Figure 7 VOL Low-level output voltage IOL = 1 mA; see Figure 7 VI(HYS) Input threshold voltage hysteresis IIH High-level input current VIH = VCCI (1) at INx or ENx IIL Low-level input current VIL = 0 V at INx or ENx -10 CMTI Common-mode transient immunity VI = VCCI or 0 V; see Figure 10 100 0.2 MAX UNIT V 0.4 0.1 x VCCO V V 10 μA kV/μs Supply Current - ISO7821DW and ISO7821FDW ICC1, ICC2 DC Signal VI = 0 V (ISO7821F) , VI = VCCI (1)(ISO7821) 1.2 1.7 mA ICC1, ICC2 DC Signal VI = VCCI (1) (ISO7821F) , VI = 0 V (ISO7821) 2.4 3.4 mA ICC1, ICC2 1 Mbps 1.8 2.6 mA 2.1 2.8 mA 4.9 5.9 mA 0.7 1.1 mA ICC1, ICC2 10 Mbps ICC1, ICC2 100 Mbps All channels switching with square wave clock input; CL = 15 pF Supply Current - ISO7821DWW and ISO7821FDWW ICC1, ICC2 EN1 = EN2 = 0V, VI = 0 V (ISO7821F) , VI = VCCI (1)(ISO7821) Disable (1) ICC1, ICC2 Disable EN1 = EN2 = 0V, VI = VCCI (ISO7821F) , VI = 0 V (ISO7821) 1.8 2.9 mA ICC1, ICC2 DC Signal VI = 0 V (ISO7821F) , VI = VCCI (1)(ISO7821) 1.2 1.7 mA 2.4 3.5 mA 1.9 2.6 mA 2.2 2.9 mA 5 6 mA (1) ICC1, ICC2 DC Signal ICC1, ICC2 1 Mbps ICC1, ICC2 10 Mbps ICC1, ICC2 100 Mbps (1) VI = VCCI (ISO7821F) , VI = 0 V (ISO7821) All channels switching with square wave clock input; CL = 15 pF VCCI = Input-side VCC; VCCO = Output-side VCC. Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ISO7821 ISO7821F Submit Documentation Feedback 11 ISO7821, ISO7821F SLLSEM2F – NOVEMBER 2014 – REVISED MARCH 2016 www.ti.com 6.9 Switching Characteristics, 5 V VCC1 = VCC2 = 5 V ± 10% (over recommended operating conditions unless otherwise noted) PARAMETER tPLH, tPHL Propagation delay time PWD (1) Pulse width distortion |tPHL – tPLH| tsk(pp) (2) See Figure 7 MIN TYP MAX 6 10.7 16 0.6 4.6 Part-to-part skew time tr Output signal rise time tf Output signal fall time tPHZ tPLZ 4.5 tfs ns 2.4 3.9 Disable propagation delay, high-to-high impedance output for ISO7821DWW and ISO7821FDWW 12 20 ns Disable propagation delay, low-to-high impedance output for ISO7821DWW and ISO7821FDWW 12 20 ns 10 20 ns 2 2.5 μs Enable propagation delay, high impedance-to-low output for ISO7821DWW 2 2.5 μs Enable propagation delay, high impedance-to-low output for ISO7821FDWW 10 20 ns 0.2 9 μs See Figure 7 Default output delay time from input power loss tie ns 3.9 Enable propagation delay, high impedance-to-high output for ISO7821FDWW tPZL UNIT 2.4 Enable propagation delay, high impedance-to-high output for ISO7821DWW tPZH (1) (2) TEST CONDITIONS See Figure 8 Measured from the time VCC goes below 1.7 V. See Figure 9 16 Time interval error ns 2 1 - 1 PRBS data at 100 Mbps ns Also known as Pulse Skew. tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads. 6.10 Switching Characteristics, 3.3 V VCC1 = VCC2 = 3.3 V ± 10% (over recommended operating conditions unless otherwise noted) PARAMETER tPLH, tPHL Propagation delay time PWD (1) Pulse width distortion |tPHL – tPLH| tsk(pp) (2) Output signal rise time tf Output signal fall time tPHZ tPLZ tPZL See Figure 7 MAX 10.8 16 0.7 4.7 UNIT ns 4.5 3 1.3 3 Disable propagation delay, high-to-high impedance output for ISO7821DWW and ISO7821FDWW 17 32 ns Disable propagation delay, low-to-high impedance output for ISO7821DWW and ISO7821FDWW 17 32 ns 17 32 ns 2 2.5 μs Enable propagation delay, high impedance-to-low output for ISO7821DWW 2 2.5 μs Enable propagation delay, high impedance-to-low output for ISO7821FDWW 17 32 ns 0.2 9 μs See Figure 7 Enable propagation delay, high impedance-to-high output for ISO7821DWW Enable propagation delay, high impedance-to-high output for ISO7821FDWW ns See Figure 8 Default output delay time from input power loss Measured from the time VCC goes below 1.7 V. See Figure 9 tie Time interval error 216 - 1 PRBS data at 100 Mbps 12 TYP 6 1.3 tfs (1) (2) MIN Part-to-part skew time tr tPZH TEST CONDITIONS 1 ns Also known as Pulse Skew. tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads. Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ISO7821 ISO7821F ISO7821, ISO7821F www.ti.com SLLSEM2F – NOVEMBER 2014 – REVISED MARCH 2016 6.11 Switching Characteristics, 2.5 V VCC1 = VCC2 = 2.5 V ± 10% (over recommended operating conditions unless otherwise noted) PARAMETER tPLH, tPHL Propagation delay time PWD (1) Pulse width distortion |tPHL – tPLH| tsk(pp) (2) Output signal rise time tf Output signal fall time tPHZ tPLZ tPZL tfs tie (1) (2) See Figure 7 MIN TYP MAX 7.5 11.7 17.5 0.7 4.7 Part-to-part skew time tr tPZH TEST CONDITIONS UNIT ns 4.5 1.8 3.5 1.8 3.5 Disable propagation delay, high-to-high impedance output for ISO7821DWW and ISO7821FDWW 22 45 ns Disable propagation delay, low-to-high impedance output for ISO7821DWW and ISO7821FDWW 22 45 ns 18 45 ns 2 2.5 μs Enable propagation delay, high impedance-to-low output for ISO7821DWW 2 2.5 μs Enable propagation delay, high impedance-to-low output for ISO7821FDWW 18 45 ns 0.2 9 μs See Figure 7 Enable propagation delay, high impedance-to-high output for ISO7821DWW Enable propagation delay, high impedance-to-high output for ISO7821FDWW Default output delay time from input power loss See Figure 8 Measured from the time VCC goes below 1.7 V. See Figure 9 16 Time interval error ns 2 - 1 PRBS data at 100 Mbps 1 ns Also known as Pulse Skew. tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads. Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ISO7821 ISO7821F Submit Documentation Feedback 13 ISO7821, ISO7821F SLLSEM2F – NOVEMBER 2014 – REVISED MARCH 2016 www.ti.com 6.12 Typical Characteristics 24 10 ICC1 at 2.5 V ICC2 at 2.5 V ICC1 at 3.3 V ICC2 at 3.3 V ICC1 at 5.0 V ICC2 at 5.0 V 16 ICC1 at 2.5 V ICC2 at 2.5 V ICC1 at 3.3 V ICC2 at 3.3 V ICC1 at 5.0 V ICC2 at 5.0 V 8 Supply Current (mA) Supply Current (mA) 20 12 8 6 4 2 4 0 0 0 25 50 TA = 25°C 75 100 Data Rate (Mbps) 125 150 0 CL = 15 pF 125 150 D002 CL = No Load 1.0 VCC at 2.5V VCC at 3.3V VCC at 5.0V 0.9 5 Low-Level Output Voltage (V) High-Level Output Voltage (V) 75 100 Data Rate (Mbps) Figure 2. Supply Current vs Data Rate (with No Load) 6 4 3 2 VCC at 2.5V VCC at 3.3V VCC at 5.0V 1 0 -15 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 -10 -5 High-Level Output Current (mA) 0 0 15 VCC1 Rising VCC1 Falling VCC2 Rising VCC2 Falling 14 Propagation Delay Time (ns) 2.10 D001 Figure 4. Low-Level Output Voltage vs Low-Level Output Current 2.25 2.15 15 TA = 25°C Figure 3. High-Level Output Voltage vs High-level Output Current 2.20 5 10 Low-Level Output Current (mA) D001 TA = 25°C Power Supply Under Voltage Threshold (V) 50 TA = 25°C Figure 1. Supply Current vs Data Rate (with 15 pF Load) 2.05 2.00 1.95 1.90 1.85 1.80 13 12 11 10 9 7 6 1.70 -50 5 -60 0 50 100 Free-Air Temperature (oC ) 150 Submit Documentation Feedback tPLH at 2.5 V tPHL at 2.5 V tPHL at 3.3 V tPLH at 3.3 V tPLH at 5 V tPHL at 5 V 8 1.75 -30 D001 Figure 5. Power Supply Undervoltage Threshold vs Free-Air Temperature 14 25 D001 0 30 60 Free-Air Temperature (oC ) 90 120 D006 Figure 6. Propagation Delay Time vs Free-Air Temperature Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ISO7821 ISO7821F ISO7821, ISO7821F www.ti.com SLLSEM2F – NOVEMBER 2014 – REVISED MARCH 2016 7 Parameter Measurement Information Isolation Barrier IN Input Generator (See Note A) VI VCCI 50 VI OUT 50% 50% 0V tPLH tPHL CL See Note B VO VOH 90% 50% VO 50% 10% VOL tf tr Copyright © 2016, Texas Instruments Incorporated A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3ns, ZO = 50 Ω. At the input, 50 Ω resistor is required to terminate Input Generator signal. It is not needed in actual application. B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 7. Switching Characteristics Test Circuit and Voltage Waveforms VCCO VCC Isolation Barrier IN Input Generator (See Note A) VI Input Generator (See Note A) VO tPZL 0V tPLZ VOH EN 0.5 V VO 50% VOL 50 OUT VCC VO VCC / 2 VCC / 2 VI 0V tPZH EN CL See Note B VI VCC / 2 VCC / 2 VI CL See Note B IN 3V ±1% OUT Isolation Barrier 0V RL = 1 k RL = 1 k ±1% VOH VO 50% 0.5 V tPHZ 50 0V Copyright © 2016, Texas Instruments Incorporated A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 10 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω. B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 8. Enable/Disable Propagation Delay Time Test Circuit and Waveform Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ISO7821 ISO7821F Submit Documentation Feedback 15 ISO7821, ISO7821F SLLSEM2F – NOVEMBER 2014 – REVISED MARCH 2016 www.ti.com Parameter Measurement Information (continued) VI VCC VCC Isolation Barrier IN = 0 V (Devices without suffix F) IN = VCC (Devices with suffix F) IN 2.7 V VI OUT 0V t fs VO fs high VO CL VOH 50% fs low V OL See Note A Copyright © 2016, Texas Instruments Incorporated A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 9. Default Output Delay Time Test Circuit and Voltage Waveforms VCCO VCCI S1 Isolation Barrier C = 0.1 µF ±1% IN C = 0.1 µF ±1% Pass-fail criteria: The output must remain stable. OUT + EN VOH or VOL CL See Note A GNDI + VCM ± ± GNDO Copyright © 2016, Texas Instruments Incorporated A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 10. Common-Mode Transient Immunity Test Circuit 16 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ISO7821 ISO7821F ISO7821, ISO7821F www.ti.com SLLSEM2F – NOVEMBER 2014 – REVISED MARCH 2016 8 Detailed Description 8.1 Overview ISO7821 employs an ON-OFF Keying (OOK) modulation scheme to transmit the digital data across a silicon dioxide based isolation barrier. The transmitter sends a high frequency carrier across the barrier to represent one digital state and sends no signal to represent the other digital state. The receiver demodulates the signal after advanced signal conditioning and produces the output through a buffer stage. These devices also incorporates advanced circuit techniques to maximize the CMTI performance and minimize the radiated emissions due the high frequency carrier and IO buffer switching. The conceptual block diagram of a digital capacitive isolator, Figure 11, shows a functional block diagram of a typical channel. 8.2 Functional Block Diagram Transmitter Receiver EN TX IN OOK Modulation TX Signal Conditioning Oscillator SiO2 based Capacitive Isolation Barrier RX Signal Conditioning RX OUT Envelope Detection Emissions Reduction Techniques Copyright © 2016, Texas Instruments Incorporated Figure 11. Conceptual Block Diagram of a Digital Capacitive Isolator Also a conceptual detail of how the ON/OFF Keying scheme works is shown in Figure 12. TX IN Carrier signal through isolation barrier RX OUT Figure 12. On-Off Keying (OOK) Based Modulation Scheme Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ISO7821 ISO7821F Submit Documentation Feedback 17 ISO7821, ISO7821F SLLSEM2F – NOVEMBER 2014 – REVISED MARCH 2016 www.ti.com 8.3 Feature Description ISO7821 is available in two channel configurations and default output state options to enable a variety of application uses. PRODUCT CHANNEL DIRECTION MAX DATA RATE DEFAULT OUTPUT ISO7821 1 Forward, 1 Reverse 5700 VRMS / 8000 VPK (1) 100 Mbps High ISO7821F 1 Forward, 1 Reverse 5700 VRMS / 8000 VPK (1) 100 Mbps Low (1) RATED ISOLATION See the Regulatory Information section for detailed isolation ratings. 8.3.1 High Voltage Feature Description NOTE This coupler is suitable for 'safe electrical insulation' only within the safety ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits. Table 1. Package Insulation and Safety-Related Specifications (over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN CLR External clearance Shortest terminal-to-terminal distance through air DW-16 CPG External creepage Shortest terminal-to-terminal distance across the package surface DW-16 CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112; UL 746A DWW-16 DWW-16 TYP MAX 8 UNIT mm 14.5 8 mm 14.5 600 V 12 Ω VIO = 500 V, TA = 25°C 10 VIO = 500 V, 100°C ≤ TA ≤ max 1011 RIO Isolation resistance, input to output (1) CIO Barrier capacitance, input to output (1) VIO = 0.4 x sin (2πft), f = 1 MHz 1 pF CI Input capacitance (2) 2 pF (1) (2) VI = VCC/2 + 0.4 x sin (2πft), f = 1 MHz, VCC = 5 V Ω All pins on each side of the barrier tied together creating a two-terminal device. Measured from input pin to ground. NOTE Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications. 18 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ISO7821 ISO7821F ISO7821, ISO7821F www.ti.com SLLSEM2F – NOVEMBER 2014 – REVISED MARCH 2016 Table 2. Insulation Characteristics PARAMETER TEST CONDITIONS SPECIFICATION DW DTI Distance through the insulation Minimum internal gap (internal clearance) VIOWM Maximum working isolation voltage Time dependent dielectric breakdown (TDDB) test UNIT DWW 21 21 μm 1500 2000 VRMS 2121 2828 VDC DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 VIOTM Maximum transient isolation voltage VTEST = VIOTM t = 60 sec (qualification) t= 1 sec (100% production) 8000 8000 VPK VIOSM Maximum surge isolation voltage Test method per IEC 60065, 1.2/50 µs waveform, VTEST = 1.6 x VIOSM = 12800 VPK (1) (qualification) 8000 8000 VPK VIORM Maximum repetitive peak isolation voltage 2121 2828 VPK Method a, After Input/Output safety test subgroup 2/3, VPR = VIORM x 1.2, t = 10 s, Partial discharge < 5 pC 2545 3394 Method a, After environmental tests subgroup 1, VPR = VIORM x 1.6, t = 10 s, Partial Discharge < 5 pC 3394 4525 Method b1,After environmental tests subgroup 1, VPR = VIORM x 1.875, t = 1 s (100% Production test) Partial discharge < 5 pC 3977 5303 VIO = 500 V at TS >109 >109 Pollution degree 2 2 Climatic category 55/125/21 55/125/21 5700 5700 VPR Input-to-output test voltage RS Isolation resistance VPK Ω UL 1577 VISO (1) Withstanding isolation voltage VTEST = VISO = 5700 VRMS, t = 60 sec (qualification); VTEST = 1.2 x VISO = 6840 VRMS , t = 1 sec (100% production) VRMS Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier. Table 3. IEC 60664-1 Ratings Table PARAMETER TEST CONDITIONS Material group Overvoltage category / Installation classification SPECIFICATION I Rated mains voltage ≤ 600 VRMS DW package DWW package I–IV Rated mains voltage ≤ 1000 VRMS I–III Rated mains voltage ≤ 1000 VRMS I–IV Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ISO7821 ISO7821F Submit Documentation Feedback 19 ISO7821, ISO7821F SLLSEM2F – NOVEMBER 2014 – REVISED MARCH 2016 www.ti.com 8.3.1.1 Regulatory Information DW package certifications are complete; DWW package certifications completed for UL and TUV and planned for VDE, CSA, and CQC. Table 4. Regulatory Information VDE Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):200612 and DIN EN 60950-1 (VDE 0805 Teil 1):201101 CSA UL Approved under CSA Component Acceptance Notice 5A, IEC 60950-1 and IEC 60601-1 Recognized under UL 1577 Component Recognition Program Reinforced insulation per CSA 60950-1-07+A1+A2 and IEC 60950-1 2nd Ed., Reinforced insulation 800 VRMS (DW package) Maximum transient and 1450 VRMS (DWW isolation voltage, 8000 package) max working VPK; voltage (pollution degree Maximum repetitive peak 2, material group I); isolation voltage, 2121 2 MOPP (Means of VPK (DW), 2828 VPK Patient Protection) per (DWW); Maximum surge isolation CSA 60601-1:14 and IEC 60601-1 Ed. 3.1, voltage, 8000 VPK 250 VRMS (354 VPK) max working voltage (DW package) Single protection, 5700 VRMS Certificate number: 40040142 File number: E181974 20 Master contract number: 220991 Submit Documentation Feedback CQC Certified according to GB 4943.1-2011 Reinforced Insulation, Altitude ≤ 5000 m, Tropical Climate, 250 VRMS maximum working voltage Certificate number: CQC15001121716 TUV Certified according to EN 61010-1:2010 (3rd Ed) and EN 60950-1:2006/A11:2009/ A1:2010/A12:2011/A2:2013 5700 VRMS Reinforced insulation per EN 61010-1:2010 (3rd Ed) up to working voltage of 600 VRMS (DW package) and 1000 VRMS (DWW package) 5700 VRMS Reinforced insulation per EN 60950-1:2006/A11:2009/ A1:2010/A12:2011/A2:2013 up to working voltage of 800 VRMS (DW package) and 1450 VRMS (DWW package) Client ID number: 77311 Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ISO7821 ISO7821F ISO7821, ISO7821F www.ti.com SLLSEM2F – NOVEMBER 2014 – REVISED MARCH 2016 8.3.1.2 Safety Limiting Values Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier potentially leading to secondary system failures. Table 5. Safety Limiting PARAMETER TEST CONDITIONS Safety input, output, or supply current for DW-16 package and DWW-16 Packages IS PS Safety input, output, or total power TS Maximum safety temperature MIN TYP MAX RθJA = 84.7°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C 268 RθJA = 84.7°C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C 410 RθJA = 84.7°C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C 537 RθJA = 84.7°C/W, TJ = 150°C, TA = 25°C UNIT mA mW 1476 150 °C The maximum safety temperature is the maximum junction temperature specified for the device. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information is that of a device installed on a High-K test board for Leaded Surface Mount Packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance. 1600 Power VCC1 = VCC2 = 2.75 V VCC1 = VCC2 = 3.6 V VCC1 = VCC2 = 5.5 V 500 1400 Safety Limiting Power (mW) Safety Limiting Current (mA) 600 400 300 200 100 1200 1000 800 600 400 200 0 0 0 50 100 150 Ambient Temperature (qC) 200 0 D014 Figure 13. Thermal Derating Curve for Safety Limiting Current per VDE 50 100 150 Ambient Temperature (qC) 200 D015 Figure 14. Thermal Derating Curve for Safety Limiting Power per VDE Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ISO7821 ISO7821F Submit Documentation Feedback 21 ISO7821, ISO7821F SLLSEM2F – NOVEMBER 2014 – REVISED MARCH 2016 www.ti.com 8.4 Device Functional Modes ISO7821 functional modes are shown in Table 6. Table 6. ISO7821 Function Table (1) VCCI PU X (1) (2) (3) 22 VCCO INPUT (INx) (2) OUTPUT ENABLE (ENx) (DWW Package Only) OUTPUT (OUTx) H H or open H L H or open L Open H or open Default X L Z PU PU PD PU X H or open Default X PD X X Undetermined COMMENTS Normal Operation: A channel output assumes the logic state of its input. Default mode: When INx is open, the corresponding channel output goes to its default high logic state. Default= High for ISO7821 and Low for ISO7821F. A low value of Output Enable causes the outputs to be highimpedance. Default mode: When VCCI is unpowered, a channel output assumes the logic state based on the selected default option.Default= High for ISO7821 and Low for ISO7821F. When VCCI transitions from unpowered to powered-up, a channel output assumes the logic state of its input. When VCCI transitions from powered-up to unpowered, channel output assumes the selected default state. When VCCO is unpowered, a channel output is undetermined (3). When VCCO transitions from unpowered to powered-up, a channel output assumes the logic state of its input VCCI = Input-side VCC; VCCO = Output-side VCC; PU = Powered up (VCC ≥ 2.25 V); PD = Powered down (VCC ≤ 1.7 V); X = Irrelevant; H = High level; L = Low level; Z = High impedance A strongly driven input signal can weakly power the floating VCC via an internal protection diode and cause undetermined output. The outputs are in undetermined state when 1.7 V < VCCI, VCCO < 2.25 V. Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ISO7821 ISO7821F ISO7821, ISO7821F www.ti.com SLLSEM2F – NOVEMBER 2014 – REVISED MARCH 2016 8.4.1 Device I/O Schematics Input (Device Without Suffix F) VCCI VCCI Input (Device With Suffix F) VCCI VCCI VCCI VCCI VCCI 1.5 MW 985 W 985 W INx INx 1.5 MW Output Enable VCCO VCCO VCCO VCCO VCCO 2 MW 1970 W ~20 W OUTx Enx Copyright © 2016, Texas Instruments Incorporated Figure 15. Device I/O Schematics Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ISO7821 ISO7821F Submit Documentation Feedback 23 ISO7821, ISO7821F SLLSEM2F – NOVEMBER 2014 – REVISED MARCH 2016 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The ISO7821 is a high-performance, dual-channel digital isolator with 5.7 kVRMS isolation voltage per UL 1577. It utilizes single-ended CMOS-logic switching technology. Its supply voltage range is from 2.25 V to 5.5 V for both supplies, VCC1 and VCC2. When designing with digital isolators, it is important to keep in mind that due to the single-ended design structure, digital isolators do not conform to any specific interface standard and are only intended for isolating single-ended CMOS or TTL digital signal lines. The isolator is typically placed between the data controller (that is, μC or UART), and a data converter or a line transceiver, regardless of the interface type or standard. 9.2 Typical Application ISO7821 can be used with Texas Instruments' mixed signal micro-controller, digital-to-analog converter, transformer driver, and voltage regulator to create an isolated 4-20 mA current loop. VS 0.1 F 3.3 V 2 VCC D2 3 1:1.33 MBR0520L 1 SN6501 10 F GND D1 0.1 F IN OUT 5 3.3VISO 10 F TPS76333 3 1 EN GND 2 10 F MBR0520L 4, 5 Isolation Barrier 0.1 F 0.1 F 20 LOOP+ 0.1 F 0.1 F 15 0.1 F 10 3 5 6 VCC1 DVCC XOUT MSP430G2132 XIN 14 8 2 4 P3.0 11 12 P3.1 5 VCC2 OUTB INB GND1 DVSS INA OUTA ISO7821 GND2 1, 7 4 9, 16 13 5 12 4 3 VA VD LOW BASE ERRLVL 16 0.1 F DAC161P997 22 DBACK DIN C1 14 3 × 2.2 nF 1 F C2 13 C3 COMA 12 9 OUT COMD 1 LOOP± 2 Figure 16. Isolated 4-20 mA Current Loop 9.2.1 Design Requirements For the ISO7821, use the parameters shown in Table 7. Table 7. Design Parameters 24 PARAMETER VALUE Supply voltage 2.25 V to 5.5 V Decoupling capacitor between VCC1 and GND1 0.1 µF Decoupling capacitor from VCC2 and GND2 0.1 µF Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ISO7821 ISO7821F ISO7821, ISO7821F www.ti.com SLLSEM2F – NOVEMBER 2014 – REVISED MARCH 2016 9.2.2 Detailed Design Procedure Unlike optocouplers, which need external components to improve performance, provide bias, or limit current, ISO7821 only needs two external bypass capacitors to operate. ISO7821DW VCC1 VCC2 GND1 GND1 1 16 GND2 GND2 0.1 µF 0.1 µF NC 2 15 NC GND2 GND1 3 OUTA 4 INB 14 VCC2 ISOLATION VCC1 OUTA 13 INA INA INB 5 12 OUTB NC 6 11 NC GND1 7 10 NC OUTB GND1 NC 8 9 GND2 GND2 Figure 17. Typical ISO7821 Circuit Hook-up 9.2.2.1 Electromagnetic Compatibility (EMC) Considerations Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge (ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level performance and reliability depends, to a large extent, on the application board design and layout, the ISO7821 incorporate many chip-level design improvements for overall system robustness. Some of these improvements include: • Robust ESD protection for input and output signal pins and inter-chip bond pads. • Low-resistance connectivity of ESD cells to supply and ground pins. • Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events. • Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance path. • PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic SCRs. • Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation. Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ISO7821 ISO7821F Submit Documentation Feedback 25 ISO7821, ISO7821F SLLSEM2F – NOVEMBER 2014 – REVISED MARCH 2016 www.ti.com 9.2.3 Application Performance Curve Typical eye diagram of ISO7821 indicate low jitter and wide open eye at the maximum data rate of 100 Mbps. Figure 18. Eye Diagram at 100 Mbps PRBS, 5 V and 25°C 10 Power Supply Recommendations To ensure reliable operation at all data rates and supply voltages, a 0.1 µF bypass capacitor is recommended at input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins as possible. If only a single primary-side power supply is available in an application, isolated power can be generated for the secondary-side with the help of a transformer driver such as Texas Instruments' SN6501. For such applications, detailed power supply design and transformer selection recommendations are available in SN6501 datasheet (SLLSEA0) . 26 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ISO7821 ISO7821F ISO7821, ISO7821F www.ti.com SLLSEM2F – NOVEMBER 2014 – REVISED MARCH 2016 11 Layout 11.1 PCB Material For digital circuit boards operating below 150 Mbps, (or rise and fall times higher than 1 ns), and trace lengths of up to 10 inches, use standard FR-4 epoxy-glass as PCB material. FR-4 (Flame Retardant 4) meets the requirements of Underwriters Laboratories UL94-V0, and is preferred over cheaper alternatives due to its lower dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and its selfextinguishing flammability-characteristics. 11.2 Layout Guidelines A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 19). Layer stacking should be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency signal layer. • Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits of the data link. • Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for transmission line interconnects and provides an excellent low-inductance path for the return current flow. • Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of approximately 100 pF/in2. • Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links usually have margin to tolerate discontinuities such as vias. If an additional supply voltage plane or signal layer is needed, add a second power / ground plane system to the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the power and ground plane of each power system can be placed closer together, thus increasing the high-frequency bypass capacitance significantly. For detailed layout recommendations, see Application Note SLLA284, Digital Isolator Design Guide. 11.3 Layout Example High-speed traces 10 mils Ground plane 40 mils Keep this space free from planes, traces, pads, and vias FR-4 0r ~ 4.5 Power plane 10 mils Low-speed traces Figure 19. Layout Example Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ISO7821 ISO7821F Submit Documentation Feedback 27 ISO7821, ISO7821F SLLSEM2F – NOVEMBER 2014 – REVISED MARCH 2016 www.ti.com 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation See the Isolation Glossary (SLLA353) 12.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 8. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY ISO7821 Click here Click here Click here Click here Click here ISO7821F Click here Click here Click here Click here Click here 12.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.4 Trademarks E2E is a trademark of Texas Instruments. 12.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 28 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ISO7821 ISO7821F ISO7821, ISO7821F www.ti.com SLLSEM2F – NOVEMBER 2014 – REVISED MARCH 2016 PACKAGE OUTLINE DW0016B SOIC - 2.65 mm max height SCALE 1.500 SOIC C 10.63 TYP 9.97 SEATING PLANE PIN 1 ID AREA A 0.1 C 14X 1.27 16 1 2X 8.89 10.5 10.1 NOTE 3 8 9 0.51 0.31 0.25 C A 16X B 7.6 7.4 NOTE 4 2.65 MAX B 0.33 TYP 0.10 SEE DETAIL A 0.25 GAGE PLANE 0.3 0.1 0 -8 1.27 0.40 DETAIL A (1.4) TYPICAL 4221009/B 07/2016 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side. 5. Reference JEDEC registration MS-013. www.ti.com Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ISO7821 ISO7821F Submit Documentation Feedback 29 ISO7821, ISO7821F SLLSEM2F – NOVEMBER 2014 – REVISED MARCH 2016 www.ti.com EXAMPLE BOARD LAYOUT DW0016B SOIC - 2.65 mm max height SOIC SYMM SYMM 16X (2) 16X (1.65) SEE DETAILS 1 SEE DETAILS 1 16 16 16X (0.6) 16X (0.6) SYMM SYMM 14X (1.27) 14X (1.27) 9 8 9 8 R0.05 TYP R0.05 TYP (9.75) (9.3) HV / ISOLATION OPTION 8.1 mm CLEARANCE/CREEPAGE IPC-7351 NOMINAL 7.3 mm CLEARANCE/CREEPAGE LAND PATTERN EXAMPLE SCALE:4X METAL SOLDER MASK OPENING SOLDER MASK OPENING METAL 0.07 MAX ALL AROUND 0.07 MIN ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS 4221009/B 07/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com 30 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ISO7821 ISO7821F ISO7821, ISO7821F www.ti.com SLLSEM2F – NOVEMBER 2014 – REVISED MARCH 2016 EXAMPLE STENCIL DESIGN DW0016B SOIC - 2.65 mm max height SOIC SYMM SYMM 16X (1.65) 16X (2) 1 1 16 16 16X (0.6) 16X (0.6) SYMM SYMM 14X (1.27) 14X (1.27) 9 8 9 8 R0.05 TYP R0.05 TYP (9.3) (9.75) IPC-7351 NOMINAL 7.3 mm CLEARANCE/CREEPAGE HV / ISOLATION OPTION 8.1 mm CLEARANCE/CREEPAGE SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:4X 4221009/B 07/2016 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ISO7821 ISO7821F Submit Documentation Feedback 31 ISO7821, ISO7821F SLLSEM2F – NOVEMBER 2014 – REVISED MARCH 2016 www.ti.com PACKAGE OUTLINE DWW0016A SOIC - 2.65 mm max height SCALE 1.000 PLASTIC SMALL OUTLINE C 17.4 17.1 A SEATING PLANE 0.1 C PIN 1 ID AREA 14X 1.27 16 1 10.4 10.2 NOTE 3 2X 8.89 8 9 16X 14.1 13.9 NOTE 4 B 0.25 0.51 0.31 A B (2.286) C 2.65 MAX 0.28 TYP 0.22 SEE DETAIL A (1.625) 0.25 GAGE PLANE 0.3 0.1 1.1 0.6 0 -8 DETAIL A TYPICAL 4221501/A 11/2014 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0,15 mm per side. 4. This dimension does not include interlead flash. www.ti.com 32 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ISO7821 ISO7821F ISO7821, ISO7821F www.ti.com SLLSEM2F – NOVEMBER 2014 – REVISED MARCH 2016 EXAMPLE BOARD LAYOUT DWW0016A SOIC - 2.65 mm max height PLASTIC SMALL OUTLINE 16X (2) 16X (1.875) (14.25) (14.5) 16X (0.6) 16X (0.6) 1 1 16 16 SYMM SYMM 14X (1.27) 9 8 SYMM 14X (1.27) 9 8 SYMM (16.375) (16.25) LAND PATTERN EXAMPLE LAND PATTERN EXAMPLE STANDARD SCALE:3X PCB CLEARANCE & CREEPAGE OPTIMIZED SCALE:3X 0.07 MAX ALL AROUND 0.07 MIN ALL AROUND METAL SOLDER MASK OPENING SOLDER MASK OPENING METAL UNDER SOLDER MASK NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS 4221501/A 11/2014 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ISO7821 ISO7821F Submit Documentation Feedback 33 ISO7821, ISO7821F SLLSEM2F – NOVEMBER 2014 – REVISED MARCH 2016 www.ti.com EXAMPLE STENCIL DESIGN DWW0016A SOIC - 2.65 mm max height PLASTIC SMALL OUTLINE 16X (2) SYMM 1 16 16X (0.6) SYMM 14X (1.27) 9 8 (16.25) SOLDER PASTE EXAMPLE STANDARD BASED ON 0.125 mm THICK STENCIL SCALE:4X 16X (1.875) SYMM 1 16 16X (0.6) SYMM 14X (1.27) 9 8 (16.375) SOLDER PASTE EXAMPLE PCB CLEARANCE & CREEPAGE OPTIMIZED BASED ON 0.125 mm THICK STENCIL SCALE:4X 4221501/A 11/2014 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. www.ti.com 34 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: ISO7821 ISO7821F PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) ISO7821DW ACTIVE SOIC DW 16 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR -55 to 125 ISO7821 ISO7821DWR ACTIVE SOIC DW 16 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -55 to 125 ISO7821 ISO7821DWW ACTIVE SOIC DWW 16 45 RoHS & Green NIPDAU Level-3-260C-168 HR -55 to 125 ISO7821 ISO7821DWWR ACTIVE SOIC DWW 16 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -55 to 125 ISO7821 ISO7821FDW ACTIVE SOIC DW 16 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR -55 to 125 ISO7821F ISO7821FDWR ACTIVE SOIC DW 16 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -55 to 125 ISO7821F ISO7821FDWW ACTIVE SOIC DWW 16 45 RoHS & Green NIPDAU Level-3-260C-168 HR -55 to 125 ISO7821F ISO7821FDWWR ACTIVE SOIC DWW 16 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -55 to 125 ISO7821F (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of