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ISO7820LL, ISO7821LL
SLLSET8A – MARCH 2016 – REVISED AUGUST 2016
ISO782xLL High-Performance, 8000-VPK Reinforced Isolated Dual-LVDS Buffer
1 Features
2 Applications
•
•
•
•
•
•
•
•
•
1
•
•
•
•
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Complies with TIA/EIA-644-A LVDS Standard
Signaling Rate: Up to 100 Mbps
Wide Supply Range: 2.25 V to 5.5 V
Wide Temperature Range: –55°C to +125°C
Ambient
Low Power Consumption, per Channel at 100
Mbps:
– Typical 9.3-mA (ISO7820LL)
– Typical 9.5-mA (ISO7821LL)
Low Propagation Delay: 17-ns Typical
Industry leading CMTI (min): ±100 kV/μs
Robust Electromagnetic Compatibility (EMC)
System-Level ESD, EFT, and Surge Immunity
Low Emissions
Isolation Barrier Life: > 40 Years
Wide Body and Extra-Wide Body SOIC-16
Package Options
Isolation Surge Withstand Voltage 12800 VPK
Safety-Related Certifications:
– 8000-VPK Reinforced Isolation per DIN V VDE
V 0884-10 (VDE V 0884-10):2006-12
– 5700-VRMS Isolation for 1 minute per UL 1577
– CSA Component Acceptance Notice 5A, IEC
60950–1 and IEC 60601–1 End Equipment
Standards
– TUV Certification per EN 61010-1 and EN
60950-1
– GB4943.1-2011 CQC Certification
– All Certifications are Planned
Motor Control
Test and Measurement
Industrial Automation
Medical Equipment
Communication Systems
3 Description
The ISO782xLL family of devices is a highperformance, isolated dual-LVDS buffer with 8000VPK isolation voltage. This device provides high
electromagnetic immunity and low emissions at lowpower consumption, while isolating the LVDS bus
signal. Each isolation channel has an LVDS receive
and transmit buffer separated by silicon dioxide
(SiO2) insulation barrier.
The ISO7820LL device has two forward-direction
channels. The ISO7821LL device has one forward
and one reverse-direction channel.
Through innovative chip design and layout
techniques, the electromagnetic compatibility of the
ISO782xLL family of devices has been significantly
enhanced to ease system-level ESD, EFT, surge, and
emission compliance.
The ISO782xLL family of devices is available in 16pin SOIC wide-body (DW) package and extra-wide
body (DWW) packages.
Device Information(1)
PART NUMBER
ISO7820LL
ISO7821LL
PACKAGE
BODY SIZE (NOM)
DW (16)
10.30 mm × 7.50 mm
DWW (16)
10.30 mm × 14.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
VCCI
Isolation
Capacitor
VCCO
INx+
OUTx+
LVDS RX
LVDS TX
INx±
OUTx±
ENx
GNDI
GNDO
Copyright © 2016, Texas Instruments Incorporated
VCCI and GNDI are supply and ground connections respectively for the input channels.
VCCO and GNDO are supply and ground connections respectively for the output channels.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ISO7820LL, ISO7821LL
SLLSET8A – MARCH 2016 – REVISED AUGUST 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
7
1
1
1
2
3
4
Absolute Maximum Ratings ..................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 5
Power Ratings........................................................... 5
Insulation Specifications............................................ 6
Safety-Related Certifications..................................... 7
Safety Limiting Values .............................................. 7
DC Electrical Characteristics .................................... 8
DC Supply Current Characteristics ......................... 9
Switching Characteristics ...................................... 11
Insulation Characteristics Curves ......................... 12
Typical Characteristics .......................................... 13
Parameter Measurement Information ................ 16
8
Detailed Description ............................................ 19
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
19
19
19
20
Application and Implementation ........................ 21
9.1 Application Information............................................ 21
9.2 Typical Application .................................................. 21
10 Power Supply Recommendations ..................... 25
11 Layout................................................................... 26
11.1 Layout Guidelines ................................................. 26
11.2 Layout Example .................................................... 26
12 Device and Documentation Support ................. 27
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
27
27
27
27
27
27
13 Mechanical, Packaging, and Orderable
Information ........................................................... 27
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (March 2016) to Revision A
•
2
Page
Changed the device status from Product Preview to Production Data and released full version of the data sheet .............. 1
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SLLSET8A – MARCH 2016 – REVISED AUGUST 2016
5 Pin Configuration and Functions
ISO7820LL DW and DWW Packages
16-Pin SOIC
Top View
ISO7821LL DW and DWW Packages
16-Pin SOIC
Top View
VCC1
1
16 VCC2
GND1 2
15 GND2
GND1
2
15 GND2
INA+
3
14 OUTA+
INA+
3
14 OUTA+
INA±
4
13 OUTA±
INA±
4
INB±
5
INB+
NC
12 OUTB±
OUTB± 5
6
11 OUTB+
OUTB+ 6
7
10
GND1 8
EN2
9 GND2
EN1
7
GND1
8
ISOLATION
16 VCC2
ISOLATION
1
VCC1
13 OUTA±
12
INB±
11
INB+
10
EN2
9 GND2
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
ISO7820LL
ISO7821LL
EN1
—
7
I
Output enable 1. Output pins on side 1 are enabled when EN1 is high or open and
in high impedance state when EN1 is low.
EN2
10
10
I
Output enable 2. Output pins on side 2 are enabled when EN2 is high or open and
in high impedance state when EN2 is low.
2
2
8
8
GND1
—
Ground connection for VCC1
—
Ground connection for VCC2
9
9
15
15
INA+
3
3
I
Positive differential input, channel A
INA–
4
4
I
Negative differential input, channel A
INB+
6
11
I
Positive differential input, channel B
INB–
5
12
I
Negative differential input, channel B
GND2
NC
7
—
—
Not connected
OUTA+
14
14
O
Positive differential output, channel A
OUTA–
13
13
O
Negative differential output, channel A
OUTB+
11
6
O
Positive differential output, channel B
OUTB–
12
5
O
Negative differential output, channel B
VCC1
1
1
—
Power supply, side 1, VCC1
VCC2
16
16
—
Power supply, side 2, VCC2
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
VCCx
Supply voltage (2)
VCC1, VCC2
–0.5
6
V
V
Voltage on input, output, and
enable pins
OUTx, INx, ENx
–0.5
VCCx + 0.5 (3)
V
IO
Maximum current through OUTx pins
–20
20
mA
TJ
Junction temperature
–55
150
°C
Tstg
Storage temperature
–65
150
°C
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak
voltage values.
Maximum voltage must not exceed 6 V.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
±4500
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
UNIT
V
±1500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
VCC1, VCC2
Supply voltage
|VID|
Magnitude of RX
input differential
voltage
VIC
RX input commonmode voltage
RL
TX far end differential termination
DR
Signaling rate
TA
Ambient temperature
4
Driven with voltage sources on
RX pins
MIN
NOM
MAX
2.25
3.3
5.5
V
600
mV
100
VCC1, VCC2 ≥ 3 V
0.5 |VID|
2.4 – 0.5 |VID|
VCC1, VCC2 < 3 V
0.5 |VID|
VCCx – 0.6 – 0.5 |VID|
100
0
–55
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25
UNIT
V
V
Ω
100
Mbps
125
°C
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SLLSET8A – MARCH 2016 – REVISED AUGUST 2016
6.4 Thermal Information
THERMAL METRIC
ISO7820LL
ISO7821LL
(1)
DW (SOIC)
DWW (SOIC)
16 PINS
16 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
82
84.6
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
44.6
46.4
°C/W
RθJB
Junction-to-board thermal resistance
46.6
55.3
°C/W
ψJT
Junction-to-top characterization parameter
17.8
18.7
°C/W
ψJB
Junction-to-board characterization parameter
46.1
54.5
°C/W
RθJC(bottom)
Junction-to-case(bottom) thermal resistance
—
—
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Power Ratings
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 5 pF, input a 50-MHz 50% duty-cycle square wave, EN1 = EN2 = 5.5 V,
RL = 100-Ω differential
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ISO7821LL
PD
Maximum power dissipation (both sides)
156
mW
PD1
Maximum power dissipation (side 1)
78
mW
PD2
Maximum power dissipation (side 2)
78
mW
ISO7820LL
PD
Maximum power dissipation (both sides)
152
mW
PD1
Maximum power dissipation (side 1)
36
mW
PD2
Maximum power dissipation (side 2)
116
mW
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6.6 Insulation Specifications
over operating free-air temperature range (unless otherwise noted) (1)
PARAMETER
SPECIFICATION
TEST CONDITIONS
DW
DWW
UNIT
GENERAL
External clearance (1)
Shortest terminal-to-terminal distance through air
>8
>14.5
mm
CPG
External creepage (1)
Shortest terminal-to-terminal distance across the package
surface
>8
>14.5
mm
DTI
Distance through the
insulation
Minimum internal gap (internal clearance)
>21
>21
μm
CTI
Tracking resistance
(comparative tracking index)
DIN EN 60112 (VDE 0303–11); IEC 60112; UL 746A
>600
>600
V
Material group
According to IEC 60664-1
CLR
I
I
I–IV
I–IV
I–III
I–IV
AC voltage (bipolar)
2121
2828
VPK
AC voltage (sine wave); time dependent dielectric
breakdown (TDDB) test; see Figure 1 and Figure 2
1500
2000
VRMS
DC voltage
2121
2828
VDC
Overvoltage category per IEC Rated mains voltage ≤ 600 VRMS
60664-1
Rated mains voltage ≤ 1000 VRMS
DIN V VDE V 0884–10 (VDE V 0884–10):2006–12 (2)
VIORM
Maximum repetitive peak
isolation voltage
VIOWM
Maximum isolation working
voltage
VIOTM
Maximum transient isolation
voltage
VTEST = VIOTM
t = 60 s (qualification)
t = 1 s (100% production)
8000
8000
VPK
VIOSM
Maximum surge isolation
voltage (3)
Test method per IEC 60065, 1.2/50 µs waveform,
VTEST = 1.6 × VIOSM = 12800 VPK (qualification)
8000
8000
VPK
Method a: After I/O safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.2 × VIORM = 2545 VPK (DW) and
3394 VPK (DWW), tm = 10 s
≤5
≤5
Method a: After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.6 × VIORM = 3394 VPK (DW) and
4525 VPK (DWW), tm = 10 s
≤5
≤5
Method b1: At routine test (100% production) and
preconditioning (type test)
Vini = VIORM, tini = 1 s;
Vpd(m) = 1.875 × VIORM= 3977 VPK (DW) and
5303 VPK (DWW), tm = 1 s
≤5
≤5
~0.7
~0.7
Apparent charge (4)
qpd
Barrier capacitance, input to
output (5)
CIO
Isolation resistance, input to
output (5)
RIO
VIO = 0.4 × sin (2πft), f = 1 MHz
12
pC
VIO = 500 V, TA = 25°C
>10
>10
VIO = 500 V, 100°C ≤ TA ≤ 125°C
>1011
>1011
9
9
VIO = 500 V at TS = 150°C
>10
pF
12
Ω
>10
Pollution degree
2
2
Climatic category
55/125/21
55/125/21
5700
5700
UL 1577
VISO
(1)
(2)
(3)
(4)
(5)
6
VTEST = VISO = 5700 VRMS, t = 60 s (qualification);
Withstanding isolation voltage VTEST = 1.2 × VISO = 6840 VRMS,
t = 1 s (100% production)
VRMS
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care
should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on
the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.
This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by
means of suitable protective circuits.
Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
Apparent charge is electrical discharge caused by a partial discharge (pd).
All pins on each side of the barrier tied together creating a two-terminal device.
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SLLSET8A – MARCH 2016 – REVISED AUGUST 2016
6.7 Safety-Related Certifications
VDE
CSA
Plan to certify according to
DIN V VDE V 0884-10
(VDE V 0884-10):2006-12
and DIN EN 60950-1 (VDE
0805 Teil 1):2011-01
UL
Plan to certify under CSA
Component Acceptance
Notice 5A, IEC 60950-1 and
IEC 60601-1
Plan to certify according
to UL 1577 Component
Recognition Program
CQC
TUV
Plan to certify according to
GB 4943.1-2011
Reinforced insulation per CSA
60950-1-07+A1+A2 and IEC
60950-1 2nd Ed., 800 VRMS
Reinforced insulation
(DW package) and 1450 VRMS
Maximum transient
isolation voltage, 8000 VPK; (DWW package) max working
voltage (pollution degree 2,
Maximum repetitive peak
Single protection,
isolation voltage, 2121 VPK material group I);
5700 VRMS
(DW), 2828 VPK (DWW);
2 MOPP (Means of Patient
Maximum surge isolation
Protection) per CSA 60601voltage, 8000 VPK
1:14 and IEC 60601-1 Ed. 3.1,
250 VRMS (354 VPK) max
working voltage (DW package)
Reinforced Insulation,
Altitude ≤ 5000 m, Tropical
Climate, 250 VRMS
maximum working voltage
Certification planned
Certification planned
Certification planned
Certification planned
Plan to certify according to
EN 61010-1:2010 (3rd Ed) and
EN 60950-1:2006/A11:2009/A1:2010/
A12:2011/A2:2013
5700 VRMS Reinforced insulation per
EN 61010-1:2010 (3rd Ed) up to
working voltage of 600 VRMS (DW
package) and 1000 VRMS (DWW
package)
5700 VRMS Reinforced insulation per
EN 60950-1:2006/A11:2009/A1:2010/
A12:2011/A2:2013 up to working
voltage of 800 VRMS (DW package) and
1450 VRMS (DWW package)
Certification planned
6.8 Safety Limiting Values
Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure of
the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat
the die and damage the isolation barrier potentially leading to secondary system failures.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DW PACKAGE
IS
Safety input, output, or supply
current
PS
Safety input, output, or total
power
TS
Maximum safety temperature
RθJA = 82°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C,
see Figure 3
277
RθJA = 82°C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C,
see Figure 3
423
RθJA = 82°C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C,
see Figure 3
554
RθJA = 82°C/W, TJ = 150°C, TA = 25°C,
see Figure 5
mA
1524
mW
150
°C
DWW PACKAGE
IS
Safety input, output, or supply
current
PS
Safety input, output, or total
power
TS
Maximum safety temperature
RθJA = 84.6°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C,
see Figure 4
269
RθJA = 84.6°C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C,
see Figure 4
410
RθJA = 84.6°C/W, VI = 2.75 V, TJ = 150°C, TA =
25°C,
see Figure 4
537
RθJA = 84.6°C/W, TJ = 150°C, TA = 25°C,
see Figure 6
mA
1478
mW
150
°C
The maximum safety temperature is the maximum junction temperature specified for the device. The power
dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines
the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information is that of a
device installed on a High-K test board for leaded surface-mount packages. The power is the recommended
maximum input voltage times the current. The junction temperature is then the ambient temperature plus the
power times the junction-to-air thermal resistance.
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6.9 DC Electrical Characteristics
(over recommended operating conditions unless otherwise noted)
PARAMETER
IIN(EN)
Leakage Current on ENx
pins
VCC+(UVLO)
Positive-going
undervoltage-lockout
(UVLO) threshold
VCC–(UVLO)
Negative-going UVLO
threshold
VHYS(UVLO)
UVLO threshold hysteresis
VEN(ON)
EN pin turn-on threshold
VEN(OFF)
EN pin turn-off threshold
VEN(HYS)
EN pin threshold hysteresis
TEST CONDITIONS
MIN
Internal pullup on ENx pins
TYP
MAX
13
40
μA
2.25
V
1.7
UNIT
V
0.2
V
0.7 VCCx
0.3 VCCx
V
V
0.1 VCCx
V
(1)
Common-mode transient
immunity
VI = VCCI or 0 V;
VCM = 1000 V; see Figure 25
100
120
|VOD|
TX DC output differential
voltage
RL = 100 Ω, See Figure 26
250
350
450
mV
∆VOD
Change in TX DC output
differential between logic 1
and 0 states
RL = 100 Ω, see Figure 26
–10
0
10
mV
VOC
TX DC output common
mode voltage
RL = 100 Ω, see Figure 26
1.125
1.2
1.375
∆VOC
TX DC common mode
voltage difference
RL = 100 Ω, see Figure 26
–25
0
25
IOS
TX output short circuit
current through OUTx
IOZ
TX output current when in
high impedance
CMTI
kV/μs
LVDS TX
TX output pad capacitance
on OUTx at 1 MHz
COUT
OUTx = 0
10
OUTxP = OUTxM
10
ENx = 0, OUTx from 0 to VCC
–5
5
DW package: ENx = 0,
DC offset = VCC / 2,
Swing = 200 mV, f = 1 MHz
10
DWW package: ENx = 0,
DC offset = VCC / 2,
Swing = 200 mV, f = 1 MHz
10
V
mV
mA
µA
pF
LVDS RX
VCC1, VCC2 ≥ 3 V
0.5 |VID|
1.2
2.4 – 0.5 |VID|
VCC1, VCC2 < 3 V
0.5 |VID|
1.2
VCCx – 0.6 – 0.5 |VID|
VIC
RX input common mode
voltage
VIT1
Positive going RX input
differential threshold
Across VIC
VIT2
Negative going RX input
differential threshold
Across VIC
IINx
Input current on INx
From 0 to VCCx (each input
independently)
IINxP – IINxM
Input current balance
From 0 to VCCx
CIN
RX input pad capacitance
on INx at 1 MHz
(1)
8
50
–50
V
mV
mV
10
–6
DW package: DC offset = 1.2 V,
Swing = 200 mV, f = 1 MHz
6.6
DWW package: DC offset = 1.2 V,
Swing = 200 mV, f = 1 MHz
7.5
20
µA
6
µA
pF
VCCI = Input-side VCCx; VCCO = Output-side VCCx.
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6.10 DC Supply Current Characteristics
(over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
ISO7821LL
EN1 = EN2 = 0, OUTx floating, VID ≥ 50 mV
2.2
3.3
EN1 = EN2 = 0, OUTx floating, VID ≤ –50 mV
3.4
5.1
EN1 = EN2 = 1, RL = 100-Ω differential, VID ≥ 50 mV
6.1
9.2
7.4
11.1
6.7
10.2
EN1 = EN2 = 1, RL = 100-Ω differential, data communication at
50 Mbps
7.4
11.5
EN1 = EN2 = 1, RL = 100-Ω differential, data communication at
100 Mbps
8.3
12.5
EN1 = EN2 = 0, OUTx floating, VID ≥ 50 mV
2.2
3.4
EN1 = EN2 = 0, OUTx floating, VID ≤ –50 mV
3.5
5.2
EN1 = EN2 = 1, RL = 100-Ω differential, VID ≥ 50 mV
6.4
9.8
EN1 = EN2 = 1, RL = 100-Ω differential, VID ≤ –50 mV
7.8
11.7
EN1 = EN2 = 1, RL = 100-Ω differential, data communication at
1 Mbps
7.1
10.8
EN1 = EN2 = 1, RL = 100-Ω differential, data communication at
50 Mbps
8.1
12.1
EN1 = EN2 = 1, RL = 100-Ω differential, data communication at
100 Mbps
9.5
14.1
EN1 = EN2 = 0, OUTx floating, VID ≥ 50 mV
2.7
4.3
EN1 = EN2 = 0, OUTx floating, VID ≤ –50 mV
5.3
7.9
EN1 = EN2 = 1, RL = 100-Ω differential, VID≥ 50 mV
2.7
4.2
5.2
8
4
6.1
EN1 = EN2 = 1, RL = 100-Ω differential, data communication at
50 Mbps
4.1
6.2
EN1 = EN2 = 1, RL = 100-Ω differential, data communication at
100 Mbps
4.3
6.4
EN1 = EN2 = 0, OUTx floating, VID ≥ 50 mV
2.8
4.4
EN1 = EN2 = 0, OUTx floating, VID ≤ –50 mV
5.5
8.2
EN1 = EN2 = 1, RL = 100-Ω differential, VID ≥ 50 mV
2.9
4.5
EN1 = EN2 = 1, RL = 100-Ω differential, VID ≤ –50 mV
5.5
8.2
EN1 = EN2 = 1, RL = 100-Ω differential, data communication at
1 Mbps
4.2
6.3
EN1 = EN2 = 1, RL = 100-Ω differential, data communication at
50 Mbps
4.3
6.4
EN1 = EN2 = 1, RL = 100-Ω differential, data communication at
100 Mbps
4.5
6.6
EN1 = EN2 = 1, RL = 100-Ω differential, VID ≤ –50 mV
2.25 V < VCC1,
EN1 = EN2 = 1, RL = 100-Ω differential, data communication at
VCC2 < 3.6 V
1 Mbps
ICC1
ICC2
Supply current
side 1 and side 2
4.5 V < VCC1,
VCC2 < 5.5 V
mA
ISO7820LL
EN1 = EN2 = 1, RL = 100-Ω differential, VID ≤ –50 mV
2.25 V < VCC1,
EN1 = EN2 = 1, RL = 100-Ω differential, data communication at
VCC2 < 3.6 V
1 Mbps
ICC1
Supply current
side 1
4.5 V < VCC1,
VCC2 < 5.5 V
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DC Supply Current Characteristics (continued)
(over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
ISO7820LL (continued)
ICC2
EN1 = EN2 = 0, OUTx floating, VID ≥ 50 mV
1.1
1.7
EN1 = EN2 = 0, OUTx floating, VID ≤ –50 mV
1.1
1.7
VID≥ 50 mV
9.1
13.7
EN1 = EN2 = 1, RL = 100-Ω differential, VID ≤ –50 mV
9.2
13.9
2.25 V < VCC1,
EN1 = EN2 = 1, RL = 100-Ω differential, data communication at
VCC2 < 3.6 V
1 Mbps
9.2
13.8
EN1 = EN2 = 1, RL = 100-Ω differential, data communication at
50 Mbps
10.3
15.5
EN1 = EN2 = 1, RL = 100-Ω differential, data communication at
100 Mbps
12.1
17.9
EN1 = EN2 = 0, OUTx floating, VID ≥ 50 mV
1.2
1.8
EN1 = EN2 = 0, OUTx floating, VID ≤ –50 mV
1.2
1.8
EN1 = EN2 = 1, RL = 100-Ω differential, VID ≥ 50 mV
9.7
14.7
EN1 = EN2 = 1, RL = 100-Ω differential, VID ≤ –50 mV
9.7
14.8
EN1 = EN2 = 1, RL = 100-Ω differential, data communication at
1 Mbps
9.7
14.7
EN1 = EN2 = 1, RL = 100-Ω differential, data communication at
50 Mbps
11.5
17.3
EN1 = EN2 = 1, RL = 100-Ω differential, data communication at
100 Mbps
14.2
21
Supply current
side 2
4.5 V < VCC1,
VCC2 < 5.5 V
10
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Product Folder Links: ISO7820LL ISO7821LL
ISO7820LL, ISO7821LL
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SLLSET8A – MARCH 2016 – REVISED AUGUST 2016
6.11 Switching Characteristics
(over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
17
25
ns
0
4.5
ns
LVDS CHANNEL
tPLH
tPHL
Propagation delay time
PWD
Pulse width distortion |tPHL – tPLH|
tsk(o)
Channel-to-channel output skew time
Same directional channels, same
voltage and temperature
2.5
ns
tsk(pp)
Part-part skew
Same directional channels, same
voltage and temperature
4.5
ns
tCMset
Common-mode settling time after
EN = 0 to EN = 1 transition.
Common-mode capacitive
load = 100 pF to 0.5 nF
20
µs
tfs
Default output delay time from input
power loss
Measured from the time VCC goes
below 1.7 V, see Figure 24
9
µs
tie
Time interval error, or peak-to-peak jitter
216 – 1 PRBS data at 100 Mbps;
RX VID = 350 mVPP, 1 ns trf 10% to
90%, TA = 25°C, VCC1, VCC2 = 3.3 V
0.2
1
ns
LVDS TX AND RX
trf
TX differential rise/fall times (20% to
80%)
∆VOC(pp)
TX common-mode voltage peak-to-peak
at 100 Mbps
tPLZ, tPHZ TX disable time—valid output to HiZ
See Figure 22
300
780
1380
ps
0
150
mVPP
See Figure 23
10
20
ns
tPZH
Enable propagation delay, high
impedance-to-high output
See Figure 23
10
20
ns
tPZL
Enable propagation delay, high
impedance-to-low output
See Figure 23
2
2.5
μs
|VID|
Driven with voltage sources on RX
Magnitude of RX input differential voltage
pins, see the figures in the Parameter
for valid operation
Measurement Information section
600
mV
trf(RX)
Allowed RX input differential rise and fall
times (20% to 80%)
0.3 × UI (1)
ns
(1)
See Figure 27
100
1
UI is the unit interval.
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11
ISO7820LL, ISO7821LL
SLLSET8A – MARCH 2016 – REVISED AUGUST 2016
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6.12 Insulation Characteristics Curves
1.E+11
87.5%
1.E+9
1.E+9
1.E+8
1.E+8
1.E+7
1.E+6
1.E+5
Safety Margin Zone: 2400 VRMS, 63 Years
Operating Zone: 2000 VRMS, 34 Years
TDDB Line (
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