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ISO7842, ISO7842F
ZHCSD14G – OCTOBER 2014 – REVISED MARCH 2017
ISO7842x 高性能、8000VPK 增强型四通道数字隔离器
1 特性
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1
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信号传输速率：高达 100Mbps
宽电源电压范围：2.25V 至 5.5V
2.25V 至 5.5V 电平转换
宽温度范围：–55°C 至 +125°C
低功耗：电流典型值为 1.7mA/通道（1Mbps 时）
低传播延迟：典型值为 11ns
（5V 电源供电时）
行业领先的 CMTI（最小值）：±100 kV/μs
优异的电磁兼容性 (EMC)
系统级静电放电 (ESD)、瞬态放电 (EFT) 以及抗浪
涌保护
低辐射
隔离层寿命：40 年以上
宽体 SOIC-16 封装和超宽体 SOIC-16 封装选项
安全及管理批准：中的“安全及管理批准”列表中的
“安全及管理批准”列表
– 8000 VPK 增强型隔离，符合 DIN V VDE V
0884-10 (VDE V 0884-10)：2006-12
– 符合 UL 1577 标准且长达 1 分钟的 5.7kVRMS
隔离
– CSA 组件验收通知 5A，IEC 60950-1 和 IEC
60601-1 终端设备标准
– 符合 GB4943.1-2011 标准的 CQC 认证
– 符合 EN 61010-1 和 EN 60950-1 标准的 TUV
认证
– 完成了所有 DW 封装认证；完成了符合 UL、
VDE、TUV 标准的 DWW 封装认证并且已针对
CSA 和 CQC 进行了规划
2 应用
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工业自动化
电机控制
电源
太阳能逆变器
医疗设备
混合动力电动汽车
3 说明
ISO7842x 器件是一款高性能四通道数字隔离器，隔离
电压为 8000VPK。该器件已通过符合 VDE、CSA、
CQC 和 TUV 标准的增强型隔离认证。在隔离互补金
属氧化物半导体 (CMOS) 或者低电压互补金属氧化物
半导体 (LVCMOS) 数字 I/O 时，该隔离器可提供高电
磁抗扰度和低辐射，同时具备低功耗特性。每个隔离通
道都有一个由二氧化硅 (SiO2) 绝缘隔栅分开的逻辑输
入和输出缓冲器。
该器件配有使能引脚，可用于将多个主驱动应用中的相
应输出置于 高阻抗状态， 也可用于降低功耗。
ISO7842 器件具有 2 个正向通道和 2 个反向通道。如
果出现输入功率或信号丢失，ISO7842 器件默认输出
高电平，ISO7842F 器件默认输出低电平。有关更多详
细信息，请参阅 Device Functional Modes器件功能模
式部分。
与隔离式电源结合使用时，该器件有助于防止数据总线
或者其他电路中的噪声电流进入本地接地，进而干扰或
损坏敏感电路。凭借创新的芯片设计和布线技
术，ISO7842 器件的电磁兼容性得到了显著增强，可
确保提供系统级 ESD、EFT 和浪涌保护并符合辐射标
准。
ISO7842 器件采用 16 引脚 SOIC 宽体 (DW) 和超宽体
(DWW) 封装。
器件信息(1)
产品型号
ISO7842
ISO7842F
封装
封装尺寸（标称值）
DW (16)
10.30mm x 7.50mm
DWW (16)
10.30mm x 14.0mm
(1) 要了解所有可用封装，请参阅数据表末尾的可订购产品附录。
简化电路原理图
VCCI
Isolation
Capacitor
VCCO
INx
OUTx
ENx
GNDI
GNDO
VCCI 和 GNDI 分别是输入通道的电源和接地
连接。
VCCO 和 GNDO 分别是输出通道的电源和接
地连接。
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLLSEJ0
ISO7842, ISO7842F
ZHCSD14G – OCTOBER 2014 – REVISED MARCH 2017
www.ti.com.cn
目录
1
2
3
4
5
6
特性 ..........................................................................
应用 ..........................................................................
说明 ..........................................................................
修订历史记录 ...........................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.14
6.15
6.16
6.17
6.18
1
1
1
2
5
6
Absolute Maximum Ratings ...................................... 6
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 7
Power Ratings........................................................... 7
Insulation Specifications............................................ 8
Safety-Related Certifications..................................... 9
Safety Limiting Values .............................................. 9
Electrical Characteristics–5-V Supply ..................... 10
Supply Current Characteristics–5-V Supply.......... 10
Electrical Characteristics—3.3-V Supply .............. 11
Supply Current Characteristics—3.3-V Supply ..... 11
Electrical Characteristics—2.5-V Supply .............. 12
Supply Current Characteristics—2.5-V Supply ..... 12
Switching Characteristics—5-V Supply................. 13
Switching Characteristics—3.3-V Supply.............. 13
Switching Characteristics—2.5-V Supply.............. 14
Insulation Characteristics Curves ......................... 15
6.19 Typical Characteristics .......................................... 16
7
8
Parameter Measurement Information ................ 17
Detailed Description ............................................ 19
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
19
19
20
21
Application and Implementation ........................ 22
9.1 Application Information............................................ 22
9.2 Typical Application .................................................. 22
10 Power Supply Recommendations ..................... 24
11 Layout................................................................... 25
11.1 Layout Guidelines ................................................. 25
11.2 Layout Example .................................................... 25
12 器件和文档支持 ..................................................... 26
12.1
12.2
12.3
12.4
12.5
12.6
12.7
文档支持................................................................
相关链接................................................................
接收文档更新通知 .................................................
社区资源................................................................
商标 .......................................................................
静电放电警告.........................................................
Glossary ................................................................
26
26
26
26
26
26
26
13 机械、封装和可订购信息 ....................................... 27
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision F (April 2016) to Revision G
Page
•
Changed part numbers in the Power Ratings table (previously Power Dissipation Characteristics) .................................... 7
•
Changed the input-to-output test voltage parameter to apparent charge in the Insulation Specifications ............................ 8
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已添加 接收文档更新通知部分 .............................................................................................................................................. 26
Changes from Revision E (March 2016) to Revision F
Page
•
已更改 隔离层寿命年数（特性部分） ..................................................................................................................................... 1
•
VDE 认证现在已完成 .............................................................................................................................................................. 1
•
Changed VCCO to VCCI for the minimum value of the input threshold voltage hysteresis parameter in all electrical
characteristics tables ............................................................................................................................................................ 10
•
Added VCM to the test condition of the common-mode transient immunity parameter in all electrical characteristics
tables .................................................................................................................................................................................... 10
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Added the lifetime projection graphs for DW and DWW packages to the Safety Limiting Values section ......................... 15
Changes from Revision D (December 2015) to Revision E
Page
•
更改了特性 .............................................................................................................................................................................. 1
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在特性中添加了“符合 EN 61010-1 和 EN 60950-1 标准的 TUV 认证” ................................................................................... 1
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将说明的第一段中的文本从“符合 VDE、CSA 和 CQC 的认证” 更改为“符合 VDE、CSA、CQC 和 TUV 的认证。” ............. 1
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Added Note 1 to Insulation Characteristics ........................................................................................................................... 8
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Changed IEC 60664-1 Ratings Table..................................................................................................................................... 8
2
版权 © 2014–2017, Texas Instruments Incorporated
ISO7842, ISO7842F
www.ti.com.cn
ZHCSD14G – OCTOBER 2014 – REVISED MARCH 2017
•
Added TUV to the Regulatory Information section and Regulatory Information. Deleted Note 1 in Regulatory
Information ............................................................................................................................................................................. 9
•
Changed Device I/O Schematics ......................................................................................................................................... 21
Changes from Revision C (July 2015) to Revision D
Page
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在特性中添加了“完成了 DW 封装认证；规划了 DWW 认证”.................................................................................................. 1
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向说明部分添加了文本：“和超宽体 (DWW) 封装”。............................................................................................................... 1
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已将封装“超宽 SOIC、DWW (16)”添加至器件信息表............................................................................................................. 1
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Added the 16-DWW Package to Package Insulation and Safety-Related Specifications...................................................... 8
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Added the DWW package information to Package Insulation and Safety-Related Specifications ........................................ 8
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Added the DWW package information to Regulatory Information.......................................................................................... 9
•
Changed the MIN value of CMTI in Electrical Characteristics–5-V Supply, 5 V table From: 70 To: 100 kV/μs, deleted
the TYP value of 100 kV/μs .................................................................................................................................................. 10
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Added the Supply Current - ISO7842DW and ISO7842FDW section to the Supply Current Characteristics–5-V Supply.. 10
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Added the Supply Current - ISO7842DWW and ISO7842FDWW section to the Supply Current Characteristics–5-V
Supply................................................................................................................................................................................... 10
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Changed the MIN value of CMTI in Electrical Characteristics—3.3-V Supply, 5 V table From: 70 To: 100 kV/μs,
deleted the TYP value of 100 kV/μs ..................................................................................................................................... 11
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Added the Supply Current - ISO7842DW and ISO7842FDW section to the Supply Current Characteristics—3.3-V
Supply................................................................................................................................................................................... 11
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Added the Supply Current - ISO7842DWW and ISO7842FDWW section to the Supply Current Characteristics—3.3V Supply ............................................................................................................................................................................... 11
•
Changed the MIN value of CMTI in Electrical Characteristics—2.5-V Supply, 5 V table From: 70 To: 100 kV/μs,
deleted the TYP value of 100 kV/μs ..................................................................................................................................... 12
•
Added the Supply Current - ISO7842DW and ISO7842FDW section to the Supply Current Characteristics—2.5-V
Supply................................................................................................................................................................................... 12
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Added the Supply Current - ISO7842DWW and ISO7842FDWW section to the Supply Current Characteristics—2.5V Supply ............................................................................................................................................................................... 12
•
Added text to the Application Information section: " isolation voltage per UL 1577." ......................................................... 22
Changes from Revision B (April 2015) to Revision C
Page
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已添加器件 ISO7482F 至数据表 ............................................................................................................................................. 1
•
已更改 说明以包含“ISO7842 器件默认输出为“高”，ISO7842F 器件默认输出为“低””。 ......................................................... 1
•
Changed Thermal Derating Curve for Safety Limiting Current per VDE , Added Thermal Derating Curve for Safety
Limiting Power per VDE ....................................................................................................................................................... 15
•
Changed From: tPLH and tPHLat 5.5V To: tPLH and tPHL at 5.0 V ........................................................................................... 16
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Changed Default Output Delay Time Test Circuit and Voltage Waveforms......................................................................... 18
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Added the Device I/O Schematics section .......................................................................................................................... 21
Changes from Revision A (November 2014) to Revision B
Page
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已将文档标题从“四通道数字隔离器”更改为“四通道 2/2 数字隔离器” ...................................................................................... 1
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在特性部分添加了“2.25V 至 5.5V 电平转换”........................................................................................................................... 1
•
将特性中的“宽体 SOIC-16 封装”更改为“宽体和超宽体 SOIC-16 封装选项”............................................................................ 1
•
更改了特性 .............................................................................................................................................................................. 1
•
VDE 认证现在已完成 .............................................................................................................................................................. 1
•
更改了简化电路原理图并增加了注释 1 和注释 2 .................................................................................................................... 1
•
Added the Power Dissipation Characteristics table................................................................................................................ 7
版权 © 2014–2017, Texas Instruments Incorporated
3
ISO7842, ISO7842F
ZHCSD14G – OCTOBER 2014 – REVISED MARCH 2017
www.ti.com.cn
•
Changed Package Insulation and Safety-Related Specifications .......................................................................................... 8
•
Changed Insulation Characteristics title From: DIN V VDE 0884-10 (VDE V 0884-10) and UL 1577 Insulation
Characteristics To: Insulation Characteristics ........................................................................................................................ 8
•
Changed Insulation Characteristics ....................................................................................................................................... 8
•
Changed the Test Condition of CTI of the table in Package Insulation and Safety-Related Specifications ......................... 8
•
Changed the MIN value of CTI From" > 600 V To: 600 V .................................................................................................... 8
•
Changed the table in Regulatory Information......................................................................................................................... 9
•
Changed Switching Characteristics Test Circuit and Voltage Waveforms .......................................................................... 17
•
Changed Enable/Disable Propagation Delay Time Test Circuit and Waveform ................................................................. 17
•
Changed From: VCC1 To: VCCI in Default Output Delay Time Test Circuit and Voltage Waveforms .................................... 18
•
Changed Common-Mode Transient Immunity Test Circuit .................................................................................................. 18
•
Deleted INPUT-SIDE and OUTPUT-SIDE from columns 1 and 2 of Function Table ......................................................... 21
•
Changed the Application Information section ...................................................................................................................... 22
•
Changed the Application Information section ...................................................................................................................... 22
•
Added text and typical circuit hook-up figure to the Detailed Design Procedure section .................................................... 23
Changes from Original (October 2014) to Revision A
Page
•
将“特性”中的“所有机构批准待定”更改为“所有机构批准已规划”............................................................................................... 1
•
将 说明 部分的语句从“该器件已通过 VDE 和 CSA 认证，满足增强型隔离要求。” 更改为“该器件正在就是否满足增强
型隔离要求进行 VDE 和 CSA 审核认证。”............................................................................................................................. 1
•
Changed RIO MIN value From: 109 To: 1011 in the Package Insulation and Safety-Related Specifications table ................ 8
•
Changed the first row of information in the Regulatory Information table ............................................................................. 9
4
Copyright © 2014–2017, Texas Instruments Incorporated
ISO7842, ISO7842F
www.ti.com.cn
ZHCSD14G – OCTOBER 2014 – REVISED MARCH 2017
5 Pin Configuration and Functions
DW and DWW Packages
16-Pin SOIC
Top View
1
16 VCC2
GND1 2
15 GND2
INA
3
INB
4
14 OUTA
ISOLATION
VCC1
OUTC 5
OUTD 6
EN1
7
GND1 8
13 OUTB
12
INC
11
IND
10
EN2
9 GND2
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
EN1
7
I
Output enable 1. Output pins on side 1 are enabled when EN1 is high or open and in highimpedance state when EN1 is low.
EN2
10
I
Output enable 2. Output pins on side 2 are enabled when EN2 is high or open and in highimpedance state when EN2 is low.
GND1
GND2
INA
2
8
9
15
—
Ground connection for VCC1
—
Ground connection for VCC2
3
I
Input, channel A
INB
4
I
Input, channel B
INC
12
I
Input, channel C
IND
11
I
Input, channel D
OUTA
14
O
Output, channel A
OUTB
13
O
Output, channel B
OUTC
5
O
Output, channel C
OUTD
6
O
Output, channel D
VCC1
1
—
Power supply, VCC1
VCC2
16
—
Power supply, VCC2
Copyright © 2014–2017, Texas Instruments Incorporated
5
ISO7842, ISO7842F
ZHCSD14G – OCTOBER 2014 – REVISED MARCH 2017
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
See
(1)
VCC1,
VCC2
Supply voltage (2)
Voltage
MAX
–0.5
6
–0.5
VCCX + 0.5
–0.5
VCCX + 0.5 (3)
–0.5
(3)
VCCX + 0.5
–15
Surge immunity
(1)
(2)
(3)
V
(3)
OUTx
Output current
Tstg
UNIT
INx
ENx
IO
MIN
Storage temperature
–65
V
15
mA
12.8
kV
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak
voltage values.
Maximum voltage must not exceed 6 V
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
±6000
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
VCC1,
VCC2
Supply voltage
2.25
VCCO
IOH
High-level output current
Low-level output current
(1)
=5V
(1)
MAX
5.5
–2
= 2.5 V
–1
4
VCCO (1) = 3.3 V
2
VCCO
V
mA
VCCO (1) = 5 V
(1)
UNIT
–4
VCCO (1) = 3.3 V
VCCO
IOL
NOM
= 2.5 V
mA
1
VIL
Low-level input voltage
0
0.3 × VCCI (1)
DR
Signaling rate
0
100
Mbps
TJ
Junction temperature (2)
–55
150
°C
TA
Ambient temperature
–55
125
°C
6
VCCI
(1)
High-level input voltage
(1)
(2)
0.7 × VCCI
(1)
VIH
25
V
V
VCCI = Input-side VCC; VCCO = Output-side VCC.
To maintain the recommended operating conditions for TJ, see Thermal Information.
Copyright © 2014–2017, Texas Instruments Incorporated
ISO7842, ISO7842F
www.ti.com.cn
ZHCSD14G – OCTOBER 2014 – REVISED MARCH 2017
6.4 Thermal Information
ISO7842
THERMAL METRIC (1)
DW (SOIC)
DWW (SOIC)
16 Pins
16 Pins
UNIT
RθJA
Junction-to-ambient thermal resistance
78.9
78.9
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
41.6
41.1
°C/W
RθJB
Junction-to-board thermal resistance
43.6
49.5
°C/W
ψJT
Junction-to-top characterization parameter
15.5
15.2
°C/W
ψJB
Junction-to-board characterization parameter
43.1
48.8
°C/W
N/A
N/A
°C/W
RθJC(bottom) Junction-to-case(bottom) thermal resistance
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Power Ratings
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF, input a 50 MHz 50% duty cycle square wave
MAX
UNIT
PD
Maximum power dissipation by ISO7842x
PARAMETER
200
mW
PD1
Maximum power dissipation by side-1 of
ISO7842x
100
mW
PD2
Maximum power dissipation by side-2 of
ISO7842x
100
mW
Copyright © 2014–2017, Texas Instruments Incorporated
TEST CONDITIONS
MIN
TYP
7
ISO7842, ISO7842F
ZHCSD14G – OCTOBER 2014 – REVISED MARCH 2017
www.ti.com.cn
6.6 Insulation Specifications
PARAMETER
TEST CONDITIONS
External clearance (1)
CPG
SPECIFICATION
UNIT
DW
DWW
Shortest pin-to-pin distance through air
>8
>14.5
mm
External creepage (1)
Shortest pin-to-pin distance across the package
surfaceHigh Voltage Feature Description
>8
>14.5
mm
DTI
Distance through the insulation
Minimum internal gap (internal clearance)
>21
>21
μm
CTI
Comparative tracking index
DIN EN 60112 (VDE 0303-11); IEC 60112; UL 746A
>600
>600
V
I
I
Rated mains voltage ≤ 600 VRMS
I–IV
I–IV
Rated mains voltage ≤ 1000 VRMS
I–III
I–IV
2121
2828
VPK
1500
2000
VRMS
GENERAL
CLR
Material group
Overvoltage category per IEC
60664-1
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 (2)
VIORM
Maximum repetitive peak isolation
voltage
VIOWM
AC voltage (sine wave); Time dependent dielectric
Maximum isolation working voltage breakdown (TDDB) Test, see Figure 1 and Figure 2
DC voltage
2121
2828
VDC
8000
8000
VPK
8000
8000
VPK
Method a: After I/O safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.2 × VIORM = 2545 VPK (DW) and 3394 VPK
(DWW), tm = 10 s
≤5
≤5
Method a: After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.6 × VIORM = 3394 VPK (DW) and 4525 VPK
(DWW), tm = 10 s
≤5
≤5
Method b1: At routine test (100% production) and
preconditioning (type test)
Vini = VIOTM, tini = 1 s;
Vpd(m) = 1.875 × VIORM = 3977 VPK (DW) and 5303 VPK
(DWW), tm = 1 s
≤5
≤5
VIO = 0.4 × sin (2πft), f = 1 MHz
2
2
VIOTM
Maximum transient isolation
voltage
VTEST = VIOTM
t = 60 s (qualification)
t= 1 s (100% production)
VIOSM
Maximum surge isolation voltage (3)
Test method per IEC 60065, 1.2/50 µs waveform,
VTEST = 1.6 × VIOSM = 12800 VPK (qualification)
qpd
Apparent charge
(4)
CIO
Barrier capacitance, input to
output (5)
RIO
Isolation resistance, input to
output (5)
>1012
>1012
11
>1011
9
>10
>109
Pollution degree
2
2
Climatic category
55/125/21
55/125/21
5700
5700
VIO = 500 V, TA = 25°C
VIO = 500 V, 100°C ≤ TA ≤ 125°C
>10
VIO = 500 V at TS = 150°C
pC
pF
Ω
UL 1577
VISO
(1)
(2)
(3)
(4)
(5)
8
Withstand isolation voltage
VTEST = VISO = 5700 VRMS, t = 60 s (qualification),
VTEST = 1.2 × VISO = 6840 VRMS, t = 1 s (100%
production)
VRMS
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care
should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on
the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications.
This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by
means of suitable protective circuits.
Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
Apparent charge is electrical discharge caused by a partial discharge (pd).
All pins on each side of the barrier tied together creating a two-pin device.
Copyright © 2014–2017, Texas Instruments Incorporated
ISO7842, ISO7842F
www.ti.com.cn
ZHCSD14G – OCTOBER 2014 – REVISED MARCH 2017
6.7 Safety-Related Certifications
Certifications for the DW package are complete. DWW package certifications are complete for UL, VDE and TUV and
planned for CSA and CQC.
VDE
Certified according to DIN
V VDE V 0884-10 (VDE V
0884-10):2006-12 and DIN
EN 60950-1 (VDE 0805
Teil 1):2011-01
CSA
Approved under CSA
Component Acceptance
Notice 5A, IEC 60950-1 and
IEC 60601-1
UL
CQC
TUV
Certified according to GB
4943.1-2011
Certified according to
EN 61010-1:2010 (3rd Ed) and
EN 60950-1:2006/A11:2009/A1:2010/
A12:2011/A2:2013
Reinforced insulation per CSA
60950-1-07+A1+A2 and IEC
60950-1 2nd Ed., 800 VRMS
Reinforced insulation
(DW package) and 1450 VRMS
Maximum transient
isolation voltage, 8000 VPK; (DWW package) max working
voltage (pollution degree 2,
Maximum repetitive peak
Single protection, 5700
isolation voltage, 2121 VPK material group I);
VRMS
(DW), 2828 VPK (DWW);
2 MOPP (Means of Patient
Maximum surge isolation
Protection) per CSA 60601voltage, 8000 VPK
1:14 and IEC 60601-1 Ed. 3.1,
250 VRMS (354 VPK) max
working voltage (DW package)
Reinforced Insulation,
Altitude ≤ 5000 m, Tropical
Climate, 250 VRMS
maximum working voltage
5700 VRMS Reinforced insulation per
EN 61010-1:2010 (3rd Ed) up to
working voltage of 600 VRMS (DW
package) and 1000 VRMS (DWW
package)
5700 VRMS Reinforced insulation per
EN 60950-1:2006/A11:2009/A1:2010/
A12:2011/A2:2013 up to working
voltage of 800 VRMS (DW package) and
1450 VRMS (DWW package)
Certificate number:
40040142
Certificate number:
CQC15001121716
Client ID number: 77311
Master contract number:
220991
Certified according to UL
1577 Component
Recognition Program
File number: E181974
6.8 Safety Limiting Values
Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure of
the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat
the die and damage the isolation barrier potentially leading to secondary system failures.
PARAMETER
IS
Safety input, output, or supply
current
PS
Safety input, output, or total
power
TS
Maximum safety temperature
TEST CONDITIONS
MIN
TYP
MAX
RθJA = 78.9°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C
288
RθJA = 78.9°C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C
440
RθJA = 78.9°C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C
576
RθJA = 78.9°C/W, TJ = 150°C, TA = 25°C
UNIT
mA
1584
mW
150
°C
The maximum safety temperature is the maximum junction temperature specified for the device. The power
dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines
the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information is that of a
device installed on a high-K test board for leaded surface-mount packages. The power is the recommended
maximum input voltage times the current. The junction temperature is then the ambient temperature plus the
power times the junction-to-air thermal resistance.
Copyright © 2014–2017, Texas Instruments Incorporated
9
ISO7842, ISO7842F
ZHCSD14G – OCTOBER 2014 – REVISED MARCH 2017
www.ti.com.cn
6.9 Electrical Characteristics–5-V Supply
VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
VCCO (1) – 0.4
VCCO (1) – 0.2
VOH
High-level output voltage
IOH = –4 mA; see Figure 11
VOL
Low-level output voltage
IOL = 4 mA; see Figure 11
VI(HYS)
Input threshold voltage hysteresis
IIH
High-level input current
VIH = VCCI (1) at INx or ENx
IIL
Low-level input current
VIL = 0 V at INx or ENx
-10
CMTI
Common-mode transient immunity
VI = VCCI (1) or 0 V, VCM = 1500 V; see
Figure 14
100
CI
Input capacitance
VI = VCC/2 + 0.4 × sin (2πft), f = 1 MHz,
VCC = 5 V
(1)
0.2
0.1 × VCCI
MAX
UNIT
V
0.4
(1)
V
V
10
μA
kV/μs
2
pF
VCCI = Input-side VCC; VCCO = Output-side VCC.
6.10 Supply Current Characteristics–5-V Supply
VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
SUPPLY
CURRENT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ICC1, ICC2
1
1.5
mA
ICC1, ICC2
3.4
4.8
mA
ICC1, ICC2
2
2.7
mA
VI = VCCI (ISO7842F), VI = 0 V
(ISO7842)
ICC1, ICC2
4.4
6.1
mA
1 Mbps
ICC1, ICC2
3.3
4.6
mA
10 Mbps
ICC1, ICC2
4.2
5.6
mA
100 Mbps
ICC1, ICC2
13.7
16.6
mA
EN1 = EN2 = 0V, VI = 0 V (ISO7842F),
VI = VCCI (1) (ISO7842)
ICC1, ICC2
1
1.5
mA
EN1 = EN2 = 0 V, VI = VCCI (1)
(ISO7842F), VI = 0 V (ISO7842)
ICC1, ICC2
3.4
4.8
mA
VI = 0 V (ISO7842F), VI = VCCI (1)
(ISO7842)
ICC1, ICC2
2
2.8
mA
VI = VCCI (1) (ISO7842F), VI = 0 V
(ISO7842)
ICC1, ICC2
4.4
6.3
mA
1 Mbps
ICC1, ICC2
3.4
4.7
mA
10 Mbps
ICC1, ICC2
4.3
5.9
mA
100 Mbps
ICC1, ICC2
14
17.3
mA
ISO7842DW AND ISO7842FDW
Disable
Supply current
DC signal
All channels switching with
square wave clock input;
CL = 15 pF
EN1 = EN2 = 0V, VI = 0 V (ISO7842F),
VI = VCCI (1) (ISO7842)
(1)
EN1 = EN2 = 0 V, VI = VCCI
(ISO7842F), VI = 0 V (ISO7842)
VI = 0 V (ISO7842F), VI = VCCI
(ISO7842)
(1)
(1)
ISO7842DWW AND ISO7842FDWW
Disable
Supply current
DC signal
All channels switching with
square wave clock input;
CL = 15 pF
(1)
10
VCCI = Input-side VCC; VCCO = Output-side VCC.
Copyright © 2014–2017, Texas Instruments Incorporated
ISO7842, ISO7842F
www.ti.com.cn
ZHCSD14G – OCTOBER 2014 – REVISED MARCH 2017
6.11 Electrical Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
VCCO (1) – 0.4
VCCO (1) – 0.2
MAX
UNIT
VOH
High-level output voltage
IOH = –2 mA; see Figure 11
VOL
Low-level output voltage
IOL = 2 mA; see Figure 11
VI(HYS)
Input threshold voltage hysteresis
IIH
High-level input current
VIH = VCCI (1) at INx or ENx
IIL
Low-level input current
VIL = 0 V at INx or ENx
–10
μA
Common-mode transient immunity
VI = VCCI (1) or 0 V, VCM = 1500 V; see
Figure 14
100
kV/μs
CMTI
(1)
0.2
V
0.4
V
10
μA
0.1 × VCCI (1)
V
VCCI = Input-side VCC; VCCO = Output-side VCC.
6.12 Supply Current Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
SUPPLY
CURRENT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ICC1, ICC2
1
1.5
mA
ICC1, ICC2
3.4
4.8
mA
ICC1, ICC2
2
2.7
mA
VI = VCCI (ISO7842F), VI = 0 V
(ISO7842)
ICC1, ICC2
4.4
6.1
mA
1 Mbps
ICC1, ICC2
3.3
4.5
mA
10 Mbps
ICC1, ICC2
4
5.2
mA
100 Mbps
ICC1, ICC2
10.8
12.9
mA
EN1 = EN2 = 0 V, VI = 0 V (ISO7842F), VI
= VCCI (1) (ISO7842)
ICC1, ICC2
1
1.5
mA
EN1 = EN2 = 0 V, VI = VCCI (1) (ISO7842F),
VI = 0 V (ISO7842)
ICC1, ICC2
3.4
4.8
mA
VI = 0 V (ISO7842F), VI = VCCI (1)
(ISO7842)
ICC1, ICC2
2
2.8
mA
VI = VCCI (1) (ISO7842F), VI = 0 V
(ISO7842)
ICC1, ICC2
4.4
6.3
mA
1 Mbps
ICC1, ICC2
3.4
4.7
mA
10 Mbps
ICC1, ICC2
4.1
5.5
mA
100 Mbps
ICC1, ICC2
11
13.6
mA
ISO7842DW AND ISO7842FDW
Disable
Supply current
DC signal
All channels switching with
square wave clock input;
CL = 15 pF
EN1 = EN2 = 0 V, VI = 0 V (ISO7842F), VI
= VCCI (1) (ISO7842)
EN1 = EN2 = 0 V, VI = VCCI
VI = 0 V (ISO7842)
(1)
(ISO7842F),
VI = 0 V (ISO7842F), VI = VCCI
(ISO7842)
(1)
(1)
ISO7842DWW and ISO7842FDWW
Disable
Supply current
DC signal
All channels switching with
square wave clock input;
CL = 15 pF
(1)
VCCI = Input-side VCC; VCCO = Output-side VCC.
Copyright © 2014–2017, Texas Instruments Incorporated
11
ISO7842, ISO7842F
ZHCSD14G – OCTOBER 2014 – REVISED MARCH 2017
www.ti.com.cn
6.13 Electrical Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
VCCO (1) – 0.4
VCCO (1) – 0.2
MAX
UNIT
VOH
High-level output voltage
IOH = –1 mA; see Figure 11
VOL
Low-level output voltage
IOL = 1 mA; see Figure 11
VI(HYS)
Input threshold voltage hysteresis
IIH
High-level input current
VIH = VCCI (1) at INx or ENx
IIL
Low-level input current
VIL = 0 V at INx or ENx
–10
μA
Common-mode transient immunity
VI = VCCI (1) or 0 V, VCM = 1500 V; see
Figure 14
100
kV/μs
CMTI
(1)
V
0.2
0.4
V
10
μA
0.1 × VCCI (1)
V
VCCI = Input-side VCC; VCCO = Output-side VCC.
6.14 Supply Current Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
SUPPLY
CURRENT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ICC1, ICC2
1
1.5
mA
ICC1, ICC2
3.4
4.8
mA
ICC1, ICC2
2
2.7
mA
VI = VCCI (ISO7842F), VI = 0 V
(ISO7842)
ICC1, ICC2
4.4
6.1
mA
1 Mbps
ICC1, ICC2
3.2
4.5
mA
10 Mbps
ICC1, ICC2
3.7
5.1
mA
100 Mbps
ICC1, ICC2
8.9
10.8
mA
EN1 = EN2 = 0 V, VI = 0 V (ISO7842F), VI
= VCCI (1) (ISO7842)
ICC1, ICC2
1
1.5
mA
EN1 = EN2 = 0 V, VI = VCCI (1) (ISO7842F),
VI = 0 V (ISO7842)
ICC1, ICC2
3.4
4.8
mA
VI = 0 V (ISO7842F), VI = VCCI (1)
(ISO7842)
ICC1, ICC2
2
2.8
mA
VI = VCCI (1) (ISO7842F), VI = 0 V
(ISO7842)
ICC1, ICC2
4.4
6.3
mA
1 Mbps
ICC1, ICC2
3.3
4.6
mA
10 Mbps
ICC1, ICC2
3.8
5.3
mA
100 Mbps
ICC1, ICC2
9
11.5
mA
ISO7842DW AND ISO7842FDW
Disable
Supply current
DC signal
All channels switching with
square wave clock input;
CL = 15 pF
EN1 = EN2 = 0 V, VI = 0 V (ISO7842F), VI
= VCCI (1) (ISO7842)
EN1 = EN2 = 0 V, VI = VCCI
VI = 0 V (ISO7842)
(1)
(ISO7842F),
VI = 0 V (ISO7842F), VI = VCCI
(ISO7842)
(1)
(1)
ISO7842DWW AND ISO7842FDWW
Disable
Supply current
DC signal
All channels switching with
square wave clock input;
CL = 15 pF
(1)
12
VCCI = Input-side VCC; VCCO = Output-side VCC.
Copyright © 2014–2017, Texas Instruments Incorporated
ISO7842, ISO7842F
www.ti.com.cn
ZHCSD14G – OCTOBER 2014 – REVISED MARCH 2017
6.15 Switching Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
MIN
TYP
MAX
6
11
16
ns
0.55
4.1
ns
2.5
ns
4.5
ns
1.7
3.9
ns
1.9
3.9
ns
tPHZ
Disable propagation delay, high-to-high impedance
output
12
20
ns
tPLZ
Disable propagation delay, low-to-high impedance
output
12
20
ns
10
20
ns
2
2.5
μs
Enable propagation delay, high impedance-to-low
output for ISO7842
2
2.5
μs
Enable propagation delay, high impedance-to-low
output for ISO7842F
10
20
ns
0.2
9
μs
tPLH, tPHL
Propagation delay time
PWD
Pulse width distortion (1) |tPHL – tPLH|
tsk(o)
Channel-to-channel output skew time (2)
tsk(pp)
Part-to-part skew time (3)
tr
Output signal rise time
tf
Output signal fall time
Enable propagation delay, high impedance-to-high
output for ISO7842
tPZH
Enable propagation delay, high impedance-to-high
output for ISO7842F
tPZL
tfs
Default output delay time from input power loss
tie
(1)
(2)
(3)
Time interval error
TEST CONDITIONS
See Figure 11
Same-direction channels
See Figure 11
UNIT
See Figure 12
Measured from the time VCC goes below 1.7 V. See
Figure 13
16
2
0.90
– 1 PRBS data at 100 Mbps
ns
Also known as pulse skew.
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
6.16 Switching Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
MIN
TYP
MAX
6
10.8
16
ns
0.7
4.2
ns
2.2
ns
4.5
ns
0.8
3
ns
0.8
3
ns
tPHZ
Disable propagation delay, high-to-high impedance
output
17
32
ns
tPLZ
Disable propagation delay, low-to-high impedance
output
17
32
ns
17
32
ns
2
2.5
μs
Enable propagation delay, high impedance-to-low
output for ISO7842
2
2.5
μs
Enable propagation delay, high impedance-to-low
output for ISO7842F
17
32
ns
0.2
9
μs
tPLH, tPHL
Propagation delay time
PWD
Pulse width distortion (1) |tPHL – tPLH|
tsk(o)
Channel-to-channel output skew time (2)
tsk(pp)
Part-to-part skew time (3)
tr
Output signal rise time
tf
Output signal fall time
tPZH
tPZL
tfs
tie
(1)
(2)
(3)
Enable propagation delay, high impedance-to-high
output for ISO7842
Enable propagation delay, high impedance-to-high
output for ISO7842F
Default output delay time from input power loss
Time interval error
TEST CONDITIONS
See Figure 11
Same-direction channels
See Figure 11
UNIT
See Figure 12
Measured from the time VCC goes below 1.7 V.
See Figure 13
16
2
– 1 PRBS data at 100 Mbps
0.91
ns
Also known as Pulse Skew.
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
Copyright © 2014–2017, Texas Instruments Incorporated
13
ISO7842, ISO7842F
ZHCSD14G – OCTOBER 2014 – REVISED MARCH 2017
www.ti.com.cn
6.17 Switching Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
7.5
11.7
17.5
ns
0.66
4.2
ns
2.2
ns
4.5
ns
1
3.5
ns
1.2
3.5
ns
tPHZ
Disable propagation delay, high-to-high impedance
output
22
45
ns
tPLZ
Disable propagation delay, low-to-high impedance
output
22
45
ns
18
45
ns
2
2.5
μs
Enable propagation delay, high impedance-to-low
output for ISO7842
2
2.5
μs
Enable propagation delay, high impedance-to-low
output for ISO7842F
18
45
ns
0.2
9
μs
tPLH, tPHL
Propagation delay time
PWD
Pulse width distortion (1) |tPHL – tPLH|
tsk(o)
Channel-to-channel output skew time (2)
tsk(pp)
Part-to-part skew time (3)
tr
Output signal rise time
tf
Output signal fall time
tPZH
tPZL
tfs
tie
(1)
(2)
(3)
14
Enable propagation delay, high impedance-to-high
output for ISO7842
Enable propagation delay, high impedance-to-high
output for ISO7842F
Default output delay time from input power loss
Time interval error
TEST CONDITIONS
See Figure 11
Same-direction Channels
See Figure 11
See Figure 12
Measured from the time VCC goes below 1.7 V.
See Figure 13
16
2
– 1 PRBS data at 100 Mbps
0.91
ns
Also known as pulse skew.
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
Copyright © 2014–2017, Texas Instruments Incorporated
ISO7842, ISO7842F
www.ti.com.cn
ZHCSD14G – OCTOBER 2014 – REVISED MARCH 2017
6.18 Insulation Characteristics Curves
1.E+11
87.5%
1.E+9
1.E+9
1.E+8
1.E+8
1.E+7
1.E+6
1.E+5
Safety Margin Zone: 2400 VRMS, 63 Years
Operating Zone: 2000 VRMS, 34 Years
TDDB Line (
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湘ICP备2023018690号
