ISOW1412DFMR

ISOW1412, ISOW1432 SLLSF86C – MAY 2018 – REVISED MARCH 2022 ISOW14x2 Isolated RS-485/RS-422 Transceiver with Integrated Low-Emissions, LowNoise, High-Efficiency DC-DC Converter – UL 1577 component recognition program – IEC 62368-1, IEC 61010-1, IEC 60601-1 and GB 4943.1-2011 certifications 1 Features • • • • • • • • • • • • • • Meets or exceeds the requirements of the TIA/ EIA-485A standard Data rates – ISOW1412 : 500 kbps – ISOW1432 : 12 Mbps Integrated low-emissions DC-DC converter with low-emissions, low-noise – Meets CISPR 32 Class B and EN 55032 Class B with margin on a two-layer PCB – Low frequency power converter at 25 MHz enabling low noise performance Additional 2 Mbps GPIO channel High efficiency output power – Typical efficiency: 46% – VISOOUT accuracy: ±5% – Additional output current: 20 mA Independent power supply for RS-485 & DC-DC – Logic supply (VIO): 1.71 V to 5.5 V – Power converter supply ( VDD): 3 V to 5.5 V RS-485 with PROFIBUS compatibility – Open, short, and idle bus failsafe – 1/8 unit load: up to 256 nodes on bus – Glitch-free power up and power down Reinforced and Basic isolation options High CMTI: 100-kV/µs (typical) High ESD bus protection – HBM: ±16 kV – IEC 61000-4-2 contact discharge: ±8 kV Operating temperature range: -40°C to 125°C Current limit and thermal shutdown 20-pin wide SOIC package 2 Applications • • • • • Factory automation Building automation Industrial transport Solar inverters, protection relay Motor drives 3 Description The ISOW14x2 devices are galvanically-isolated RS-485/RS-422 transceivers with a built-in isolated DC-DC converter, that eliminates the need for a separate isolated power supply in space constrained isolated designs. The low-emissions, isolated DCDC converter meets CISPR 32 radiated emissions Class B standard with just two ferrite beads on a simple two-layer PCB. Additional 20 mA output current can be used to power other circuits on the board. An integrated 2 Mbps GPIO channel helps remove any additional digital isolator or optocoupler for diagnotstics, LED indication or supply monitoring. Device Information FEATURE ISOW1412 ISOW1432 Protection Level Reinforced Basic Surge Test Voltage 10 kVPK 7.8 kVPK Isolation Rating 5000 VRMS 5000 VRMS Working Voltage Section 8.6: – VDE reinforced and basic insulation per DIN VDE V 0884-11:2017-01 ISOW1412B ISOW1432B (1) 1000 VRMS/1500 VPK 1000 VRMS/1500 VPK Package(1) DFM (20) DFM (20) Body Size 12.83 mm x 7.5 mm 12.83 mm x 7.5 mm For all available packages, see the orderable addendum at the end of the data sheet. VCC VIO MCU DE D R RE VISOIN Sign al Isol atio n Sign al Isol atio n Must be connected on PCB, not connected internally Y Z B A RS485 RS485 Bu s GISOIN GNDIO VISOOU T VDD GND1 DC-DC Primary DC-DC Second ary GND2 Gal van ic Isola tion Bar rier Simplified Schematic An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. ISOW1412, ISOW1432 www.ti.com SLLSF86C – MAY 2018 – REVISED MARCH 2022 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Description Continued.................................................... 3 6 Device Comparison Table ..............................................3 7 Pin Configuration and Functions...................................4 8 Specifications.................................................................. 6 8.1 Absolute Maximum Ratings........................................ 6 8.2 Recommended Operating Conditions.........................7 8.3 Thermal Information....................................................7 8.4 Power Ratings.............................................................8 8.5 Insulation Specifications............................................. 9 8.6 Safety-Related Certifications.................................... 10 8.7 Safety Limiting Values...............................................10 8.8 Electrical Characteristics...........................................11 8.9 Supply Current Characteristics at VISOOUT = 3.3 V... 13 8.10 Supply Current Characteristics at VISOOUT = 5 V... 15 8.11 Switching Characteristics at VISOOUT = 3.3 V..........16 8.12 Switching Characteristics at VISOOUT = 5 V.............18 8.13 Insulation Characteristics Curves........................... 19 8.14 Typical Characteristics............................................ 20 9 Parameter Measurement Information.......................... 26 10 Detailed Description....................................................29 10.1 Overview................................................................. 29 10.2 Power Isolation....................................................... 29 10.3 Signal Isolation........................................................29 10.4 RS-485....................................................................29 10.5 Functional Block Diagram....................................... 30 10.6 Feature Description.................................................30 10.7 Device Functional Modes........................................32 10.8 Device I/O Schematics............................................35 11 Application and Implementation................................ 36 11.1 Application Information............................................36 11.2 Typical Application.................................................. 37 12 Power Supply Recommendations..............................39 13 Layout...........................................................................41 13.1 Layout Guidelines................................................... 41 13.2 Layout Example...................................................... 41 14 Device and Documentation Support..........................42 14.1 Documentation Support.......................................... 42 14.2 Receiving Notification of Documentation Updates..42 14.3 Support Resources................................................. 42 14.4 Trademarks............................................................. 42 14.5 Electrostatic Discharge Caution..............................42 14.6 Glossary..................................................................42 15 Mechanical, Packaging, and Orderable Information.................................................................... 42 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (October 2021) to Revision C (March 2022) Page • Changed ISOW1432 from Advanced Information to Production Data................................................................1 Changes from Revision A (May 2021) to Revision B (October 2021) Page • Changed ISOW1412 from Advanced Information to Production Data................................................................1 Changes from Revision * (May 2018) to Revision A (May 2021) Page • Updated data sheet to include ISOW1432 device.............................................................................................. 1 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ISOW1412 ISOW1432 ISOW1412, ISOW1432 www.ti.com SLLSF86C – MAY 2018 – REVISED MARCH 2022 5 Description Continued Two options of data rates are provided: ISOW1412 is optimized for maximum 500 kbps and ISOW1432 is suitable for maximum 12 Mbps data rate. These devices do not require any external components other than bypass capacitors to realize an isolated RS-485 port, ideal for long distance communications. Isolation breaks the ground loop between the communicating nodes, allowing for a much larger common mode voltage range. Both signal and power paths are 5-kVRMS isolated per UL1577 and are qualified for reinforced and basic isolation per VDE, TUV, CSA and CQC. The ISOW14x2 can operate from a single supply voltage of 3 V to 5.5 V by connecting VIO and V DD together on PCB. If lower logic levels are required, 1.71 V to 5.5 V logic supply (VIO) can be separated and independent from the power converter supply (VDD) of 3 V to 5.5 V. These devices support a wide operating ambient temperature range from –40°C to +125°C and are available in 20-pin DFM (SOIC-20 footprint compatible package) offering a minimum of 8-mm creepage and clearance. 6 Device Comparison Table Part number Isolation Duplex Data Rate Package ISOW1412/ISOW1412B Reinforced/Basic Full 500 kbps 20-DFM(SOIC) ISOW1432/ISOW1432B Reinforced/Basic Full 12 Mbps 20-DFM(SOIC) Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ISOW1412 ISOW1432 3 ISOW1412, ISOW1432 www.ti.com SLLSF86C – MAY 2018 – REVISED MARCH 2022 7 Pin Configuration and Functions 1 20 A D 2 19 B DE 3 18 Z R 4 17 Y RE 5 16 VIS OIN GNDIO 6 15 GISOIN OUT 7 14 IN EN/FLT 8 13 MODE VDD 9 12 VIS OOUT 10 11 GND2 GND1 IS O L AT IO N VIO Figure 7-1. ISOW14x2 20-pin DFM Top View 4 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ISOW1412 ISOW1432 ISOW1412, ISOW1432 www.ti.com SLLSF86C – MAY 2018 – REVISED MARCH 2022 Table 7-1. Pin Functions PIN NAME NO. I/O DESCRIPTION VIO 1 -- Side 1 logic supply D 2 I Data input DE 3 I Driver enable. If pin is floating, driver is disabled (internal pull-down resistor) R 4 O Received data output RE 5 I Receiver enable. If pin is floating, receiver buffer is disabled (internal pull-up resistor) GNDIO 6 -- Ground connections for VIO . GNDIO and GND1 need be shorted directly on PCB. OUT 7 O General purpose logic output Multi-function power converter enable input pin or fault output pin. Can only be used as either an input pin or an output pin. • EN/FLT 8 I/O • If it's used as Power converter enable input pin, it enables and disables the integrated DC-DC power converter. Connect directly to microcontroller or through a series current limiting resistor to use as an enable input pin. DC-DC power converted is enabled when EN is high (connected to VIO) and disabled when low (connected to GND1). If EN is floating, DC-DC converter is enabled (internal pull-up resistor) If it's used as Fault output pin, it gives an alert signal if power converter is not operating properly. This pin is active low. Connect to microcontroller through a 5 kΩ or greater pull-up resistor in order to use as a fault outpin pin. VDD 9 -- Side 1 DC-DC converter power supply GND1 10 -- Ground connection for VIO. GNDIO and GND1 need be shorted directly on PCB. GND2 11 -- Ground connection for VISOOUT. GND2 and GISOIN need be shorted direclty on PCB, or connected through a ferrite bead. VISOOUT 12 -- Isolated power converter output voltage. VISOOUT and VISOIN need be shorted directly on PCB, or connected through a ferrite bead. MODE 13 I Mode select. For RS-485 transceiver to operate at 3.3V supply, connect MODE to GND2. For RS-485 transceiver to operate in 5V supply PROFIBUS mode, connect MODE to VISOOUT (internal pull-down resistor) IN 14 I General purpose logic input GISOIN 15 -- Ground connections for VISOIN. GND2 and GISOIN need be shorted direclty on PCB, or connected through a ferrite bead. VISOIN 16 -- Side 2 supply voltage for RS485. VISOOUT and VISOIN need be shorted directly on PCB, or connected through a ferrite bead. Y 17 O RS-485 driver non-inverting output Z 18 O RS-485 driver inverting output B 19 I RS-485 receiver inverting input A 20 I RS-485 receiver non-inverting input Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ISOW1412 ISOW1432 5 ISOW1412, ISOW1432 www.ti.com SLLSF86C – MAY 2018 – REVISED MARCH 2022 8 Specifications 8.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) (2) MAX UNIT VDD Power converter supply voltage –0.5 6 V VISOIN Isolated supply voltage, input supply for RS-485 transceiver –0.5 6 V VISOOUT Isolated supply voltage, Power converter output at RS485 mode (MODE = GND2) –0.5 4 V VISOOUT Isolated supply voltage, Power converter output at Profibus mode (MODE = VISOOUT) –0.5 6 V VIO Logic supply voltage –0.5 6 V VBUS Voltage on bus pins (A, B, Y, Z with respect to GND2) –12 15 V Logic I/O voltage level (D, DE, RE, R, EN, OUT) –0.5 0.5(3) V IN -0.5 VISOIN + 0.5 V VLOGIC_IO VIO + MODE -0.5 VISOOUT + 0.5 IO Output current on R and OUT pins –15 15 mA TJ Junction temperature –40 150 °C Tstg Storage temperature –65 150 °C (1) (2) (3) 6 MIN V Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the deviceat these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values except differential I/O bus voltages are with respect to the local ground pin (GND1 or GND2). All voltage values except differential I/O bus voltages are peak voltage values. The maximum voltage must not be greater than 6 V. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ISOW1412 ISOW1432 ISOW1412, ISOW1432 www.ti.com SLLSF86C – MAY 2018 – REVISED MARCH 2022 8.2 Recommended Operating Conditions MIN NOM 1.8-V operation 1.71 1.89 2.5-V, 3.3-V, and 5-V operation 2.25 5.5 VIO Logic supply voltage VDD Power converter supply voltage VDD(UVLO+) Positive threshold when power converter supply is rising VDD(UVLO-) Positive threshold when power converter supply is falling 3 VHYS1(UVLO) Power converter supply voltage hysteresis VIO(UVLO+) Rising threshold of logic supply voltage VIO(UVLO-) Falling threshold of logic supply voltage MAX 2.8 UNIT V 5.5 V 2.93 V 2.40 2.55 V 0.15 0.25 V 1.7 1 V V VHYS2(UVLO) Logic supply voltage hysteresis 75 VBUS –7 12 V 0.7 × VIO VIO V 0.7 × VISOIN VISOIN V 0 0.3 × VIO V 0 0.3 × VISOIN V Input voltage at any bus terminal (seperately w.r.t GND2 or common mode) High-level input voltage (D, DE, EN, and RE inputs) VIH High- level input voltage (IN input) Low-level input voltage (D, DE, EN, and RE inputs) VIL Low- level input voltage (IN input) 125 mV VID Differential input voltage (receiver terminals A w.r.t B) –12 12 V IO(DRV) Output current, driver (Y, Z) IO Output current, R and OUT pins –60 60 mA VIO = 4.5 to 5.5 V –4 4 mA VIO = 3 to 3.6 V -2 2 mA VIO = 2.25 to 2.75 V, 1.71 to 1.89 V -1 1 mA RL Differential load resistance on bus 1/tUI Signaling rate ISOW1412 500 kbps 1/tUI Signaling rate ISOW1432 12 Mbps DR Data rate for GPIO channel 2 Mbps tpwrup Power up time after applying input supply(Isolated output supply reaches 90% of setpoint and data transmission can start after this) TA (1) 54 Ω 5 ms Ambient operating temperature (MODE= GND2), no extra current availalbe on VISOUT (1) –40 125 °C Ambient operating temperature (MODE= GND2), 20 mA extra current available on VISOUT (1) –40 105 °C Ambient operating temperature (MODE= VISOOUT), 50% duty cycle on DE, no extra current available on VISOUT (1) –40 125 °C Ambient operating temperature (MODE= VISOOUT), no extra current available on VISOUT (1) –40 105 °C Ambient operating temperature (MODE= VISOOUT), 20 mA extra current available on VISOUT (1) –40 85 °C Extra current is only available at VDD=5 V ± 10% mode 8.3 Thermal Information ISOW14x2 THERMAL METRIC(1) DFM UNIT 20 PINS RθJA Junction-to-ambient thermal resistance 68.5 °C/W RθJC(top) Junction-to-case (top) thermal resistance 20.9 °C/W Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ISOW1412 ISOW1432 7 ISOW1412, ISOW1432 www.ti.com SLLSF86C – MAY 2018 – REVISED MARCH 2022 ISOW14x2 THERMAL METRIC(1) UNIT DFM 20 PINS RθJB Junction-to-board thermal resistance ΨJT ΨJB RθJC(bot) (1) 44.8 °C/W Junction-to-top characterization parameter 13 °C/W Junction-to-board characterization parameter 44 °C/W Junction-to-case (bottom) thermal resistance -- °C/W For more informationabout traditional and new thermal metrics, see theSemiconductor andIC Package Thermal Metrics application report. 8.4 Power Ratings PARAMETER 8 PD Maximum power dissipation (both sides) PD1 Maximum power dissipation (side-1) PD2 Maximum power dissipation by (side-2) PD Maximum power dissipation (both sides) PD1 Maximum power dissipation (side-1) PD2 Maximum power dissipation by (side-2) TEST CONDITIONS MAX UNIT VDD = VIO = 5.5V, MODE = VISOOUT, TJ = 150°C, Y-Z load = 54Ω||50pF, Y shorted to A, Z shorted to B(loopback), Load on R = 15pF, Input a 250kHz 50% duty cycle square wave to D pin with VDE = VIO, VRE = GND1, ISOW1412 1060 mW 490 mW 570 mW VDD= VIO= 5.5V, MODE= VISOOUT, TJ=150°C, Y-Z load= 54Ω||50pF, Y shorted to A, Z shorted to B(loopback), Load on R=15pF, Input a 6MHz 50% duty cycle square wave to D pin with VDE=VIO, VRE=GND1, ISOW1432 1110 mW 510 mW 610 mW Submit Document Feedback MIN TYP Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ISOW1412 ISOW1432 ISOW1412, ISOW1432 www.ti.com SLLSF86C – MAY 2018 – REVISED MARCH 2022 8.5 Insulation Specifications PARAMETER TEST CONDITIONS VALUE UNIT GENERAL CLR External clearance(1) Shortest terminal-to-terminal distance through air >8 mm CPG External creepage(1) Shortest terminal-to-terminal distance across the package surface >8 mm Distance through the insulation Minimum internal gap (internal clearance – capacitive signal isolation) > 17 DTI Minimum internal gap (internal clearance- transformer power isolation) > 120 Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112 > 600 Material group According to IEC 60664-1 CTI Overvoltage category per IEC 60664-1 um V I Rated mains voltage ≤ 150 VRMS I-IV Rated mains voltage ≤ 300 VRMS I-IV Rated mains voltage ≤ 600 VRMS I-IV Rated mains voltage ≤ 1000 VRMS I-III DIN VDE V 0884-11:2017-01(2) VIORM VIOWM Maximum repetitive peak isolation voltage AC voltage (bipolar) 1500 VPK Maximum working isolation voltage AC voltage (sine wave) Time dependent dielectric breakdown (TDDB) test 1000 VRMS DC voltage 1500 VDC 7071 VPK VIOTM Maximum transient isolation voltage VTEST = VIOTM, t = 60 s (qualification); VTEST = 1.2 × VIOTM, t = 1 s (100% production) VIOSM Maximum surge isolation voltage ISOW14x2(3) Test method per IEC 62368-1, 1.2/50 µs waveform, VTEST = 1.6 × VIOSM = 10 kVPK (qualification) 6250 VPK VIOSM Maximum surge isolation voltage ISOW14x2B(3) Test method per IEC 62368-1, 1.2/50 µs waveform, VTEST = 1.3 × VIOSM = 7.8 kVPK (qualification) 6000 VPK Apparent charge(4) qpd Barrier capacitance, input to output(5) CIO Isolation resistance, input to output(5) RIO Method a: After I/O safety test subgroup 2/3, Vini = VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM , tm = 10 s ≤5 Method a: After environmental tests subgroup 1, Vini = VIOTM, tini = 60 s; ISOW14x2: Vpd(m) = 1.6 × VIORM , tm = 10 s. ISOW14x2B: Vpd(m) = 1.2 × VIORM , tm = 10 s ≤5 Method b1: At routine test (100% production) and preconditioning (type test) Vini = 1.2 × VIOTM, tini = 1 s; ISOW14x2: Vpd(m) = 1.875 × VIORM , tm = 1 s. ISOW14x2B: Vpd(m) = 1.5 × VIORM , tm = 1 s ≤5 VIO = 0.4 sin (2πft), f = 1 MHz pC ~3.5 pF VIO = 500 V, TA = 25°C > 1012 Ω VIO = 500 V, 100°C ≤ TA ≤ 125°C > 1011 Ω VIO = 500 V at TS = 150°C > 109 Ω Pollution degree 2 Climatic category 40/125/21 UL 1577 VISO (1) (2) (3) (4) (5) Withstand isolation voltage VTEST = VISO = 5000 VRMS, t = 60 s (qualification); VTEST = 1.2 × VISO = 6000 VRMS, t = 1 s (100% production) 5000 VRMS Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications. ISOW14x2 is suitable for safe electrical insulation and ISOW14x2B is suitable for basic electrical insulation only within the safety ratings.. Compliance with the safety ratings shall be ensured by means of suitable protective circuits. Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier. Apparent charge is electrical discharge caused by a partial discharge (pd). All pins on each side of the barrier tied together creating a two-terminal device Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ISOW1412 ISOW1432 9 ISOW1412, ISOW1432 www.ti.com SLLSF86C – MAY 2018 – REVISED MARCH 2022 8.6 Safety-Related Certifications VDE CSA UL Certified under UL 1577 Component Recognition Program TUV CQC Certified according to DIN VDE V 0884-11 :2017-01 Certified according to IEC 62368-1, IEC 61010-1 and IEC 60601-1 Maximum transient isolation voltage 7071 VPK; Maximum repetitive peak isolation voltage, 1500 VPK; Maximum surge isolation voltage, ISOW14x2: 6250 VPK (Reinforced), ISOW14x2B: 6000 VPK (Basic) Per CSA62368-1:19, IEC 62368-1:2018 Ed. 3, CSA 61010-1-12+A1 and IEC 61010-1 3rd Ed., ISOW14x2 (Reinforced): 600 VRMS, ISOW14x2B (Basic): 1000 VRMS maximum working voltage (pollution Single protection, 5000 VRMS degree 2, material group I, ambient temperature 90 ℃), 2 MOPP (Means of Patient Protection) per CSA 60601- 1:14 . IEC 60601-1 (ISOW14x2 only) Ed.3+A1, 250 VRMS maximum working voltage ISOW14x2 (Reinforced): 5000 VRMS reinforced insulation per EN 61010-1:2010/A1:2019 and EN 62368-1:2014 up to working voltage of 600 VRMS . ISOW14x2B (Basic): 1000 VRMS Reinforced insulation, Altitude ≤ 5000 m, Tropical Climate, 700 VRMS maximum working voltage. Certification number: 40040142. ISOW1432 planned Master Contract Number: 220991. ISOW1432 planned Client ID number: 77311. ISOW1432 planned Certificate number: CQC21001297517. ISOW1432 planned File number: E181974. ISOW1432 planned Certified ccording to EN 61010-1:2010/ A1:2019 and EN 62368-1:2014 Plan to certify according to GB4943.1-2011 8.7 Safety Limiting Values Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. PARAMETER IS Safety input, output, or supply current(1) PS Safety input, output, or total power(1) TS Safety temperature(1) (1) 10 TEST CONDITIONS MIN TYP MAX UNIT RθJA = 68.5°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C , See Figure 8-1 332 RθJA = 68.5°C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C , See Figure 8-1 507 RθJA = 68.5°C/W, TJ = 150°C, TA = 25°C , See Figure 8-2 1826 mW 150 °C mA The maximum safety temperature,TS, has the same value as the maximum junction temperature,TJ, specified for the device. The IS and PS parameters represent the safety current and safety power respectively.The maximum limits of IS and PS should not beexceeded. These limits vary with the ambient temperature, TA. The junction-to-air thermal resistance, RθJA, in the Thermal Information table is that of a device installed on a high-K test board forleaded surface-mount packages. Use these equations to calculate the value for each parameter: TJ = TA + RθJA × P, where P is the power dissipated in the device. TJ(max) = TS = TA +RθJA × PS, where TJ(max) is the maximum allowed junction temperature. PS = IS × VI, where VI is the maximum input voltage. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ISOW1412 ISOW1432 ISOW1412, ISOW1432 www.ti.com SLLSF86C – MAY 2018 – REVISED MARCH 2022 8.8 Electrical Characteristics Over recommended operating conditions, typical values are at VDD = VIO = 3.3 V and TA =25°C, GND1 = GNDIO, GND2 = GISOIN (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 3.135 3.3V 3.465 V 4.75 5 5.25 V Device Isolated output supply voltage MODE=GND2, DE=GND1, D, RE and IN floating Isolated output supply voltage MODE=VISOOUT, DE=GND1, D, RE and IN floating Output high voltage on OUT pin VIO = 5 V ± 10%, IOH = –4 mA, IN=VISOIN VIO – 0.4 V Output high voltage on OUT pin VIO = 3.3 V ± 10% , IOH = –2 mA, IN=VISOIN VIO – 0.3 V Output high voltage on OUT pin VIO = 2.5 V ± 10% , IOH = –1 mA, IN=VISOIN VIO – 0.2 V Output high voltage on OUT pin VIO = 1.8 V ± 5%, IOH = –1 mA, IN=VISOIN VIO – 0.2 V VISOOUT VOH VOL Output low voltage on OUT pin VIO = 5 V ± 10%, IOL = 4 mA, IN=GND2 0.4 V Output low voltage on OUT pin VIO = 3.3 V ± 10% , IOL = 2 mA, IN=GND2 0.3 V Output low voltage on OUT pin VIO = 2.5 V ± 10%, IOL = 1 mA, IN=GND2 0.2 V Output low voltage on OUT pin VIO = 1.8 V ± 5%, IOL = 1 mA, IN=GND2 0.2 V II Input current, IN IN at 0 V or VISOIN –25 25 µA II Input current, EN EN at 0 V or VIO –25 25 µA |CMH| High-level common-mode transient immunity Driver and receiver path, VCM = 1000 V, see Figure 9-4 100 kV/µs |CML| Low-level common-mode transient immunity Driver and receiver path, VCM = 1000 V, see Figure 9-4 100 kV/µs Driver |VOD| Differential output voltage magnitude Unloaded bus, VDD = 3 V to 3.6 V with MODE=GND2, or 4.5 V to 5.5 V with MODE= VISOOUT 1.5 VISOIN RL = 60 Ω, –7 V ≤ VTEST ≤ 12 V (see Figure 9-1), VDD = 3 V to 3.6 V, MODE = GND2 1.5 VISOIN RL = 100 Ω (see Figure 9-2) (RS-422 load), VDD = 3 V to 3.6 V, MODE = GND2 2 VISOIN RL = 54 Ω (see Figure 9-2) (RS-485 load), VDD = 3 V to 3.6 V, MODE = GND2 1.5 VISOIN V |VOD| Differential output voltage magnitude RL = 54 Ω, VDD = 4.5 V to 5.5 V, MODE = VISOOUT , see Figure 9-2 2.1 VISOIN V |VOD| Differential output voltage magnitude RL = 100 Ω (see Figure 9-2) (RS-422 load), VDD = 4.5 V to 5.5 V, MODE = VISOOUT 2.1 VISOIN V |VOD| Differential output voltage magnitude RL = 60 Ω, –7 V ≤ VTEST ≤ 12 V (see Figure 9-1), VDD = 4.5 V to 5.5V, MODE = VISOOUT 2.1 VISOIN V Δ|VOD| Change in differential output R = 54 Ω or 100 Ω (see Figure 9-2) voltage between the two states L –200 200 VOC Common-mode output voltage RL = 54 Ω or 100 Ω (see Figure 9-2) ΔVOC(SS) Change in steady-state common-mode output voltage between the two states RL = 54 Ω or 100 Ω (see Figure 9-2) VOC(PP) Peak-to-peak common mode output voltage RL = 54 Ω or 100 Ω, VISOIN=VISOOUT=3.3V, see Figure 9-2 400 mV IOS Short-circuit output current VDE = VIO, VD=VIO or GND1, –7 V ≤ Y or Z ≤ 12 V, or Y shorted to Z, see Figure 9-10 180 mA 1 0.5 × VISOIN –200 3 200 mV V mV Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ISOW1412 ISOW1432 11 ISOW1412, ISOW1432 www.ti.com SLLSF86C – MAY 2018 – REVISED MARCH 2022 Over recommended operating conditions, typical values are at VDD = VIO = 3.3 V and TA =25°C, GND1 = GNDIO, GND2 = GISOIN (unless otherwise noted) PARAMETER II TEST CONDITIONS MIN Input current , D, DE VD, VDE at 0 V or VIO II1 Bus input current VDE = 0 V, VISOIN = 0 V or 3.3 V or 5V, ISOW1412 or ISOW1432, VA or VB = –7 V to 12 V, other input at 0 V VTH+ Positive-going input-threshold voltage –7 V ≤ VCM ≤ 12 V See(1) VTH– Negative-going input-threshold –7 V ≤ VCM ≤ 12 V voltage Vhys Input hysteresis (VTH+ – VTH–) TYP MAX UNIT –25 25 µA –100 125 µA –78 –20 mV –200 –141 See(1) mV 40 63 Receiver VOH VOL Output high voltage on R pin Output low voltage on R pin –7 V ≤ VCM ≤ 12 V VIO = 5 V ± 10%, IOH = –4 mA, VID ≥ 200 mV VIO – 0.4 VIO = 3.3 V ± 10%, IOH = –2 mA, VID ≥ 200 mV VIO – 0.3 VIO = 2.5 V ± 10% , IOH = –1 mA, VID ≥ 200 mV VIO – 0.2 VIO = 1.8 V ± 5%, IOH = –1 mA, VID ≥ 200 mV VIO – 0.2 0.4 VIO = 3.3 V ± 10%, IOL = 2 mA, VID ≤ –200 mV 0.3 VIO = 2.5 V ± 10% , IOL = 1 mA, VID ≤ –200 mV 0.2 VIO = 1.8 V ± 5%, IOL = 1 mA, VID ≤ –200 mV 0.2 Output high-impedance current VR = 0 V or VIO, VRE = VIO on R pin II(RE) Input current on RE pin 12 V VIO = 5 V ± 10%, IOL = 4 mA, VID ≤ –200 mV IOZ (1) mV VRE at 0 V or VIO V –1 1 µA –25 25 µA The VTH+ voltage is specified to be greater than the VTH– voltage by at least the Vhys voltage under any specific conditions. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ISOW1412 ISOW1432 ISOW1412, ISOW1432 www.ti.com SLLSF86C – MAY 2018 – REVISED MARCH 2022 8.9 Supply Current Characteristics at VISOOUT = 3.3 V over recommended operating conditions, VDD = VIO = 3 to 5.5 V, MODE=GND2, GND1 = GNDIO, GND2 = GISOIN (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Power converter disabled IDD Power converter supply current EN=GND1, D, DE, RE floating 0.23 0.45 mA IIO Logic supply current EN=GND1, D, DE, RE floating 0.24 0.55 mA VDE = VIO, VRE = VIO, bus load = 120 Ω, VD= VIO, VDD = 5 V ± 10%, A and B floating 56 77 mA VDE = VIO, VRE = VIO, bus load = 120 Ω, VD= VIO, VDD = 3.3 V ± 10%, A and B floating 69 125 mA VDE = VIO, VRE = VIO, bus load = 120 Ω || 50 pF, D = 500-kbps square wave 50% duty, VDD = 5 V ± 10% 62 86 mA VDE = VIO, VRE = VIO, bus load = 100 Ω || 50 pF, D = 500-kbps square wave 50% duty, VDD = 5 V ± 10% 69 88 mA VDE = VIO, VRE = VIO, bus load = 54 Ω || 50 pF, D = 500-kbps square wave 50% duty, VDD = 5 V ± 10% 90 122 mA VDE = VIO, VRE = VIO, bus load = 120 Ω || 50 pF, D = 500-kbps square wave 50% duty, VDD = 3.3 V ± 10% 76 131 mA VDE = VIO, VRE = VIO, bus load = 100 Ω || 50 pF, D = 500-kbps square wave 50% duty, VDD = 3.3 V ± 10% 84 131 mA VDE = VIO, VRE = VIO, bus load = 54 Ω || 50 pF, D = 500-kbps square wave 50% duty, VDD = 3.3 V ± 10% 111 158 mA VDE = VIO, VRE = VIO, bus load = 120 Ω || 50 pF, D = 12-Mbps square wave 50% duty, VDD = 5 V ± 10% 87 99 mA VDE = VIO, VRE = VIO, bus load = 100 Ω || 50 pF, D = 12-Mbps square wave 50% duty, VDD = 5 V ± 10% 69 96 mA VDE = VIO, VRE = VIO, bus load = 54 Ω || 50 pF, D = 12-Mbps square wave 50% duty, VDD = 5 V ± 10% 114 130 mA VDE= VIO, VRE = VIO, bus load = 120 Ω || 50 pF, D = 12-Mbps square wave 50% duty, VDD = 3.3 V ± 10% 105 135 mA VDE= VIO, VRE = VIO, bus load = 100 Ω || 50 pF, D = 12-Mbps square wave 50% duty, VDD = 3.3 V ± 10% 84 140 mA VDE = VIO, VRE = VIO, bus load = 54 Ω || 50 pF, D = 12-Mbps square wave 50% duty, VDD = 3.3 V ± 10% 137 163 mA VDE = VGND1, VRE= VGND1, Y and Z bus loaded and unloaded, A-B = square wave 500-kbps 50% duty VD= VGND1, VDD = 5 V ± 10%, CL on R = 15 pF 16 28 VDE = VGND1, VRE= VGND1, Y and Z bus loaded and unloaded, A-B = square wave 500-kbps 50% duty VD= VGND1, VDD = 3.3 V ± 10%, CL on R = 15 pF 18 30 VDE = VGND1, VRE= VGND1, Y and Z bus loaded and unloaded, A-B = square wave 12-Mbps 50% duty VD= VGND1, VDD = 5 V ± 10%, CL on R = 15 pF 15 22 VDE = VGND1, VRE= VGND1, Y and Z bus loaded and unloaded, A-B = square wave 12-Mbps 50% duty VD= VGND1, VDD = 3.3 V ± 10%, CL on R = 15 pF 17 Power converter supply current: Driver enabled, receiver disabled IDD IDD IDD Power converter supply current Power converter supply current, ISOW1412 Power converter supply current, ISOW1432 Power converter supply current: Driver disabled, receiver enabled IDD IDD Power converter supply current, ISOW1412 Power converter supply current, ISOW1432 mA mA 27 Power converter supply current: Driver enabled, receiver enabled Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ISOW1412 ISOW1432 13 ISOW1412, ISOW1432 www.ti.com SLLSF86C – MAY 2018 – REVISED MARCH 2022 over recommended operating conditions, VDD = VIO = 3 to 5.5 V, MODE=GND2, GND1 = GNDIO, GND2 = GISOIN (unless otherwise noted) PARAMETER IDD IDD Power converter supply current, ISOW1412 Power converter supply current, ISOW1432 TEST CONDITIONS MIN TYP MAX UNIT VDE = VIO, VRE= VGND1, Y and Z bus load = 120 Ω || 50 pF, loopback(1), D = 500-kbps 50% duty, VDD = 5 V ± 10%, CL on R = 15 pF 63 102 VDE = VIO, VRE= VGND1, Y and Z bus load = 120 Ω || 50 pF, loopback(1), D = 500-kbps 50% duty, VDD = 3.3 V ± 10%, CL on R = 15 pF 77 129 VDE = VIO, VRE= VGND1, Y and Z bus load = 120 Ω || 50 pF, loopback(1), D = 12-Mbps 50% duty, VDD = 5 V ± 10%, CL on R = 15 pF 90 105 VDE = VIO, VRE= VGND1, Y and Z bus load = 120 Ω || 50 pF, loopback(1), D = 12-Mbps 50% duty, VDD = 3.3 V ± 10%, CL on R = 15 pF 109 138 3.2 6.0 mA 4 6.8 mA mA mA Logic supply current: Driver disabled, receiver disabled IIO Logic supply current VDE = VGND1, VRE = VIO , VD = VIO, VIO= 3.3 V ± 10% Logic supply current: Driver enabled, Receiver enabled, static IIO Logic supply current VDE = VIO, VRE= VGND1, VD = VIO, loopback(1), VIO= 3.3 V ± 10% Logic supply current: Driver enabled, receiver enabled, dynamic IIO Logic supply current, ISOW1412 VDE = VIO, VRE= VGND1, D = 500-kbps 50% duty square wave, loopback(1), VIO = 3.3 V ± 10% 4.6 7.2 mA IIO Logic supply current, ISOW1432 VDE = VIO, VRE = VGND1 , D = 12-Mbps 50% duty square wave, loopback(1), VIO = 3.3 V ± 10% 4.6 7.2 mA (1) 14 The output of the driver is connected to the input of a receiverin a loopback mode. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ISOW1412 ISOW1432 ISOW1412, ISOW1432 www.ti.com SLLSF86C – MAY 2018 – REVISED MARCH 2022 8.10 Supply Current Characteristics at VISOOUT = 5 V over recommended operating conditions, VDD = VIO = 4.5 V to 5.5 V, MODE=VISOOUT , GND1 = GNDIO, GND2 = GISOIN (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Power converter disabled IDD Power converter supply current EN=GND1, D, DE, RE floating 0.23 0.45 mA IIO Logic supply current EN=GND1, D, DE, RE floating 0.24 0.55 mA 97 160 mA VDE = VIO, VRE = VIO, bus load = 120 Ω || 50 pF, D = 500-kbps square wave 50% duty, VDD = 5 V ± 10% 123 161 mA VDE = VIO, VRE = VIO, bus load = 54 Ω || 50 pF, D = 500-kbps square wave 50% duty, VDD = 5 V ± 10% 175 227 mA VDE = VIO, VRE = VIO, bus load = 120 Ω || 50 pF, D = 12-Mbps square wave 50% duty, VDD = 5 V ± 10% 146 185 mA VDE = VIO, VRE = VIO, bus load = 54 Ω || 50 pF, D = 12-Mbps square wave 50% duty, VDD = 5 V ± 10% 202 240 mA Power converter supply current: Driver enabled, receiver disabled IDD Power converter supply current IDD Power converter supply current, ISOW1412 IDD Power converter supply current, ISOW1432 VDE = VIO, VRE = VIO, bus load = 120 Ω, VD= VIO, VDD = 5 V ± 10%, A and B floating Power converter supply current: Driver disabled, receiver enabled IDD Power converter supply current VDE= VGND1, VRE= VGND1, Y and Z bus loaded and unloaded, A-B = square wave 500-kbps 50% duty VD= VIO, VDD= 5 V ± 10%, CL on R = 15 pF 17 31 mA IDD Power converter supply current VDE= VGND1, VRE= VGND1, Y and Z bus loaded and unloaded, A-B = square wave 12-Mbps 50% duty (ISOW1432) VD= VIO, VDD= 5 V ± 10%, CL on R = 15 pF 24 36 mA Power converter supply current: Driver enabled, receiver enabled IDD Power converter supply current, ISOW1412 VDE = VIO, VRE= VGND1, Y and Z bus load = 120 Ω || 50 pF, loopback(1), D = 500-kbps 50% duty, VDD = 5 V ± 10%, CL on R = 15 pF 123 207 mA IDD Power converter supply current, ISOW1432 VDE = VIO, VRE= VGND1, Y and Z bus load = 120 Ω || 50 pF, loopback(1), D = 12-Mbps 50% duty, VDD = 5 V ± 10%, CL on R = 15 pF 145 210 mA (1) The output of the driver is connected to the input of a receiverin a loopback mode. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ISOW1412 ISOW1432 15 ISOW1412, ISOW1432 www.ti.com SLLSF86C – MAY 2018 – REVISED MARCH 2022 8.11 Switching Characteristics at VISOOUT = 3.3 V Min / Max specifications are over recommended operating conditions, typical values are at VDD = VIO = 3.3 V, MODE=GND2 ( VISOOUT= 3.3V), GND1 = GNDIO, GND2 = GISOIN, TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 190 300 600 ns 450 610 ns Driver: 500-kbps device (ISOW1412) tr, tf Differential output rise time and fall time tPHL, tPLH Propagation delay PWD Pulse width distortion(1), RL = 54 Ω, CL = 50 pF, see Figure 9-3 RL = 54 Ω, CL = 50 pF, see Figure 9-3 3 40 ns tPHZ, tPLZ Disable time |tPHL - tPLH| RL = 54 Ω, CL = 50 pF, see Figure 9-3 See Figure 9-5 and Figure 9-6 56 200 ns tPZH, tPZL Enable time See Figure 9-5 and Figure 9-6 280 600 ns 4 ns Receiver: 500-kbps device (ISOW1412) tr, tf Output rise time and fall time CL = 15 pF, see Figure 9-7 tPHL, tPLH Propagation delay CL = 15 pF, see Figure 9-7 60 135 ns CL = 15 pF, see Figure 9-7 2 15 ns tPHZ, tPLZ Disable time See Figure 9-8 and Figure 9-9 9 30 ns tPZH, tPZL Enable time See Figure 9-8 and Figure 9-9 8 30 ns 15 25 ns PWD Pulse width distortion(1), |tPHL - tPLH| Driver: 12-Mbps device (ISOW1432) tr, tf Differential output rise time and fall time RL = 54 Ω, CL = 50 pF, see Figure 9-3 6 tPHL Propagation delay RL = 54 Ω, CL = 50 pF, see Figure 9-3 49 125 ns tPLH Propagation delay RL = 54 Ω, CL = 50 pF, see Figure 9-3 49 125 ns tPHL, tPLH Propagation delay RL = 54 Ω, CL = 50 pF, see Figure 9-3 52 125 ns PWD Pulse width distortion(1), |tPHL - tPLH| RL = 54 Ω, CL = 50 pF, see Figure 9-3 1 10 ns tPHZ Disable time See Figure 9-5 and Figure 9-6 35 125 ns tPLZ Disable time See Figure 9-5 and Figure 9-6 35 125 ns tPHZ, tPLZ Disable time See Figure 9-5 and Figure 9-6 36 125 ns tPZH Enable time See Figure 9-5 and Figure 9-6 46 150 ns tPZL Enable time See Figure 9-5 and Figure 9-6 36 150 ns tPZH, tPZL Enable time See Figure 9-5 and Figure 9-6 48 110 ns 16 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ISOW1412 ISOW1432 ISOW1412, ISOW1432 www.ti.com SLLSF86C – MAY 2018 – REVISED MARCH 2022 Min / Max specifications are over recommended operating conditions, typical values are at VDD = VIO = 3.3 V, MODE=GND2 ( VISOOUT= 3.3V), GND1 = GNDIO, GND2 = GISOIN, TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Receiver: 12-Mbps device (ISOW1432) tr, tf Output rise time and fall time CL = 15 pF, see Figure 9-7 tPHL Propagation delay CL = 15 pF, see Figure 9-7 tPLH Propagation delay CL = 15 pF, see Figure 9-7 tPHL, tPLH Propagation delay 4 ns 59 120 ns 59 120 ns CL = 15 pF, see Figure 9-7 42 120 ns PWD Pulse width distortion(1), |tPHL - tPLH| CL = 15 pF, see Figure 9-7 1.7 10 ns tPHZ Disable time See Figure 9-8 and Figure 9-9 7 30 ns tPLZ Disable time See Figure 9-8 and Figure 9-9 6 30 ns tPHZ, tPLZ Disable time See Figure 9-8 and Figure 9-9 9 30 ns tPZH Enable time See Figure 9-8 and Figure 9-9 6 30 ns tPZL Enable time See Figure 9-8 and Figure 9-9 5 30 ns tPZH, tPZL Enable time See Figure 9-8 and Figure 9-9 8 30 ns 227 347 ns 20 110 ns 1 4 ns 1 4 ns GPIO channel tPHL, tPLH Propagation delay time PWD Pulse width distortion, |tPHL - tPLH| tr Output signal rise time tf Output signal fall time (1) See Figure 9-11 Also known as pulse skew. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ISOW1412 ISOW1432 17 ISOW1412, ISOW1432 www.ti.com SLLSF86C – MAY 2018 – REVISED MARCH 2022 8.12 Switching Characteristics at VISOOUT = 5 V Min / Max specifications are over recommended operating conditions, typical values are at VDD = VIO = 5 V, MODE=VISOOUT ( VISOOUT= 5 V), GND1 = GNDIO, GND2 = GISOIN, TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 200 300 600 ns 400 610 ns Driver: 500-kbps device (ISOW1412) tr, tf Differential output rise time and fall time tPHL, tPLH Propagation delay PWD Pulse width distortion(1), RL = 54 Ω, CL = 50 pF, see Figure 9-3 RL = 54 Ω, CL = 50 pF, see Figure 9-3 2 40 ns tPHZ, tPLZ Disable time |tPHL – tPLH| RL = 54 Ω, CL = 50 pF, see Figure 9-3 See Figure 9-5 and Figure 9-6 30 200 ns tPZH, tPZL Enable time See Figure 9-5 and Figure 9-6 115 600 ns 4 ns Receiver: 500-kbps device (ISOW1412) tr, tf Output rise time and fall time CL = 15 pF, see Figure 9-7 tPHL, tPLH Propagation delay CL = 15 pF, see Figure 9-7 49 135 ns CL = 15 pF, see Figure 9-7 2 20 ns tPHZ, tPLZ Disable time See Figure 9-8 and Figure 9-9 8 30 ns tPZH, tPZL Enable time See Figure 9-8 and Figure 9-9 7 30 ns 10 18 ns PWD Pulse width distortion(1), |tPHL – tPLH| Driver: 12-Mbps device (ISOW1432) tr, tf Differential output rise time and fall time RL = 54 Ω, CL = 50 pF, see Figure 9-3 4 tPHL Propagation delay RL = 54 Ω, CL = 50 pF, see Figure 9-3 40 125 ns tPLH Propagation delay RL = 54 Ω, CL = 50 pF, see Figure 9-3 40 125 ns tPHL, tPLH Propagation delay RL = 54 Ω, CL = 50 pF, see Figure 9-3 40 125 ns PWD Pulse width distortion(1), |tPHL – tPLH| RL = 54 Ω, CL = 50 pF, see Figure 9-3 2 10 ns tPHZ Disable time See Figure 9-5 and Figure 9-6 30 125 ns tPLZ Disable time See Figure 9-5 and Figure 9-6 30 125 ns tPHZ, tPLZ Disable time See Figure 9-5 and Figure 9-6 28 40 ns tPZH Enable time See Figure 9-5 and Figure 9-6 34 150 ns tPZL Enable time See Figure 9-5 and Figure 9-6 25 150 ns tPZH, tPZL Enable time See Figure 9-5 and Figure 9-6 33 150 ns 6 ns Receiver: 12-Mbps device (ISOW1432) tr, tf Output rise time and fall time CL = 15 pF, see Figure 9-7 tPHL Propagation delay CL = 15 pF, see Figure 9-7 55 120 ns tPLH Propagation delay CL = 15 pF, see Figure 9-7 55 120 ns tPHL, tPLH Propagation delay CL = 15 pF, see Figure 9-7 52 120 ns PWD Pulse width distortion(1), |tPHL – tPLH| CL = 15 pF, see Figure 9-7 2.5 10 ns tPHZ Disable time See Figure 9-8 and Figure 9-9 5 30 ns tPLZ Disable time See Figure 9-8 and Figure 9-9 5 30 ns tPHZ, tPLZ Disable time See Figure 9-8 and Figure 9-9 8 30 ns tPZH Enable time See Figure 9-8 and Figure 9-9 4 30 ns tPZL Enable time See Figure 9-8 and Figure 9-9 4 30 ns tPZH, tPZL Enable time See Figure 9-8 and Figure 9-9 7 30 ns 227 347 ns GPIO channel tPHL, tPLH Propagation delay time PWD Pulse width distortion, |tPHL - tPLH| tr Output signal rise time tf Output signal fall time (1) 18 See Figure 9-11 20 110 ns 2.2 4 ns 2.2 4 ns Also known as pulse skew. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ISOW1412 ISOW1432 ISOW1412, ISOW1432 www.ti.com SLLSF86C – MAY 2018 – REVISED MARCH 2022 8.13 Insulation Characteristics Curves 2000 VI = 5.5 V VI = 3.6 V 500 1800 Safety Limiting Power (mW) Safety Limiting Current (mA) 600 400 300 200 100 1600 1400 1200 1000 800 600 400 200 0 0 0 50 100 150 Ambient Temperature (qC) 200 0 D001 Figure 8-1. Thermal Derating Curve for Limiting Current per VDE 50 100 150 Ambient Temperature (qC) 200 D002 Figure 8-2. Thermal Derating Curve for Limiting Power per VDE Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ISOW1412 ISOW1432 19 ISOW1412, ISOW1432 www.ti.com SLLSF86C – MAY 2018 – REVISED MARCH 2022 8.14 Typical Characteristics 120 100 IDD (mA) 80 Open Load 54 Load 120 Load 60 40 20 0 100 150 200 250 300 350 Data Rate (kbps) MODE = GND2 TA = 25°C 400 450 VDD = 3.3 V DE = VIO 500 MODE = GND2 TA = 25°C RE = GND1 Figure 8-3. ISOW1412 VDD Supply Current vs. Data Rate - RS485 Mode RE = GND1 Figure 8-4. ISOW1432 VDD Supply Current vs. Data Rate - RS485 Mode 5.1 5.2 Open Load 54  Load 120  Load 5.1 5 5 4.9 4.9 4.8 IIO (mA) IIO (mA) VDD = 3.3 V DE = VIO 4.7 4.6 4.5 4.8 Open Load 54 Load 120 Load 4.7 4.6 4.4 4.5 4.3 4.2 100 150 200 250 300 350 Data Rate (kbps) MODE = GND2 TA = 25°C 400 450 VDD = 3.3 V DE = VIO 500 RE = GND1 Figure 8-5. ISOW1412 VIO Supply Current vs. Data Rate - RS485 Mode 4.4 0 2 MODE = GND2 TA = 25°C 4 6 8 Data Rate (Mbps) VDD = 3.3 V DE = VIO 10 12 RE = GND1 Figure 8-6. ISOW1432 VIO Supply Current vs. Data Rate - RS485 Mode 120 Open Load 54  Load 120  Load 110 100 IDD (mA) 90 80 70 60 50 40 30 20 -40 -25 -10 5 20 35 50 65 Tempearture (C) MODE = GND2 DE = VIO VDD = 3.3 V 80 95 110 125 RE = GND1 Figure 8-7. ISOW1412 VDD Current vs. Temperature - RS485 Mode 20 MODE = GND2 DE = VIO VDD = 3.3 V RE = GND1 Figure 8-8. ISOW1432 VDD Current vs. Temperature - RS485 Mode Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ISOW1412 ISOW1432 ISOW1412, ISOW1432 www.ti.com SLLSF86C – MAY 2018 – REVISED MARCH 2022 6 6 Open Load 54  Load 120  Load 5.5 IIO (mA) IIO (mA) 5.5 5 5 4.5 4.5 4 -40 -25 -10 5 MODE = GND2 DE = VIO 20 35 50 65 Tempearture (C) 80 95 VDD = 3.3 V 4 -40 110 125 -25 -10 5 MODE = GND2 DE = VIO RE = GND1 20 35 50 65 Temperature (C) 80 95 VDD = 3.3 V 110 125 RE = GND1 Figure 8-10. ISOW1432 VIO Current vs. Temperature - RS485 Mode Figure 8-9. ISOW1412 VIO Current vs. Temperature - RS485 Mode 60 440 tPLH tPHL 435 tPLH tPHL 58 430 56 Delay Time (ns) Delay Time(ms) Open Load 54 Load 120 Load 425 420 415 54 52 50 410 48 405 46 400 -40 -25 -10 5 MODE = GND2 LOAD = 54 Ω || 50pF 20 35 50 65 Temperature (C) 80 95 VDD = 3.3 V 44 -40 110 125 DE = VIO Figure 8-11. ISOW1412 Driver Propagation Delay vs. Temperature - RS485 Mode -25 -10 5 MODE = GND2 LOAD = 54 Ω || 50pF 20 35 50 65 Temperature (C) 80 95 VDD = 3.3 V 110 125 DE = VIO Figure 8-12. ISOW1432 Driver Propagation Delay vs. Temperature - RS485 Mode 46 390 tPLH tPHL tPLH tPHL 44 Delay Time (ns) Delay Time (ns) 380 370 360 42 40 38 36 350 -45 -30 -15 0 MODE = VISOOUT LOAD = 54 Ω || 50pF 15 30 45 60 Temperature (C) VDD = 5 V 75 90 105 120 34 -40 -25 -10 5 DE = VIO MODE = VISOOUT DE = VIO Figure 8-13. ISOW1412 Driver Propagation Delay vs. Temperature - Profibus Mode 20 35 50 65 Temperature (C) VDD = 5 V 80 95 110 125 DE = VIO Figure 8-14. ISOW1432 Driver Propagation Delay vs. Temperature - Profibus Mode Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ISOW1412 ISOW1432 21 ISOW1412, ISOW1432 www.ti.com SLLSF86C – MAY 2018 – REVISED MARCH 2022 66 80 tPLH tPHL 70 65 60 tPLH tPHL 64 Delay Time (ns) Delay Time (ns) 75 55 62 60 58 56 50 -40 -25 -10 5 20 35 50 65 Temperature (C) MODE = GND2 LOAD = 54 Ω || 50pF 80 95 VDD = 3.3 V 54 -40 110 125 RE = GND1 -25 -10 5 MODE = GND2 LOAD = 54 Ω || 50pF 20 35 50 65 Temperature (C) 80 95 VDD = 3.3 V 110 125 RE = GND1 Figure 8-15. ISOW1412 Receiver Propagation Delay Figure 8-16. ISOW1432 Receiver Propagation Delay vs. Temperature - RS485 Mode vs. Temperature - RS485 Mode 62 70 tPLH tPHL tPLH tPHL 60 Delay Time (ns) Delay Time (ns) 65 60 58 56 54 55 52 50 -40 -25 -10 5 20 35 50 65 Temperature (C) MODE = VISOOUT LOAD = 54 Ω || 50pF VDD = 5 V 80 95 110 125 RE = GND1 50 -40 -25 -10 5 MODE = VISOOUT LOAD = 54 Ω || 50pF 20 35 50 65 Temperature (C) VDD = 5 V 80 95 110 125 RE = GND1 Figure 8-17. ISOW1412 Receiver Propagation Delay Figure 8-18. ISOW1432 Receiver Propagation Delay vs. Temperature - Profibus Mode vs. Temperature - Profibus Mode 22 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ISOW1412 ISOW1432 ISOW1412, ISOW1432 www.ti.com MODE = VISOOUT LOAD = 54 Ω || 50pF SLLSF86C – MAY 2018 – REVISED MARCH 2022 VDD = 5 V TA = 25°C DE = VIO Figure 8-19. ISOW1412 Driver Propagation Delay Profibus Mode MODE = VISOOUT LOAD = 54 Ω || 50pF VDD = 5 V TA = 25°C RE = GND1 MODE = GND2 LOAD = 54 Ω || 50pF VDD = 3.3 V TA = 25°C DE = VIO Figure 8-20. ISOW1412 Driver Propagation Delay RS485 Mode MODE = GND2 LOAD = 54 Ω || 50pF VDD = 3.3 V TA = 25°C RE = GND1 Figure 8-21. ISOW1412 Receiver Propagation Delay Figure 8-22. ISOW1412 Receiver Propagation Delay - RS485 Mode - Profibus Mode Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ISOW1412 ISOW1432 23 ISOW1412, ISOW1432 www.ti.com SLLSF86C – MAY 2018 – REVISED MARCH 2022 5 3.5 VOH VOL 3 4.5 4 3.5 Voltage (V) Voltage (V) 2.5 2 1.5 VOH VOL 2 1.5 1 1 0.5 0.5 0 0 0 10 20 30 40 Driver Output Current (mA) MODE = GND2 LOAD = 54 Ω 50 VDD = 3.3 V TA = 25°C 0 60 10 20 30 40 Driver Output Current (mA) MODE = VISOOUT LOAD = 54 Ω DE = VIO Figure 8-23. ISOW1412 Driver output voltage vs. Driver output current - RS485 Mode 50 VDD = 5 V TA = 25°C 60 DE = VIO Figure 8-24. ISOW1412 Driver output voltage vs. Driver output current - Profibus Mode 5 5 High Level Output Voltage (VOH) (V) High Level Output Voltage (VOH) (V) 3 2.5 4.5 4 MODE = GND MODE = VISOOUT 3.5 3 2.5 -15 -12 -9 -6 -3 High Level Output Current (IOH) (mA) RE = GND1 Load = 54 Ω 4.75 4.5 4.25 3.75 3.5 3.25 3 -40 0 MODE = GND MODE = VISOOUT 4 -25 -10 5 20 35 50 65 Temperature (C) RE = GND1 TA = 25°C 80 95 110 125 LOAD = -2 mA (RS485 Mode), -4mA (Profibus Mode) Figure 8-25. ISOW1412 Receiver Buffer High Level Figure 8-26. ISOW1412 Receiver Buffer High Level output voltage vs. High Level output current output voltage vs. Temperature - RS485 & Profibus RS485 & Profibus Mode Mode 0.3 0.8 0.6 0.4 0.2 MODE = GND MODE = VISOOUT 0 -0.2 0 2 RE = GND1 4 6 8 10 12 Low Level Output Current (IOL) (mA) LOAD = 54 Ω 14 16 0.25 0.2 MODE = GND MODE = VISOOUT 0.15 0.1 0.05 -40 -25 -10 5 20 35 50 65 Temperature (C) 80 95 110 125 RE = GND1 LOAD = 2 mA (RS485 Mode), 4mA (Profibus Mode) TA = 25°C Figure 8-27. ISOW1412 Receiver Buffer Low Level output voltage vs. Low Level output current RS485 & Profibus Mode 24 Low Level Output Voltage (VOL) (V) Low Level Output Voltage (VOL) (V) 1 Figure 8-28. ISOW1412 Receiver Buffer Low Level output voltage vs. Temperature - RS485 & Profibus Mode Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ISOW1412 ISOW1432 ISOW1412, ISOW1432 400 380 360 340 320 300 280 260 240 220 200 180 160 140 120 100 100 SLLSF86C – MAY 2018 – REVISED MARCH 2022 1000 VDD = 5 V, VISOOUT = 5 V VDD = 3.3 V, VISOOUT = 3.3 V VDD = 5 V, VISOOUT = 5 V VDD = 3.3 V, VISOOUT = 3.3 V 800 Voltage (mV) Voltage (mV) www.ti.com 600 400 140 180 220 For PWD ≤±5% 260 300 340 380 Data Rate (kbps) 420 460 500 1 2 3 4 TA = 25°C Figure 8-29. ISOW1412 Receiver VID vs. Data Rate - RS485 & Profibus Mode MODE = GND2 RE = GND1 200 D = VIO TA = 25°C DE = VIO LOAD = 54 Ω || 50pF Figure 8-31. Glitch-free Power up/down- RS485 Mode For PWD ≤±5% 5 6 7 8 Data Rate (Mbps) 9 10 11 12 TA = 25°C Figure 8-30. ISOW1432 Receiver VID vs. Data Rate - RS485 & Profibus Mode MODE = VISOOUT TA = 25°C D = VIO LOAD = 54 Ω || 50pF DE = VIO Figure 8-32. Glitch-free Power up/down- Profibus Mode Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ISOW1412 ISOW1432 25 ISOW1412, ISOW1432 www.ti.com SLLSF86C – MAY 2018 – REVISED MARCH 2022 9 Parameter Measurement Information In this section, GND1 = GNDIO, GND2 = GISOIN unless otherwise noted. DE = VIO VISOIN Y RL VOD D = 0 or VIO VTEST Z + ± GND2 Figure 9-1. Driver Voltages RL(1) / 2 Y Y VY Z VZ 0 V or D VIO RL(1) / 2 Z VOC VOC GND2 ûVOC(SS) VOC(PP) A. VOD RL = 100 Ω for RS-422, RL = 54 Ω for RS-485 Figure 9-2. Driver Voltages VIO DE = VIO Input Generator VI VI VOD Y RL 54 D CL 50 pF ± 20% ± 1% tPHL tPLH 90% Z 50 50% (1) VOD GND1 A. 90% 0V 10% tr tf VOD (H) 0V 10% VOD (L) CL includes fixture and instrumentation capacitance Figure 9-3. Driver Switching Specifications VIO VISOIN (Connected to VISOOUT on PCB) 10 µF VIO 0.1 µF GND1 Y D Z GND1 54 A R + VOH or VOL ± 10 µF 0.1 µF DE 1k CL 15 pF(1) B 1.5 V or 0 V 54 RE GND1 + VOH or VOL ± 0 V or 1.5 V GND2 + VCM ± A. 26 Includes probe and fixture capacitance Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ISOW1412 ISOW1432 ISOW1412, ISOW1432 www.ti.com B. SLLSF86C – MAY 2018 – REVISED MARCH 2022 Pass-fail criteria: Device is tested in both half-duplex and full-duplex conditions. Both the signal path and power path should be in specification compliant region during the application of CMTI pulse. This means no bit flips on R, and both VISOOUT and Driver VOD should be within specifications mentioned in electrical characterisitcs table. Figure 9-4. Common Mode Transient Immunity (CMTI)—Full Duplex Y S1 D Input Generator VI 50 % VI Z DE VIO VO CL(1) 50 pF 50 % 0V RL 110 tPZH 90% 50 VOH 50% VO §0V tPHZ GND2 GND1 A. CL includes fixture and instrumentation capacitance Figure 9-5. Driver Enable and Disable Times VISOIN RL 110 Y VIO VI D VI tPLZ tPZL CL(1) 50 pF Z DE 50 % 0V S1 Input Generator 50 % VO VISOIN 50% 10% 50 VOL GND2 GND1 Figure 9-6. Driver Enable and Disable Times 3V 50 % A R Input Generator VI 50 1.5 V B RE CL(1) 15 pF 0V tPHL tPLH 90% 50% 10% 50% VO tr A. 50 % VI VO tf VOH VOL CL includes fixture and instrumentation capacitance Figure 9-7. Receiver Switching Specifications VISOIN 50% VI 0V tPHZ tPZH VO 90% 50% VOH §0V tPZL tPLZ VO 50% VIO 10% VOL Figure 9-8. Receiver Enable and Disable Times Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ISOW1412 ISOW1432 27 ISOW1412, ISOW1432 www.ti.com SLLSF86C – MAY 2018 – REVISED MARCH 2022 VIO VIO VI A 0 V or 1.5 V R VO B 1.5 V or 0 V Input Generator VI 1k 0V S1 CL 15 pF RE 50% tPZH VOH VO A at 1.5 V B at 0 V § 0 V S1 to GND 50% tPZL 50 VIO VO 50% VOL A at 0 V B at 1.5 V S1 to VIO Figure 9-9. Receiver Enable and Disable Times Steady-State Logic Input (1 or 0) Y G Z Y Steady State Logic Input (1 or 0) ±7 V ” V ” 12 V I(1) V Z C C GND A. G GND The driver should not sustain any damage with this configuration Isolation Barrier Figure 9-10. Short-Circuit Current Limiting IN Input Generator (See Note A) VI 50 VISOIN VI OUT 50% 50% 0V tPLH VO tPHL CL See Note B VO 50% 90% VOH 50% 10% tr VOL tf The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω. At the input, 50-Ω resistor is required to terminate the input generator signal. The resistor is not required in the actual application. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 9-11. GPIO Channel: Switching Characteristics Test Circuit and Voltage Waveforms 28 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ISOW1412 ISOW1432 ISOW1412, ISOW1432 www.ti.com SLLSF86C – MAY 2018 – REVISED MARCH 2022 10 Detailed Description 10.1 Overview The ISOW14x2 family of devices has signal isolation channels, power isolation with integrated transformer and RS-485 transceiver all integrated in one package. ISOW1412 supports maximum signaling rate up to 500 kbps, while ISOW1432 is designed for 12 Mbps maximum data rate. Figure 10-1 shows functional block diagram of ISOW14x2 family of devices. 10.2 Power Isolation The integrated isolated DC-DC converter uses advanced circuit and on-chip layout techniques to reduce radiated emissions and achieve up to 46% typical efficiency. The integrated transformer uses thin film polymer as the insulation barrier. Output voltage of power converter can be controlled to 3.3 V or 5 V using MODE pin. In case bus communication is not needed, the DC-DC converter can be switched off using EN (enable) pin to save power. The output voltage, VISOOUT, is monitored and feedback information is conveyed to the primary side through a dedicated isolation channel. The duty cycle of the primary switching stage is adjusted accordingly. The fast feedback control loop of the power converter ensures low overshoots and undershoots during load transients. Undervoltage lockout (UVLO) with hysteresis is integrated on the VIO, VDD and VISOOUT supplies which ensures robust fails-safe system performance under noisy conditions. An integrated soft-start mechanism ensures controlled inrush current and avoids any overshoot on the output during power up. 10.3 Signal Isolation The integrated signal isolation channels employ an ON-OFF keying (OOK) modulation scheme to transmit the digital data across a silicon-dioxide based isolation barrier. The transmitter sends a high frequency carrier across the barrier to represent one state and sends no signal to represent the other state. The receiver demodulates the signal after signal conditioning and produces the output through a buffer stage. The signalisolation channels incorporate advanced circuit techniques to maximize the CMTI performance and minimize the radiated emissions from the high frequency carrier and IO buffer switching. Figure 10-2 shows a functional block diagram of a typical signal isolation channel. In order to keep any noise coupling from power converter away from signal path, power supplies on side1 for power converter (VDD) and signal path(VIO) are kept separate. Similarly on side2, power converter output (VISOOUT ) needs to be connected to power supply for RS-485 (VISOIN) externally on PCB. For more details, refer to Layout guidelines section. 10.4 RS-485 In a typical RS-485 network, multiple nodes may be connected on the bus and the distance of communicating nodes can be as far as 4000-5000 feet. While communicating at such large distances, usual common mode of non-isolated RS-485 transceiver is not sufficient. ISOW14x2 has integrated isolation barrier with upto 1500 Vpk working voltage rating. Isolation breaks the ground loop between the communicating nodes and allows for data transfer in the presence of large ground potential differences. These devices have a higher typical differential output voltage (VOD) than traditional transceivers for better noise immunity. A minimum differential output voltage of 2.1 V is specified when VISOIN is configured for 5 V supply which meets the requirements for PROFIBUS applications. The ISOW14x2 family of devices is suitable for applications that have limited board space and require more integration. Only external bypass capacitors are needed to fully realize an isolated RS-485 port. This family of devices is also suitable for very-high voltage applications, where power transformers for discrete isolated supply meeting the required isolation specifications are bulky and expensive. Though the device family is full-duplex, it can also be used for half-duplex applications by connecting driver output (Y , Z) to receiver input (A , B) on PCBthis helps to reduce cabling costs. For more details, refer to Application Information. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ISOW1412 ISOW1432 29 ISOW1412, ISOW1432 www.ti.com SLLSF86C – MAY 2018 – REVISED MARCH 2022 10.5 Functional Block Diagram VIO VISOIN VISOIN DE Tx Rx D Tx Rx Y Z B R Rx Tx Full Du plex A GND RE OUT Rx Tx IN GNDIO GISOIN GND1 GNDIO VDD EN/FLT GISOIN GND2 DC-DC Primary MODE DC-DC Second ary VISOOU T GND1 GND2 Figure 10-1. Block Diagram Receiver Transmitter TX IN TX IN OOK Modulation TX Signal Conditioning Carrier signal through isolation barrier RX OUT Oscillator SiO2 based Capacitive Isolation Barrier RX Signal Conditioning Envelope Detection RX OUT Emissions Reduction Techniques Figure 10-2. Signal Isolation channel 10.6 Feature Description 10.6.1 Power-Up and Power-Down Behavior The ISOW14x2 family of devices has built-in under-voltage lockout (UVLO) on all supplies (VDD, VIO and VISOOUT) with positive-going and negative-going thresholds and hysteresis. Both the power converter supply (VDD) and Logic supply (VIO) need to be present for the device to work. If either of them is below its UVLO, both the signal path and the power converter are disabled. Assuming VIO is above its UVLO+, when the VDD voltage crosses the positive-going UVLO threshold during power-up, the DC-DC converter initializes and the power converter duty cycle is increased in a controlled manner. This soft-start scheme limits primary peak currents drawn from the VDD supply and charges the VISOOUT output in a controlled manner, avoiding overshoots. RS-485 driver output is in high impedance state in this duration. When the UVLO positive-going threshold is crossed on the secondary side VISOOUT pin, the feedback channel starts providing feedback to the primary controller. The regulation loop takes over and RS-485 drive output, Received data output R and general purpose logic output OUT take their respective states defined by the inputs to the device i.e. Driver enable(DE), Driver data to be transmitted D, Receiver enable RE and general 30 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ISOW1412 ISOW1432 ISOW1412, ISOW1432 www.ti.com SLLSF86C – MAY 2018 – REVISED MARCH 2022 purpose logic input IN respectively. Designers should consider a sufficient time margin (typically 5 ms with 10-µF load capacitance) to allow this power up sequence before any usable system functionality. When either of VDD or VIO is lost, the primary side DC-DC controller turns off when the UVLO lower threshold is reached. The VISOOUT capacitor then discharges depending on the isolation channels and RS-485 load. 10.6.2 Protection Features The ISOW14x2 family of devices has multiple protection features to create a robust system level solution. • The first feature is an Enable/Fault protection feature. This EN/FLT pin can be used as either an input pin to enable or disable the integrated DC-DC power converter or as an output pin which works as an alert signal if the power converter is not operating properly. In the /Fault use case, a fault is reported if VDD > 7 V, VDD < 2.5 V, or if the junction temperature >170°C. When a fault is detected, this pin will go low, disabling the DC-DC converter to prevent any damage. • k MCU OUTPUT EN/FLT Powers Down RS-485 Transceiver and DC-DC Converter. IQ < 1 mA Typical MCU INPUT Fault Reported If VDD < 2.5 V VDD > 7 V Junction Temp > 170° C Figure 10-3. EN Fault Pin Diagram • • • • An over-voltage clamp feature is present on VISOOUT which will clamp the voltage at 6 V at Profibus mode (MODE = VISOOUT ) or 4V at RS485 mode (MODE = GND2), if there is an increase in voltage seen. For device reliability, it is recommended that VISOOUT stays lower than the over-clamp voltage for device reliability. Over-Voltage Lock Out (OVLO) on VDD will occur when a voltage higher than 7 V on VDD is seen. At OVLO, the device will go into a low power state and the EN/FLT pin will go low. These devices are protected against output overload and short circuit. In cases of overload or short on power converter output VISOOUT, maximum duty cycle of power converter is limited. In cases of driver bus short circuit due to the external power supply cable shorting to the bus cable, or due to bus contention, short circuit current protection on RS-485 chip restricts the bus current to ±250 mA maximum. Thermal protection is also integrated to help prevent the device from getting damaged under such scenarios. An increase in the die temperature is monitored and the device is disabled when the die temperature becomes 165℃ (typical), thus disabling the short condition. The device is re-enabled when the junction temperature becomes 155℃ (typical). If an overload or output short-circuit condition prevails, this protection cycle is repeated. Care should be taken in the system design to prevent repeated or prolonged exposure to bus shorts as this exposes the device to high junction temperatures for extreme amounts of time affecting device reliability. 10.6.3 Failsafe Receiver The differential receiver of the ISOW14x2 devices has failsafe protection from invalid bus states caused by: • • • Open bus conditions such as a broken cable or a disconnected connector Shorted bus conditions such as insulation breakdown of a cable that shorts the twisted-pair Idle bus conditions that occur when no driver on the bus is actively driving. The differential input of the RS-485 receiver is 0 in any of these conditions for a terminated transmission line. The receiver outputs a failsafe logic-high state on R pin so that the output of the receiver is determinate. The receiver thresholds are offset in the receiver design so that the indeterminate range does not include a 0 V differential. See Receiver functional table for more details. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ISOW1412 ISOW1432 31 ISOW1412, ISOW1432 www.ti.com SLLSF86C – MAY 2018 – REVISED MARCH 2022 10.6.4 Glitch-Free Power Up and Power Down Communication on the bus that already exist between a master node and slave node in an RS-485 network must not be disturbed when a new node is swapped in or out of the network. No glitches on the bus should occur when the device is: • • • Hot plugged into the network in an unpowered state Hot plugged into the network in a powered state and disabled state Powered up or powered down in a disabled state when already connected to the bus The ISOW14x2 devices meet above criteria and do not cause any false data toggling on the bus when powered up or powered down in a disabled state with supply ramp rates >= 50 us. 10.7 Device Functional Modes Table 10-1 lists the supply configuration for these devices: Table 10-1. Supply configuration Function Table INPUTS OUTPUT VDD (1) VIO < VDD(UVLO+) >VIO(UVLO+) X OFF >VDD(UVLO+) VIT+ L H VIT- < VID < VIT+ L Indeterminate VID < VIT- L L X H Hi-Z X Open Hi-Z Open, Short, Idle L H L X X H Hi-Z X X X H or Open X X L X X Invalid Operation PU=Powered up, PD=Powered down; H=high level; L=Low level; X=Irrelevant; Hi-Z=High impedance state A strongly driven input signal on D, DE or RE can weakly power the floating VIO through an internal protection diode and cause an undetermined output. VISOOUT shorted to VISOIN on PCB and both GND2 pins are shorted to each other and EN/FLT=High The receiver is enabled when the receiver enable pin, RE, is logic low. The receiver output, R, goes high when the differential input voltage defined by Equation 2 is greater than the positive input threshold, VTH+. VID = VA – VB (2) The receiver output, R, goes low when the differential input voltage defined by Equation 2 is less than the negative input threshold, VTH– . If the VID voltage is between the VTH+ and VTH– thresholds, the output is indeterminate. The receiver output is in the Hi-Z state and the magnitude and polarity of VID are irrelevant when the RE pin is logic high or left open. The internal biasing of the receiver inputs causes the output to go to a failsafe-high when the transceiver is disconnected from the bus (open-circuit), the bus lines are shorted to one another (short-circuit), or the bus is not actively driven (idle bus). Other device feature functional states in shown in Table 10-4 and Table 10-5 below: Table 10-4. DC-DC Converter Enable/Disable INPUTS OUTPUT VDD VIO EN/FLT VISOOUT PU PU H or Open 3.3 V or 5 V depending on MODE pin setting PU PU L OFF Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ISOW1412 ISOW1432 33 ISOW1412, ISOW1432 www.ti.com SLLSF86C – MAY 2018 – REVISED MARCH 2022 Table 10-5. General Purpose Logic Input/Output INPUTS VDD (1) (2) PU (1) (2) 34 VIO PU OUTPUT EN/FLT H or Open Comments IN OUT H H L L Output channel assumes logic state governed by IN Default state Open L L X Hi-Z PD PU X X Hi-Z PU PD X X Invalid Operation Device is in disabled state when either of VDD or VIO is missing PU = Powered Up; PD = Powered Down; H = Logic High; L= Logic Low; X = Irrelevant, Hi-Z = High Impedance (OFF) state VISOOUT shorted to VISOIN on PCB. GISOIN and GND2 pins are shorted to each other and EN/FLT=High Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ISOW1412 ISOW1432 ISOW1412, ISOW1432 www.ti.com SLLSF86C – MAY 2018 – REVISED MARCH 2022 10.8 Device I/O Schematics D, RE VIO DE VIO VIO VIO VIO VIO VIO 500 k DE D, RE 500 k GNDIO IN VISOIN GNDIO GNDIO GNDIO GNDIO GNDIO EN/FLT VISOIN VISOIN VIO VIO VIO VIO 550 k EN/FLT IN 500 k GISOIN GISOIN GISOIN MODE VISOOU T 1mA GND1 GND1 GND1 GND1 R, OUT VIO VISOOU T VISOOU T a R or OUT MODE 500 k GND2 GND2 GND2 GNDIO Figure 10-4. Device I/O schematics Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ISOW1412 ISOW1432 35 ISOW1412, ISOW1432 www.ti.com SLLSF86C – MAY 2018 – REVISED MARCH 2022 11 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 11.1 Application Information The ISOW14x2 devices are designed for bidirectional data transfer on multipoint RS-485 networks. An RS-485 bus has multiple transceivers that connect in parallel to a bus cable. Both cable ends are terminated with a termination resistor, RT, to remove line reflections. The value of RT matches the characteristic impedance, Z0, of the cable. This method, known as parallel termination, lets higher data rates be used over a longer cable length. Full-duplex implementation shown in Figure 9-1 requires two signal pairs (four wires). Full-duplex implementation lets each node to transmit data on one pair while simultaneously receiving data on the other pair. Y DE RT Z ISOW14x2 Master B R RE ISOW14x2 Slave c R RE A B Z D DE D A RT RT B Z Y D DE R RE ISOW14x2 Slave A Y Figure 11-1. Typical RS-485 network with Full-duplex Isolated transceivers Figure 9-2 below, shows ISOW14x2 devices used in half duplex configuration. Driver outputs Y and Z are shorted to A and B respectively. This reduces overall cabling requirements. Also DE/RE are shorted to each other, and at a time, any node acts as either a driver or a receiver. Split termination is also shown in this configuration which helps to boost network immunity in noisy environments by providing common-mode noise filtering and also reduces radiated emissions by providing low impedance path to earth to the bus common mode excursions. 36 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ISOW1412 ISOW1432 ISOW1412, ISOW1432 www.ti.com SLLSF86C – MAY 2018 – REVISED MARCH 2022 Integrated isolation barrier allows for communication between nodes with ground potential differences of up to 1500 V R RE DE A A 60 ISOW14x2 B 100pF 60 100pF 60 60 B ISOW14x2 DE D D GND2 GND2 B A GND2 B GND2 D ISOW14x2 DE R RE D DE R RE ISOW14x2 A R RE Figure 11-2. Typical RS-485 Network With Half-Duplex Isolated Transceivers 11.2 Typical Application 4.7 k FB 0.1 …F VIO GPIO1 MCU 3.3 V PE 5V GND FB FB VISOIN 16 GISOIN 4 R R 5 0.1 …F 10 …F 15 NC 20 A BB 19 RE DE ISOW14x2 Z 18 17 Y RE DE 2 D D 7 OUT NC 9 VDD GND1 10 GND1 10 µF 1 µF 10 nF GPIO3 DGND GPIO4 N PSU 6 GNDIO GND1 3 GPIO2 L1 8 1 V EN/FLT VIOCC 1 MODE RS-485 BUS 13 VIS OOUT 12 GND2 GND2 11 10 nF 1 µF 10 µF Gal van ic Isol atio n B arrier FB FB Extr a Curr ent ~2 0 mA Other Field Circuitr y Notes: 1. Extra current is only available in V DD = 5 V +/- 10% mode. 2. Keep 10 nF bypass capacitors close to VDD and VISOOUT pins (< 1 mm) for optimum radiated emissions performance. 3. GND1 and GNDIO must be shorted directly. GND2 and GISOIN must be shorted directly, or through ferrite beads. Figure 11-3. Application circuit for ISOW14x2 11.2.1 Design Requirements Unlike an optocoupler-based solution, which requires several external components to improve performance, provide bias, or limit current, the ISOW14x2 devices only require external bypass capacitors to operate as shown in above application diagram. Because of high peak currents flowing through VDD and VISOOUT supplies, bulk capacitance of minimum 10 μF is recommended on both pins. Higher values of bulk capacitors will attenuate noise and ripple further, enhancing performance. 11.2.2 Detailed Design Procedure The RS-485 bus is a robust electrical interface suitable for long-distance communications. The RS-485 interface can be used in a wide range of applications with varying requirements of distance of communication, data rate, and number of nodes. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ISOW1412 ISOW1432 37 ISOW1412, ISOW1432 www.ti.com SLLSF86C – MAY 2018 – REVISED MARCH 2022 11.2.2.1 Data Rate, Bus Length and Bus Loading The RS-485 standard has typical curves similar to those shown in Figure 11-4. These curves show the inverse relationship between signaling rate and cable length. If the data rate of the payload between two nodes is lower, the cable length between the nodes can be longer. Use below Figure as a guideline for cable selection, data rate, cable length and subsequent jitter budgeting. 10000 Cable Length (ft) 5%, 10%, and 20% Jitter 1000 Conservative Characteristics 100 10 100 1k 10 k 100 k 1M 10 M 100 M Data Rate (bps) Figure 11-4. Cable length vs Data rate characteristics The current supplied by the driver must supply into a load because the output of the driver depends on this current. Add transceivers to the bus to increase the total bus loading. The RS-485 standard specifies a hypothetical term of a unit load (UL) to estimate the maximum number of possible bus loads. The UL represents a load impedance of approximately 12 kΩ. Standard-compliant drivers must be able to drive 32 of these ULs. The ISOW14x2 devices have 1/8 UL impedance transceiver and can connect up to 256 nodes to the bus. 11.2.2.2 Stub Length In an RS-485 network, the distance between the transceiver inputs and the cable trunk is known as the stub. The stub should be as short as possible when a node is connected to the bus. Stubs are a non-terminated piece of bus line that can introduce reflections of varying phase as the length of the stub increases. The electrical length, or round-trip delay, of a stub should be less than one-tenth of the rise time of the driver as a general guideline. Therefore, the maximum physical stub length (L(STUB)) is calculated as shown in Equation 3. L(STUB) ≤ 0.1 × tr × v × c (3) where: • • • tr is the 10/90 rise time of the driver. c is the speed of light (3 × 108 m/s). v is the signal velocity of the cable or trace as a factor of c. 11.2.2.3 Insulation Lifetime Insulation lifetime projection data is collected by using industry-standard Time Dependent Dielectric Breakdown (TDDB) test method. In this test, all pins on each side of the barrier are tied together creating a two-terminal device and high voltage applied between the two sides as shown in below TDDB test setup. The insulation breakdown data is collected at various high voltages switching at 60 Hz over temperature. For reinforced insulation, VDE standard requires the use of TDDB projection line with failure rate of less than 1 part per million (ppm). Even though the expected minimum insulation lifetime is 20 years at the specified working isolation voltage, VDE reinforced certification requires additional safety margin of 20% for working voltage and 87.5% for lifetime which translates into minimum required insulation lifetime of 37.5 years at a working voltage that's 20% higher than the specified value. 38 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ISOW1412 ISOW1432 ISOW1412, ISOW1432 www.ti.com SLLSF86C – MAY 2018 – REVISED MARCH 2022 A Vcc 1 Vcc 2 Time Counter > 1 mA DUT GND 1 GND 2 VS Oven at 150 °C Figure 11-5. Test Setup for Insulation Lifetime Measurement The insulation lifetime projection data shows the intrinsic capability of the isolation barrier to withstand high voltage stress over its lifetime. Based on the TDDB data, the intrinsic capability of the insulation is 1000 VRMS with a lifetime of 1184 years. Figure 11-6. Insulation Lifetime Projection Data 12 Power Supply Recommendations To make sure that operation is reliable at all data rates and supply voltages, adequate decoupling capacitors must be located as close to supply pins as possible. Power converter input VDD and output VISOOUT supply pins should have high frequency ceramic capacitors 10 nF and bulk capacitors 10 μF atleast close to the pins. Signal path supply pins, VIO and VISOIN, should have 100 nF or higher value ceramic bypass capacitors close to device pins. ISOW1412 can consume typical peak pulse currents of upto 250 mA under fully loaded conditions for short Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ISOW1412 ISOW1432 39 ISOW1412, ISOW1432 www.ti.com SLLSF86C – MAY 2018 – REVISED MARCH 2022 durations (10s of µs) from the power source that is powering VDD of ISOW1412. Please make sure the current limit of upstream power device is at least 300 mA typical. 40 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: ISOW1412 ISOW1432 ISOW1412, ISOW1432 www.ti.com SLLSF86C – MAY 2018 – REVISED MARCH 2022 13 Layout 13.1 Layout Guidelines Figure 11-1 shows the recommended placement and routing of device bypass capacitors. Below guidelines must be followed to achieve low emissions design: 1. High frequency bypass capacitors 10 nF must be placed close to VDD and VISOOUT pins, less than 1 mm distance away from device pins. This is very essential for optimised radiated emissions performance. Ensure that these capacitors are 0402 size so that they offer least inductance (ESL). 2. Bulk capacitors of atleast 10 µF must be placed on power converter input (VDD) and output (VISOOUT) supply pins. 3. Traces on VDD and GND1 must be symmetric till bypass capacitors. Similarly traces on VISOOUT and GND2 must be symmetric. 4. Place two 0402 size Ferrite beads (Part number: BLM15EX331SN1) on power supply pins, one between VISOOUT and VISOIN and the other between GND2 (11) and GISOIN(15), as shown in example PCB layout, so that any high frequency noise from power converter output sees a high impedance before it goes to other components on PCB. 5. Do not have any metal traces or ground pour within 4 mm of power converter output terminals VISOOUT (pin12) and GND2 (pin11). MODE pin is also in VISOOUT domain and should be shorted to either pin 11 or pin 12 for output voltage selection. 6. Common mode choke or ferrite beads on bus terminals (Y/Z/A/B) can minimise any high frequency noise that can couple of RS-485 bus cable which can act as antenna and amplify that noise. This will improve Radiated emissions performance on a system level. 7. Following the layout guidelines of EVM as much as possible is highly recommended for a low radiated emissions design. EVM Link is available in Related Documentation. 13.2 Layout Example ISOW14x2