ISOW7721
SLLSFP4 – JULY 2022
ISOW7721 Two-Channel Digital Isolator with Integrated Low-Emissions, Low-Noise
DC-DC Converter
1 Features
2 Applications
•
•
•
•
•
•
•
•
•
•
•
•
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•
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100 Mbps data rate
Integrated DC-DC converter with low-emissions,
low-noise
– Emissions optimized to meet CISPR 32 and EN
55032 Class B with >5 dB margin on 2 layer
board
– Low frequency power converter at 25 MHz
enabling low noise performance
– Low output ripple: 24 mV
High efficiency output power
– Efficiency at max load: 46%
– Up to 0.55-W output power
– VISOOUT accuracy of ± 5%
– 5 V to 5 V: Max available load current = 110 mA
– 5 V to 3.3 V: Max available load current = 140
mA
– 3.3 V to 3.3 V: Max available load current = 60
mA
Support for multi-ISOW7721 chain to increase
system power output to > 1-W and > 200 mA
Independent power supply for channel isolator &
power converter
– Logic supply (VIO): 1.71-V to 5.5-V
– Power converter supply (VDD): 3-V to 5.5-V
Robust electromagnetic compatibility (EMC)
– System-level ESD, EFT, and surge immunity
– ±8 kV IEC 61000-4-2 contact discharge
protection across isolation barrier
Reinforced and Basic isolation options
High CMTI: 100-kV/µs (typical)
Safety Related Certifications (Planned):
– VDE reinforced and basic insulation per DIN
VDE V 0884-11:2017-01
– UL 1577 component recognition program
– IEC 62368-1, IEC 61010-1, IEC 60601-1 and
GB 4943.1-2011 certifications
Extended temperature range: –40°C to +125°C
20-pin wide body SOIC package
Factory automation
Motor control
Grid infrastructure
Medical equipment
Test and measurement
3 Description
The ISOW7721 device is a galvanically-isolated
dual-channel digital isolator with an integrated highefficiency power converter with low emissions. The
integrated DC-DC converter provides up to 550
mW of isolated power, eliminating the need for a
separate isolated power supply in space-constrained
isolation designs. If additional power is needed, the
ISOW7721 supports multi-device chaining, increasing
the integrated power output to > 1 W using two
devices in a system.
Device Information
FEATURE
ISOW7721
ISOW7721F
Protection Level
Reinforced
Surge Test Voltage
10 kVPK
Isolation Rating
5000 VRMS
Working Voltage
1000 VRMS / 1500 VPK
Package
DFM (20)
Body Size (Nom)
12.83 mm × 7.5 mm
VISOIN
VIO
INA
Tx
Rx
OUTA
OUTB
Rx
Tx
INB
EN_IO1
EN_IO2
GNDIO
GISOIN
GND1
GND2
VDD
VSEL
LF
CC
DC-DC
Primary
DC-DC
Secondary
VISOOUT
EN
GND1
GND2
ISOW7721 Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ISOW7721
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SLLSFP4 – JULY 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Description (continued).................................................. 3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 6
7.1 Absolute Maximum Ratings........................................ 6
7.2 ESD Ratings............................................................... 6
7.3 Recommended Operating Conditions.........................7
7.4 Thermal Information....................................................8
7.5 Power Ratings.............................................................8
7.6 Insulation Specifications............................................. 9
7.7 Safety-Related Certifications.................................... 10
7.8 Safety Limiting Values...............................................10
7.9 Electrical Characteristics - Power Converter.............11
7.10 Supply Current Characteristics - Power
Converter.....................................................................12
7.11 Electrical Characteristics Channel Isolator VIO, VISOIN = 5-V..........................................................13
7.12 Supply Current Characteristics Channel
Isolator - VIO, VISOIN = 5-V...........................................13
7.13 Electrical Characteristics Channel Isolator VIO, VISOIN = 3.3-V.......................................................14
7.14 Supply Current Characteristics Channel
Isolator - VIO, VISOIN = 3.3-V........................................14
7.15 Electrical Characteristics Channel Isolator VIO, VISOIN = 2.5-V.......................................................15
7.16 Supply Current Characteristics Channel
Isolator - VIO, VISOIN = 2.5-V........................................15
7.17 Electrical Characteristics Channel Isolator VIO, VISOIN = 1.8-V.......................................................16
7.18 Supply Current Characteristics Channel
Isolator - VIO, VISOIN = 1.8-V........................................16
7.19 Switching Characteristics - 5-V Supply................... 17
7.20 Switching Characteristics - 3.3-V Supply................ 18
7.21 Switching Characteristics - 2.5-V Supply................ 19
7.22 Switching Characteristics - 1.8-V Supply................ 20
7.23 Insulation Characteristics Curves........................... 21
7.24 Typical Characteristics............................................ 22
8 Parameter Measurement Information.......................... 27
9 Detailed Description......................................................29
9.1 Overview................................................................... 29
9.2 Functional Block Diagram......................................... 30
9.3 Feature Description...................................................31
9.4 Device Functional Modes..........................................35
10 Application and Implementation................................ 37
10.1 Application Information........................................... 37
10.2 Typical Application.................................................. 37
11 Power Supply Recommendations..............................41
12 Layout...........................................................................42
12.1 Layout Guidelines................................................... 42
12.2 Layout Example...................................................... 43
13 Device and Documentation Support..........................44
13.1 Device Support....................................................... 44
13.2 Documentation Support.......................................... 44
13.3 Receiving Notification of Documentation Updates..44
13.4 Support Resources................................................. 44
13.5 Trademarks............................................................. 44
13.6 Electrostatic Discharge Caution..............................44
13.7 Glossary..................................................................44
14 Mechanical, Packaging, and Orderable
Information.................................................................... 45
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
July 2022
*
Initial release.
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5 Description (continued)
The high-efficiency of the power converter allows for operation at a wide operating ambient temperature range
of –40°C to +125°C. This device provides improved emissions performance, allowing for simplified board design
and has provisions for ferrite beads to further attenuate emissions. The ISOW7721 has been designed with
enhanced protection features in mind, including soft-start to limit inrush current, over-voltage and under-voltage
lock out, overload and short-circuit protection, and thermal shutdown.
The ISOW7721 provide high electromagnetic immunity while isolating CMOS or LVCMOS digital I/Os. The
signal-isolation channel has a logic input and output buffer separated by a double capacitive silicon dioxide
(SiO2) insulation barrier, whereas, power isolation uses on-chip transformers separated by thin film polymer as
insulating material. The ISOW7721 has 1 forward channel and 1 reverse channel. If the input signal is lost, the
default output is high for the ISOW7721 device without the F suffix and low for the ISOW7721F with the F suffix.
The ISOW7721 can operate from a single supply voltage of 3 V to 5.5 V by connecting VIO and V DD together on
a PCB. If lower logic levels are required, these devices support 1.71 V to 5.5 V logic supply (VIO) that can be
independent from the power converter supply (VDD) of 3 V to 5.5 V. VISOIN and VISOOUT need to be connected on
board with either a ferrite bead or fed through a LDO.
These devices help prevent noise currents on data buses, such as UART, RS-485, RS-232, and CAN, or other
circuits from entering the local ground and interfering with or damaging sensitive circuitry. Through innovative
chip design and layout techniques, electromagnetic compatibility of the device has been significantly enhanced
to ease system-level ESD, EFT, surge and emissions compliance. The device is available in a 20-pin SOIC
wide-body (SOIC-WB) DFM package.
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6 Pin Configuration and Functions
1
20
VISOIN
INA
2
19
OUTA
OUTB
3
18
INB
EN_IO1
4
17
EN_IO2
EN
5
16
NC
GNDIO
6
15
GISOIN
LF
7
14
NC
CC
8
13
VSEL
VDD
9
12
VISOOUT
GND1
10
11
GND2
ISOLATION
VIO
Figure 6-1. ISOW7721 DFM Package 20-Pin SOIC Top View
Table 6-1. Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
ISOW7721
EN_IO1
4
I
Output Enable 1: When EN_IO1 is high or open then the channel output pin on side 1 is enabled.
When EN_IO1 is low then the channel output pin on side 1 is in a high impedance state and the
transmitter of the channel input pin on side 1 is disabled.
EN_IO2
17
I
Output Enable 2: When EN_IO2 is high or open then the channel output pin on side 2 is enabled.
When EN_IO2 is low then the channel output pin on side 2 is in a high impedance state and the
transmitter of the channel input pin on side 2 is disabled.
GNDIO
6
—
Ground connection for VIO. GND1 and GNDIO need to be shorted on board.
GISOIN
15
—
Ground connection for VISOIN. GND2 and GISOIN pins can be shorted on board or connected
through a ferrite bead. See the Layout Section for more information.
GND1
10
—
Ground connection for VDD. GND1 and GNDIO needs to be shorted on board.
GND2
11
—
Ground connection for VISOOUT. GND2 and GISOIN pins can be shorted on board or connected
through a ferrite bead. See the Layout Section for more information.
INA
2
I
Input channel A
INB
18
I
Input channel B
Multiple device pimary/secondary synchronization pin.
When LF is set to GND1, CC is an output used to sync to an additional ISOW7721. When LF is set
CC
8
I/O
to VDD, CC is an input. Connect the CC pin of the primary device to all the secondary devices. Leave
CC floating if unused.
See Multi-Device Chaining for Increased Power Output for more information.
LF
7
I
Multiple device primary/secondary control logic.
Connect the LF to GND1 when used as the primary device or to VDD if used as the secondary device.
Tie LF to GND1 if used as a standalone device when not chaining the power converters.
See Multi-Device Chaining for Increased Power Output for more information.
4
OUTA
19
O
Output channel A
OUTB
3
O
Output channel B
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Table 6-1. Pin Functions (continued)
PIN
NAME
NO.
I/O
DESCRIPTION
ISOW7721
Power converter enable input pin: enables and disables the integrated DC-DC power converter.
Connect directly to microcontroller or through a series current limiting resistor to use as an enable
EN
5
I/O
input pin. DC-DC power converter is enabled when EN is high to the VIO voltage level and disabled
when low at GND1 voltage level.
See Section 9.3.3 for more information
VISOOUT selection pin. VISOOUT = 5 V when VSEL shorted to VISOOUT. VISOOUT = 3.3 V, when VSEL
shorted to GND2. For more information see the Device Functional Modes.
VSEL
13
I
VIO
1
—
Side 1 logic supply.
VDD
9
—
Side 1 DC-DC converter power supply.
VISOIN
20
—
Side 2 supply voltage for isolation channels. VISOIN and VISOOUT pins can be shorted on board or
connected through a ferrite bead. See Application and Implementation for more information.
VISOOUT
12
—
Isolated power converter output voltage. VISOIN and VISOOUT pins can be shorted on board or
connected through a ferrite bead. See Application and Implementation for more information.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN
MAX
UNIT
VDD
Power converter supply voltage
–0.5
6
V
VISOIN
Isolated supply voltage, input supply for secondary side isolation channels
–0.5
6
V
VISOOUT
Isolated supply voltage, Power converter output
VSEL shorted to GND2
–0.5
4
V
VISOOUT
Isolated supply voltage, Power converter output
VSEL shorted to VISOOUT
–0.5
6
V
VIO
Primary side logic supply voltage
–0.5
6
V
VLF
Voltage at LF
-0.5
6
V
Voltage at INx, OUTx,
V
EN_IOx(3)
–0.5
VSI + 0.5
V
Voltage at EN/FLT
–0.5
VSI + 0.5
V
Voltage at VSEL
–0.5
VISOOUT + 0.5
IO
Maximum output current through data channels
–15
15
mA
TJ
Junction temperature
–40
150
°C
Tstg
Storage temperature
–65
150
°C
(1)
(2)
(3)
V
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated
under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
VDD, VISOIN VISOOUT, and VIO are with respect to the local ground pin (GND1 or GND2). All voltage values except differential I/O bus
voltages are peak voltage values.
VSI = input side supply; Cannot exceed 6 V.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
6
Electrostatic
discharge
Human-body model (HBM), per AEC Q100-002(1)
HBM ESD Classification Level 2
±3000
Charged-device model (CDM), per AEC Q100-011
CDM ESD Classification Level C6
±1500
Contact discharge per IEC 61000-4-2(2)
Isolation barrier withstand test
±8000
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
IEC ESD strike is applied across the barrier with all pins on each side tied together creating a two-terminal device.
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7.3 Recommended Operating Conditions
Over recommended operating conditions, typical values are at VDD = VIO = 3.3 V and TA =25°C, GND1 = GNDIO, GND2 =
GISOIN (unless otherwise noted)
MIN
NOM
MAX
UNIT
2.97
3.3
3.63
V
4.5
5
5.5
V
2.7
2.95
V
Power Converter
3.3 V operation
VDD
Power converter supply
voltage
VDD(UVLO+)
Positive threshold when
power converter supply is
rising
Positive threshold when power
converter supply is rising
VDD(UVLO-)
Positive threshold when
power converter supply is
falling
Positive threshold when power
converter supply is falling
2.40
VDD(HYS)
Power converter supply
voltage hysteresis
Power converter supply voltage
hysteresis
0.15
1.8 V operation
1.71
2.5 V, 3.3 V, and 5 V operation
2.25
5 V operation
2.55
V
V
Channel Isolation
VIO, VISOIN
(3)
Channel logic supply voltage
V
5.5
V
1.7
V
VIO(UVLO+)
Rising threshold of logic supply voltage
VIO(UVLO-)
Falling threshold of logic supply voltage
1.0
VIO(HYS)
Logic supply voltage hysteresis
75
mV
VISOIN = 5 V
–4
mA
VISOIN = 3.3 V
–2
mA
VISOIN = 2.5 V
–1
mA
VISOIN = 1.8 V
–1
mA
High level output current(1)
IOH
Low level output current(1)
IOL
High-level input
VIL
Low-level input voltage
DR
Data rate
tPWRUP
Channel isolator ready after
power up or EN/FLT high
TA
Ambient temperature
(1)
(2)
(3)
1.41
V
VISOIN = 5 V
4
mA
VISOIN = 3.3 V
2
mA
VISOIN = 2.5 V
1
mA
VISOIN = 1.8 V
1
mA
voltage(2)
VIH
1.55
1.89
0.7 × VSI
VSI
V
0
0.3 × VSI
V
100
VISOIN > VIO(UVLO+)
5
–40
Mbps
ms
125
°C
This current is for data output channel.
VSI = input side supply; VSO = output side supply
The channel outputs are in undetermined state when 1.89 V < VSI < 2.25 V and 1.05 V < VSI < 1.71 V
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7.4 Thermal Information
ISOW7721
THERMAL
METRIC(1)
UNIT
DFM (SOIC)
20 PINS
RθJA
Junction-to-ambient thermal resistance
68.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
24.6
°C/W
RθJB
Junction-to-board thermal resistance
53.7
°C/W
ΨJT
Junction-to-top characterization parameter
17.1
°C/W
ΨJB
Junction-to-board characterization parameter
50.9
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Power Ratings
VDD = VIO = 5.5 V, IISO = 110 mA, TJ = 150°C, TA ≤ 80°C, CL = 15 pF, input a 50-MHz 50% duty-cycle square wave
PARAMETER
PD
PD1
PD2
8
TEST CONDITIONS
Maximum power dissipation (both sides) VDD = 5.5 V, VIO = 5.5 V, VISOOUT =
VISOIN, IISOOUT = 100 mA, TJ = 150°C,
Maximum power dissipation (side-1)
TA ≤ 80°C, CL = 15 pF, input a 50-MHz
Maximum power dissipation (side-2)
50% duty-cycle square wave
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MIN
TYP
MAX
UNIT
1.48
W
0.74
W
0.74
W
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7.6 Insulation Specifications
PARAMETER
TEST CONDITIONS
VALUE
UNIT
GENERAL
CLR
External clearance(1)
Shortest terminal-to-terminal distance through air
>8
mm
CPG
External creepage(1)
Shortest terminal-to-terminal distance across the
package surface
>8
mm
DTI
Minimum internal gap (internal clearance – capacitive
signal isolation)
> 17
Minimum internal gap (internal clearance –
transformer power isolation)
>120
Comparative tracking index
DIN EN 60112 (VDE 0303-11); IEC 60112
> 600
Material group
According to IEC 60664-1
Distance through the insulation
CTI
Overvoltage category per IEC 60664-1
DIN VDE V
Maximum repetitive peak isolation
voltage
VIOWM
Maximum working isolation voltage
I-IV
Rated mains voltage ≤ 600 VRMS
I-IV
Rated mains voltage ≤ 1000 VRMS
I-III
AC voltage (bipolar)
1500
VPK
AC voltage; Time dependent dielectric breakdown
(TDDB) Test
1000
VRMS
DC voltage
1500
VDC
7071
VPK
6250
VPK
VIOTM
Maximum transient isolation voltage
VIOSM
Maximum surge isolation voltage
ISOW7721(3)
Test method per IEC 62368-1, 1.2/50 µs waveform,
VTEST = 1.6 × VIOSM = 10000 VPK(qualification)
Apparent charge(4)
Barrier capacitance, input to output(5)
Insulation resistance(5)
RIO
I
Rated mains voltage ≤ 300 VRMS
VTEST = VIOTM; t = 60 s (qualification);
VTEST = 1.2 × VIOTM; t = 1 s (100% production)
CIO
V
0884-11:2017-01(2)
VIORM
qpd
µm
Method a, after input/output safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s, Vpd(m) = 1.2 × VIORM, tm = 10 s
≤5
Method a, after environmental tests subgroup 1, Vini =
VIOTM, tini = 60 s, Vpd(m) = 1.6 × VIORM, tm = 10 s
≤5
Method b1, at routine test (100% production) and
preconditioning (type test), Vini = 1.2 × VIOTM, tini = 1
s, Vpd(m) = 1.875 × VIORM, tm = 1 s
≤5
VIO = 0.4 × sin (2πft), f = 1 MHz
~3.5
>
VIO = 500 V, 100°C ≤ TA ≤ 125°C
> 1011
>
pF
1012
VIO = 500 V, TA = 25°C
VIO = 500 V, TS = 150°C
pC
Ω
109
Pollution degree
2
Climatic category
40/125/21
UL 1577
VISO(UL)
(1)
(2)
(3)
(4)
(5)
Withstand isolation voltage
VTEST = VISO(UL)= 5000 VRMS, t = 60 s (qualification),
VTEST = 1.2 × VISO(UL) = 6000 VRMS, t = 1 s (100%
production)
5000
VRMS
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application.
Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the
isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal
in certain cases. Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these
specifications.
ISOW77xx is suitable for safe electrical insulation and ISOW77xxB is suitable for basic electrical insulation only within the safety
ratings.. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
Apparent charge is electrical discharge caused by a partial discharge (pd).
All pins on each side of the barrier tied together creating a two-terminal device.
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7.7 Safety-Related Certifications
VDE
CSA
UL
Certified according to DIN Certified according to IEC
VDE V 0884-11:2017-01
62368-1, and IEC 60601-1
Recognized under
UL 1577 Component
Recognition Program
CQC
TUV
Certified according to
GB 4943.1-2011
Certified according to
EN 61010-1:2010/A1:2019
and EN 62368-1:2014
Reinforced insulation;
Maximum transient
isolation voltage, 7071
VPK;
Maximum repetitive peak
isolation voltage, 1500
VPK;
Maximum surge isolation
voltage, 6250 VPK.
CSA 62368-1-19 and IEC
62368-1:2018 Ed. 3 and EN
62368-1:2020. (pollution degree
2, material group I) 600
VRMS maximum working voltage;
2 MOPP (Means of Patient
Single protection, 5000
Protection) per CSA 60601-1:14
VRMS
and IEC 60601-1 Ed. 3+A1,
250 VRMS maximum working
voltage. Temperature rating is
90°C for reinforced insulation
and 125°C for basic insulation;
see certificate for details.
5000 VRMS Reinforced
insulation per EN 61010Reinforced Insulation,
1:2010 up to working
Altitude ≤ 5000 m,
voltage of 600 VRMS;
Tropical Climate, 700
5000 VRMS Reinforced
VRMS maximum working insulation per EN
voltage;
62368-1:2014 up to
working voltage of 600
VRMS.
Certificate #: Pending
Basic: Pending
Master Contract#: Pending
Certificate #: Pending
File #: Pending
Client ID: Pending
7.8 Safety Limiting Values
Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.
PARAMETER
IS
PS
TS
(1)
10
Safety input, output, or supply current(1)
Safety input, output, or total power(1)
Maximum safety
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RθJA = 68.5°C/W, VI = 5.5 V, TJ = 150°C,
TA = 25°C
332
RθJA = 68.5°C/W, VI = 3.6 V, TJ = 150°C,
TA = 25°C
507
RθJA = 68.5°C/W, TJ = 150°C, TA = 25°C
1825
mW
150
°C
temperature(1)
mA
The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The
IS and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be
exceeded. These limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the Thermal Information table is that of a device installed on a high-K test board for
leaded surface-mount packages. Use the following equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum allowed junction temperature.
PS = IS × VI, where VI is the maximum input voltage.
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7.9 Electrical Characteristics - Power Converter
VDD = 5 V ±10% or 3.3 V ±10% and VISOIN power externally, GND1 = GNDIO, GND2 = GISOIN (over recommended
operating conditions, unless otherwise specified)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDD = 5 V, VISOOUT = 5 V, VSEL = VISOOUT
VISOOUT
Isolated supply voltage
External IISOOUT = 0 to 55 mA
4.75
5
5.25
V
VISOOUT
Isolated supply voltage
External IISOOUT = 0 to 110 mA
4.5
5
5.25
V
VISOOUT(LINE
DC line regulation
IISOOUT = 55 mA, VDD = 4.5 V to 5.5 V
DC load regulation
IISOOUT = 0 to 110 mA
EFF
Efficiency at maximum load
current (1)
IISOOUT = 110 mA, CLOAD = 0.01 µF || 10 µF;
VI = VDD (ISOW772x); VI =0 V (ISOW772x
with F suffix).
VISOOUT(RIP)
Output ripple on isolated supply
(pk-pk)
20-MHz bandwidth, CLOAD = 0.01 µF || 20 µF,
IISOOUT = 110 mA
IISOOUT_SC
DC current from VDD supply
under short circuit on VISOOUT
VISOOUT shorted to GND2
)
VISOOUT(LOA
D)
2
mV/V
1%
46%
24
mV
250
mA
VDD = 5 V, VISOOUT = 3.3 V, VSEL = GND2
VISOOUT
Isolated supply voltage
External IISOOUT = 0 to 70 mA
3.135
3.3
3.465
V
VISOOUT
Isolated supply voltage
External IISOOUT = 0 to 140 mA
3.135
3.3
3.465
V
VISOOUT(LINE
DC line regulation
IISOOUT = 70 mA, VDD = 4.5 V to 5.5 V
DC load regulation
IISOOUT = 0 to 140 mA
EFF
Efficiency at maximum load
current (1)
IISOOUT = 140 mA, CLOAD = 0.01 µF || 10 µF;
VI = VDD (ISOW772x); VI =0 V (ISOW772x
with F suffix).
VISOOUT(RIP)
Output ripple on isolated supply
(pk-pk)
20-MHz bandwidth , CLOAD = 0.01 µF || 20 µF,
IISOOUT = 110 mA
IISOOUT_SC
DC current from VDD supply
under short circuit on VISOOUT
VISOOUT shorted to GND2
)
VISOOUT(LOA
D)
2
mV/V
1%
36%
30
mV
250
mA
VDD = 3.3 V, VISOOUT = 3.3 V, VSEL = GND2
VISOOUT
Isolated supply voltage
External IISOOUT = 0 to 30 mA
3.135
3.3
3.465
V
VISOOUT
Isolated supply voltage
External IISOOUT = 0 to 60 mA
3.135
3.3
3.465
V
VISOOUT(LINE
DC line regulation
IISOOUT = 30 mA, VDD = 3.0 V to 3.6 V
DC load regulation
IISOOUT = 0 to 60 mA
EFF
Efficiency at maximum load
current (1)
IISOOUT = 60 mA, CLOAD = 0.01 µF || 10 µF;
VI = VDD (ISOW772x); VI =0 V (ISOW772x
with F suffix).
VISOOUT(RIP)
Output ripple on isolated supply
(pk-pk)
20-MHz bandwidth, CLOAD = 0.01 µF || 20 µF,
IISOOUT = 60 mA
IISOOUT_SC
DC current from VDD supply
under short circuit on VISOOUT
VISOOUT shorted to GND2
)
VISOOUT(LOA
D)
(1)
2
mV/V
1%
43%
14
mV
185
mA
Power converter ILOAD = current required to power the secondary side. ILOAD does not take into account the channel isolator current.
See Supply Current Characteristics Channel Isolator section for details.
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7.10 Supply Current Characteristics - Power Converter
VDD = 5 V ±10% or 3.3 V ±10% GND1 = GNDIO, GND2 = GISOIN (over recommended operating conditions unless otherwise
noted).
PARAMETER
SUPPLY
CURRENT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Power Converter Disabled
Power converter supply
current
EN/FLT = GND1, VISOOUT = No ILOAD
IDD
0.28
0.45
mA
Logic supply current
EN/FLT = GND1
IIO
0.27
0.57
mA
Power Converter Enabled
Power converter supply
current input
Power converter output
current (1)
(1)
12
VDD = 5 V, VSEL = VISOOUT
ILOAD = 55 mA
115
171
mA
VDD = 5 V, VSEL = VISOOUT
ILOAD = 110 mA
225
316
mA
VDD = 5 V, VSEL = GND2
ILOAD = 70 mA
127
169
mA
VDD = 5 V, VSEL = GND2
ILOAD = 140 mA
250
310
mA
VDD = 3.3 V, VSEL = GND2
ILOAD = 30 mA
74
112
mA
VDD = 3.3 V, VSEL = GND2
ILOAD = 60 mA
143
216
mA
VDD = 5 V
VSEL = VISOOUT
VDD = 5 V
VSEL = GND2
VDD = 3.3 V
VSEL = GND2
IDD
IISOOUT
110
mA
140
mA
60
mA
ILOAD does not take into account the channel isolator current. See Supply Current Characteristics Channel Isolator section for details.
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7.11 Electrical Characteristics Channel Isolator - VIO, VISOIN = 5-V
VIO, VISOIN = 5 V ±10% GND1 = GNDIO, GND2 = GISOIN (over recommended operating conditions, unless otherwise
specified)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Channel Isolation
VITH
Input pin rising threshold
VITL
Input pin falling threshold
0.3 x VSI
V
VI(HYS)
Input pin threshold hysteresis
(INx)
0.1 x VSI
V
IIL
Low level input current
–25
µA
IIH
0.7 x VSI
VIL = 0 at INx
(1)
High level input current
VIH = VSI
VOH
High level output voltage
IO = –4 mA, see Switching Characteristics
Test Circuit and Voltage Waveforms
VOL
Low level output voltage
IO = 4 mA, see Switching Characteristics Test
Circuit and Voltage Waveforms
CMTI
Common mode transient
immunity
VI = VSI or 0 V, VCM = 1000 V; see CommonMode Transient Immunity Test Circuit
(1)
at INx
V
25
µA
VSO (1) –
0.4
V
0.4
85
V
100
kV/us
VSI = input side supply; VSO = output side supply
7.12 Supply Current Characteristics Channel Isolator - VIO, VISOIN = 5-V
VIO, VISOIN = 5 V ±10% GND1 = GNDIO, GND2 = GISOIN (over recommended operating conditions, unless otherwise
specified)
PARAMETER
SUPPLY
CURRENT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IDD_IO
3.5
6
mA
IISOIN
3.5
5
mA
IDD_IO
3.5
6
mA
IISOIN
3.5
5
mA
EN_IO1 = EN_IO2 = VCCI; VI = VCCI (ISOW7721);
VI = 0 V (ISOW7721 with F suffix)
IDD_IO
3.5
6
mA
IISOIN
3.5
5
mA
EN_IO1 = EN_IO2 = VCCI; VI = 0 V (ISOW7721);
VI = VCCI (ISOW7721 with F suffix)
IDD_IO
4.5
7
mA
IISOIN
5
7
mA
IDD_IO
4
6.5
mA
IISOIN
4
6
mA
IDD_IO
4.8
7
mA
IISOIN
4.9
6.7
mA
IDD_IO
11.6
14.6
mA
IISOIN
11.8
14.3
mA
ISOW7721 Channel Supply Current
Supply current - Disable
Channel Supply current DC signal
EN_IO1 = EN_IO2 = 0 V; VI = VCCI
VI = 0 V (ISOW7721 with F suffix)
(1)
(ISOW7721);
1 Mbps
Channel Supply current AC signal
All channels switching with square
wave clock input; CL = 15 pF
10 Mbps
100 Mbps
(1)
VCCI = VIO or VISOIN
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7.13 Electrical Characteristics Channel Isolator - VIO, VISOIN = 3.3-V
VIO, VISOIN = 3.3 V ±10% GND1 = GNDIO, GND2 = GISOIN (over recommended operating conditions, unless otherwise
specified)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Channel Isolation
VITH
Input pin rising threshold
VITL
Input pin falling threshold
0.3 x VSI
V
VI(HYS)
Input pin threshold hysteresis
(INx)
0.1 x VSI
V
IIL
Low level input current
-25
µA
IIH
0.7 x VSI
VIL = 0 at INx
(1)
High level input current
VIH = VSI
VOH
High level output voltage
IO = –4 mA, see Switching Characteristics
Test Circuit and Voltage Waveforms
VOL
Low level output voltage
IO = 4 mA, see Switching Characteristics Test
Circuit and Voltage Waveforms
CMTI
Common mode transient
immunity
VI = VSI or 0 V, VCM = 1000 V; see CommonMode Transient Immunity Test Circuit
(1)
at INx
V
25
µA
VSO (1) –
0.3
V
0.3
85
V
100
kV/us
VSI = input side supply; VSO = output side supply
7.14 Supply Current Characteristics Channel Isolator - VIO, VISOIN = 3.3-V
VIO, VISOIN = 3.3 V ±10% GND1 = GNDIO, GND2 = GISOIN (over recommended operating conditions, unless otherwise
specified)
PARAMETER
SUPPLY
CURRENT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IDD_IO
3.5
6
mA
IISOIN
3.5
5
mA
IDD_IO
3.5
6
mA
IISOIN
3.5
5
mA
EN_IO1 = EN_IO2 = VCCI; VI = VCCI (ISOW7721);
VI = 0 V (ISOW7721 with F suffix)
IDD_IO
3.5
6
mA
IISOIN
3.5
5
mA
EN_IO1 = EN_IO2 = VCCI; VI = 0 V (ISOW7721);
VI = VCCI (ISOW7721 with F suffix)
IDD_IO
4.5
7
mA
IISOIN
5
7
mA
IDD_IO
4
6.5
mA
IISOIN
4
6
mA
IDD_IO
4.4
6.7
mA
IISOIN
4.6
6.4
mA
IDD_IO
8.6
11.7
mA
IISOIN
8.7
11.4
mA
ISOW7721 Channel Supply Current
Supply current - Disable
Channel Supply current DC signal
EN_IO1 = EN_IO2 = 0 V; VI = VCCI
VI = 0 V (ISOW7721 with F suffix)
(1)
(ISOW7721);
1 Mbps
Channel Supply current AC signal
All channels switching with square
wave clock input; CL = 15 pF
10 Mbps
100 Mbps
(1)
14
VCCI = VIO or VISOIN
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7.15 Electrical Characteristics Channel Isolator - VIO, VISOIN = 2.5-V
VIO, VISOIN = 2.5 V ±10% GND1 = GNDIO, GND2 = GISOIN (over recommended operating conditions, unless otherwise
specified)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Channel Isolation
VITH
Input pin rising threshold
VITL
Input pin falling threshold
0.3 x VSI
V
VI(HYS)
Input pin threshold hysteresis
(INx)
0.1 x VSI
V
IIL
Low level input current
-25
µA
IIH
0.7 x VSI
VIL = 0 at INx
(1)
High level input current
VIH = VSI
VOH
High level output voltage
IO = –4 mA, see Switching Characteristics
Test Circuit and Voltage Waveforms
VOL
Low level output voltage
IO = 4 mA, see Switching Characteristics Test
Circuit and Voltage Waveforms
CMTI
Common mode transient
immunity
VI = VSI or 0 V, VCM = 1000 V; see CommonMode Transient Immunity Test Circuit
(1)
at INx
V
25
µA
VSO (1) –
0.1
V
0.1
85
V
100
kV/us
VSI = input side supply; VSO = output side supply
7.16 Supply Current Characteristics Channel Isolator - VIO, VISOIN = 2.5-V
VIO, VISOIN = 2.5 V ±10% GND1 = GNDIO, GND2 = GISOIN (over recommended operating conditions, unless otherwise
specified)
PARAMETER
SUPPLY
CURRENT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IDD_IO
3.5
6
mA
IISOIN
3.5
5
mA
IDD_IO
3.5
6
mA
IISOIN
3.5
5
mA
EN_IO1 = EN_IO2 = VCCI; VI = VCCI (ISOW7721);
VI = 0 V (ISOW7721 with F suffix)
IDD_IO
3.5
6
mA
IISOIN
3.5
5
mA
EN_IO1 = EN_IO2 = VCCI; VI = 0 V (ISOW7721);
VI = VCCI (ISOW7721 with F suffix)
IDD_IO
4.5
7
mA
IISOIN
5
7
mA
IDD_IO
4
6
mA
IISOIN
4
6
mA
IDD_IO
4.3
6.5
mA
IISOIN
4.4
6.1
mA
IDD_IO
7.2
10
mA
IISOIN
7.4
9.7
mA
ISOW7721 Channel Supply Current
Supply current - Disable
Channel Supply current DC signal
EN_IO1 = EN_IO2 = 0 V; VI = VCCI
VI = 0 V (ISOW7721 with F suffix)
(1)
(ISOW7721);
1 Mbps
Channel Supply current AC signal
All channels switching with square
wave clock input; CL = 15 pF
10 Mbps
100 Mbps
(1)
VCCI = VIO or VISOIN
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7.17 Electrical Characteristics Channel Isolator - VIO, VISOIN = 1.8-V
VIO, VISOIN = 1.8 V ±5% GND1 = GNDIO, GND2 = GISOIN (over recommended operating conditions, unless otherwise
specified)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Channel Isolation
VITH
Input pin rising threshold
VITL
Input pin falling threshold
0.3 x VSI
V
VI(HYS)
Input pin threshold hysteresis
(INx)
0.1 x VSI
V
IIL
Low level input current
-25
µA
IIH
0.7 x VSI
VIL = 0 at INx
(1)
High level input current
VIH = VSI
VOH
High level output voltage
IO = –4 mA, see Switching Characteristics
Test Circuit and Voltage Waveforms
VOL
Low level output voltage
IO = 4 mA, see Switching Characteristics Test
Circuit and Voltage Waveforms
CMTI
Common mode transient
immunity
VI = VSI or 0 V, VCM = 1000 V; see CommonMode Transient Immunity Test Circuit
(1)
at INx
V
25
µA
VSO (1) –
0.1
V
0.1
85
V
100
kV/us
VSI = input side supply; VSO = output side supply
7.18 Supply Current Characteristics Channel Isolator - VIO, VISOIN = 1.8-V
VIO, VISOIN = 1.8 V ±5% GND1 = GNDIO, GND2 = GISOIN (over recommended operating conditions, unless otherwise
specified)
PARAMETER
SUPPLY
CURRENT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ISOW7721 Channel Supply Current
Supply current - Disable
Channel Supply current DC signal
EN_IO1 = EN_IO2 = 0 V; VI = VCCI (1) (ISOW7721);
VI = 0 V (ISOW7721 with F suffix)
IDD_IO
3.5
6
mA
IISOIN
3.5
5
mA
EN_IO1 = EN_IO2 = 0 V; VI = 0 V (ISOW7721);
VI = VCCI (ISOW7721 with F suffix)
IDD_IO
3.5
6
mA
IISOIN
3.5
5
mA
EN_IO1 = EN_IO2 = VCCI; VI = VCCI (ISOW7721);
VI = 0 V (ISOW7721 with F suffix)
IDD_IO
3.5
6
mA
IISOIN
3.5
5
mA
EN_IO1 = EN_IO2 = VCCI; VI = 0 V (ISOW7721);
VI = VCCI (ISOW7721 with F suffix)
IDD_IO
4.5
7
mA
IISOIN
5
6
mA
IDD_IO
4
6
mA
IISOIN
3.5
5
mA
IDD_IO
4.3
6.5
mA
IISOIN
4.4
6.1
mA
IDD_IO
6.7
9.1
mA
IISOIN
6.9
8.8
mA
1 Mbps
Channel Supply current AC signal
All channels switching with square
wave clock input; CL = 15 pF
10 Mbps
100 Mbps
(1)
16
VCCI = VIO or VISOIN
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7.19 Switching Characteristics - 5-V Supply
VISOIN = 5 V ±10%, VIO = 5 V ±10%, GND1 = GNDIO, GND2 = GISOIN (over recommended operating conditions unless
otherwise noted)
PARAMETER
tPLH, tPHL
Propagation delay time
PWD
Pulse width distortion(1) |tPHL – tPLH|
TEST CONDITIONS
See Switching Characteristics Test
Circuit and Voltage Waveforms
ENIO_tPLH,
ENIO_tPHL
ENIO propagation delay time (opposite side)
See Enable/Disable Propagation Delay
Time Test Circuit and Waveform
tsk(o)
Channel-to-channel output skew time(2)
Same-direction channels
tsk(pp)
Part-to-part skew time(3)
tr
Output signal rise time
tf
Output signal fall time
MIN
TYP
MAX
UNIT
7.6
10.7
15.7
ns
0.9
5
ns
210
473.8
ns
4
ns
5.5
ns
2.5
3.6
ns
2.4
3.5
ns
tPHZ
Channel disable propagation delay, high-to-high impedance
output
217
286
ns
tPLZ
Channel disable propagation delay, low-to-high impedance
output
217
286
ns
237
333
ns
237
333
ns
Channel enable propagation delay, high impedance-to-low
output for ISOW7721
237
333
ns
Channel enable propagation delay, high impedance-to-low
output for ISOW7721 with F suffix
237
333
ns
0.3
μs
tPZH
tPZL
See Switching Characteristics Test
Circuit and Voltage Waveforms
Channel enable propagation delay, high impedance-to-high
output for ISOW7721
Channel enable propagation delay, high impedance-to-high
output for ISOW7721 with F suffix
See Enable/Disable Propagation Delay
Time Test Circuit and Waveform
tDO
Default output delay time from input power loss
Measured from the time VIO or VISOIN
goes below 1.6 V at 10 mV/ns.
See Default Output Delay Time Test
Circuit and Voltage Waveforms
0.1
tie
Time interval error
216 – 1 PRBS data at 100 Mbps
0.7
(1)
(2)
(3)
ns
Also known as pulse skew.
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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7.20 Switching Characteristics - 3.3-V Supply
VISOIN = 3.3 V ±10%, VIO = 3.3 V ±10%, GND1 = GNDIO, GND2 = GISOIN (over recommended operating conditions unless
otherwise noted)
PARAMETER
tPLH, tPHL
Propagation delay time
PWD
Pulse width distortion(1) |tPHL – tPLH|
TEST CONDITIONS
MIN
6
See Switching Characteristics Test
Circuit and Voltage Waveforms
ENIO_tPLH,
ENIO_tPHL
ENIO propagation delay time (opposite side)
See Enable/Disable Propagation Delay
Time Test Circuit and Waveform
tsk(o)
Channel-to-channel output skew time(2)
Same-direction channels
tsk(pp)
Part-to-part skew time(3)
tr
Output signal rise time
tf
Output signal fall time
TYP
MAX
UNIT
11
16.2
ns
0.6
4.7
ns
220
474
ns
4.1
ns
4.5
ns
1.8
2.7
ns
1.6
2.4
ns
tPHZ
Channel disable propagation delay, high-to-high impedance
output
230
300.4
ns
tPLZ
Channel disable propagation delay, low-to-high impedance
output
230
299.6
ns
226
318.9
ns
226
319.1
ns
Channel enable propagation delay, high impedance-to-low
output for ISOW7721
225
317.9
ns
Channel enable propagation delay, high impedance-to-low
output for ISOW7721 with F suffix
225
317.6
ns
0.1
0.3
μs
tPZH
tPZL
See Switching Characteristics Test
Circuit and Voltage Waveforms
Channel enable propagation delay, high impedance-to-high
output for ISOW7721
Channel enable propagation delay, high impedance-to-high
output for ISOW7721 with F suffix
See Enable/Disable Propagation Delay
Time Test Circuit and Waveform
tDO
Default output delay time from input power loss
Measured from the time VIO or VISOIN
goes below 1.6 V at 10 mV/ns.
See Default Output Delay Time Test
Circuit and Voltage Waveforms
tie
Time interval error
216 – 1 PRBS data at 100 Mbps
(1)
(2)
(3)
18
0.65
ns
Also known as pulse skew.
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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7.21 Switching Characteristics - 2.5-V Supply
VISOIN = 2.5 V ±10%, VIO = 2.5 V ±10%, GND1 = GNDIO, GND2 = GISOIN (over recommended operating conditions unless
otherwise noted)
PARAMETER
tPLH, tPHL
Propagation delay time
PWD
Pulse width distortion(1) |tPHL – tPLH|
TEST CONDITIONS
See Switching Characteristics Test
Circuit and Voltage Waveforms
ENIO_tPLH,
ENIO_tPHL
ENIO propagation delay time (opposite side)
See Enable/Disable Propagation Delay
Time Test Circuit and Waveform
tsk(o)
Channel-to-channel output skew time(2)
Same-direction channels
tsk(pp)
Part-to-part skew time(3)
tr
Output signal rise time
tf
Output signal fall time
MIN
7.5
TYP
MAX
UNIT
12
18
ns
0.36
5.1
ns
225
478
ns
4.1
ns
6
ns
2
3.26
ns
1.8
3.2
ns
tPHZ
Channel disable propagation delay, high-to-high impedance
output
237
326
ns
tPLZ
Channel disable propagation delay, low-to-high impedance
output
236
325
ns
228
360
ns
228
360
ns
Channel enable propagation delay, high impedance-to-low
output for ISOW7721
227
350
ns
Channel enable propagation delay, high impedance-to-low
output for ISOW7721 with F suffix
227
350
ns
0.3
μs
tPZH
tPZL
See Switching Characteristics Test
Circuit and Voltage Waveforms
Channel enable propagation delay, high impedance-to-high
output for ISOW7721
Channel enable propagation delay, high impedance-to-high
output for ISOW7721 with F suffix
See Enable/Disable Propagation Delay
Time Test Circuit and Waveform
tDO
Default output delay time from input power loss
Measured from the time VIO or VISOIN
goes below 1.6 V at 10 mV/ns.
See Default Output Delay Time Test
Circuit and Voltage Waveforms
0.1
tie
Time interval error
216 – 1 PRBS data at 100 Mbps
0.7
(1)
(2)
(3)
ns
Also known as pulse skew.
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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SLLSFP4 – JULY 2022
7.22 Switching Characteristics - 1.8-V Supply
VISOIN = 1.8 V ±5%, VIO = 1.8 V ±5%, GND1 = GNDIO, GND2 = GISOIN (over recommended operating conditions unless
otherwise noted)
PARAMETER
tPLH, tPHL
Propagation delay time
PWD
Pulse width distortion(1) |tPHL – tPLH|
TEST CONDITIONS
See Switching Characteristics Test
Circuit and Voltage Waveforms
ENIO_tPLH,
ENIO_tPHL
ENIO propagation delay time (opposite side)
See Enable/Disable Propagation Delay
Time Test Circuit and Waveform
tsk(o)
Channel-to-channel output skew time(2)
Same-direction channels
tsk(pp)
Part-to-part skew time(3)
tr
Output signal rise time
tf
Output signal fall time
MIN
TYP
MAX
UNIT
7.5
15
21.5
ns
0
5.8
ns
243
475
ns
4.1
ns
8.6
ns
1.9
3
ns
1.8
3
ns
tPHZ
Channel disable propagation delay, high-to-high impedance
output
260
410
ns
tPLZ
Channel disable propagation delay, low-to-high impedance
output
260
406
ns
240
444
ns
240
444
ns
Channel enable propagation delay, high impedance-to-low
output for ISOW7721
237
439
ns
Channel enable propagation delay, high impedance-to-low
output for ISOW7721 with F suffix
237
439
ns
0.3
μs
tPZH
tPZL
See Switching Characteristics Test
Circuit and Voltage Waveforms
Channel enable propagation delay, high impedance-to-high
output for ISOW7721
Channel enable propagation delay, high impedance-to-high
output for ISOW7721 with F suffix
See Enable/Disable Propagation Delay
Time Test Circuit and Waveform
tDO
Default output delay time from input power loss
Measured from the time VIO or VISOIN
goes below 1.6 V at 10 mV/ns.
See Default Output Delay Time Test
Circuit and Voltage Waveforms
0.1
tie
Time interval error
216 – 1 PRBS data at 100 Mbps
0.7
(1)
(2)
(3)
20
ns
Also known as pulse skew.
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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7.23 Insulation Characteristics Curves
550
VDD = VIO = VISOIN = 3.6 V
VDD = VIO = VISOIN = 5.5 V
Safety Limiting Current (mA)
500
450
400
350
300
250
200
150
100
50
0
0
20
40
60
80
100
120
Ambient Temperature (C)
140
160
Figure 7-1. Thermal Derating Curve for Safety
Limiting Current for DFM-20 Package
Figure 7-2. Thermal Derating Curve for Safety
Limiting Power for DFM-20 Package
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7.24 Typical Characteristics
3.4
5.1
VDD = 5 V
VDD = 3.3 V
5.08
3.36
5.06
3.34
5.04
Output Voltage (V)
Output Voltage (V)
3.38
3.32
3.3
3.28
3.26
5
4.98
4.96
3.24
4.94
3.22
4.92
3.2
4.9
0
20
40
60
80
100
Load Current (mA)
VSEL = GND2
TA = 25°C
120
140
0
VISOOUT = 3.3 V
Figure 7-3. Isolated Supply Voltage (VISOOUT) vs
Load Current (IISOOUT)
48
240
45
210
42
180
39
120
90
VDD = 5 V, VISOOUT = 5 V
VDD = 3.3 V, VISOOUT = 3.3 V
VDD = 5 V, VISOOUT = 3.3 V
60
30
20
40
60
80
100
Load Current (mA)
120
600
500
400
300
VDD = 5 V, VISOOUT = 5 V
VDD = 3.3 V, VISOOUT = 3.3 V
VDD = 5 V, VISOOUT = 3.3 V
0
40
60
80
100
Output Load Current (mA)
120
140
30
VDD = 5 V, VISOOUT = 5 V
VDD = 3.3 V, VISOOUT = 3.3 V
VDD = 5 V, VISOOUT = 3.3 V
0
20
40
60
80
100
Load Current (mA)
120
140
Figure 7-6. Efficiency vs Load Current (IVISOOUT)
3.35
3.34
3.33
3.32
3.31
3.3
3.29
3.28
3.27
3.26
3.25
-40
-25
-10
5
VSEL = GND2
TA = 25°C
Figure 7-7. Power Dissipation vs Load Current
(IISOOUT)
22
VISOOUT = 5 V
21
Output Power Supply Voltage, VISOOUT (V)
Power Dissipation (mW)
700
20
TA = 25°C
TA = 25°C
800
0
90 100 110 120
33
24
140
Figure 7-5. Supply Current (IDD) vs Load Current
(IISOOUT)
100
40 50 60 70 80
Load Current (mA)
36
TA = 25°C
200
30
27
0
0
20
Figure 7-4. Isolated Supply Voltage (VISOOUT) vs
Load Current (IISOOUT)
270
150
10
VSEL = VISOOUT
Efficiency (%)
Input Supply Current (mA)
5.02
20
35
50
65
Temperature (C)
VDD = 5 V
80
95
110 125
No VISOOUT Load
Figure 7-8. 3.3-V Isolated Supply Voltage (VISOOUT)
vs Free-Air Temperature
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5.05
340
5.04
320
Short-Circuit Supply Current (mA)
Output Power Supply Voltage, VISOOUT (V)
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5.03
5.02
5.01
5
4.99
4.98
4.97
4.96
4.95
-40
-25
-10
5
20
35
50
65
Temperature (C)
VSEL = VISOOUT
VDD = 5 V
80
95
300
280
260
240
220
200
180
160
110 125
3
No VISOOUT Load
Figure 7-9. 5-V Isolated Supply Voltage (VISOOUT) vs
Free-Air Temperature
3.25
3.5
3.75
4
4.25 4.5 4.75
Input Supply Voltage, VDD (mA)
VSEL = VISOOUT
5
5.25
5.5
VISOOUT = GND2 TA = 25°C = GND1
Figure 7-10. Short-Circuit Supply Current (ICC) vs
Supply Voltage (VCC)
7
11
10
6.5
Supply Current (mA)
8
7
6
5
IIO, VIO = 5 V
IISOIN, VISOIN = 5 V
IIO, VIO = 3.3 V
IISOIN, VISOIN = 3.3 V
4
3
2
0
20
40
60
80
Data Rate (Mbps)
100
CL = 0 pF
5.5
5
4.5
0
20
40
2.75
16
VIO UVLO+
VIO UVLOVISOIN UVLO+
VISOIN UVLOVDD UVLO+
VDD UVLO-
2.25
2
1.75
1.5
100
120
TA = 25°C
Figure 7-12. ISOW7721 Channel Supply Currents
vs Data Rate For CL = 0 pF
17
2.5
60
80
Data Rate (Mbps)
CL = 15 pF
TA = 25°C
3
1.25
-40
IIO, VIO = 5 V
IISOIN, VISOIN = 5 V
IIO, VIO = 3.3 V
IISOIN, VISOIN = 3.3 V
3.5
120
Figure 7-11. ISOW7721 Channel Supply Currens vs
Data Rate For CL = 15pF
Power Supply UVLO Threshold (V)
6
4
Propogation Delay Time (ns)
Supply Current (mA)
9
tPHL,
tPLH,
tPHL,
tPLH,
tPHL,
tPLH,
15
14
VIO
VIO
VIO
VIO
VIO
VIO
=
=
=
=
=
=
5 V, VISOIN = 5 V
5 V, VISOIN = 5 V
5 V, VISOIN = 3.3 V
5 V, VISOIN = 3.3 V
3.3 V, VISOIN = 3.3 V
3.3 V, VISOIN = 3.3 V
13
12
11
10
-25
-10
5
20
35
50
65
Temperature (C)
CL = 0 pF
80
95
110 125
TA = 25°C
Figure 7-13. Power-Supply Undervoltage
Threshold vs Free Air Temperature
9
-40
-25
-10
5
20
35
50
65
Temperature (C)
80
95
110 125
Figure 7-14. Propagation Delay Time vs Free-Air
Temperature
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0.8
Low-Level Output Voltage (V)
High-Level Output Voltage (V)
5
4.5
VSO = 3.3 V
VSO = 5 V
4
3.5
3
2.5
-15
0.6
0.4
0.2
VSO = 3.3 V
VSO = 5 V
0
-12
-9
-6
-3
High-Level Output Current (mA)
0
Figure 7-15. High-Level Output Voltage vs HighLevel Output Current
VDD = 5 V VISOOUT = 3.3
V
TA = 25°C
10 uF
Capacitor on
VISOOUT
3
6
9
12
Low-Level Output Current (mA)
15
Figure 7-16. Low-Level Output Voltage vs LowLevel Output Current
VDD = 5 V VISOOUT = 3.3
V
Figure 7-17. 10-mA to 110-mA Load Transient
Response
VDD = 5 V VISOOUT = 3.3
V
0
10 uF
Capacitor on
VISOOUT
Figure 7-18. Soft Start at 10-mA Load For VISOOUT =
3.3 V
VDD = 5 V VISOOUT = 3.3
V
10 uF
Capacitor on
VISOOUT
Figure 7-19. Soft Start at 50-mA Load For VISOOUT = Figure 7-20. Soft Start at 110-mA Load For VISOOUT
= 3.3 V
3.3 V
24
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VDD = 5 V VISOOUT = 5 V
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VDD = 5 V VISOOUT = 5 V
10 uF
Capacitor on
VISOOUT
10 uF
Capacitor on
VISOOUT
Figure 7-21. Soft Start at 10-mA Load For VISOOUT = Figure 7-22. Soft Start at 50-mA Load For VISOOUT =
5V
5V
VDD = 5 V VISOOUT = 5 V
VDD = 3.3 V VISOOUT = 3.3
V
10 uF
Capacitor on
VISOOUT
Figure 7-23. Soft Start at 110-mA Load For VISOOUT
=5V
VDD = 5 V VISOOUT = 5 V
10 uF
Capacitor on
VISOOUT
Figure 7-24. VISOOUT Ripple Voltage at 3.3 V with 10
uF Capacitor and 60 mA load
VDD = 3.3 V VISOOUT = 3.3
V
Figure 7-25. VISOOUT Ripple Voltage at 5 V with 10
uF Capacitor and 110 mA load
10 uF
Capacitor on
VISOOUT
100 uF
Capacitor on
VISOOUT
Figure 7-26. VISOOUT Ripple Voltage at 3.3 V with
100 uF Capacitor and 60 mA load
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70
VDD = 5 V, VISOOUT = 5 V, 110 mA load
VDD = 5 V, VISOOUT = 3.3 V, 140 mA load
VDD = 3.3 V, VISOOUT = 3.3 V, 60 mA load
VISOOUT Voltage Ripple (V)
60
50
40
30
20
10
VDD = 5 V VISOOUT = 5 V
100 uF
Capacitor on
VISOOUT
0
10
Figure 7-27. VISOOUT Ripple Voltage at 5 V with 100
uF Capacitor and 110 mA load
26
20
30
40
50
60
70
VISOOUT Capacitor (F)
80
90
100
TA = 25°C
Figure 7-28. VISOOUT Ripple Voltage vs Load
Capacitor
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8 Parameter Measurement Information
In the below images, VCCI and VCCO refers to the power supplies VIO and VISOIN, respectively.
Isolation Barrier
IN
Input Generator
(See Note A)
VI
VCCI
VI
OUT
50%
50%
0V
tPLH
VO
50
tPHL
CL
See Note B
VOH
90%
50%
VO
50%
10%
VOL
tf
tr
Copyright © 2016, Texas Instruments Incorporated
A.
B.
CL = 15 pF and The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns,
tf ≤ 3ns, ZO = 50 Ω. At the input, 50 Ω resistor is required to terminate Input Generator signal. It is not needed in actual application.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 8-1. Switching Characteristics Test Circuit and Voltage Waveforms
VCC1
Isolation Barrier
0 V or 3 V
IN
0V
tPZH
VO
OUT
VOH
50%
VO
EN
RL = 1 k
Input
Generator
(See Note A)
±1%
0.5 V
0V
tPHZ
CL
See Note B
VI
VCC / 2
VCC / 2
VI
tPZL
tPLZ
VOH
50
VO
0.5 V
50%
VOL
A.
B.
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3ns, ZO
= 50 Ω. At the input, 50 Ω resistor is required to terminate Input Generator signal. It is not needed in actual application.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 8-2. Enable/Disable Propagation Delay Time Test Circuit and Waveform
VCCI
See Note B
IN = 0 V (Devices without suffix F)
IN = VCC (Devices with suffix F)
IN
Isolation Barrier
VCCI
VI
1.4 V
0V
OUT
VO
CL
See Note A
tDO
VO
default high
VOH
50%
VOL
default low
Note
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
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Note
B. Power Supply Ramp Rate = 10 mV/ns.
Figure 8-3. Default Output Delay Time Test Circuit and Voltage Waveforms
5V
Connected to Visoout on PCB
VISOIN
VIO
1uF
10uF
0.01uF
0.01uF
1uF
10uF
VIO
GND1
OUT
IN
5V
GND1
VDD
CL
10uF
1uF
0.01uF
GND2
GND1
+
–
VCM
Note
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Note
Pass-fail criteria: Outputs must remain stable.
Figure 8-4. Common-Mode Transient Immunity Test Circuit
28
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9 Detailed Description
9.1 Overview
The ISOW7721 family of devices have a low-noise, low-emissions isolated DC-DC converter, and two highspeed isolated data channels. Section 9.2 shows the functional block diagram of the ISOW7721 device.
9.1.1 Power Isolation
The integrated isolated DC-DC converter uses advanced circuit and on-chip layout techniques to reduce
radiated emissions and achieve up to 46% typical efficiency. The integrated transformer uses thin film polymer
as the insulation barrier. Output voltage of power converter can be controlled to 3.3 V or 5 V using VSEL pin. The
DC-DC converter can be switched off using the EN pin to save power. The output voltage, VISOOUT , is monitored
and feedback information is conveyed to the primary side through a dedicated isolation channel. VISOOUT needs
to be connected to VISOIN to ensure the feedback channel is properly powered to regulate the DC-DC converter.
This can be achieved by connecting the pins directly or through an LDO that remains powered up at all times.
A ferrite bead is recommended between VISOOUT and VISOIN to further reduce emissions. See the Section 10.2
section. The duty cycle of the primary switching stage is adjusted accordingly. The fast feedback control loop
of the power converter ensures low overshoots and undershoots during load transients. Undervoltage lockout
(UVLO) with hysteresis is integrated on the VIO, V DD and VISOIN supplies which ensures robust fails-safe system
performance under noisy conditions. An integrated soft-start mechanism ensures controlled inrush current and
avoids any overshoot on the output during power up.
9.1.2 Signal Isolation
The integrated signal isolation channels employ an ON-OFF keying (OOK) modulation scheme to transmit the
digital data across a silicon-dioxide based isolation barrier. The transmitter sends a high frequency carrier
across the barrier to represent one state and sends no signal to represent the other state. The receiver
demodulates the signal after signal conditioning and produces the output through a buffer stage. The signalisolation channels incorporate advanced circuit techniques to maximize the CMTI performance and minimize the
radiated emissions from the high frequency carrier and IO buffer switching. Figure 9-1 shows a functional block
diagram of a typical signal isolation channel. In order to keep any noise coupling from the power converter away
from the signal path, power supplies on side 1 for the power converter (VDD) and the signal path(VIO) are kept
separate. Similarly on side 2, the power converter output (VISOOUT) needs to be connected to VISOIN externally
on PCB. Emissions can be further improved by placing a ferrite bead between VISOOUT and VISOIN as well as
between the GND2 pins. For more details, refer to the Layout Guidelines section.
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9.2 Functional Block Diagram
VIO
VISOIN
Isolation Barrier
I/O Channels
Data Channels
(2)
Data Channels
(2)
FB Channel (Rx)
FB Channel (Tx)
VISOOUT and
VISOIN needs to
be directly
connected or
through an
LDO on board
that is always
powered.
I/O Channels
FB Controller
Vref
Thermal
Shutdown,
UVLO, Soft-start
UVLO, Soft-start
Power
Controller
Transformer
Driver
Rectifier
VISOOUT
LF
CC
VDD
Transformer
Figure 9-1. Block Diagram
Receiver
Transmitter
TX IN
OOK
Modulation
TX Signal
Conditioning
Oscillator
SiO2 based
Capacitive
Isolation
Barrier
RX Signal
Conditioning
Envelope
Detection
RX OUT
Emissions
Reduction
Techniques
Figure 9-2. Conceptual Block Diagram of a Capacitive Data Channel
30
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Figure 9-3 shows a conceptual detail of how the OOK scheme works.
TX IN
Carrier signal through
isolation barrier
RX OUT
Figure 9-3. On-Off Keying (OOK) Based Modulation Scheme
9.3 Feature Description
Device Features shows an overview of the device features.
Table 9-1. Device Features
PART NUMBER(1)
ISOW7721
ISOW7721 with F suffix
(1)
(2)
CHANNEL DIRECTION
MAXIMUM DATA RATE
1 forward, 1 reverse
100 Mbps
DEFAULT OUTPUT
STATE
RATED ISOLATION(2)
High
5 kVRMS / 7071 VPK
Low
The F suffix is part of the orderable part number. See the Section 14 section for the full orderable part number.
For detailed isolation ratings, see the Section 7.7 table.
9.3.1 Electromagnetic Compatibility (EMC) Considerations
The ISOW7721 uses emissions reduction schemes for the internal oscillator and advanced internal layout
scheme to minimize radiated emissions at the system level.
Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge
(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances
are regulated by international standards such as IEC 61000-4-x and CISPR 32. Although system-level
performance and reliability depends, to a large extent, on the application board design and layout, the
ISOW7721 incorporates many chip-level design improvements for overall system robustness. Some of these
improvements include:
• Robust ESD protection cells for input and output signal pins and inter-chip bond pads.
• Low-resistance connectivity of ESD cells to supply and ground pins.
• Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.
• Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance
path.
• PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic
SCRs.
• Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.
• Power path and signal path separated to minimize internal high frequency coupling and an external filtering
knob using ferrite beads available to further reduce emissions
• Reduced power converter switching frequency to 25 MHz to reduce strength of high frequency components in
emissions spectrum
9.3.2 Power-Up and Power-Down Behavior
The ISOW7721 has built-in UVLO on the VIO, VDD, and VISOIN supplies with positive-going and negative-going
thresholds and hysteresis. Both the power converter supply (VDD) and logic supply (VIO) need to be present
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for the device to work. If either of them is below its UVLO, both the signal path and the power converter are
disabled.
When the VDD voltage crosses the positive-going UVLO threshold during power-up, the DC-DC converter
initializes and the power converter duty cycle is increased in a controlled manner. This soft-start scheme limits
primary peak currents drawn from the VDD supply and charges the VISOOUT output in a controlled manner,
avoiding overshoots. Outputs of the isolated data channels are in an indeterminate state until the VIO and VDD
voltage crosses the positive-going UVLO threshold. When the UVLO positive-going threshold is crossed on the
secondary side VISOOUT pin, the feedback data channel starts providing feedback to the primary controller. The
regulation loop takes over and the isolated data channels go to the normal state defined by the respective input
channels or their default states. Design should consider a sufficient time margin (typically 10 ms with 10-µF load
capacitance) to allow this power up sequence before valid data channels are accounted for system functionality.
When either VIO or VDD power is lost, the primary side DC-DC controller turns off when the UVLO lower
threshold is reached. The VISOOUT capacitor then discharges depending on the external load. The isolated data
outputs on the VISOIN side are returned to the default state for the brief time that the VISOIN voltage takes to
discharge to zero.
9.3.3 Protection Features
The ISOW7721 has multiple protection features to create a robust system level solution.
•
•
•
•
An over-voltage clamp feature is present on VISOOUT which will clamp the voltage at 6 V, when VSEL =
VISOOUT, or 4 V, when VSEL = GND2, if there is an increase in voltage seen on VISOOUT. It is recommended
that the VISOOUT stays lower than the over-clamp voltage for device reliability.
Over-voltage lock out on VDD will occur when a voltage higher than 7 V is seen. The device will go into a low
power state and the EN pin will go low.
The device is protected against output overload and short circuit. Output voltage starts dropping when the
power converter is not able to deliver the current demanded during overload conditions. For a VISOOUT
short-circuit to ground, the duty cycle of the converter is limited to help protect against any damage.
Thermal protection is also integrated to help prevent the device from getting damaged during overload
and short-circuit conditions on the isolated output. Under these conditions, the device temperature starts to
increase. When the temperature goes above 165°C, thermal shutdown activates and the primary controller
turns off which removes the energy supplied to the VISOOUT load, which causes the device to cool off.
When the junction temperature goes below 150°C, the device starts to function normally. If an overload or
output short-circuit condition prevails, this protection cycle is repeated. Care should be taken in the design to
prevent the device junction temperatures from reaching such high values.
9.3.4 Multi-Device Chaining for Increased Power Output
The ISOW7721 supports daisy chaining multiple ISOW7721 devices to achive > 110 mA load as shown in Figure
9-4. The below equation provides an estimate for the required number of ISOW7721 devices to meet a target
load current.
Number of device = ceil
Example:
Target load current − Maxiumum available load current
0.8 Maxiumum available load current
+1
Design a multi-device chaning using ISOW7721 to drive a 680 mA load for VDD = 5 V and VSEL = 5 V.
The Maximum avaialble load current for VDD = 5 V, and VSEL = 5 V is 100 mA from page 1.
Number of device = ceil
680 − 110
0.8 110
+1 =8
From the above calculation, we need 8 ISOW7721 to drive a 680 mA load.
Follow the procedures below to configure multi-device chaining.
1. Set LF to GND1 to make a device as the leader of the daisy chain (only one leader is allowed in a daisy
chain). The CC pin of the leader is configured as an output
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2. Set LF to VDD to make the other device as a follower (may use more than one follower to meet your system
current requirement). The CC pin of the follower is configured as an input.
3. A voltage change on the LF pin requires a power cycling to put the device into the desired role. Please
ensure that all devices are powered during multi-device chaining operation to prevent the VISOOUT pin
of an unpowered device from exposing to an overvoltage condition. An unpowered device can cause the
VSEL to set to GND and thus the maximum rating for its VISOOUT is 4 V. Device damage is possible if this
VISOOUT pin is driven by another 5 V VISOOUT pin for an extensive long time.
4. Connect the CC pin of the leader to the CC pin of the follower (may use more than one follower) and this will
allow the leader to synchronize with the follower.
5. Connect all the VISOOUT pins and VISOIN pins together for the leader and the follower(s).
6. Connect all the GISOUT pins together for the leader and the follower(s).
7. Connect all the VDD pins together for the leader and the follower(s).
8. All the VSEL pins should be set to the same logic state.
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Leader
VIO
1
20
VISOIN
INA
2
19
OUTA
3
18
INB
4
17
EN_IO2
EN
5
GNDIO
6
LF
7
CC
ISOLATION
OUTB
EN_IO1
16
NC
15
GISOIN
14
NC
8
13
VSEL
VDD
9
12
VISOOUT
GND1
10
11
GND2
1
20
VISOIN
2
19
OUTA
OUTB
3
18
INB
EN_IO1
4
17
EN_IO2
EN
5
16
NC
GNDIO
6
15
GISOIN
ISOLATION
VIO
INA
LF
7
14
NC
CC
8
13
VSEL
VDD
9
12
VISOOUT
GND1
10
11
GND2
FB
FB
FB
FB
Follower
Figure 9-4. Multi-Device Chaining
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9.4 Device Functional Modes
Table 9-2 lists the supply configurations for these devices.
Table 9-2. Supply Configuration Function Table
VDD
VIO
VSEL
VISOOUT(2)
< VDD(UVLO+)
>VIO(UVLO+)
X
OFF
OFF
>VDD(UVLO+)
1.7 V, VISOIN > 1.7 V); PD = Powered down
(VIO < 1 V, VISOIN < 1 V); X = Irrelevant; H = High level; L = Low level.
In the default condition, the output is high for the ISOW7721 and low with the F suffix.
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9.4.1 Device I/O Schematics
CC
LF
VDD
VDD
CC
LF
1 kΩ
1 kΩ
LF
600 kΩ
Figure 9-5. Device I/O Schematics
36
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10 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
10.1 Application Information
This device is a high-performance, two channel digital isolator with integrated DC-DC converter. Typically digital
isolators require two power supplies isolated from each other to power up both sides of device. Due to the
integrated DC-DC converter in the device, the isolated supply is generated inside the device that can be used
to power isolated side of the device and peripherals on isolated side, thus saving board space. The device
uses single-ended CMOS-logic switching technology. When designing with digital isolators, keep in mind that
because of the single-ended design structure, digital isolators do not conform to any specific interface standard
and are only intended for isolating single-ended CMOS or TTL digital signal lines. The isolator is typically placed
between the data controller (Microcontroller or UART), and a data converter or a line transceiver, regardless of
the interface type or standard.
The device is suitable for applications that have limited board space and desire more integration. The device
is also suitable for very high voltage applications, where power transformers meeting the required isolation
specifications are bulky and expensive.
10.2 Typical Application
For step-by-step design procedure, circuit schematics, bill of materials, printed circuit board (PCB) files,
simulation results, and test results, refer to TI Design TIDA-01333, Eight-Channel, Isolated, High-Voltage
Analog Input Module With ISOW7841 Reference Design.
Figure 10-1 shows the typical schematic for SPI isolation.
Reference
F
F
10 nF
3.3 VIN
10 nF
VIO
VISOIN
INA
OUTA
F
F
3.3VOUT
DVCC
REF
RX
ADC
MCU
RX
OUTB
TX
INB
AGND
ISOW7721
GNDIO
GISOIN
DVSS
F
10 nF
GND1
VISOOU T
GND2
HV+ to
Chassi s
HV- to Chassis
DGND
at 1 00 MHz
(BL M15 EX33 1SN1D)
VSE L
VDD
F
DVDD
AV DD
TX
IN OUT
10 nF
F
F
at 1 00 MHz
(BL M15 EX33 1SN1D)
GND
Optiona l L DO
Figure 10-1. Isolated Power and UART for ADC Sensing Application with ISOW7721
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10.2.1 Design Requirements
To design with this device, use the parameters listed in Table 10-1.
Table 10-1. Design Parameters
PARAMETER
VALUE
VDD input voltage
3 V to 5.5 V
VIO input voltage
1.71 V to 5.5 V
VISOIN input voltage
1.71 V to 5.5 V
VDD decoupling capacitors
10 µF + 1 µF + 0.01 µF + optional additional capacitance
VIO decoupling capacitors
0.1 µF + optional additional capacitance
VISOIN decoupling capacitors
0.1 µF + optional additional capacitance
VISOOUT decoupling capacitors
10 µF + 1 µF + 0.01 µF + optional additional capacitance
VISOOUT to VISOIN series inductor
BLM15ELX9331SN1D
GND2 to GISOIN series inductor
BLM15ELX9331SN1D
VIO series inductor
BLM15ELX9331SN1D
VDD series inductor
BLM15ELX9331SN1D
Because of very-high current flowing through the ISOW7721 VDD and VISOOUT supplies, higher decoupling
capacitors typically provide better noise and ripple performance. Although a 10-µF capacitor is adequate, higher
decoupling capacitors (such as 47 µF) on both the VDD and VISOOUT pins to the respective grounds are strongly
recommended to achieve the best performance.
10.2.2 Detailed Design Procedure
The devices requires specific placement of external bypass capacitors and ferrite beads to operate at high
performance. These low-ESR ceramic bypass capacitors must be placed as close to the chip pads as possible.
10 μF
10 μF
VIO
330 Ω at 100 MHz
(BLM15EX331SN1D)
1 μF
1 μF
10 nF
10 nF
VISOIN
1
20
INA
2
19
OUTA
OUTB
3
18
INB
4
17
5
16
6
15
LF
7
14
CC
8
13
9
12
10
11
EN_IO1
VIO
EN
GNDIO
330 Ω at 100 MHz
(BLM15EX331SN1D)
VDD
10 μF
1 μF
10 nF
GND1
EN_IO2
VISOIN
NC
GISOIN
NC
VSEL
VISOOUT
330 Ω at 100 MHz
(BLM15EX331SN1D)
VISOOUT
VISOIN
GND2 10 nF
330 Ω at 100 MHz
(BLM15EX331SN1D)
1 μF 10 μF
330 Ω at 100 MHz
(BLM15EX331SN1D)
Figure 10-2. Typical ISOW7721Circuit Hook-Up
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10.2.3 Application Curve
VDD = 5 V
VISOOUT = 5 V
IISOOUT = 100 mA
Figure 10-3. ISOW77xx Radiated Emissions versus CISPR32B line (Blue)
10.2.4 Insulation Lifetime
Insulation lifetime projection data is collected by using industry-standard Time Dependent Dielectric Breakdown
(TDDB) test method. In this test, all pins on each side of the barrier are tied together creating a two-terminal
device and high voltage applied between the two sides; See Figure 10-4 for TDDB test setup. The insulation
breakdown data is collected at various high voltages switching at 60 Hz over temperature. For reinforced
insulation, VDE standard requires the use of TDDB projection line with failure rate of less than 1 part per million
(ppm). Even though the expected minimum insulation lifetime is 20 years at the specified working isolation
voltage, VDE reinforced certification requires additional safety margin of 20% for working voltage and 87.5% for
lifetime which translates into minimum required insulation lifetime of 37.5 years at a working voltage that's 20%
higher than the specified value.
Figure 10-5 shows the intrinsic capability of the isolation barrier to withstand high voltage stress over its lifetime.
Based on the TDDB data, the intrinsic capability of the insulation is 1000 VRMS with a lifetime of 1184 years.
A
Vcc 1
Vcc 2
Time Counter
> 1 mA
DUT
GND 1
GND 2
VS
Oven at 150 °C
Figure 10-4. Test Setup for Insulation Lifetime Measurement
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Figure 10-5. Insulation Lifetime Projection Data
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11 Power Supply Recommendations
To help make sure that operation is reliable at data rates and supply voltages, adequate decoupling capacitors
must be located as close to supply pins as possible. VISOOUT needs to be connected to VISOIN to ensure the
feedback channel is properly powered to regulate the DC-DC converter. If VISOOUT and VISOIN are not connected,
the DC-DC converter will run open loop and the VISOOUT voltage will drift until the over-voltage clamp clamps at 6
V. There are two ways to connect VISOOUTand VISOIN:
1) Connect VISOOUT and VISOIN directly with a ferrite bead. A ferrite bead is recommended between VISOOUTand
VISOIN to further reduce emissions.
2) Connect VISOOUT and VISOIN with a ferrite bead through an LDO that remains powered up at all times. If the
LDO has an EN pin then keep the EN high at all times.
The input supply (VIO and VDD) must have an appropriate current rating to support output load and switching at
the maximum data rate required by the end application. For more information, refer to the Section 10.2 section.
For an output load current of 110 mA, it is recommended to have >600 mA of input current limit and for lower
output load currents, the input current limit can be proportionally lower.
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12 Layout
12.1 Layout Guidelines
A low cost two layer PCB should be sufficient to achieve good EMC performance:
•
•
•
•
Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/in2.
Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system
to the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping.
Also the power and ground plane of each power system can be placed closer together, thus increasing the
high-frequency bypass capacitance significantly.
Because the device has no thermal pad to dissipate heat, the device dissipates heat through the respective GND
pins. Ensure that enough copper is present on both GND pins to prevent the internal junction temperature of the
device from rising to unacceptable levels.
Figure 12-1 shows the recommended placement and routing of device bypass capacitors. Below guidelines must
be followed to meet application EMC requirements:
•
•
•
•
•
•
High frequency bypass capacitors 10 nF must be placed close to VDD and VISOOUT pins, less than 1 mm
distance away from device pins. This is very essential for optimised radiated emissions performance. Ensure
that these capacitors are 0402 size so that they offer least inductance (ESL).
Bulk capacitors of atleast 10 μF must be placed on power converter input (VDD) and output (VISOOUT) supply
pins.
Traces on VDD and GND1 must be symmetric till bypass capacitors. Similarly traces on VISOOUT and GND2
must be symmetric.
Place two 0402 size Ferrite beads (Part number: BLM15EX331SN1) on VISOOUT and GND2 path so that any
high frequency noise from power converter output sees a high impedance before it goes to other components
on PCB.
Do not have any metal traces or ground pour within 4 mm of power converter output terminals VISOOUT pin12
and GND2 pin11. VSEL pin is also in VISOOUT domain and should be shorted to either pin 11 or pin 12 for
output voltage selection.
Following the layout guidelines of EVM as much as possible is highly recommended for a low radiated
emissions design.
12.1.1 PCB Material
For digital circuit boards operating at less than 150 Mbps, (or rise and fall times greater than 1 ns), and trace
lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper
alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater strength
and stiffness, and the self-extinguishing flammability-characteristics.
42
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12.2 Layout Example
FB
5
Input Supply 1
C
C
C
10 μF
1 μF
10 nF
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