JL156BGA

National Semiconductor is now part of Texas Instruments. Search http://www.ti.com/ for the latest technical information and details on our current products and services. LF156JAN JFET Input Operational Amplifiers General Description Applications This is the first monolithic JFET input operational amplifier to incorporate well matched, high voltage JFETs on the same chip with standard bipolar transistors (BI-FET™ Technology). This amplifier features low input bias and offset currents/low offset voltage and offset voltage drift, coupled with offset adjust which does not degrade drift or common-mode rejection. The device is also designed for high slew rate, wide bandwidth, extremely fast settling time, low voltage and current noise and a low 1/ƒ noise corner. n n n n n n n Features Advantages n Replace expensive hybrid and module FET op amps n Rugged JFETs allow blow-out free handling compared with MOSFET input devices n Excellent for low noise applications using either high or low source impedance — very low 1/f corner n Offset adjust does not degrade drift or common-mode rejection as in most monolithic amplifiers n New output stage allows use of large capacitive loads (5,000 pF) without stability problems n Internal compensation and large differential input voltage capability Precision high speed integrators Fast D/A and A/D converters High impedance buffers Wideband, low noise, low drift amplifiers Logarithmic amplifiers Photocell amplifiers Sample and Hold circuits Common Features n Low input bias current: n Low Input Offset Current: n High input impedance: n Low input noise current: n High common-mode rejection ratio: n Large dc voltage gain: Uncommon Features n Extremely fast settling time to 0.01% n Fast slew rate n Wide gain bandwidth n Low input noise voltage 30pA 3pA 1012Ω 100 dB 106 dB 1.5µs 12V/µs 5MHz 12 Ordering Information NS PART NUMBER SMD PART NUMBER NS PACKAGE NUMBER PACKAGE DISCRIPTION JL156BGA JM38510/11402 H08C 8LD Metal Can JL156SGA JM38510/11402 H08C 8LD Metal Can Connection Diagrams Metal Can Package (H) 20151114 Top View See NS Package Number H08C BI-FET™, BI-FET II™ are trademarks of National Semiconductor Corporation. © 2006 National Semiconductor Corporation DS201511 www.national.com LF156JAN JFET Input Operational Amplifiers March 2006 LF156JAN Simplified Schematic 20151101 *3pF in LF357 series. Detailed Schematic 20151113 *C = 3pF in LF357 series. www.national.com 2 LF156JAN Absolute Maximum Ratings (Note 1) ± 22V ± 40V ± 20V Supply Voltage Differential Input Voltage Input Voltage Range (Note 3) Output Short Circuit Duration (Note 4) Continuous TJMAX 175˚C Power Dissipation at TA = 25˚C (Note 2) Still Air 560 mW 500 LF/Min Air Flow 1200 mW Thermal Resistance θJA Still Air 160˚C/W 400 LF/Min Air Flow 65˚C/W θJC 23˚C/W −65˚C ≤ TA ≤ +150˚C Storage Temperature Range Lead Temperature (Soldering 10 sec.) 300˚C ESD tolerance (Note 5) 1200V Recommended Operating Conditions ± 5 to ± 20 VDC Supply voltage range −55˚C ≤ TA ≤ +125˚C Ambient temperature range Quality Conformance Inspection MIL-STD-883, Method 5005 - Group A Subgroup Description Temp ( C) 1 Static tests at +25 2 Static tests at +125 3 Static tests at -55 4 Dynamic tests at +25 5 Dynamic tests at +125 6 Dynamic tests at -55 7 Functional tests at +25 8A Functional tests at +125 8B Functional tests at -55 9 Switching tests at +25 10 Switching tests at +125 11 Switching tests at -55 12 Settling time at +25 3 www.national.com LF156JAN LF156 Electrical Characteristics DC Parameters The following conditions apply, unless otherwise specified. DC: VCC = ± 20V, VCM = 0V Symbol Parameter Conditions ICC Supply Current +VCC = 15V, -VCC = -15V VIO Input Offset Voltage Notes Input Bias Current Unit Subgroups 7.0 mA 1 6.0 mA 2 11 mA 3 -5.0 5.0 mV 1 -7.0 7.0 mV 2, 3 +VCC = 35V, -VCC = -5V, VCM = -15V -5.0 5.0 mV 1 -7.0 7.0 mV 2, 3 -5.0 5.0 mV 1 -7.0 7.0 mV 2, 3 -5.0 5.0 mV 1 -7.0 7.0 mV 2, 3 +VCC = 5V, -VCC = -35V, VCM = 15V -0.1 3.5 nA 1 -10 60 nA 2 +VCC = 35V, -VCC = -5V, VCM = -15V -0.1 0.1 nA 1 2 +VCC = 5V, -VCC = -25V, VCM = 10V IIO Max +VCC = 5V, -VCC = -35V, VCM = 15V +VCC = 5V, -VCC = -5V ± IIB Min Input Offset Current -10 50 nA -0.1 0.1 nA 1 -10 50 nA 2 -0.1 0.3 nA 1 -10 50 nA 2 -0.02 0.02 nA 1 -20 +20 nA 2 +PSRR Power Supply Rejection Ratio +VCC = 10V, -VCC = -20V 85 dB 1, 2, 3 -PSRR Power Supply Rejection Ratio +VCC = 20V, -VCC = -10V 85 dB 1, 2, 3 CMR Input Voltage Common Mode Rejection VCM = -15V to 15V 85 dB 1, 2, 3 8.0 mV 1, 2, 3 mV 1, 2, 3 mA 1, 2, 3 50 mA 1, 2, 3 VIO Adj(+) Adjustment for Input Offset Voltage VIO Adj(-) Adjustment for Input Offset Voltage -8.0 +IOS Output Short Circuit Current (For Positive Output) +VCC = 15V, -VCC = -15V, t ≤ 25mS -IOS Output Short Circuit Current (For Negative Output) +VCC = 15V, -VCC = -15V, t ≤ 25mS ∆ VIO/∆T Temperature Coefficient of Input Offset Voltage 25˚C ≤ TA ≤ +125˚C (Note 7) -30 30 µV/˚C 2 -55˚C ≤ TA ≤ 25˚C (Note 7) -30 30 µV/˚C 3 (Note 6) 50 V/mV 4 (Note 6) 25 V/mV 5, 6 (Note 6) 50 V/mV 4 (Note 6) 25 V/mV 5, 6 (Note 6) 10 V/mV 4, 5, 6 -50 -AVS Open Loop Voltage Gain (Single Ended) VO = -15V, RL = 2KΩ +AVS Open Loop Voltage Gain (Single Ended) VO = +15V, RL = 2KΩ AVS Open Loop Voltage Gain (Single Ended) VCC = ± 5V, VO = ± 2V, RL = 2KΩ -VOP Output Voltage Swing VCM = 20V, RL = 10KΩ -16 V 4, 5, 6 VCM = 20V, RL = 2KΩ -15 V 4, 5, 6 +VOP Output Voltage Swing www.national.com VCM = -20V, RL = 10KΩ 16 V 4, 5, 6 VCM = -20V, RL = 2KΩ 15 V 4, 5, 6 4 LF156JAN LF156 Electrical Characteristics (Continued) AC Parameters The following conditions apply, unless otherwise specified. AC: VCC = ± 15V, VCM = 0V Symbol Parameter Conditions Notes -SR Slew Rate Fall VI = 5V to -5V, AV = 1 +SR Slew Rate Rise VI = -5V to 5V, AV = 1 TRTR Transient Response Rise Time RL = 2KΩ, CL= 100pF, VI = 50mV, AV = 1 TROS Transient Response Overshoot NIBB Min Max Subgroups Unit 7.5 V/µS 7 5 V/µS 8A, 8B 7.5 V/µS 7 5 V/µS 8A, 8B 100 nS 7, 8A, 8B RL = 2KΩ, CL = 100pF, VI = 50mV, AV = 1 40 % 7, 8A, 8B Noise Broad Band BW = 5KHz, VCC = ± 20V 10 µVRMS 7 NIPC Noise Popcorn BW = 5KHz, VCC = ± 20V 40 µVPK 7 tS (+) Settling Time AV = -1 1500 nS 12 tS (-) Settling Time AV = -1 1500 nS 12 Drift Values The following conditions apply, unless otherwise specified. AC: VCC = ± 20V, VCM = 0V Delta calculations performed on JAN S devices at group B, subgroup 5 only Symbol Parameter VIO Input Offset Voltage ± IIB Input Bias Current Conditions Notes Max Unit Subgroups -1.0 1.0 mV 1 -0.05 0.05 nA 1 Min Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate condition for which the device is functional, but do not guarantee specific performance limits . For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax(maximum junction temperature), θJA(package junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature is PD=(TJmax−TA)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower. Note 3: The absolute maximum negative input voltage is equal to the negative power supply voltage. Note 4: Short circuit may be to ground or either supply. Rating applies to +125˚C case temperature or +75˚C ambient temperature. Note 5: Human body model, 100pF discharged through 1.5KΩ. Note 6: Datalog Reading in K = V/mV. Note 7: Calculated parameter. 5 www.national.com LF156JAN Typical DC Performance Characteristics Input Bias Current Input Bias Current 20151138 20151137 Input Bias Current Voltage Swing 20151140 20151139 Supply Current Supply Current 20151142 20151141 www.national.com 6 Negative Current Limit LF156JAN Typical DC Performance Characteristics (Continued) Positive Current Limit 20151143 20151144 Positive Common-Mode Input Voltage Limit Negative Common-Mode Input Voltage Limit 20151145 20151146 Open Loop Voltage Gain Output Voltage Swing 20151148 20151147 7 www.national.com LF156JAN Typical AC Performance Characteristics Gain Bandwidth Normalized Slew Rate 20151150 20151151 Output Impedance Output Impedance 20151153 20151152 LF156 Large Signal Puls Response, AV = +1 LF156 Small Signal Pulse Response, AV = +1 20151109 20151106 www.national.com 8 Inverter Settling Time LF156JAN Typical AC Performance Characteristics (Continued) Open Loop Frequency Response 20151156 20151157 Bode Plot Common-Mode Rejection Ratio 20151159 20151161 Power Supply Rejection Ratio 20151163 9 www.national.com LF156JAN Typical AC Performance Characteristics Undistorted Output Voltage Swing (Continued) Equivalent Input Noise Voltage 20151164 20151165 Equivalent Input Noise Voltage (Expanded Scale) 20151166 www.national.com 10 These are op amps with JFET input devices. These JFETs have large reverse breakdown voltages from gate to source and drain eliminating the need for clamps across the inputs. Therefore large differential input voltages can easily be accommodated without a large increase in input current. The maximum differential input voltage is independent of the supply voltages. However, neither of the input voltages should be allowed to exceed the negative supply as this will cause large currents to flow which can result in a destroyed unit. Exceeding the negative common-mode limit on either input will force the output to a high state, potentially causing a reversal of phase to the output. Exceeding the negative common-mode limit on both inputs will force the amplifier output to a high state. In neither case does a latch occur since raising the input back within the common-mode range again puts the input stage and thus the amplifier in a normal operating mode. Exceeding the positive common-mode limit on a single input will not change the phase of the output however, if both inputs exceed the limit, the output of the amplifier will be forced to a high state. Typical Circuit Connections VOS Adjustment 20151167 These amplifiers will operate with the common-mode input voltage equal to the positive supply. In fact, the commonmode voltage can exceed the positive supply by approximately 100 mV independent of supply voltage and over the full operating temperature range. The positive supply can therefore be used as a reference on an input as, for example, in a supply current monitor and/or limiter. Precautions should be taken to ensure that the power supply for the integrated circuit never becomes reversed in polarity or that the unit is not inadvertently installed backwards in a socket as an unlimited current surge through the resulting forward diode within the IC could cause fusing of the internal conductors and result in a destroyed unit. All of the bias currents in these amplifiers are set by FET current sources. The drain currents for the amplifiers are therefore essentially independent of supply voltage. As with most amplifiers, care should be taken with lead dress, component placement and supply decoupling in order to ensure stability. For example, resistors from the output to an input should be placed with the body close to the input to minimize “pickup” and maximize the frequency of the feedback pole by minimizing the capacitance from the input to ground. A feedback pole is created when the feedback around any amplifier is resistive. The parallel resistance and capacitance from the input of the device (usually the inverting input) to AC ground set the frequency of the pole. In many instances the frequency of this pole is much greater than the expected 3dB frequency of the closed loop gain and consequently there is • VOS is adjusted with a 25k potentiometer • The potentiometer wiper is connected to V+ • For potentiometers with temperature coefficient of 100 ppm/˚C or less the additional drift with adjust is ≈ 0.5µV/ ˚C/mV of adjustment • Typical overall drift: 5µV/˚C ± (0.5µV/˚C/mV of adj.) Driving Capacitive Loads 20151168 * LF156 R = 5k Due to a unique output stage design, these amplifiers have the ability to drive large capacitive loads and still maintain stability. CL(MAX) . 0.01µF. Overshoot ≤ 20% Settling time (ts) . 5µs 11 www.national.com LF156JAN negligible effect on stability margin. However, if the feedback pole is less than approximately six times the expected 3 dB frequency a lead capacitor should be placed from the output to the input of the op amp. The value of the added capacitor should be such that the RC time constant of this capacitor and the resistance it parallels is greater than or equal to the original feedback pole time constant. Application Hints LF156JAN Typical Applications Settling Time Test Circuit 20151116 • Settling time is tested with the LF156 connected as unity gain inverter. • FET used to isolate the probe capacitance • Output = 10V step Large Signal Inverter Output, VOUT (from Settling Time Circuit) LF356 20151118 www.national.com 12 LF156JAN Typical Applications (Continued) Low Drift Adjustable Voltage Reference 20151120 • • • • ∆ VOUT/∆T = ± 0.002%/˚C All resistors and potentiometers should be wire-wound P1: drift adjust P2: VOUT adjust Fast Logarithmic Converter 20151121 • • • • • Dynamic range: 100µA ≤ Ii ≤ 1mA (5 decades), |VO| = 1V/decade Transient response: 3µs for ∆Ii = 1 decade C1, C2, R2, R3: added dynamic compensation VOS adjust the LF156 to minimize quiescent error RT: Tel Labs type Q81 + 0.3%/˚C 13 www.national.com LF156JAN Typical Applications (Continued) Precision Current Monitor 20151131 • VO = 5 R1/R2 (V/mA of IS) • R1, R2, R3: 0.1% resistors 8-Bit D/A Converter with Symmetrical Offset Binary Operation 20151132 • R1, R2 should be matched within ± 0.05% • Full-scale response time: 3µs EO www.national.com B1 B2 B3 B4 B5 B6 B7 B8 Comments +9.920 1 1 1 1 1 1 1 1 +0.040 1 0 0 0 0 0 0 0 (+) Zero-Scale −0.040 0 1 1 1 1 1 1 1 (−) Zero-Scale −9.920 0 0 0 0 0 0 0 0 Negative Full-Scale 14 Positive Full-Scale LF156JAN Typical Applications (Continued) Wide BW Low Noise, Low Drift Amplifier 20151170 • Parasitic input capacitance C1 . 3pF interacts with feedback elements and creates undesirable high frequency pole. To compensate add C2 such that: R2 C2 . R1 C1. Boosting the LF156 with a Current Amplifier 20151173 • • IOUT(MAX).150mA (will drive RL≥ 100Ω) • No additional phase shift added by the current amplifier 15 www.national.com LF156JAN Typical Applications (Continued) 3 Decades VCO 20151124 R1, R4 matched. Linearity 0.1% over 2 decades. Isolating Large Capacitive Loads 20151122 • Overshoot 6% • ts 10µs • When driving large CL, the VOUT slew rate determined by CL and IOUT(MAX): www.national.com 16 LF156JAN Typical Applications (Continued) Low Drift Peak Detector 20151123 • • • • By adding D1 and Rf, VD1=0 during hold mode. Leakage of D2 provided by feedback path through Rf. Leakage of circuit is essentially Ib plus capacitor leakage of Cp. Diode D3 clamps VOUT (A1) to VIN−VD3 to improve speed and to limit reverse bias of D2. Maximum input frequency should be 100 • Use LF155 for j Low IB j Low supply current 19 www.national.com LF156JAN Revision History Date Released 03/10/06 www.national.com Revision A Section Originator New Released, Corporate format. 20 R. Malone Changes New Release, Corporate format 1 MDS data sheet converted into a Corp. data sheet format. Following MDS data sheet will be Archived MJLF156-X, Rev. 0A0. LF156JAN JFET Input Operational Amplifiers Physical Dimensions inches (millimeters) unless otherwise noted Metal Can Package (H) NS Package Number H08C National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. 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