LFC789D25CDE4

  

    

 SLLS565B − MARCH 2003 − REVISED SEPTEMBER 2004 D Two Independent Controllers for D OR PW PACKAGE (TOP VIEW) Regulation of: − Fixed 2.5-V and an Adjustable Output − ±2% (Max) Regulation Across Temperature and Load (1 mA to 3 A) DRV_VADJ SEN_VADJ VREF GND D Adjustable Output Can Be Set Via an External Reference Pin, Allowing for the Creation of a Tracking Regulator 1 8 2 7 3 6 4 5 VCC DRV_V25 SEN_V25 NC NC − No internal connection D Great Design Flexibility With Minimal External Components D Applications: High-Current, Low-Dropout Regulators for: − DDR/RDRAM Memory Termination − Motherboards − Chipset I/O − GTLP Termination description/ordering information The LFC789D25 is a dual linear FET controller that simplifies the design of dual power supplies. The device consists of two independent controllers, each of which drives an external MOSFET to implement a low-dropout regulator. One controller is programmed to regulate a fixed 2.5-V output, while the second controller can be programmed to regulate any desired output voltage via a reference input pin, allowing for the creation of a tracking regulator often needed for termination schemes. And, because heating effects of the external FETs easily can be isolated from the controllers, the controllers can regulate the output voltages to a maximum tolerance of ±2% across temperature and load. The LFC789D25 allows designers a great deal of flexibility in selecting external components and topology to implement their specific power-supply needs. With appropriate heat sinking, the designer can build a regulator with as much current capability as allowed by the external MOSFET and power supply. And, because the dropout of the regulator simply is the product of the RDS(on) of the external power MOSFET and the load current, very low dropout can be achieved via proper selection of the power MOSFET. Packaged in 8-pin SOIC and space-saving TSSOP, the LFC789D25 is characterized for operation from 0°C to 70°C. ORDERING INFORMATION ORDERABLE PART NUMBER PACKAGE† TA SOIC (D) 0°C to 70°C TSSOP (PW) Tube of 75 LFC789D25CD Reel of 2500 LFC789D25CDR Tube of 150 LFC789D25CPW Reel of 2000 LFC789D25CPWR TOP-SIDE MARKING KADAC KADAC † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2004, Texas Instruments Incorporated         !" #$ #     %   &  ## '($ # ) #  "( "# )  "" $ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 
  

    

 SLLS565B − MARCH 2003 − REVISED SEPTEMBER 2004 functional block diagram DRV_VADJ SEN_VADJ VREF + _ 1 8 VCC 2 3 Bandgap Reference + _ 7 6 DRV_V25 SEN_V25 4 kΩ 3.6 kΩ GND 4 5 NC PIN DESCRIPTION PIN PIN NAME PIN FUNCTION 1 DRV_VADJ SEN_VADJ Output of adjustable controller. Drives gate(s) of FET(s) to output user-programmable voltage (VADJ). Input pin used to program VADJ, allowing VADJ to track changes in VREF 4 VREF GND 5 NC No connection 6 Sense Input of 2.5-V controller. Senses changes in 2.5-V supply. 7 SEN_V25 DRV_V25 8 VCC Power supply for device 2 3 2 Sense input of adjustable controller. Senses changes in VADJ. Ground Output of 2.5-V controller. Drives gate(s) of FET(s) to output fixed 2.5 V. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
  

    

 SLLS565B − MARCH 2003 − REVISED SEPTEMBER 2004 VCC (12V) VPWR (3.3V) LFC789D25 1 DRV_VADJ VREF 1.25 V C4 0.1 µF DRV_V25 C3 22 µF 7 VDDQ 2.5 V 2 3 C5 0.1 µF VCC 8 4 C1 100 µF SEN_VADJ SEN_V25 VREF C2 100 µF 6 GND R1† R2† † R1 = R2 = 100 Ω (0.1% matched resistors) Figure 1. Typical Application Circuit for DDR1 − Memory Voltage (VDDQ) and VREF Buffer for DIMMs absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Input voltage range, VREF, SEN_VADJ, SEN_V25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 18 V Package thermal impedance, θJA (see Notes 2 and 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . 149°C/W Operating virtual junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to the network ground terminal. 2. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) − TA)/θJA. Operating at the absolute maximum TJ of 150°C can impact reliability. 3. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions VCC TA MIN MAX Supply voltage 9 16 V Operating free-air temperature 0 70 °C POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT 3 
  

    

 SLLS565B − MARCH 2003 − REVISED SEPTEMBER 2004 electrical characteristics, VCC = 12 V ± 5%, TA = 25°C (unless otherwise noted) PARAMETER I SEN_V TA TEST CONDITIONS MIN VDRV VADJ sense-pin current 25 V25 sense-pin current Full range −500 125 Driver output voltage V25 = 2.5 V IDRV Driver output current IV Pin current, VREF Output regulation (see Figure 1) 4 500 IDRV = 0 VDRV = 4 V, VSEN = 0.8 VOUT (nom) Full range VCC − 3 ICC UNIT Full range 5 VADJ output voltage regulation IOUT = 1 mA to 2 A, VPWR = 3.3 V ±10%, VREF = V25/2 mA −250 −500 Full range 2.45 2.5 2.55 V VREF Full range Full range POST OFFICE BOX 655303 nA 2.5 0.98 × VREF VREF 1.02 × VREF 2 Supply current µA A 10 Full range IOUT = 1 mA to 3 A, VPWR = 3 .3 V ± 10% nA V −20 REF V25 output voltage regulation Supply Full range VCC − 1.5 Driver Reference MAX −20 ADJ Sense I SEN_V TYP • DALLAS, TEXAS 75265 2.5 mA 
  

    

 SLLS565B − MARCH 2003 − REVISED SEPTEMBER 2004 APPLICATION INFORMATION FUNCTIONAL DESCRIPTION A linear voltage regulator can be broken down into four essential building blocks: a pass transistor, a voltage reference, a feedback network, and a control circuit to drive the pass element, based on the comparison between the output voltage (as sampled by the feedback network) and the voltage reference. With the exception of the pass transistor, the -ADJ provides the other three building blocks needed. Thus, with minimal external components and low overall solution cost, a designer can create two independent, tightly regulated output voltages capable of delivering high currents in excess of 3 A (as limited by the external pass transistor). One output is fixed at 2.5 V. The other output can be adjusted to any desired voltage via an externally applied signal to the VREF pin. Because the output of the regulator always tracks any changes to this VREF pin, it is relatively easy to implement a tracking regulator. See the typical application circuit (Figure 1). internal reference The fixed 2.5-V output controller uses an internal temperature-compensated bandgap reference centered at 1.2 V. Its tolerance is designed to be VT for operation. With a separate VCC pin to the controller, the voltage at the gate of the NMOS readily can exceed the voltage at the drain; thus, VGS easily can exceed VDS + VT, allowing the NMOS to operate in the triode region (VDS ≥ VGS − VT). In the triode region, VDS can be very small, thus achieving very low dropout. D The external NMOS selected for the pass transistor has significant impact on the overall characteristics of the regulator, as discussed in the following paragraphs. Maximum output current D A benefit of an external pass element is that the designer can size the NMOS to easily sustain the maximum IOUT expected. This allows great flexibility, along with cost and space savings, because each regulator has its pass element tailored to its individual needs. In addition, using an NMOS pass element allows for smaller size (and subsequently, lower cost) than a PMOS element for the same current-carrying ability. Dropout D Choosing an NMOS with very low RDS(on) characteristics provides the regulator with very low dropout because dropout will be ∼IOUT × RDS(on). This lower dropout also results in better efficiency and lower heat dissipation in the pass element for a given IOUT. Maximum programmable output voltage and NMOS threshold voltage, VT The maximum output voltage that can be regulated by the programmable regulator depends on the device’s power supply (VCC) and threshold voltage (VT) of the NMOS. With the drive voltage tied to the gate and VOUT connected to the source of the NMOS, a minimum VGS = VT must be maintained in order to maintain the n-channel inversion layer. The maximum VOUT is calculated as follows: VOUT = VS = VG − VT D With VCC = 12 V and a corresponding worst-case gate drive voltage of 9 V, the highest achievable VOUT = 9 V − VT. Stability A quality of the old npn regulators was their inherent stability under almost any type of load conditions and output capacitors. An NMOS regulator has the same benefit. Thus, capacitor selection and equivalent-series-resistance (ESR) values are not needed for stability, but still should be chosen properly for best transient response (see below). capacitor selection Cout: Although a minimum capacitance is not needed for stability with an NMOS pass device, higher capacitance values improve transient response. In addition, low-ESR capacitors also help transient response. Tantalum or aluminum electrolytics can be used for bulk capacitances, while ceramic bypass capacitors can be used to decouple high-frequency transients due to their low ESL (equivalent series inductance). Cin: Input capacitors placed at the drain of the NMOS pass transistor (VPWR) help improve the overall transient response by suppressing surges in VPWR during fast load changes. Low-ESR tantalum or aluminum electrolytic capacitors can be used; higher capacitance values improve transient response. A 0.1-µF ceramic capacitor can be placed at the VCC pin of the LFC789D25 to provide bypassing. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
  

    

 SLLS565B − MARCH 2003 − REVISED SEPTEMBER 2004 APPLICATION INFORMATION layout Another benefit of a separate controller and pass element is that the heat dissipated in the external NMOS can be well isolated from the controller, which has very low power dissipation. Both of these factors allow the bandgap reference and control circuitry to operate over a more stable temperature range, resulting in very good accuracy over full-load conditions. The LFC789D25 should be placed as close as possible to the external pass element because short PCB traces allow minimal EMI coupling to both the drive and sense lines. For best accuracy, connect the SEN pins as close to the load as possible, not to the source of the NMOS. Also, place the SEN trace in the same direction and plane as the power trace that connects the source of the NMOS to the load. Also, it is good practice to keep the load current return path as far as possible from the SEN trace. Place the 0.1-µF bypass capacitor as close as possible to the VCC pin and connect it directly to the ground plane. The GND pin of the LFC789D25 should be connected to the ground plane. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) LFC789D25CDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 KADAC (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of