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LM10507
SNVS999 – MAY 2014
LM10507 Triple Buck + LDO Power Management Unit
1 Features
•
1
•
•
•
•
•
Three Highly Efficient Programmable Buck
Regulators
– Integrated FETs with Low RDS-ON
– Bucks Operate with their Phases Shifted to
Reduce the Input Current Ripple and Capacitor
Size
– Programmable Output Voltage via the SPI
Interface
– Over and Under-Voltage-Lockout
– Automatic Internal Soft Start with Power-On
Reset
– Current Overload and Thermal Shutdown
Protection
– PFM Mode for High Efficiency at Light Load
Conditions
Low-Dropout Regulator 2.5 V, 250mA
Hardware ENABLE and PWR_OK Terminal
Fast Start-up for All Voltage Rails in about 3.5ms
to PWR_OK
Fast Turn-off / Active Discharge on Regulator
Outputs
Programmable Buck Regulators:
– Buck 1: 0.9 - 3.4 V; 1.6A
– Buck 2: 0.9 - 3.4 V; 1A
– Buck 3: 0.865 - 1.5 V; 1A
– ±3% Feedback Voltage Accuracy
– Up to 95% efficient Buck Regulators
– 2MHz Switching Frequency for Smaller
Inductor Size
– 2.8 x 2.8 mm, 0.4 mm pitch, 34-bump µSMD
Package
2 Applications
Solid-State Drives
3 Description
The LM10507 is an advanced PMU containing three
configurable, high-efficiency buck regulators for
supplying variable voltages. The device is ideal for
supporting ASIC and SOC designs for Solid-State
and Flash drives.
LM10507 operates cooperatively with ASIC to
optimize the supply voltage for low power conditions
and power saving modes via SPI interface. It also
supports a 2.5 V 250 mA LDO.
Device Information(1)
PART NUMBER
LM10507
PACKAGE
BODY SIZE (NOM)
DSBGA (34)
2.82 mm x 2.82 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
4 Simplified Schematic
Power Supply
3.3 / 5V
(x3)
Cvin
2.2uF
VIN
(x3)
VINB
SW
Cin
4.7uF
Buck (x3)
IO supply
LDO
Vout1
2.2uH
FB
1.75 ± 3.6V
Cinio
2.2uF
Vout2
Cout
22uF
Vout3
Vldo
Cldo
4.7uF
VINIO
DEV_SLP
ENABLE
RESET PWR_OK
(x4)
SPI
LM10507
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM10507
SNVS999 – MAY 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
8
8.1
8.2
8.3
8.4
8.5
8.6
1
1
1
1
2
3
5
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
Register Maps .........................................................
12
12
12
13
18
19
Applications and Implementation ...................... 23
9.1 Application Information............................................ 23
9.2 Typical Application .................................................. 23
Absolute Maximum Ratings ...................................... 5
Handling Ratings ...................................................... 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
General Electrical Characteristics............................. 6
Buck 1 Electrical Characteristics............................... 7
Buck 2 Electrical Characteristics............................... 8
Buck 3 Electrical Characteristics............................... 9
LDO Electrical Characteristics ................................ 10
Typical Characteristics .......................................... 11
10 Power Supply Recommendations ..................... 30
11 Layout................................................................... 31
11.1 Layout Guidelines ................................................. 31
11.2 Layout Example .................................................... 32
12 Device and Documentation Support ................. 33
12.1 Trademarks ........................................................... 33
12.2 Electrostatic Discharge Caution ............................ 33
12.3 Glossary ................................................................ 33
13 Mechanical, Packaging, and Orderable
Information ........................................................... 34
Detailed Description ............................................ 12
5 Revision History
2
DATE
REVISION
NOTES
May 2014
*
Initial release.
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6 Pin Configuration and Functions
34 bump DSBGA with 0.4mm pitch
TOP VIEW
7
GND_B1
GND_B1
6
SW_B1
5
RESET
GND_B3
SW_B1
SW_B3
SW_B3
VIN_B1
VIN_B1
FB_B3
VIN_B3
4
FB_B1
FB_B1
GND
ENABLE
3
VIN
GND
FB_B2
VIN_B2
2
LDO
GND
SW_B2
SW_B2
PWR_
OK
VIN_IO
SPI_
CLK
SPI_DI
SPI_DO
SPI_CS
GND_B2
A
B
C
D
E
F
G
1
GND
GND
DEVSLP
Pin Functions
Pin
I/O
Description
Name
No.
VIN_B1
A/B5
I
Buck Switcher Regulator 1 - Power supply voltage input for power stage PFET, if buck 1 is
not used, tie to ground to reduce leakage.
SW_B1
A/B6
O
Buck Switcher Regulator 1 - Power Switching node, connect to inductor
FB_B1
A/B4
I
Buck Switcher Regulator 1 - Voltage output feedback for Buck Regulator 1
GND_B1
A/B7
G
Buck Switcher Regulator 1 - Power ground for Buck Regulator
VIN_B2
G3
I
Buck Switcher Regulator 2 - Power supply voltage input for power stage PFET, if buck 2 is
not used, tie to ground to reduce leakage.
SW_B2
F/G2
O
Buck Switcher Regulator 2 - Power Switching node, connect to inductor
FB_B2
F3
I
Buck Switcher Regulator 2 - Voltage output feedback for Buck Regulator 2
GND_B2
G1
G
Buck Switcher Regulator 2 - Power ground for Buck Regulator
VIN_B3
G5
I
Buck Switcher Regulator 3 - Power supply voltage input for power stage PFET
SW_B3
F/G6
O
Buck Switcher Regulator 3 - Power Switching node, connect to inductor
FB_B3
F5
I
Buck Switcher Regulator 3 - Voltage output feedback for Buck Regulator 3
GND_B3
G7
G
Buck Switcher Regulator 3 - Power ground for Buck Regulator
VIN
A3
I
Power supply Input Voltage, must be present for device to work
LDO
A2
O
LDO Regulator - LDO regulator output voltage
SPI_CS
F1
I
SPI Interface – chip select
SPI_DI
D1
I
SPI Interface – serial data input
SPI_DO
E1
O
SPI Interface – serial data output
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SNVS999 – MAY 2014
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Pin Functions (continued)
Pin
I/O
Description
Name
No.
SPI_CLK
C1
I
SPI Interface – serial clock input
ENABLE
G4
I
Digital Input Control Signal to Enable/Disable PMIC. Signal Level is related to VIN_IO. This
is an active High pin with an internal pull-down resistor.
GND
F4
I
Digital Input Control Signal – Not Used – Connect to GND.
DEVSLP
E7
I
Digital Input Control Signal for entering Device Sleep Mode – see table 1. This is an active
High pin with an internal pull-down resistor.
RESET
F7
I
Digital Input Control Signal to abort SPI transactions and resets the PMIC to default
Voltages. This is an active Low pin with an internal pull-up resistor.
GND
C7
I
Not Used – Connect to GND.
PWR_OK
A1
O
Digital Output of Power Good signal – all output rails are started.
VIN_IO
B1
P
Supply Voltage for Digital Interface Signals to ASIC like SPI, RESET, DEVSLP, ENABLE,
PWR_OK.
GND
B2
G
Ground. Connect to system Ground.
GND
B3
G
Ground. Connect to system Ground.
GND
D7
G
Ground. Connect to system Ground.
A: Analog Pin D : Digital Pin G: Ground Pin P: Power Pin I: Input Pin O: Output Pin
4
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SNVS999 – MAY 2014
7 Specifications
7.1 Absolute Maximum Ratings (1) (2) (3)
MIN
MAX
UNIT
VIN,
-0.3
6.0
V
VIN_IO, VIN_B1, VIN_B2, VIN_B3, SPI_CS, SPI_DI, SPI_CLK, SPI_DO, ENABLE, RESET, PWR_OK,
DEVSLP
-0.3
VIN
V
150
°C
Junction Temperature (TJ-MAX)
(1)
(2)
(3)
Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is ensured. Operating Ratings do not imply ensured performance limits. For ensured performance limits and
associated test conditions, see the Electrical Characteristics tables.
Internal thermal shutdown protects device from permanent damage. Thermal shutdown engages at TJ = +140°C and disengages at TJ =
+120°C (typ.). Thermal shutdown is ensured by design.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
7.2 Handling Ratings
Tstg
Storage temperature range
V(ESD)
(1)
Electrostatic discharge
MIN
MAX
UNIT
-65
150
°C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
1.0
kV
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions (1) (2)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VIN_B1, VIN_B2_VIN_B3, VIN
3.0
5.5
V
VIN_IO
1.75
3.63, but less than VIN
V
Junction Temperature (TJ)
-30
125
°C
-30
85
°C
0.9
W
Ambient Temperature (TA)
Maximum Continuous Power Dissipation (PD-MAX)
(1)
(2)
(1)
In applications where high power dissipation and/or poor thermal resistance is present the maximum ambient temperature may have to
be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = +125°C),
the maximum power dissipation of the device in the application (PD-MAX), and the junction-to-ambient thermal resistance of the
part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX).
The amount of Absolute Maximum power dissipation allowed for the device depends on the ambient temperature and can be calculated
using the formula: P = (TJ–TA)/θJA, where TJ is the junction temperature, TA is the ambient temperature, and θJA is the junction-toambient thermal resistance. θJA is highly application and board-layout dependent. Internal thermal shutdown circuitry protects the device
from permanent damage (see General Electrical Characteristics)
7.4 Thermal Information
THERMAL METRIC
RθJA
(1)
Junction-to-Ambient Thermal Resistance
(1)
TYP
UNIT
44.5
°C/W
In applications where high power dissipation and/or poor thermal resistance is present the maximum ambient temperature may have to
be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = +125°C),
the maximum power dissipation of the device in the application (PD-MAX), and the junction-to-ambient thermal resistance of the
part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX).
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SNVS999 – MAY 2014
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7.5 General Electrical Characteristics (1) (2) (3)
SYMBOL
IQ(STANDBY)
PARAMETER
Quiescent Supply
Current
TEST CONDITIONS
MIN
DEVSLP=High Only Buck3 is ON
,PFM mode, no load. (4)
TYP
MAX
UNIT
50
150
µA
UNDER/OVERVOLTAGE LOCK OUT
VUVLO_RISING
LM10507-A (4)
VUVLO_FALLING
(4)
VOVLO_RISING
VOVLO_FALLING
2.5
2.8
2.95
2.35
2.5
2.65
LM10507-A (4)
5.7
5.9
LM10507-A (4)
5.6
5.8
V
DIGITAL INTERFACE
VIL
Logic input low
VIH
Logic input high
VOL
Logic output low
VOH
Logic output high
Input current, pindriven
low
IIL
SPI_CS, SPI_DI, SPI_CLK, ENABLE,
RESET, DEVSLP (5) (4)
PWR_OK (at 2mA load), SPI_DO (4)
0.3*VVIN_IO
0.7*VVIN_I0
0.2*VVIN_IO
0.8*VVIN_IO
SPI_CS, SPI_DI, SPI_CLK, ENABLE,
DEVSLP
−2
RESET
−5
µA
IIH
Input current, pindriven
high
SPI_CS, SPI_DI, SPI_CLK, RESET
2
ENABLE, DEVSLP
5
fSPI_MAX
SPI max frequency
(4)
tDEVSLP
tRESET
tENABLE
tCOMP
(1)
(2)
(3)
(4)
(5)
6
10
Minimum pulse width
2
(5)
Minimum pulse width
V
µA
MHz
µs
2
(5)
Minimum pulse width
(5)
5
Transition time of
PWR_OK output (5)
0
µs
1
All limits are ensured by design, test and/or statistical analysis. All electrical characteristics having room-temperature limits are tested
during production with TJ = 25°C. All hot and cold limits are ensured by correlating the electrical characteristics to process and
temperature variations and applying statistical process control.
Capacitors: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics.
Unless otherwise noted, VIN = 5.0V where: VIN = VVIN_B1 = VVIN_B2 = VVIN_B3. Limits apply for TJ = 25°C unless otherwise noted.
Limits apply over the entire operating junction temperature range of −30°C ≤TA = TJ ≤ +85°C.
Specification ensured by design. Not tested during production.
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7.6 Buck 1 Electrical Characteristics (1) (2) (3) (4)
SYMBOL
PARAMETER
IQ
DC Bias Current in VIN
IOUT-MAX
Continuous maximum load
current (6) (7) (8)
Buck 1 enabled, switching in PWM
IPEAK
Peak switching current limit
Buck 1 enabled, switching in PWM (5)
η
Efficiency peak, Buck 1
IOUT = 0.3A, VVIN = 5.0 V
FSW
Switching Frequency (6)
(5)
CIN
Input Capacitor
COUT
L
TEST CONDITIONS
(5)
MAX
UNIT
15
50
µA
1.9
A
2.2
2.8
A
2.3
MHz
90%
1.75
2
4.7
Output Filter Capacitor
(6)
Output Capacitor ESR
(6)
DC Line regulation
TYP
1.6
(6)
Output Filter Inductance
ΔVOUT
MIN
No Load, PFM Mode (5)
0mA ≤ IOUT ≤ IOUT-MAX
10
DC Load regulation, PWM
(6)
100
20
(6)
(6)
10
µF
mΩ
2.2
µH
3.3V ≤ VIN ≤ 5.0V, IOUT = IOUT-MAX
0.5
%/V
VVIN=5 V, 0.1 *IOUT-MAX≤ IOUT ≤ IOUT-
0.3
%/A
MAX
IFB
Feedback pininput bias current
VFB = 1 V (5)
VFB
Feedback accuracy
VFB =1 V (5)
RDS-ON-HS
High Side Switch On Resistance
RDS-ON-LS
Low Side Switch On Resistance
1.2
-3%
5
µA
3%
VIN =5.0 V
135
VIN = 2.6 V
215
VVIN=5.0 V (5)
85
Startup from shutdown, VOUT = 0V, no
load, LC = recommended circuit, using
software enable, to VOUT = 95% of final
value
0.1
ms
Startup from shutdown, VOUT = 0V,
Maximum Load, LC = recommended
circuit, using software enable, to VOUT
= 95% of final value
0.5
ms
mΩ
190
mΩ
STARTUP
TSTART_NoLoad
Internal soft-start (turn on time)
(6)
TSTART_FullLoad
Internal soft-start (turn on time)
(6)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
All limits are ensured by design, test and/or statistical analysis. All electrical characteristics having room-temperature limits are tested
during production with TJ = 25°C. All hot and cold limits are ensured by correlating the electrical characteristics to process and
temperature variations and applying statistical process control.
Capacitors: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics.
BUCK normal operation is ensured if VIN ≥ VOUT+1.0V.
Unless otherwise noted, VIN = 5.0V where: VIN = VVIN_B1 = VVIN_B2 = VVIN_B3. Limits apply for TJ = 25°C unless otherwise noted.
Limits apply over the entire operating junction temperature range of −30°C ≤TA = TJ ≤ +85°C.
Specification ensured by design. Not tested during production.
In applications where high power dissipation and/or poor thermal resistance is present the maximum ambient temperature may have to
be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = +125°C),
the maximum power dissipation of the device in the application (PD-MAX), and the junction-to-ambient thermal resistance of the
part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX).
The amount of Absolute Maximum power dissipation allowed for the device depends on the ambient temperature and can be calculated
using the formula: P = (TJ–TA)/θJA, where TJ is the junction temperature, TA is the ambient temperature, and θJA is the junction-toambient thermal resistance. θJA is highly application and board-layout dependent. Internal thermal shutdown circuitry protects the device
from permanent damage (see General Electrical Characteristics)
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7.7 Buck 2 Electrical Characteristics (1) (2) (3) (4)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
No Load, PFM Mode (5)
IQ
DC Bias Current in VIN
IOUT -MAX
Continuous maximum load
current (6) (7) (8)
Buck 1 enabled, switching in PWM
IPEAK
Peak switching current limit
Buck 1 enabled, switching in PWM (5)
η
Efficiency peak, Buck 2
IOUT = 0.3A, VVIN = 5.0 V
FSW
Switching Frequency (6)
(5)
CIN
Input Capacitor
(5)
1.35
DC Load regulation
A
1.6
1.85
A
2.3
MHz
90%
1.75
0mA ≤ IOUT ≤IOUT-MAX
Output Filter Inductance
ΔVOUT
µA
2
10
10
(6)
Output Capacitor ESR
DC Line regulation
UNIT
50
4.7
(6)
L
MAX
15
1
(6)
Output Filter Capacitor
COUT
TYP
20
(6)
(6)
(6)
, PWM
100
µF
mΩ
2.2
µH
3.3 V ≤ VIN ≤ 5.0 V, IOUT = IOUT-MAX
0.5
%/V
VIN = 5 V, 0.1*IOUT-MAX≤ IOUT ≤ IOUTMAX
0.3
%/A
(5)
IFB
Feedback pininput bias current
VFB = 1.8 V
VFB
Feedback accuracy
VFB = 2 V (5)
2.2
RDS-ON-HS
High Side Switch On
Resistance
VVIN = 5.0 V
135
VIN = 2.6 V
215
RDS-ON-LS
Low Side Switch On Resistance VVIN = 5.0 V (5)
-3%
5
µA
-3%
85
mΩ
190
STARTUP
TSTART_NoLoad
TSTART_FullLoad
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
8
Internal soft-start (turn on time)
(6)
Internal soft-start (turn on time)
(6)
Startup from shutdown, VOUT = 0V, no
load, LC = recommended circuit, using
software enable, to VOUT = 95% of final
value
0.1
ms
Start up from shutdown, VOUT =0V,
Maximum Load, LC = recommended
circuit, using software enable, to VOUT =
95% of final value
0.5
ms
All limits are ensured by design, test and/or statistical analysis. All electrical characteristics having room-temperature limits are tested
during production with TJ = 25°C. All hot and cold limits are ensured by correlating the electrical characteristics to process and
temperature variations and applying statistical process control.
Capacitors: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics.
BUCK normal operation is ensured if VIN ≥ VOUT+1.0V.
Unless otherwise noted, VIN = 5.0V where: VIN = VVIN_B1 = VVIN_B2 = VVIN_B3. Limits apply for TJ = 25°C unless otherwise noted.
Limits apply over the entire operating junction temperature range of −30°C ≤TA = TJ ≤ +85°C.
Specification ensured by design. Not tested during production.
In applications where high power dissipation and/or poor thermal resistance is present the maximum ambient temperature may have to
be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = +125°C),
the maximum power dissipation of the device in the application (PD-MAX), and the junction-to-ambient thermal resistance of the
part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX).
The amount of Absolute Maximum power dissipation allowed for the device depends on the ambient temperature and can be calculated
using the formula: P = (TJ–TA)/θJA, where TJ is the junction temperature, TA is the ambient temperature, and θJA is the junction-toambient thermal resistance. θJA is highly application and board-layout dependent. Internal thermal shutdown circuitry protects the device
from permanent damage (see General Electrical Characteristics)
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7.8 Buck 3 Electrical Characteristics (1) (2) (3) (4)
SYMBOL
PARAMETER
IQ
DC Bias Current in VIN
TEST CONDITIONS
IOUT-MAX
Continuous maximum load
current (6) (7) (8)
Buck 1 enabled, switching in PWM
IPEAK
Peak switching current limit
Buck 1 enabled, switching in PWM (5)
η
Efficiency peak, Buck 3
FSW
Switching Frequency (6)
CIN
Input Capacitor
COUT
L
(6)
VFB
MAX
UNIT
15
50
µA
1.35
A
1.6
1.85
A
2.3
MHz
90%
1.75
2
4.7
Output Filter Capacitor
(6)
Output Capacitor ESR
(6)
DC Line regulation
TYP
1
IOUT = 0.3A, VVIN=5.0 V
(5)
0mA ≤ IOUT ≤ IOUT-MAX
10
(6)
DC Load regulation, PWM
(6)
10
100
20
(6)
Feedback pininput bias
current
IFB
(5)
(6)
Output Filter Inductance
ΔVOUT
MIN
No Load, PFM Mode (5)
µF
mΩ
2.2
µH
3.3 V ≤ VIN ≤ 5.0 V, IOUT = IOUT-MAX
0.5
%/V
VIN=5 V, 0.1* IOUT-MAX ≤ IOUT≥IOUT-MAX
0.3
%/A
VFB = 1.5 V (5)
1.0
(5)
-3%
5
µA
Feedback accuracy
VFB = 3 V
RDS-ON-HS
High Side Switch On
Resistance
VVIN=5.0 V
-3%
RDS-ON-LS
Low Side Switch On
Resistance
VVIN=5.0 V
TSTART_NoLoad
Internal soft-start (turn on
time) (6)
Startup from shutdown, VOUT = 0 V, no
load, LC = recommended circuit, using
software enable, to VOUT = 95% of final
value
0.1
ms
TSTART_FullLoad
Internal soft-start (turn on
time) (6)
Start up from shutdown, VOUT=0 V,
Maximum Load, LC = recommended
circuit, using software enable, to VOUT =
95% of final value
0.5
ms
135
VIN = 2.6 V
(5)
215
85
mΩ
190
STARTUP
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
All limits are ensured by design, test and/or statistical analysis. All electrical characteristics having room-temperature limits are tested
during production with TJ = 25°C. All hot and cold limits are ensured by correlating the electrical characteristics to process and
temperature variations and applying statistical process control.
Capacitors: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics.
BUCK normal operation is ensured if VIN ≥ VOUT+1.0 V.
Unless otherwise noted, VIN = 5.0V where: VIN = VVIN_B1 = VVIN_B2 = VVIN_B3. Limits apply for TJ = 25°C unless otherwise noted.
Limits apply over the entire operating junction temperature range of −30°C ≤TA = TJ ≤ +85°C.
Specification ensured by design. Not tested during production.
In applications where high power dissipation and/or poor thermal resistance is present the maximum ambient temperature may have to
be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = +125°C),
the maximum power dissipation of the device in the application (PD-MAX), and the junction-to-ambient thermal resistance of the
part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX).
The amount of Absolute Maximum power dissipation allowed for the device depends on the ambient temperature and can be calculated
using the formula: P = (TJ–TA)/θJA, where TJ is the junction temperature, TA is the ambient temperature, and θJA is the junction-toambient thermal resistance. θJA is highly application and board-layout dependent. Internal thermal shutdown circuitry protects the device
from permanent damage (see General Electrical Characteristics)
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7.9 LDO Electrical Characteristics (1) (2) (3)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
VOUT
Output Voltage Accuracy
IOUT = 1mA, VOUT= 2.5 V (4)
−3%
IOUT
Maximum Output Current
(4)
250
ISC
Short-Circuit Current Limit
VDO
(5)
200
Line Regulation
3.3 V ≤ VIN ≤ 5.5 V, IOUT = 1mA
5
Load Regulation
1mA ≤ IOUT ≤ 250 mA, VIN = 3.3 V, 5.0 V
5
IOUT = 250 mA
(6)
PSRR
Power Supply Rejection Ratio
tSTARTUP
Startup Time from Shutdown
(6)
TTRANSIENT
Startup Transient Overshoot
(6)
(2)
(3)
(4)
(5)
(6)
10
VIN = 5.0 V
10
VIN = 3.3 V
35
F = 10 kHz, COUT = 4.7 µF,
IOUT = 20 mA
VIN = 5.0 V
65
VIN = 3.3 V
40
COUT = 4.7 µF IOUT =
250mA
VIN = 5.0 V
45
VIN = 3.3 V
60
10 Hz ≤ f ≤ 100 kHz
Output Noise Voltage
(6)
COUT = 4.7 µF IOUT = 250mA (4)
UNIT
mA
0.5
eN
(1)
MAX
+3%
(4)
Dropout Voltage
ΔVOUT
TYP
A
260
mV
µVRMS
dB
µs
30
mV
All limits are ensured by design, test and/or statistical analysis. All electrical characteristics having room-temperature limits are tested
during production with TJ = 25°C. All hot and cold limits are ensured by correlating the electrical characteristics to process and
temperature variations and applying statistical process control.
Capacitors: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics.
Unless otherwise noted, VIN = 5.0V where: VIN = VVIN_B1 = VVIN_B2 = VVIN_B3. Limits apply for TJ = 25°C unless otherwise noted.
Limits apply over the entire operating junction temperature range of −30°C ≤TA = TJ ≤ +85°C.
Dropout voltage is the voltage difference between the input and the output at which the output voltage drops to 100 mV below its
nominal value.
Specification ensured by design. Not tested during production.
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Output Voltage (1V/DIV)
Output Voltage (1V/DIV)
7.10 Typical Characteristics
VIN 5V/DIV
LDO
Buck 1
Buck 2
DEV_SLP
Buck 1
LDO
Buck 2
Time (1ms/DIV)
Time (500µs/DIV)
C003
C004
Figure 2. Power-up Out of DEVSLP
Output Voltage (0.5V/DIV)
Output Voltage (0.5V/DIV)
Figure 1. Start-up from VIN Enable
LDO
Buck1
Buck2
Buck3
PWR_OK
Buck2
Buck1
Buck3
Time (500µs/DIV)
Time (200µs/DIV)
C012
C013
Output Voltage (1V/DIV)
Figure 3. Start-up Plot
Figure 4. POK Plot
LDO
Buck 1_2
Buck 3_1.5V
DEVSLP
Time (200ms/DIV)
C014
Figure 5. DEVSLP Plot
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8 Detailed Description
8.1 Overview
LM10507 is a highly efficient and integrated Power Management Unit for Systems-on-a-Chip (SoCs), ASICs, and
processors. It operates cooperatively and communicates with processors over an SPI interface with output
Voltage programmability and Standby Mode. The device incorporates three high-efficiency synchronous buck
regulators and one LDO that deliver four output voltages from a single power source. The device also includes a
SPI-programmable Comparator Block that provides an interrupt output signal
GND
GND
GND
GND
GND
LDO
VIN
SPI_DO
SPI_CLK
SPI_DI
SPI_CS
VIN_IO
8.2 Functional Block Diagram
SPI
RESET
DEVSLP
VIN_B2
CONTROL
REGISTERS
LOGIC
LDO
ENABLE
SW_B2
SW2
EN
BUCK2
GND_B2
FB_B2
EN
VIN_B1
SW_B1
SW1
SEQUENCER
TSD
EN
BUCK1
GND_B1
OVLO
UVLO
FB_B1
EN
VIN_B3
SW_B3
SW3
PWR_OK
POWER GOOD STATUS
BUCK3
GND_B3
FB_B3
8.3 Feature Description
8.3.1 Buck Regulators Operation
A buck converter contains a control block, a switching PFET connected between input and output, a synchronous
rectifying NFET connected between the output and ground and a feedback path. The following figure shows the
block diagram of each of the three buck regulators integrated in the device.
12
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Feature Description (continued)
FB
CONTROL
G
CIN
P
SW
D
D
N
S
L
COUT
PGND
VOUT
S
G
VIN
PVIN
U1
LM10507
GND
Figure 6. Buck Functional Diagram
During the first portion of each switching cycle, the control block turns on the internal PFET switch. This allows
current to flow from the input through the inductor to the output filter capacitor and load. The inductor limits the
current to a ramp with a slope of (VIN – VOUT)/L by storing energy in a magnetic field. During the second portion
of each cycle, the control block turns the PFET switch off, blocking current flow from the input, and then turns the
NFET synchronous rectifier on. The inductor draws current from ground through the NFET to the output filter
capacitor and load, which ramps the inductor current down with a slope of (–VOUT)/L.
The output filter stores charge when the inductor current is high, and releases it when low, smoothing the voltage
across the load. The output voltage is regulated by modulating the PFET switch on time to control the average
current sent to the load. The effect is identical to sending a duty-cycle modulated rectangular wave formed by the
switch and synchronous rectifier at the SW pinto a low-pass filter formed by the inductor and output filter
capacitor. The output voltage is equal to the average voltage at the SW terminal.
8.3.2 Buck Regulators Description
The LM10507 incorporates three high-efficiency synchronous switching buck regulators that deliver various
voltages from a single DC input voltage. They include many advanced features to achieve excellent voltage
regulation, high efficiency and fast transient response time. The bucks feature voltage mode architecture with
synchronous rectification.
Each of the switching regulators is specially designed for high-efficiency operation throughout the load range.
With a 2MHz typical switching frequency, the external L- C filter can be small and still provide very low output
voltage ripple. The bucks are internally compensated to be stable with the recommended external inductors and
capacitors as detailed in the application diagram. Synchronous rectification yields high efficiency for low voltage
and high output currents.
All bucks can operate up to a 100% duty cycle allowing for the lowest possible input voltage that still maintains
the regulation of the output. The lowest input to output dropout voltage is achieved by keeping the PMOS switch
on.
Additional features include soft-start, undervoltage lockout, bypass, and current and thermal overload protection.
To reduce the input current ripple, the device employs a control circuit that operates the 3 bucks at 120° phase.
These bucks are nearly identical in performance and mode of operation. They can operate in FPWM (forced
PWM) or automatic mode (PWM/PFM).
8.4 Device Functional Modes
8.4.1 PWM Operation
During PWM operation the converter operates as a voltage-mode controller with input voltage feed forward. This
allows the converter to achieve excellent load and line regulation. The DC gain of the power stage is proportional
to the input voltage. To eliminate this dependence, a feed forward voltage inversely proportional to the input
voltage is introduced.
In Forced PWM Mode the bucks always operate in PWM mode regardless of the output current.
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Device Functional Modes (continued)
In Automatic Mode, if the output current is less than 70 mA (typ.), the bucks automatically transition into PFM
(Pulse Frequency Modulation) operation to reduce the current consumption. At higher than 70 mA (typ.) they
operate in PWM mode. This increases the efficiency at lower output currents.
PWM Mode at
Moderate to
Heavy Loads
VOUT
PFM Mode at Light Load
Load current
increases, draws
Vout towards Low 2
PFM Threshold
High PFM
Threshold
~1.016*VOUT
Low1 PFM
Threshold
~1.008*VOUT
PFET on
until
LPFM
limit
reached
NFET on
drains
inductor
current
until
I inductor=0
High PFM
Voltage
Threshold
reached,
go into
idle mode
Low PFM
Threshold,
turn on
PFET
Load
current
increases
Low 2 PFM
Threshold,
switch back to
PWM mode
Low2 PFM
Threshold
VOUT
Time
Figure 7. PFM vs PWM Operation
8.4.2 PFM Operation (Bucks 1, 2 & 3)
At very light loads, Bucks 1, 2, and Buck 3 enter PFM mode and operate with reduced switching frequency and
supply current to maintain high efficiency.
Bucks 1, 2 and 3 will automatically transition into PFM mode when either of two conditions occurs for a duration
of 32 or more clock cycles:
1. The inductor current becomes discontinuous, or
2. The peak PMOS switch current drops below the IMODE level.
During PFM operation, the converter positions the output voltage slightly higher than the nominal output voltage
during PWM operation, allowing additional headroom for voltage drop during a load transient from light to heavy
load. The PFM comparators sense the output voltage via the feedback pinand control the switching of the output
FETs such that the output voltage ramps between 0.8% and 1.6% (typical) above the nominal PWM output
voltage. If the output voltage is below the ‘high’ PFM comparator threshold, the PMOS power switch is turned on.
It remains on until the output voltage exceeds the ‘high’ PFM threshold or the peak current exceeds the IPFM level
set for PFM mode.
Once the PMOS power switch is turned off, the NMOS power switch is turned on until the inductor current ramps
to zero. When the NMOS zero-current condition is detected, the NMOS power switch is turned off. If the output
voltage is below the ‘high’ PFM comparator threshold (see Figure 7), the PMOS switch is again turned on and
the cycle is repeated until the output reaches the desired level. Once the output reaches the ‘high’ PFM
threshold, the NMOS switch is turned on briefly to ramp the inductor current to zero and then both output
switches are turned off and the part enters an extremely low power mode. Quiescent supply current during this
‘idle’ mode is less than 100 µA, which allows the part to achieve high efficiencies under extremely light load
conditions. When the output drops below the ‘low’ PFM threshold, the cycle repeats to restore the output voltage
to ~1.6% above the nominal PWM output voltage.
If the load current should increase during PFM mode causing the output voltage to fall below the ‘low2’ PFM
threshold, the part will automatically transition into fixed-frequency PWM mode.
14
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Device Functional Modes (continued)
8.4.3 Soft Start
Each of the buck converters has an internal soft-start circuit that limits the in-rush current during startup. This
allows the converters to gradually reach the steady-state operating point, thus reducing startup stresses and
surges. During startup, the switch current limit is increased in steps.
For Bucks 1, 2 and 3 the soft start is implemented by increasing the switch current limit in steps that are
gradually set higher. The startup time depends on the output capacitor size, load current and output voltage.
Typical startup time with the recommended output capacitor of 10 µF is 0.1-0.5ms. It is expected that in the final
application the load current condition will be more likely in the lower load current range during the startup.
8.4.4 Current Limiting
A current limit feature protects the device and any external components during overload conditions. In PWM
mode the current limiting is implemented by using an internal comparator that trips at current levels according to
the buck capability. If the output is shorted to ground the device enters a timed current limit mode where the
NFET is turned on for a longer duration until the inductor current falls below a low threshold, ensuring inductor
current has more time to decay, thereby preventing runaway.
8.4.5 Internal Synchronous Rectification
While in PWM mode, the bucks use an internal NFET as a synchronous rectifier to reduce the rectifier forward
voltage drop and the associated power loss. Synchronous rectification provides a significant improvement in
efficiency whenever the output voltage is relatively low compared to the voltage drop across an ordinary rectifier
diode.
8.4.6 Low Dropout Operation
The device can operate at 100% duty cycle (no switching; PMOS switch completely on) for low dropout support.
In this way the output voltage will be controlled down to the lowest possible input voltage. When the device
operates near 100% duty cycle, output voltage ripple is approximately 25 mV.
The minimum input voltage needed to support the output voltage:
VIN_MIN=VOUT+ILOAD*(RDSON_PFET+RIND)
where
•
•
•
ILOAD : Load Current
RDSON_PFET : Drain to source resistance of PFET (high side)
RIND : Inductor resistance
(1)
8.4.7 Device Operating Modes
8.4.7.1 Startup Sequence
Once VVIN reaches the UVLO threshold and the ENABLE pin= High the LM10507 will start up. There is a fixed
delay of approx. 1 ms before the LDO starts up, followed by Buck1 at 1ms. After a delay of 1msec from Buck1,
Buck2 and Buck3 regulators start together. There is a maximum of 500us soft-start with full load for the Bucks
The Startup Sequence will be:
1. 2.5ms delay after ENABLE.
2. LDO -> 2.5 V,
3. 2ms delay.
4. Buck1 -> 1.8 V, Buck2 -> 1.8 V, Buck3 -> 1.5 V
5. PWR_OK goes high
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Device Functional Modes (continued)
2.5 V
2.8 V
~2.25 V
VIN
Enable
DEVSLP
2.5 V
LDO
2.5 V
Buck1
1.8 V
Buck2
1.8 V
Buck3
1.5 V
PWR_OK
UVLO
2ms 1ms 1ms
UVLO
1ms
STARTUP
STARTUP
Figure 8. Normal Operating Mode
8.4.7.2 Power-On Default and Device Enable
The device will be enabled over the ENABLE terminal, unless outside of operating voltage range. Once VVIN
reaches a minimum required input Voltage and ENABLE=High the power-up sequence will be started. Once the
device is started, the output voltage of the Bucks can be individually disabled by accessing their corresponding
BK1EN, BK2EN register bits (BUCK CONTROL).
8.4.7.3 RESET: Pin Function
The RESET pinis internally pulled up. If the RESET pinis set low, the device will perform a complete reset of all
the registers to their default states. This means that all of the voltage settings on the regulators will go back to
their default state and all Regulators will be turned ON. All Registers will be set back to default instantaneously
but no Start-Up Sequence initiated like it would be with ENABLE terminal.
8.4.7.4 DEVSLP (Device Sleep) Function
The Device can be programmed into Standby mode. There are 2 ways for doing that:
1. DEVSLP terminal
2. Programming via SPI
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Device Functional Modes (continued)
8.4.7.5 DEVSLP Terminal
When the DEVSLP pinis asserted high, the LM10507 will enter Device Sleep Mode. While in Device Sleep Mode,
all Regulator outputs are turned OFF except Buck3. Note: Bucks1,2 and LDO will turn off when the DEVSLP
signal is given. All disabled output Rails will turn off immediately and at the same time (no sequencing). An
internal 22 kΩ (typ.) pull down resistor is attached to the FB pinof Buck 1 and Buck2. Buck 1 and 2 outputs are
pulled to ground level when they are disabled to discharge any residual charge present in the output circuitry.
When Device Sleep transitions to a low, Buck 1, Buck2 and LDO are enabled. Buck 3 will go back to its previous
state
8.4.7.6 Device Sleep (DEVSLP) Programming via SPI
There is no bit which has the same function as DEVSLP terminal. Disabling or programming the Bucks to new
level is the user’s decision based on power consumption and other requirements
The following section describes how to program the chip into Device Sleep Mode corresponding to DEVSLP
pinfunction: Buck 3 must be PFM. To program the LM10507 to Device Sleep Mode via SPI, Buck 1 and Buck2
must be disabled by host device (Register 0x0A bit 0). The LDO must be disabled (Register 0x0B bit 1 and 0).
Then stop the oscillator (Register 0x0E bit 1) To wake LM10507 from Device Sleep Mode, reverse this
sequence.
8.4.7.7 ENABLE, Function
The ENABLE pinis a digital function to control the Start-Up of PMIC. ENABLE has an internal pull-down and is
active High. A pull-down resistor is connected to GND. Transitions of the ENABLE pinto Low during device
operation will disable all regulators and actively force down all the output voltages. Register defaults are restored
while ENABLE is low.
8.4.7.8 Under Voltage Lock Out (UVLO)
The VIN voltage is monitored for a supply under voltage condition, for which the operation of the device cannot
be guaranteed. The part will automatically disable PMIC. To prevent unstable operation, the UVLO has a
hysteresis window of about 300mV. An under voltage lockout (UVLO) will disable all buck outputs, all internal
registers are reset. Once the supply voltage is above the UVLO hysteresis, the device will initiate a power-up
sequence and then enter the active state.
The LDO will remain functional past the UVLO threshold until VVIN reaches approximately 2.25V.
8.4.7.9 Over Voltage Lock Out (OVLO)
The VIN voltage is monitored for a supply over voltage condition, for which the operation of the device cannot be
guaranteed. The purpose of OVLO is to protect the part and all other components connected to the PMU outputs
from any damage and malfunction. Once VVIN rises over about 5.8V all the Bucks and LDO will be disabled
automatically. To prevent unstable operation, the OVLO has a hysteresis window of about 100mV. An over
voltage lockout (OVLO) will force the device into the reset state, all internal registers are reset. Once the supply
voltage goes below the OVLO lower threshold, the device will initiate a power-up sequence and then enter the
active state. Operating maximum input voltage at which parameters are guaranteed is 5.5 V. Absolute maximum
of the device is 6.0 V.
8.4.7.10 PWR_OK – Pin Function
The LM10507 has PWR_OK pinto signal that all output rails are valid. PWR_OK is Low if Buck3 is disabled in
register0x0A. If PWR_OK condition is detected, then the Hardware PWR_OK pinwill be set immediately. There
are four PWR_OK generating conditions, all must be fulfilled :
• Buck 3 output is over flag level (90% when rising,85% when falling).
• Buck 2 output is over flag level (90% when rising,85% when falling) , but not applicable if disabled in register
0x0A.
• Buck 1 output is over flag level (90% when rising,85% when falling) , but not applicable if disabled in register
0x0A
• LDO output is over flag level (90% when rising,85% when falling) , but not applicable if disabled in register
0x0B.
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Device Functional Modes (continued)
NOTE
SPI commanded Disable of any output, followed by a subsequent SPI commanded
ENABLE will cause a temporary logic LOW of the PWR_OK pinuntil that Buck output
voltage has risen back to the 90% flag level.
8.4.7.11 Thermal Shutdown (TSD)
The temperature of the silicon die is monitored for an over-temperature condition, for which the operation of the
device cannot be guaranteed. The part will automatically be disabled if the temperature is too high. The thermal
shutdown (TSD) will force the device into the reset state. In reset, all circuitry is disabled. To prevent unstable
operation, the TSD has a hysteresis window of about 20۫°C. Once the temperature has decreased below the TSD
hysteresis, the device will initiate a power-up sequence and then enter the active state. In the active state, the
part will start up as if for the first time, all registers will be in their default state.
8.5 Programming
8.5.1 SPI Data Interface
The device is programmable via 4-wire SPI Interface. The signals associated with this interface are CS, DI, DO
and CLK. Through this interface, the user can enable/disable the device, program the output voltages of the
individual bucks and of course read the status of Flag registers.
By accessing the registers in the device through this interface, the user can get access and control the operation
of the buck controllers and program the reference voltage of the comparator in the device.
CS
CLK
DI
1
1
2
0
Write
Command
DO
3
A4
7
A3
A2
A1
Register Address
A0
9
0
D7
16
D6
D5
D4
D3
D2
D1
D0
Write Data
0
Figure 9. SPI Interface Write
•
•
18
Data In (DI)
– 1 to 0 Write Command
– A4to A0 Register address to be written
– D7 to D0 Data to be written
Data Out (DO)
– All Os
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Programming (continued)
CS
1
CLK
DI
1
2
1
3
A4
Read
Command
7
A3
A2
A1
9
16
0
A0
Register Address
DO
D7
D6
D5
D4
D3
D2
D1
D0
Read Data
Figure 10. SPI Interface Read
•
•
Data In (DI)
– 1 to 1 Read Command
– A4to A0 Register address to be read
Data Out (DO)
– D7 to D0 Data Read
8.6 Register Maps
8.6.1 Registers Configurable Via The SPI Interface
Addr
Reg Name
Bit
R/W
Default
7
—
—
Description
Notes
Reset default:
0x7F (1.5 V)
0x00
0x07
0x08
Buck 3 Voltage
Buck 1 Voltage
Buck 2 Voltage
6
R/W
1
Buck 3 Voltage Code[6]
5
R/W
1
Buck 3 Voltage Code[5]
4
R/W
1
Buck 3 Voltage Code[4]
3
R/W
1
Buck 3 Voltage Code[3]
2
R/W
1
Buck 3 Voltage Code[2]
1
R/W
1
Buck 3 Voltage Code[1]
0
R/W
1
Buck 3 Voltage Code[0]
7
—
—
—
6
—
—
5
R/W
0
Buck 1 Voltage Code[5]
4
R/W
1
Buck 1 Voltage Code[4]
3
R/W
0
Buck 1 Voltage Code[3]
2
R/W
0
Buck 1 Voltage Code[2]
1
R/W
1
Buck 1 Voltage Code[1]
0
R/W
0
Buck 1 Voltage Code[0]
7
—
—
—
Reset default:
6
—
—
—
0x12 (1.8 V)
5
R/W
0
Buck 2 Voltage Code[5]
4
R/W
1
Buck 2 Voltage Code[4]
3
R/W
0
Buck 2 Voltage Code[3]
2
R/W
0
Buck 2 Voltage Code[2]
1
R/W
1
Buck 2 Voltage Code[1]
0
R/W
0
Buck 2 Voltage Code[0]
Range: 0.865-1.5 V
Reset default:
0x12 (1.8 V)
Range: 0.9-3.4
Range: 0.9-3.4
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Register Maps (continued)
Addr
0x09
0x0A
0x0B
0x0D
0x0E
Reg Name
DevSLP Mode
Voltage for Buck 3
Buck Control
LDO Control
Status
MISC Control
Bit
R/W
Default
7
R/W
—
—
Reset default:
6
R/W
1
Buck 3 Voltage Code[6]
0x7F (1.5 V)
5
R/W
1
Buck 3 Voltage Code[5]
4
R/W
1
Buck 3 Voltage Code[4]
3
R/W
1
Buck 3 Voltage Code[3]
2
R/W
1
Buck 3 Voltage Code[2]
1
R/W
1
Buck 3 Voltage Code[1]
0
R/W
1
Buck 3 Voltage Code[0]
7
R/W
1
BK3EN
6
—
—
—
5
—
—
—
4
R/W
—
BK1FPWM
Buck 1 forced PWM mode when high
3
R/W
0
BK2FPWM
Buck 2 forced PWM mode when high
2
R/W
0
BK3FPWM
Buck 3 forced PWM mode when high
1
R/W
1
BK1EN
Enables Buck 1 0-disabled, 1-enabled
0
R/W
1
BK2EN
Enables Buck 2 0-disabled, 1-enabled
7
—
—
—
6
—
—
—
5
—
—
—
4
—
—
—
3
—
—
—
2
—
—
—
1
—
—
—
0
R/W
1
LDO Enable
7
—
6
—
5
—
4
R
LDO OK
LDO is greater than 90% of target
3
R
Buck 3 OK
Buck 3 is greater than 90% of target
2
R
Buck 2 OK
Buck 2 is greater than 90% of target
1
R
Buck 1 OK
Buck 1 is greater than 90% of target
0
R
PWR_OK
PWR_OK output is high
7
—
6
—
5
—
4
—
3
—
Oscillator Disable
OSC ENABLE/DISABLE
2
—
1
R/W
0
Description
Notes
Enable/Disable Buck 3
0
20
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8.6.1.1 ADDR 0x07 & 0x08: Buck 1 and Buck 2 Voltage Code and VOUT Level Mapping
Voltage Code
Voltage
Voltage Code
Voltage
0x00
0.9
0x20
2.5
0x01
0.95
0x21
2.55
0x02
1
0x22
2.6
0x03
1.05
0x23
2.65
0x04
1.1
0x24
2.7
0x05
1.15
0x25
2.75
0x06
1.2
0x26
2.8
0x07
1.25
0x27
2.85
0x08
1.3
0x28
2.9
0x09
1.35
0x29
2.95
0x0A
1.4
0x2A
3
0x0B
1.45
0x2B
3.05
0x0C
1.5
0x2C
3.1
0x0D
1.55
0x2D
3.15
0x0E
1.6
0x2E
3.2
0x0F
1.65
0x2F
3.25
0x10
1.7
0x30
3.3
0x11
1.75
0x31
3.35
0x12
1.8
0x32
3.4
0x13
1.85
0x33
3.4
0x14
1.9
0x34
3.4
0x15
1.95
0x35
3.4
0x16
2
0x36
3.4
0x17
2.05
0x37
3.4
0x18
2.1
0x38
3.4
0x19
2.15
0x39
3.4
0x1A
2.2
0x3A
3.4
0x1B
2.25
0x3B
3.4
0x1C
2.3
0x3C
3.4
0x1D
2.35
0x3D
3.4
0x1E
2.4
0x3E
3.4
0x1F
2.45
0x3F
3.4
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8.6.1.2 ADDR 0x00 Buck 3 Voltage Code and VOUT Level Mapping
Voltage Code
Voltage
Voltage Code
Voltage
Voltage Code
Voltage
Voltage Code
Voltage
0x00
0.865
0x20
1.025
0x40
1.185
0x60
1.345
0x01
0.87
0x21
1.03
0x41
1.19
0x61
1.35
0x02
0.875
0x22
1.035
0x42
1.195
0x62
1.355
0x03
0.88
0x23
1.04
0x43
1.2
0x63
1.36
0x04
0.885
0x24
1.045
0x44
1.205
0x64
1.365
0x05
0.89
0x25
1.05
0x45
1.21
0x65
1.37
0x06
0.895
0x26
1.055
0x46
1.215
0x66
1.375
0x07
0.9
0x27
1.06
0x47
1.22
0x67
1.38
0x08
0.905
0x28
1.065
0x48
1.225
0x68
1.385
0x09
0.91
0x29
1.07
0x49
1.23
0x69
1.39
0x0A
0.915
0x2A
1.075
0x4A
1.235
0x6A
1.395
0x0B
0.92
0x2B
1.08
0x4B
1.24
0x6B
1.4
0x0C
0.925
0x2C
1.085
0x4C
1.245
0x6C
1.405
0x0D
0.93
0x2D
1.09
0x4D
1.25
0x6D
1.41
0x0E
0.935
0x2E
1.095
0x4E
1.255
0x6E
1.415
0x0F
0.94
0x2F
1.1
0x4F
1.26
0x6F
1.42
0x10
0.945
0x30
1.105
0x50
1.265
0x70
1.425
0x11
0.95
0x31
1.11
0x51
1.27
0x71
1.43
0x12
0.955
0x32
1.115
0x52
1.275
0x72
1.435
0x13
0.96
0x33
1.12
0x53
1.28
0x73
1.44
0x14
0.965
0x34
1.125
0x54
1.285
0x74
1.445
0x15
0.97
0x35
1.13
0x55
1.29
0x75
1.45
0x16
0.975
0x36
1.135
0x56
1.295
0x76
1.455
0x17
0.98
0x37
1.14
0x57
1.3
0x77
1.46
0x18
0.985
0x38
1.145
0x58
1.305
0x78
1.465
22
0x19
0.99
0x39
1.15
0x59
1.31
0x79
1.47
0x1A
0.995
0x3A
1.155
0x5A
1.315
0x7A
1.475
0x1B
1
0x3B
1.16
0x5B
1.32
0x7B
1.48
0x1C
1.005
0x3C
1.165
0x5C
1.325
0x7C
1.485
0x1D
1.01
0x3D
1.17
0x5D
1.33
0x7D
1.49
0x1E
1.015
0x3E
1.175
0x5E
1.335
0x7E
1.495
0x1F
1.02
0x3F
1.18
0x5F
1.34
0x7F
1.5
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9 Applications and Implementation
9.1 Application Information
The LM10507 device provides 4 regulated outputs from 3 step-down switching regulators and one linear
regulator. The regulated outputs are achieved using a minimum of external components. The device outputs are
controlled via an ENABLE input with control for a sleep mode via a further input, DEV_SLP.
A 4-wire SPI interface may be used to reconfigure the device outputs and return an indication of output status. A
separate device output also provides a digital indication of output status. All programmed settings may be
returned to default state via a RESET input.
9.2 Typical Application
ASIC / SoC
RESET
DEVSLP
LM10507
SPI_CS
IO input
supply
SPI
VIN_IO
SP_CLK
C8
2.2 µF
CONTROL LOGIC and REGISTERS
C9
2.2 µF
Power Supply
3.3 / 5 V
System
Control
SPI_DI
SPI_DO
VIN
VIN_B1
C5
4.7 µF
VIN_B2
C6
4.7 µF
ENABLE
PWR_OK
LDO
2.5 V
LDO
SW_B1
BUCK1
C4
4.7 µF
L1
1.8 V
2.2 µH
C1
22 µF
FB_B1
L2
SW_B2
BUCK2
VIN_B3
BUCK3
22 µF
1.5 V
2.2 µH
C3
22 µF
GND
GND
FB_B3
GND
1.8 V
@1A
C2
L3
C7
4.7 µF
1.8 V
@ 1.6 A
1.8 V
2.2 µH
FB_B2
SW_B3
2.5 V
@ 250 mA
1.5 V
@1A
Figure 11. Typical Application Diagram
9.2.1 Design Requirements
Regulator
Default VOUT DEVSLP=Low
Default VOUT DEVSLP=High
VOUT Range
Maximum Output
Current
BUCK 1
1V
OFF
0.9 – 3.4 V; 50mV
steps
1.6 A
BUCK 2
1.8 V
OFF
0.9 – 3.4 V; 50mV
steps
1A
BUCK 3
1.5 V
1.5 V
0.865-1.5 V; 5mV
steps
1A
LDO
2.5 V
OFF
2.5 V
250 mA
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Default voltage values are determined when working in PWM mode. Voltage may be 0.8-1.6% higher when in
PFM mode.
9.2.2 Detailed Design Procedure
9.2.2.1 Input Voltage
VIN, VIN_B1, VIN_B2 and VIN_B3 must all be connected to the same power source.
9.2.2.2 Output Enable
For normal operation it is recommended that the ENABLE input is controlled via an independent voltage applied
to the input.
To enable the device outputs at device power up the ENABLE input may be connected to the supply voltage
either directly or via a divider to the input supply to ensure correct voltage within the specified range. In this case
start up timing may vary from the specified values depending on the supply start up slew rate.
9.2.2.3 Recommendations for Unused Functions and Pins
If any function is not used in the end application then the following recommendations for tying-off the associated
pins on the circuit boards should be used.
FUNCTION
PIN
IF UNUSED
BUCK1
VIN_B1
Connect to VIN
SW_B1
Connect to VIN
FB_B1
Connect to GND
VIN_B2
Connect to VIN
SW_B2
Connect to VIN
FB_B2
Connect to GND
VIN_B3
Connect to VIN
SW_B3
Connect to VIN
FB_B3
Connect to GND
SPI_CS
Connect to VIN_IO
SPI_DI
Connect to GND
SPI_DO
Connect to GND
SPI_CK
Connect to GND
DEVSLP
Connect to GND
RESET
Connect to VIN_IO
PWR_OK
Leave open
BUCK2
BUCK3
SPI
CONTROL and MONITOR
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9.2.2.4 External Components Selection
All three switchers require an input capacitor, and an output inductor-capacitor filter. These components are
critical to the performance of the device. All three switchers are internally compensated and do not require
external components to achieve stable operation. The output voltage of the Bucks can be programmed through
the SPI terminals.
9.2.2.5 Output Inductors and Capacitors Selection
There are several design considerations related to the selection of output inductors and capacitors:
• Load transient response
• Stability
• Efficiency
• Output ripple voltage
• Over current ruggedness
The device has been optimized for use with nominal LC values as shown in the Application Diagram.
9.2.2.6 Inductor Selection
The recommended inductor values are shown in the Application Diagram. It is important to guarantee the
inductor core does not saturate during any foreseeable operational situation. The inductor should be rated to
handle the peak load current plus the ripple current: Care should be taken when reviewing the different saturation
current ratings that are specified by different manufacturers. Saturation current ratings are typically specified at
25C, so ratings at maximum ambient temperature of the application should be requested from the manufacturer.
IL(MAX) = ILOAD(MAX) + û IRIPPLE
= ILOAD(MAX) +
D x (VIN - VOUT)
2 x L x FS
D x (VIN - VOUT)
~ ILOAD(MAX) +
(A typ.),
~
2 x 2.2 x 2.0
D = VOUT , FS = 2 MHz, L = 2.2 µH
VIN
where
•
•
•
•
•
•
•
IL(MAX) : Max inductor Current
ILOAD(MAX): Max load current
IRIPPLE : Peak-to-Peak inductor current
D : Estimated duty factor
VIN : Input voltage
VOUT : Output voltage
FS : Switching frequency, Hertz
(2)
There are two methods to choose the inductor saturation current rating:
9.2.2.7 Recommended Method for Inductor Selection
The best way to guarantee the inductor does not saturate is to choose an inductor that has saturation current
rating greater than the maximum device current limit, as specified in the Electrical Characteristics. In this case
the device will prevent inductor saturation by going into current limit before the saturation level is reached.
9.2.2.8 Alternate Method for Inductor Selection
If the recommended approach cannot be used care must be taken to guarantee that the saturation current is
greater than the peak inductor current:
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ISAT > ILPEAK
IRIPPLE
2
D x (VIN ± VOUT)
IRIPPLE =
L x FS
VOUT
D=
VIN x EFF
ILPEAK = IOUTMAX +
where
•
•
•
•
•
•
•
•
•
•
ISAT : Inductor saturation current at operating temperature
ILPEAK : Peak inductor current during worst case conditions
IOUTMAX : Maximum average inductor current
IRIPPLE : Peak-to-Peak inductor current
VOUT : Output voltage
VIN : Input voltage (VVIN_B1, VVIN_B2, VVIN_B3)
L : Inductor value in Henries at IOUTMAX
FS : Switching frequency, Hertz
D : Estimated duty factor
EFF : Estimated power supply efficiency
(3)
ISAT may not be exceeded during any operation, including transients, startup, high temperature, worst case
conditions, etc.
9.2.2.9 Suggested Inductors and Their Suppliers
The designer should choose the inductors that best match the system requirements. A very wide range of
inductors are available as regarding physical size, height, maximum current (thermally limited, and inductance
loss limited), series resistance, maximum operating frequency, losses, etc. In general, smaller physical size
inductors will have higher series resistance (DCR) and implicitly lower overall efficiency is achieved. Very low
profile inductors may have even higher series resistance. The designer should try to find the best compromise
between system performance and cost.
Table 1. Typical Recommended Inductors
Value
Mfr
Part Number
DCR
Current
Package
2.2µH
Murata
LQH55PN2R2NR0L
31mOhms
2.5A
2220
2.2µH
TDK
NLC565050T-2R2K-PF
60mOhms
1.3A
2220
2.2µH
Murata
LQM2MPN2R2NG0
110mOhms
1.2A
806
2.2uH
Vishay Dale
IFSC1008ABER2R2M01
80mOhms
1.85A
2.5 x 2.0
2.2uH
Taiyo Yuden
MAMK2520T2R2M
117mOhm
1.9A
2.5 x 2.0
9.2.2.10 Output and Input Capacitors Characteristics
Special attention should be paid when selecting these components. As shown in the following figure, the DC bias
of these capacitors can result in a capacitance value that falls below the minimum value given in the
recommended capacitor specifications table. Note that the graph shows the capacitance out of spec for the 0402
case size capacitor at higher bias voltages. It is therefore recommended that the capacitor manufacturers’
specifications for the nominal value capacitor are consulted for all conditions, as some capacitor sizes (e.g. 0402)
may not be suitable in the actual application.
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CAP VALUE (% of NOMINAL 1 PF)
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0603, 10V, X5R
100
80
60
0402, 6.3V, X5R
40
20
0
1.0
2.0
3.0
4.0
5.0
DC BIAS (V)
Figure 12. Typical Variation in Capacitance vs. DC Bias
The ceramic capacitor’s actual capacitance can vary with temperature. The capacitor type X7R, which operates
over a temperature range of −55°C to +125°C, will only vary the capacitance to within ±15%. The capacitor type
X5R has a similar tolerance over a reduced temperature range of −55°C to +85°C. Many large value ceramic
capacitors, larger than 1 μF are manufactured with Z5U or Y5V temperature characteristics. Their capacitance
can drop by more than 50% as the temperature varies from 25°C to 85°C. Therefore X5R or X7R is
recommended over Z5U and Y5V in applications where the ambient temperature will change significantly above
or below 25°C.
Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more
expensive when comparing equivalent capacitance and voltage ratings in the 0.47 μF to 44 μF range. Another
important consideration is that tantalum capacitors have higher ESR values than equivalent size ceramics. This
means that while it may be possible to find a tantalum capacitor with an ESR value within the stable range, it
would have to be larger in capacitance (which means bigger and more costly) than a ceramic capacitor with the
same ESR value. It should also be noted that the ESR of a typical tantalum will increase about 2:1 as the
temperature goes from 25°C down to −40°C, so some guard band must be allowed.
9.2.2.11 Output Capacitor Selection
L
ESR
SW1/2/3
COUT
The output capacitor of a switching converter absorbs the AC ripple current from the inductor and provides the
initial response to a load transient. The ripple voltage at the output of the converter is the product of the ripple
current flowing through the output capacitor and the impedance of the capacitor. The impedance of the capacitor
can be dominated by capacitive, resistive, or inductive elements within the capacitor, depending on the frequency
of the ripple current. Ceramic capacitors have very low ESR and remain capacitive up to high frequencies. Their
inductive component can be usually neglected at the frequency ranges the switcher operates.
VOUT1/2/3
OUTPUT
CAPACITOR
Figure 13. Output Filter
The output-filter capacitor smoothes out the current flow from the inductor to the load and helps maintain a
steady output voltage during transient load changes. It also reduces output voltage ripple. These capacitors must
be selected with sufficient capacitance and low enough ESR to perform these functions.
Note that the output voltage ripple increases with the inductor current ripple and the Equivalent Series
Resistance of the output capacitor (ESRCOUT). Also note that the actual value of the capacitor’s ESRCOUT is
frequency and temperature dependent, as specified by its manufacturer. The ESR should be calculated at the
applicable switching frequency and ambient temperature.
VOUT-RIPPLE-PP =
D x (VIN - VOUT)
V
üIRIPPLE
and D = OUT
where üIRIPPLE =
2 x L x FS
8 x FS x COUT
VIN
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where
•
•
•
VOUT-RIPPLE-PP : estimated output voltage ripple
IRIPPLE : estimated current ripple
D : Estimated duty factor
(4)
Output ripple can be estimated from the vector sum of the reactive (capacitance) voltage component and the real
(ESR) voltage component of the output capacitor:
VOUT-RIPPLE-PP =
2
V
2
ROUT
+V
COUT
VROUT = IRIPPLE x ESRCOUT and VCOUT =
(5)
IRIPPLE
8 x FS x COUT
where
•
•
•
VOUT-RIPPLE-PP : estimated output ripple,
VROUT : estimated real output ripple,
VCOUT : estimated reactive output ripple.
(6)
The device is designed to be used with ceramic capacitors on the outputs of the buck regulators. The
recommended dielectric type of these capacitors is X5R, X7R, or of comparable material to maintain proper
tolerances over voltage and temperature. The recommended value for the output capacitors is 22 μF, 6.3V with
an ESR of 2mΩ or less. The output capacitors need to be mounted as close as possible to the output/ground
terminals of the device.
Table 2. Typical Recommended Output Capacitors
Model
Vendor Type
Vendor
Voltage Rating
Inch (mm) Case Size
08056D226MAT2A
Ceramic, X5R
AVX Corporation
6.3 V
0805, (2012)
C0805L226M9PACTU
Ceramic, X5R
Kemet
6.3 V
0805, (2012)
ECJ-2FB0J226M
Ceramic, X5R
Panasonic – ECG
6.3 V
0805, (2012)
JMK212BJ226MG-T
Ceramic, X5R
Taiyo Yuden
6.3 V
0805, (2012)
C2012X5R0J226M
Ceramic, X5R
TDK Corporation
6.3 V
0805, (2012)
GRM188R60G226MEA0L
Ceramic, X5R
Murata
4.0 V
0603
9.2.2.12 Input Capacitor Selection
There are 3 buck regulators in the LM10507 device. Each of these buck regulators has its own input capacitor
which should be located as close as possible to their corresponding VIN_Bx and GND_Bx terminals, where x
designates the buck 1,2 or 3. The 3 buck regulators operate at 120o out of phase, which means that is they
switch on at equally spaced intervals, in order to reduce the input power rail ripple. It is recommended to connect
all the supply/ground terminals of the buck regulators, VIN_Bx to two solid internal planes located under the
device. In this way, the 3 input capacitors work together and further reduce the input current ripple. A larger
tantalum capacitor can also be located in the proximity of the device.
The input capacitor supplies the AC switching current drawn from the switching action of the internal power
FETs. The input current of a buck converter is discontinuous, so the ripple current supplied by the input capacitor
is large. The input capacitor must be rated to handle both the RMS current and the dissipated power.
The input capacitor must be rated to handle this current:
IRMS_CIN = IOUT
VOUT (VIN - VOUT)
VIN
(7)
The power dissipated in the input capacitor is given by:
PD_CIN = I2RMS_CIN x RESR_CIN
(8)
The device is designed to be used with ceramic capacitors on the inputs of the buck regulators. The
recommended dielectric type of these capacitors is X5R, X7R, or of comparable material to maintain proper
tolerances over voltage and temperature.
The minimum recommended value for the input capacitor is 10 μF with an ESR of 10 mΩ or less. The input
capacitors need to be mounted as close as possible to the power/ground input terminals of the device.
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The input power source supplies the average current continuously. During the PFET switch on-time, however,
the demanded di/dt is higher than can be typically supplied by the input power source. This delta is supplied by
the input capacitor.
A simplified “worst case” assumption is that all of the PFET current is supplied by the input capacitor. This will
result in conservative estimates of input ripple voltage and capacitor RMS current.
Input ripple voltage is estimated as follows:
VPPIN =
IOUT x D
+ IOUT x ESRCIN
CIN x FS
where
•
•
•
•
VPPIN : Estimated peak-to-peak input ripple voltage
IOUT : Output current
CIN : Input capacitor value
ESRIN Input capacitor ESR
(9)
This capacitor is exposed to significant RMS current, so it is important to select a capacitor with an adequate
RMS current rating. Capacitor RMS current estimated as follows:
©
I2RIPPLE
12
§
©
IRMSCIN = D x §I2OUT +
where
•
IRMSCIN Estimated input capacitor RMS current
(10)
100
100
90
90
80
80
70
70
Efficiency (%)
Efficiency (%)
9.2.3 Application Performance Plots
60
50
40
30
60
50
40
30
VIN = 3.3V
VIN = 4.2V
VIN = 5.0V
20
10
0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
Load Current (A)
1.6
VIN = 3.3V
VIN = 4.2V
VIN = 5.0V
20
10
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
Load Current (A)
C009
Figure 14. Efficiency Buck 1
1.0
C010
Figure 15. Efficiency Buck 2
100
VOUT
(100mV/DIV)
90
80
60
50
40
30
VIN = 3.3V
VIN = 4.2V
VIN = 5.0V
20
10
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
Load Current (A)
Figure 16. Efficiency Buck 3
0.8
0.9
Load Current
(500mA/DIV)
Efficiency (%)
70
Time (50µs/DIV)
1.0
C015
C011
Figure 17. Buck 1 Load Transient (0 to 800mA)
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Load Current
(500mA/DIV)
Load Current
(500mA/DIV)
VOUT
(100mV/DIV)
VOUT
(100mV/DIV)
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Time (50µs/DIV)
Time (50µs/DIV)
C005
C017
Figure 19. Buck 2 Load Transient (0 to 500mA)
VOUT
(100mV/DIV)
Load Current
(500mA/DIV)
Load Current
(500mA/DIV)
VOUT
(100mV/DIV)
Figure 18. Buck 1 Load Transient (800mA to 1.6A)
Time (50µs/DIV)
Time (50µs/DIV)
C006
C007
Figure 21. Buck 3 Load Transient (0 to 500mA)
Load Current
(500mA/DIV)
VOUT
(100mV/DIV)
Figure 20. Buck 2 Load Transient (500mA to 1A)
Time (50µs/DIV)
C008
Figure 22. Buck 3 Load Transient (500mA to 1A)
10 Power Supply Recommendations
The devices are designed to operate from an input voltage supply range between 4.5 V and 28 V. This input
supply must be well regulated. If the input supply is located more than a few inches from the GDS9999 device or
GDS9991 converter, additional bulk capacitance may be required in addition to the ceramic bypass capacitors.
An electrolytic capacitor with a value of 47 µF is a typical choice.
30
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11 Layout
11.1 Layout Guidelines
P
CONTROL
SW
D
LOOP1
CIN
L
G
N
COUT
GND
LOOP2
D
VIN
S
VOUT
G
VIN
PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance
of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss
in the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability.
Good layout can be implemented by following a few simple design rules.
S
U1 LM10507
Figure 23. Schematic of LM10507 Highlighting Layout Sensitive Nodes
1. Minimize area of switched current loops. In a buck regulator there are two loops where currents are switched
rapidly. The first loop starts from the CIN input capacitor, to the regulator VIN terminal, to the regulator SW
terminal, to the inductor then out to the output capacitor COUT and load. The second loop starts from the
output capacitor ground, to the regulator GND terminals, to the inductor and then out to COUT and the load
(see Figure 23). To minimize both loop areas the input capacitor should be placed as close as possible to
the VIN terminal. Grounding for both the input and output capacitors should consist of a small localized top
side plane that connects to GND. The inductor should be placed as close as possible to the SW pin and
output capacitor.
2. Minimize the copper area of the switch node. The SW terminals should be directly connected with a trace
that runs on top side directly to the inductor. To minimize IR losses this trace should be as short as possible
and with a sufficient width. However, a trace that is wider than 100 mils will increase the copper area and
cause too much capacitive loading on the SW terminal. The inductors should be placed as close as possible
to the SW terminals to further minimize the copper area of the switch node.
3. Have a single point ground for all device analog grounds. The ground connections for the feedback
components should be connected together then routed to the GND pin of the device. This prevents any
switched or load currents from flowing in the analog ground plane. If not properly handled, poor grounding
can result in degraded load regulation or erratic switching behavior.
4. Minimize trace length to the FB terminal. The feedback trace should be routed away from the SW pin and
inductor to avoid contaminating the feedback signal with switch noise.
5. Make input and output bus connections as wide as possible. This reduces any voltage drops on the input or
output of the converter and can improve efficiency. If voltage accuracy at the load is important make sure
feedback voltage sense is made at the load. Doing so will correct for voltage drops at the load and provide
the best output accuracy.
11.1.1 PCB Layout Thermal Dissipation for DSBGA Package
1. Position ground layer as close as possible to uSMD package. Second PCB layer is usually good option.
LM10507 evaluation board is a good example.
2. Draw power traces as wide as possible. Bumps which pass through high currents should be connected to
wide area this helps the silicon to cool down. Look at LM10507 evaluation board PCB layout for reference
Packaging Information
34 pin uSMD Package, 0.4mm pitch
The dimension for X1, X2 and X3 are as given:
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Layout Guidelines (continued)
X1 = 2.815 mm + / - 0.030 mm
X2 = 2.815 mm + / - 0.030 mm
X3 = 0.600 mm + / - 0.075 mm
11.2 Layout Example
xxx
xxx
xx
xxx
xx
xx
xx
xx
xx xxx
xxx
xxx
Buck2
SPI_DO
xx
xx
xx
xx
xx
VINIO
SPI_DI SPI_CLK
gnd
SW_B2
x
LDO
x
gnd
G1 F1 E1 D1 C1 B1 A1
x
gnd
VIN
G2 F2
B2 A2
G3 F3
B3 A3
G4 F4
B4 A4
G5 F5
B5 A5
G6 F6
B6 A6
x
VIN
G7 F7 E7 D7 C7 B7 A7
SW_B3
x
x
x
x
gnd
Buck3
Via to board
layer 2 - Ground
SW_B1
Via to board
bottom layer- VIN
Via to board layer 2 - SW_B1
optional additional copper track
Buck1
x
Signal Via
Feedback Via
Figure 24. Example of PCB Layout Configuration
x
Figure 25. Detail of Device Pins and Centre Vias
32
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12 Device and Documentation Support
12.1 Trademarks
All trademarks are the property of their respective owners.
12.2 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
34
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LM10507TME-A/NOPB
NRND
DSBGA
YFR
34
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-30 to 125
V087
LM10507TMX-A/NOPB
NRND
DSBGA
YFR
34
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-30 to 125
V087
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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