User's Guide
SNVA373A – January 2009 – Revised May 2013
AN-1903 LM20136 Evaluation Board
1
Introduction
The LM20136 is a full-featured synchronous buck switching regulator capable of driving up to 6A of load
current. This device features a clock synchronization input that allows the switching frequency to be
synchronized to an external clock source. The ability to adjust the operating frequency from 500kHz to
1.5MHz gives the designer flexibility in component selection. The LM20136 is capable of converting an
input voltage between 2.95V and 5.5V down to an output voltage as low as 0.8V. Fault protection features
include cycle-by-cycle current limit, output power good, and output over-voltage protection. The dual
function soft-start/tracking pin can be used to control the startup response of the LM20136, and the
precision enable pin can be used to easily sequence the LM20136 in sequence-critical applications. The
LM20136 is available in a 16-pin HTSSOP package with an exposed pad for enhanced thermal
performance.
The LM20136 evaluation board is designed to balance overall solution size and efficiency. The evaluation
board measures 1.5” × 1.5” on a two layer PCB with all components placed on the top layer. The power
stage and compensation components of the LM20136 evaluation board have been optimized for an input
voltage of 5V. The output voltage is nominally 3.3V, but this voltage can be easily changed by replacing
one of the feedback resistors (RFB1 or RFB2). The control loop compensation of the LM20136 evaluation
board has been designed to provide a stable solution over the entire input and output voltage range with a
reasonable transient response. The EN pin must be above 1.18V (typ) on the board to initiate switching.
The EN pin is tied to VIN with a 10kΩ resistor and can be toggled directly through the enable test point.
LM20136
PGOOD
PGOOD
SYNC
L
SYNC
RPG
PVIN
VIN
CIN
RFB1
REN
RF
FB
AVIN
CF
VOUT
SW
EN
EN
COMP
RC1
CC2
CO1
RFB2
VCC
CVCC
SS/TRK
PGND AGND
CSS
CC1
Figure 1. Evaluation Board Schematic
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AN-1903 LM20136 Evaluation Board
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Connection Descriptions
2
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Connection Descriptions
Terminal Silkscreen
This terminal is the input voltage to the device. The device will operate over the input voltage
range of 2.95V to 5.5V. The absolute maximum voltage rating for this pin is 6V.
GND
This terminal is the ground connection to the device. There are two different GND connections on
the PCB. One should be used for the input supply and the other for the load.
VOUT
This terminal connects to the output voltage of the power supply and should be connected to the
load.
EN
This terminal connects to the enable pin of the device. This terminal should be connected to VIN or
driven externally. If driven externally, a voltage typically greater than 1.18V will enable the device.
The operating voltage for this pin should not exceed 5.5V. The absolute maximum voltage rating
on this pin is 6V.
SS/TRACK
This terminal provides access to the SS/TRK pin of the device. Connections to this terminal are
not needed for most applications. The feedback pin of the device will track the voltage on the
SS/TRK pin if it is driven with an external voltage source that is below the 0.8V reference. The
voltage on this pin should not exceed 5.5V during normal operation. The absolute maximum
voltage rating on this pin is 6V.
PGOOD
This terminal connects to the power good output of the device. There is a 10kΩ pull-up resistor
from this pin to the input voltage. The voltage on this pin should not exceed 5.5V during normal
operation and has an absolute maximum voltage rating of 6V.
SYNC
This terminal connects to the SYNC pin of the device. If this pin is left open the switching
frequency will default to approximately 400kHz. The voltage on this pin should not exceed 5.5V
during normal operation and has an absolute maximum voltage rating of 6V.
SW
VOUT TP
3
Description
VIN
This point allows a scope probe to be connected to observe the switch node voltage.
This terminal provides an oscilloscope probe connection directly to VOUT to probe the transient
response and output voltage ripple.
Component Selection
This section provides a walk-through of the design process for the LM20136 evaluation board. Unless
otherwise indicated all equations assume units of Amps (A) for current, Farads (F) for capacitance,
Henries (H) for inductance, and Volts (V) for voltage.
3.1
Input Capacitor
The required RMS current rating of the input capacitor for a buck regulator can be estimated by the
following equation:
ICIN(RMS) = IOUT D(1 - D)
(1)
The variable D refers to the duty cycle and can be approximated by:
D=
VOUT
VIN
(2)
From this equation, it follows that the maximum ICIN(RMS) requirement will occur at a full 6A load current with
the system operating at 50% duty cycle. Under this condition, the maximum ICIN(RMS) is given by:
ICIN(RMS) = 6A 0.66 x 0.34 = 2.8A
(3)
Ceramic capacitors feature a very large IRMS rating in a small footprint, making a ceramic capacitor ideal
for this application. A 100µF X5R ceramic capacitor from TDK provides the necessary input capacitance
for the evaluation board.
2
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Component Selection
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3.2
AVIN Filter
An RC filter should be added to prevent any switching noise on PVIN from interfering with the internal
analog circuitry connected to AVIN. This can be seen on the schematic as components RF and CF. There
is a practical limit to the value of resistor RF as the AVIN pin will draw a short 60mA burst of current during
startup. If RF is too large the resulting voltage drop can trigger the UVLO comparator. For the evaluation
board a 1.0Ω resistor is used for RF ensuring that UVLO will not be triggered after the part is enabled. A
1.0µF capacitor in conjunction with the 1.0Ω resistor is recommended to filter the input to AVIN.
3.3
Inductor
As per the datasheet recommendations, the inductor value should initially be chosen to give a peak to
peak ripple current equal to roughly 30% of the maximum output current. The peak to peak inductor ripple
current can be calculated by the equation:
'IP-P =
(VIN - VOUT) x D
L x fSW
(4)
Rearranging this equation and solving for the inductance reveals that for this application (VIN = 5V, VOUT
= 3.3V, fSW = 500kHz, and IOUT = 6A) the nominal inductance value is roughly 1.25µH. However, to allow
evaluation of the LM20136 over the full frequency range of operation, a final inductance of 1µH was
selected. This results in a peak-to-peak ripple current of 2.2A when the converter is operating from 5V and
500kHz . Once an inductance value is calculated, an actual inductor needs to be selected based on a
tradeoff between physical size, efficiency, and current carrying capability. For the LM20136 evaluation
board, a TDK SPM6530T-1R0M120 inductor offers a good balance between efficiency (7.8mΩ DCR), size
(7.1mm × 6.5mm), and saturation current rating (12A ISAT).
3.4
Output Capacitor
The value of the output capacitor in a buck regulator influences the voltage ripple that will be present on
the output voltage, as well as the large signal output voltage response to a load transient. Given the peakto-peak inductor current ripple (ΔIP-P) the output voltage ripple can be approximated by the equation:
'VOUT = 'IP-P x RESR +
1
8 x fSW x COUT
(5)
The variable RESR above refers to the ESR (Effective Series Resistance) of the output capacitor. As can be
seen in the above equation, the ripple voltage on the output can be divided in two parts. One part is
attributed to the AC ripple current flowing through the ESR of the output capacitor. The other part is due to
the AC ripple current charging and discharging the output capacitor. The output capacitor also has an
affect on the amount of droop that is seen on the output voltage in response to a load transient event.
For the evaluation board, a TDK 100µF ceramic capacitor is selected for the output capacitor to provide
good transient and DC performance in a relatively small package. From the technical specifications of this
capacitor, the ESR is roughly 3mΩ and the effective in-circuit capacitance is approximately 35µF (reduced
from 100µF due to the 3.3V DC bias and worse case tolerance). With these values, the peak to peak
voltage ripple on the output when operating from a 5V input can be calculated to be about 20mV.
3.5
CSS
A soft-start capacitor can be used to control the startup time of the LM20136. The startup time when using
a soft-start capacitor can be estimated by the following equation:
tSS =
0.8V x CSS
ISS
(6)
For the LM20136, ISS is nominally 5µA. For the evaluation board, the soft-start time has been designed to
be roughly 5 ms, resulting in a CSS capacitor value of 33nF.
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Component Selection
3.6
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CVCC
The CVCC capacitor is necessary to bypass an internal 2.7V subregulator. This capacitor should be sized
equal to or greater than 1µF, but less than 10µF. A value of 1µF is sufficient for most applications.
3.7
CC1
The capacitor CC1 is used to set the crossover frequency of the LM20136 control loop. Since this board
was optimized to work well over the full input voltage, output voltage, and frequency range, the value of
CC1 was selected to be 1nF. Once the operating conditions for the device are known, the transient
response can be optimized by reducing the value of CC1 and calculating the value for RC1 as outlined in the
next section.
3.8
RC1
Once the value of CC1 is known, resistor RC1 is used to place a zero in the control loop to cancel the output
filter pole. This resistor can be sized according to the equation:
CC1
RC1 =
COUT
x
IOUT
VOUT
+
D x fSW
D
+
fSW x L 48750 x VIN
1
1
-1
2 x fSW x L
(7)
For stability purposes the device should be compensated for the maximum output current expected in the
application.
3.9
CC2
A second compensation capacitor CC2 can be used in some designs to provide a high frequency pole,
useful for cancelling a possible zero introduced by the ESR of the output capacitor. For the LM20136
evaluation board, the CC2 footprint is unpopulated because the low ESR ceramic capacitor used on the
output does not contribute a zero to the control loop before the crossover frequency. If the ceramic
capacitor on the evaluation board is replaced with a different capacitor having significant ESR, the
required value of the capacitor CC2 can be estimated by the equation:
CC2 =
COUT x RESR
RC1
(8)
3.10 RFB1 and RFB2
The resistors labeled RFB1 and RFB2 create a voltage divider from VOUT to the feedback pin that is used to
set the output of the voltage regulator. Nominally, the output of the LM20136 evaluation board is set to
3.3V, giving resistor values of RFB1 = 30.9kΩ and RFB2 = 10.0kΩ. If a different output voltage is required,
the value of RFB1 can be adjusted according to the equation:
RFB1 =
VOUT
0.8
- 1 x RFB2
(9)
RFB2 does not need to be changed from its value of 10.0kΩ.
4
AN-1903 LM20136 Evaluation Board
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Bill of Materials
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4
Bill of Materials
Table 1. Bill of Materials
Designator
Description
Part Number
Qty
Manufacturer
U1
Synchronous Buck Regulator
LM20136
1
Texas Instruments
CIN
100µF, 1210, X5R, 6.3V
C3225X5ROJ107M
1
TDK
CO1
100µF, 1210, X5R, 6.3V
C3225X5ROJ107M
1
TDK
CO2
OPEN
N/A
N/A
N/A
L
1.0µH, 7.8 mΩ
SPM6530T-1R0M120
1
TDK
RF
1.0Ω, 0603
CRCW06031R0J-e3
1
Vishay-Dale
CF
1.0µF, 0603, X5R, 6.3V
GRM188R60J105KA01
1
Murata
CVCC
1.0µF, 0603, X5R, 6.3V
GRM188R60J105KA01
1
Murata
RPG
10.0kΩ, 0603
CRCW06031002F-e3
1
Vishay-Dale
RC1
14.3kΩ, 0603
CRCW06031432F-e3
1
Vishay-Dale
CC1
1.0nF, 0603, COG, 50V
GRM1885C1H102JA01
1
Murata
CC2
OPEN
N/A
N/A
N/A
CSS
33.0nF, 0603, X7R, 50V
GRM188R71H333kA61
1
Murata
RFB1
30.9kΩ, 0603
CRCW060330921F-e3
1
Vishay-Dale
RFB2
10.0kΩ, 0603
CRCW06031002F-e3
1
Vishay-Dale
REN
10.0kΩ, 0603
CRCW06031002F-e3
1
Vishay-Dale
VOUT TP
Test Point
131503100
1
Tektronix
EN, PGOOD, SW,
SS/RK
Test Points
52F7279
4
Keystone
P1,P2,P3,P4
POWER I/O
160-1026-02-01-00
4
Cambion
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Performance Characteristics
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Performance Characteristics
FSW = 500 kHz
FSW = 1 MHz
Figure 2. Efficiency vs Load
Figure 3. Line Regulation (ILOAD = 6A)
VOUT (200 mV/DIV)
IOUT (2A/DIV)
IOUT (1.5A to 6A)
TIME (40 és/DIV)
Figure 4. Load Regulation (VIN = 5V)
Figure 5. 1.5A to 6A Load Transient Response
VEN (5V/DIV)
RLOAD = 0.2Ö
VOUT (1V/DIV)
IOUT (2A/DIV)
PGOOD (2V/DIV)
TIME (1 ms/DIV)
Figure 6. Startup Waveform
6
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PCB Layout
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6
PCB Layout
Figure 7. Top Layer
Figure 8. MidLayer 1
Figure 9. MidLayer 2
Figure 10. Bottom Layer
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