User's Guide
SNVA497B – July 2011 – Revised May 2013
AN-2175 LM21305 POL Demonstration Module and
Reference Design
1
Introduction
This LM21305 synchronous buck switching regulator board-mounted module is a complete, easy-to-use
DC-DC point-of-load (POL) solution capable of driving up to 5A of load current with excellent conversion
efficiency, output voltage accuracy, load and line regulation. The POL module can accept an input voltage
between 3V and 18V and deliver an adjustable and accurate output voltage as low as 0.598V. The
module has been designed to balance overall solution size with regulator efficiency while showcasing high
current density. The power stage has been optimized for an input voltage of 12V and a switching
frequency of 500 kHz. While the output voltage setpoint is nominally 1.8V, it can be easily re-defined by
modifying one of the feedback resistors. Moreover, by attaching a resistor between the TRIM pin and GND
or VOUT, the output voltage can be adjusted up or down, respectively. For fast load transient response
and stable operation over the entire input voltage range, the compensation of the current-mode control
loop has been designed to provide a loop bandwidth of 50 kHz and phase margin of 60°. The Enable (EN)
and Power Good (PGOOD) pins can be applied to easily configure the LM21305 in power systems
architected with multiple voltage rails and explicit sequencing requirements.
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POL Module Features
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Output current range of 0A to 5A
Input voltage range of 3V to 18V (no external bias supply required)
All ceramic capacitor design
Programmable input under-voltage lock-out (UVLO) via precision enable
Default output voltage of 1.8V. For other VOUT setpoints, see Table 2. VOUT can also be adjusted
using a resistor connected to the module’s TRIM pin
90% efficiency at 3.3V/5A, 85% efficiency at 1.8V/5A
Fixed switching frequency for predictable EMI characteristic and easy filtering
500 kHz default switching frequency; adjusted using the SYNC pin
Optional AVIN external bias input if system level 5V is available
POL Module Package Highlights
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0.9” x 0.7” (22.8 mm x 17.8 mm) reduced size form factor
0.04” diameter pins (with intrinsic standoffs) for PVIN, VOUT, GND, TRIM, SYNC, EN, PGOOD, and
AVIN
4 layer construction standard FR4 laminate PCB
Top and bottom PCBs layers and the two inner layers are all 2oz/ft2 (70 µm) copper weight
62 mil (0.062”, 1.6 mm) overall PCB thickness
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SNVA497B – July 2011 – Revised May 2013
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AN-2175 LM21305 POL Demonstration Module and Reference Design
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1
LM21305 Regulator IC Features
4
LM21305 Regulator IC Features
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Integrated, low RDSon, low QG high- and low-side power MOSFETs (44 mΩ and 22 mΩ, respectively)
Optimized MOSFET gate drivers enable low switch deadtimes for efficient high frequency operation
True monotonic startup into pre-biased loads
±1.6% feedback (FB) voltage accuracy over full junction temperature range TJ = -40°C to 125°C
Peak current-mode control with cycle-by-cycle current limiting
Output power good flag
Resistor adjustable switching frequency from 300 kHz to 1.5 MHz
Frequency synchronization
Diode emulation mode at light loads
Precision enable with hysteresis
Output over-voltage protection (OVP)
5 mm x 5 mm WQFN-28 package with an exposed die attach pad (DAP)
POL Module Design Concept
This POL module has been designed to mount on a system motherboard as close as possible to the
point-of-load. While it can operate on a standalone basis for bench measurements and the like, the
module has demonstrably improved thermal characteristics when solder connected into a motherboard.
Most of the conductive heat transfer associated with the module’s thermal dissipation is achieved through
its VIN, VOUT and GND connection terminals. Leveraging the copper polygons and planes that are
typically available in the motherboard PCB stack-up, the module effective thermal impedance and, hence,
the LM21305 regulator IC junction temperature rise are reduced. Note that if the module is operated as a
standalone entity, adequate airflow should be available to mitigate excessive temperature rise.
Furthermore, extra passive components to facilitate additional functionality can be located on the
motherboard, for example, TRIM resistors to margin or adjust VOUT, any components tied to EN or
PGOOD for particular startup sequencing or delay requirements, and so forth. Additional input and output
filter capacitors can also be connected, if required. The power and signal terminal pins of the module are
manufactured by Mill-Max. The pin employed has 0.04” (1 mm) diameter and the recommended
motherboard PCB hole to accommodate such a pin is 0.043” (1.1 mm) diameter. The standoff inherent in
the pin design dictates that the bottom of the module PCB will be 0.17” (4.3 mm) above the top of the
motherboard, providing adequate clearance for airflow to the bottom side components.
6
Additional Component Footprints
A component footprint on the module is provided for a bootstrap diode in SOD523 package. The LM21305
has an internal boot diode. At low input voltages, however, it may be advantageous to connect an external
Schottky diode to maximize the available gate drive voltage for the integrated high-side MOSFET.
7
Typical Applications
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POL conversions from 3.3V, 5V and 12V intermediate bus rails.
Communications infrastructure, for example, optical networking, data centers, servers, base stations,
storage systems
Space constrained applications, industrial controls and factory automation
Radio, medical, test, and data acquisition systems (where the switching frequency is tuned to avoid
interference with other circuitry)
AN-2175 LM21305 POL Demonstration Module and Reference Design
Copyright © 2011–2013, Texas Instruments Incorporated
SNVA497B – July 2011 – Revised May 2013
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POL Module Photos
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POL Module Photos
Figure 1. LM21305 POL Module Photos
9
Module Mechanical Specifications
The mechanical details are specified in Figure 2. Notwithstanding the pinout shown, other module pinout
configurations, including POLA standards, are readily realizable with minor layout changes.
95
167
167
700
167
900
73
73
Figure 2. LM21305 POL Module Mechanical Details
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AN-2175 LM21305 POL Demonstration Module and Reference Design
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3
Module Circuit Schematic
10
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Module Circuit Schematic
U1
PVIN
PVIN
3V to 18V
CBOOT
Cboot
Cin
SW
AVIN
AVIN
0.598V to 5V
Cout
Cf
Ren1
EN
VOUT
L1
Rvin
Rfb1
LM21305
EN
FB
0.598V
Ren2
5V0
C5v0
Cc
Rc
TRIM
COMP
2V5
Rpg
Rtrim
Rfb2
C2v5
PGOOD
Csync
PGOOD
SYNC
FREQ
AGND PGND
Rfq
Figure 3. LM21305 POL Module Schematic
11
Bill of Materials (BOM)
Table 1. Bill of Materials (BOM) for LM21305 POL Module, VIN = 3V to 18V, VOUT = 1.8V
Quantity
4
Reference Designator
Description
Manufacturer
Manufacturer Part
Number
1
PCB1
Printed Circuit Board
3
C2v5, Cboot, Cf
CAP, CERM, 0.1 μF, 25V, ±5%, X7R, 0603
AVX
06033C104JAT2A
1
C5v0
CAP, CERM, 1 μF, 10V, ±10%, X5R, 0603
AVX
0603ZD105KAT2A
1
Cc
CAP, CERM, 4700 pF, 50V, ±10%, X7R, 0603
AVX
06035C472KAT2A
1
Cin
CAP, CERM, 22 μF, 25V, ±10%, X5R, 1210
TDK
C3225X5R1E226M
1
Cout
CAP, CERM, 100 μF, 6.3V, ±20%, X5R, 1210
MuRata
GRM32ER60J107ME2
0L
1
Csync
CAP, CERM, 100 pF, 16V, ±10%, X7R, 0603
AVX
0603YC101KAT2A
0
Dboot
N/A
Infineon
BAT64-02W
8
VIN, VOUT, GND, TRIM,
SYNC, EN, PGOOD,
AVIN
Circuit pin prntd 0.170", 0.082"
Mill-Max
3125-2-00-34-00-0008-0
1
L1
Inductor, 1.5 μH, 11A, 9.7 mΩ, SMD
TDK
SPM6530T-1R5M100
1
Rc
RES, 3.3 kΩ, 1%, 0.1W, 0603
Vishay-Dale
CRCW06033K30FKEA
1
Ren1
RES, 27.4 kΩ, 1%, 0.1W, 0603
Vishay-Dale
CRCW060327K4FKEA
2
Ren2, Rfq
RES, 100 kΩ, 1%, 0.1W, 0603
Vishay-Dale
CRCW0603100KFKEA
2
Rfb1, Rtrim
RES, 20.0 kΩ, 1%, 0.1W, 0603
Vishay-Dale
CRCW060320K0FKEA
2
Rfb2, Rpg
RES, 10.0 kΩ, 1%, 0.1W, 0603
Vishay-Dale
CRCW060310K0FKEA
1
Rvin
RES, 1Ω, 1%, 0.1W, 0603
Vishay-Dale
CRCW06031R00FKEA
1
U1
LM21305 Buck Regulator IC, WQFN-28
Texas Instruments
LM21305
AN-2175 LM21305 POL Demonstration Module and Reference Design
Copyright © 2011–2013, Texas Instruments Incorporated
SNVA497B – July 2011 – Revised May 2013
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Adjusting the Output Voltage - Feedback Resistors
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12
Adjusting the Output Voltage - Feedback Resistors
While the output voltage setpoint is nominally 1.8V, it can be easily changed by modifying one of the
feedback resistors as shown in Table 2.
Table 2. Output Voltage Setting (Rfb2 = 10 kΩ)
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VOUT
Rfb1
5.0V
73.3 kΩ
3.3V
45.3 kΩ
2.5V
31.6 kΩ
1.8V
20 kΩ (default)
1.5V
15 kΩ
1.2V
10 kΩ
0.9V
5 kΩ
0.8V
3.4 kΩ
0.7V
1.7 kΩ
0.598V
0Ω
Adjusting the Output Voltage - Trim Functionality
The output voltage can also be adjusted above or below the nominal setpoint by attaching a resistor to the
module’s TRIM pin. The resistor between the LM21305’s feedback (FB) node and the TRIM pin (Rtrim)
determines the output voltage adjustable range. To increase the output voltage, a resistor needs to be
attached between the TRIM pin and GND (Rtrim_up in Figure 4). Conversely, to decrease the output voltage,
a resistor needs to be attached between the TRIM pin and the VOUT pin (Rtrim_down in Figure 4).
A value of Rtrim = 20 kΩ is recommended to adjust the output voltage from 1.2V to 2.4V (±33% of
nominal) while retaining an acceptable control loop behavior. With Rtrim = 20 kΩ, an output voltage of
2.4V can be achieved simply by shorting the TRIM pin to GND, and an output voltage of 1.2V can be
achieved by shorting the TRIM pin to VOUT. Selecting Rtrim_down = 40 kΩ gives an output voltage of 1.5V.
To retain the nominal output voltage setpoint of 1.8V, the TRIM pin should be left open.
R trim_
up
R trim_
dow
n
Figure 4. Output Voltage Trim and Adjustment
The resistor values required to trim the output voltage up or down are given, respectively, as follows:
(1)
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Loop Compensation
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(2)
Thus, given the resistor values from Table 1, a nominal output voltage of 1.8V, Vref = 0.6V, it follows that:
(3)
(4)
NOTE: Resistor values are in kΩ and VOUT represents the desired output voltage. The accuracy of
the output voltage adjustment is subject to the tolerances of the respective resistors. The
resistor values for a desired output voltage can also be found using the curves provided in
Figure 5.
TRIM UP
TRIM DOWN
OUTPUT VOLTAGE (V)
2.2
2.0
1.8
1.6
1.4
1.2
0
100
200
300
TRIM RESISTANCE (k )
400
Figure 5. Trim Curve for Output Voltage Trim, Margining and Adjustment
14
Loop Compensation
Note that a change in output voltage directly affects the gain from VOUT to the FB pin of the LM21305
and, hence, the overall loop gain. Loop gain is highest when the output voltage is trimmed down to its
minimum. Operation at higher output voltage (with comparatively lower loop gain) may call for recompensation of the control loop if optimal transient performance is desired For example, the crossover
frequency reduces to 40 kHz when the output voltage is trimmed to its maximum level of 2.4V. You are
encouraged to avail of the LM21305 quick-start calculator to derive appropriate compensation components
to maximize performance of the loop for a given output voltage.
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Programmable UVLO With Hysteresis
There is a resistive divider implemented on the module that can be used to establish a precision UVLO
level, this is currently set below the minimum input operating voltage so that the module turns on at VIN =
2.93V (typical). A common user change to this circuit is to adjust the values of Ren1 and/or Ren2 to vary
the UVLO level to suit the target application. For calculation, see the LM21305 5A Adjustable Frequency
Synchronous Buck Regulator Data Sheet (SNVS639). The EN pin can be pulled low to shutdown the
module.
6
AN-2175 LM21305 POL Demonstration Module and Reference Design
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External Bias Supply
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16
External Bias Supply
By removing resistor Rf, an external bias supply rail (5V) can be connected to the AVIN pin. This allows
increased gate drive level at low input voltages and alleviates the LM21305 LDO bias supply power
dissipation at high input voltages. Note that the LM21305 UVLO is referenced to the voltage at AVIN; to
achieve a valid soft-start, PVIN should come up before AVIN.
17
Test Connections
The module should be connected to a power supply and load as portrayed in Figure 6. The relevant
voltmeters and ammeters for measuring efficiency are also shown. A tip and barrel scope probe setup
should be used to measure output voltage ripple and load transient response.
AMMETER
AMMETER
VIN
VOUT
ELECTRONIC
LOAD
POWER SUPPLY
VIN = 3V ± 18V
Set from 0A to 5A
VOLTMETER
VOLTMETER
VOUT = 1.8V
Figure 6. Module Efficiency Measurement Setup
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Typical Performance Characteristics
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Typical Performance Characteristics
Module Efficiency, VIN = 5V, TAMB = 25°C
95
90
85
EFFICIENCY (%)
EFFICIENCY (%)
Module Efficiency, VIN = 12V, TAMB = 25°C
90
80
85
80
75
75
70
70
0
1
2
3
4
LOAD CURRENT (A)
5
0
1
2
3
4
LOAD CURRENT (A)
5
Module Output Voltage Ripple,
VIN = 12V, VOUT = 1.8V, IOUT = 1A, 20 MHz Bandwidth
Module Efficiency, VIN = 3.3V, TAMB = 25°C
95
EFFICIENCY (%)
90
VOUT 20 mV/DIV
85
80
75
1 Ps/DIV
70
0
1
2
3
4
LOAD CURRENT (A)
5
Module Load Transient Response,
VIN = 12V, VOUT = 1.8V, IOUT = 1.25A to 3.75A
(25% to 75% rated full load)
Module Load Transient Response,
VIN = 12V, VOUT = 1.8V, IOUT = 0.5A to 5A
(10% to 100% rated full load)
IOUT 1A/DIV
5A
IOUT 1A/DIV
3.75A
VOUT
50 mV/DIV
1.8V
VOUT
50 mV/DIV
1.8V
1.25A
0.5A
40 Ps/DIV
8
AN-2175 LM21305 POL Demonstration Module and Reference Design
Copyright © 2011–2013, Texas Instruments Incorporated
40 Ps/DIV
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Typical Performance Characteristics
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Module Startup Waveform
VIN = 12V, VOUT = 1.8V, no load
Module Startup Waveform
VIN = 12V, VOUT = 1.8V, IOUT = 5A resistive load
VIN 2V/DIV
VIN 2V/DIV
IOUT 1A/DIV
VOUT
0.5V/DIV
VOUT
0.5V/DIV
PGOOD
1V/DIV
PGOOD
1V/DIV
1 ms/DIV
1 ms/DIV
Module Enable Waveform with 0.9V
Pre-Biased Output, VIN = 12V, VOUT = 1.8V, no load
EN 1V/DIV
0.9V
VOUT
0.5V/DIV
PGOOD
1V/DIV
1 ms/DIV
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Module PCB View and Layout Diagrams
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Module PCB View and Layout Diagrams
The associated gerber and CAD files can be downloaded from the LM21305 product folder.
Figure 7. Top Layer and Assembly
Figure 8. Internal Layer I (Ground)
Heat Sinking Layer
10
AN-2175 LM21305 POL Demonstration Module and Reference Design
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Module PCB View and Layout Diagrams
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Figure 9. Internal Layer II (Ground)
Heat Sinking Layer
Figure 10. Bottom Layer and Assembly (viewed from top side)
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