User's Guide
SNVA152A – March 2006 – Revised April 2013
AN-1453 LM25007 Evaluation Board
1
Introduction
The LM25007EVAL evaluation board provides the design engineer with a fully functional buck regulator,
employing the constant on-time (COT) operating principle. This evaluation board provides a 5V output
over an input range of 9V - 42V. The circuit delivers load currents to 450 mA, with current limit at ≊670
mA. The board is populated with all external components except C6 and C9. These components provide
options for managing the output ripple as described later in this document.
The board’s specification are:
• Input Voltage: 9V to 42V
• Output Voltage: 5V
• Maximum load current: 450 mA
• Minimum load current: 0 mA
• Current Limit: ≊670 mA
• Measured Efficiency: 92.6% (VIN = 9V, IOUT = 150 mA)
• Nominal Switching Frequency: 306 kHz
• Size: 1.6 in. x 1.0 in. x 0.5 in
Figure 1. Evaluation Board - Top Side
2
Theory of Operation
Figure 5 contains a simplified block diagram of the LM25007. When the circuit is in regulation, the buck
switch is on each cycle for a time determined by R1 and the input voltage according to Equation 1:
tON =
1.42 x 10-10 x R1
VIN
(1)
The nominal switching frequency is calculated from Equation 2:
FS =
VOUT
1.42 x 10-10 x R1
(2)
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1
Board Layout and Probing
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The on-time in this evaluation board ranges from ≊1800 ns at Vin = 9V, to ≊390 ns at Vin = 42V. The ontime varies inversely with VIN to maintain a nearly constant switching frequency, which is nominally 306
kHz in this evaluation board . At the end of each on-time the Minimum Off-Timer ensures the buck switch
is off for at least 300 ns. In normal operation the off-time is much longer. During the off-time the output
capacitor (C2) is discharged by the load current. When the output voltage falls sufficiently that the voltage
at FB is below 2.5V, the regulation comparator initiates a new on-time period. For stable, fixed frequency
operation, ≊25 mVp-p of ripple is required at FB to switch the regulation comparator. For a more detailed
block diagram and a complete description of the various functional blocks, see the LM25007 42V, 0.5A
Step-Down Switching Regulator Data Sheet (SNVS401).
3
Board Layout and Probing
Figure 1 shows the placement of the circuit components. The following should be kept in mind when the
board is powered:
1) When operating at high input voltage and high load current, forced air flow is recommended.
2) The LM25007 may be hot to the touch when operating at high input voltage and high load current.
3) Use CAUTION when probing the circuit at high input voltages to prevent injury, as well as possible
damage to the circuit.
4) Ensure the wires connecting this board to the load are sized appropriately for the load current. Ensure
there is not a significant drop in the wires between this evaluation board and the load.
4
Board Connection/Start-up
The input connections are made to the J1 connector. The load is normally connected to the V1 and GND
terminals of the J3 connector. Ensure the wires are adequately sized for the intended load current. Before
start-up a voltmeter should be connected to the input terminals, and to the output terminals. The load
current should be monitored with an ammeter or a current probe. It is recommended that the input voltage
be increased gradually to 9V, at which time the output voltage should be 5V. If the output voltage is
correct with 9V at VIN, then increase the input voltage as desired and proceed with evaluating the circuit.
5
Output Ripple Control
The LM25007 requires a minimum of 25 mVp-p ripple at the FB pin, in phase with the switching waveform
at the SW pin, for proper operation. In the simplest configuration that ripple is derived from the ripple at
VOUT1, generated by the inductor’s ripple current flowing through R4. That ripple voltage is attenuated by
the feedback resistors, requiring that the ripple amplitude at VOUT1 be higher than the minimum of 25 mVpp by the gain factor. Options for reducing the output ripple are discussed below, and the results are shown
in the graph of Figure 8.
5.1
Minimum Output Ripple
This evaluation board is supplied configured for minimum ripple at VOUT1 by setting R4 to zero ohms, and
including components R6, C7 and C8. The output ripple that ranges from 2 mVp-p at VIN = 9V to 7 mVp-p
at VIN = 42V, is determined primarily by the ESR of output capacitor (C2), and the inductor’s ripple current
that ranges from 75 mAp-p to 144 mAp-p over the input voltage range. This performance applies only to
continuous conduction mode as the ripple amplitude is higher in discontinuous conduction mode. The
ripple voltage required by the FB pin is generated by R6, C7 and C8 since the SW pin switches from -1V
to VIN, and the right end of C7 is a virtual ground. The values for R6 and C7 are chosen to generate a 3040 mVp-p triangle waveform at their junction. That triangle wave is then coupled to the FB pin through C8.
The following procedure is used to calculate values for R6, C7 and C8:
• Calculate the voltage VA:
VA = VOUT - (VSW x (1 - (VOUT/VIN)))
(3)
where, VSW is the absolute value of the voltage at the SW pin during the off-time (typically 1V), and VIN
is the minimum input voltage. For this circuit VA calculates to 4.55V. This is the DC voltage at the
R6/C7 junction, and is used in Equation 4.
2
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•
Calculate the R6 x C7 product:
R6 x C7 =
(VIN ± VA) x tON
'V
(4)
where, tON is the maximum on-time (≊1800 ns), VIN is the minimum input voltage, and ΔV is the desired
ripple amplitude at the R6/C7 junction, 30 mVp-p for this example.
R6 x C7 =
(9V ± 4.55V) x 1800 ns
= 2.67 x 10-4
0.03V
(5)
R6 and C7 are then chosen from standard value components to satisfy the above product. For example,
C7 can be 2200 pF requiring R6 to be 121 kΩ. C8 is chosen to be 0.01 µF, large compared to C7. This
portion of the circuit, as supplied on this EVB, is shown in Figure 2.
LM25007
BST
2
C5
0.01PF
L1
100 PH
C7
R6
SW
1
121k
5V
VOUT1
2200 pF
D1
R2
3k
C8
0.01 PF
FB
R4
0
VOUT2
5
R3
3k
C2
22 PF
GND
RTN
4
Figure 2. Minimum Ripple Using R6, C7, C8
5.2
Intermediate Ripple Level Configuration
This configuration generates more ripple at VOUT1 than the above configuration, but uses one less
capacitor. If some ripple can be tolerated in the application, this configuration is slightly more economical,
and simpler. R4 and C6 are used instead of R6, C7, and C8, as shown in Figure 3.
LM25007
BST
2
C5
0.01 PF
L1
SW
100 PH
5V
1
VOUT1
D1
FB
C6
1500 pF
R2
3k
5
R3
3k
4
R4
0.34:
C2
22 PF
RTN
VOUT2
GND
Figure 3. Intermediate Ripple Level Configuration Using C6 and R4
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3
Current Limit
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R4 is chosen to generate ≥25 mV at VOUT1, knowing that the minimum ripple current in this circuit is 75
mAp-p at minimum VIN. C6 couples that ripple to the FB pin without the attenuation of the feedback
resistors. C6's minimum value is calculated from:
C6 =
tON(max)
(R2//R3)
(6)
where, tON(max) is the maximum on-time (at minimum VIN), and R2//R3 is the equivalent parallel value of the
feedback resistors. For this evaluation board tON(max) is approximately 1800 ns, and R2//R3 = 1.5 kΩ, and
C6 calculates to a minimum of 1200 pF. The resulting ripple at VOUT1 ranges from ≊25 mVp-p to 50 mVp-p
over the input voltage range with the circuit in continuous conduction mode. The ripple amplitude is higher
if the load current is low enough to force the circuit into discontinuous conduction mode.
5.3
Minimum Cost Configuration
This configuration is the same as Section 5.2, but without C6. Since 25 mVp-p are required at the FB pin,
R4 is chosen to generate 50 mvp-p at VOUT1, knowing that the minimum ripple current in this circuit is 75
mAp-p at minimum VIN. To allow for tolerances, 0.68Ω is used for R4. The resulting ripple at VOUT1 ranges
from ≊50 mVp-p to ≊100 mVp-p over the input voltage range. If the application can accept this ripple level,
this is the most economical solution. The circuit is shown in Figure 4.
LM25007
BST
2
C5
0.01PF
L1
SW
100 PH
5V
1
VOUT1
D1
R2
3k
R4
0.68:
R3
3k
C2
22 PF
FB
5
4
VOUT2
GND
RTN
Figure 4. Minimum Cost Configuration
5.4
Alternate Low Ripple Configuration
A low ripple output can be obtained by connecting the load to VOUT2 in the circuits of Section 5.2 or
Section 5.3. Since R4 degrades load regulation, this alternative may be viable for applications where the
load current is relatively constant. If this method is used, ensure R4’s power rating is appropriate for the
load current.
6
Current Limit
The LM25007 contains an intelligent current limit off-timer. The current limit threshold is 725 mA, ±25%. If
the current in the buck switch (the peak of the inductor’s current waveform) reaches the threshold the
present on-time cycle is immediately terminated, and a non-resetable off-time is initiated. The length of the
off-time is controlled by an external resistor (R5) and the voltage at the FB pin. If FB = 0V (output is
shorted to ground) the off-time is the preset maximum of 17 µs. This off-time ensures safe short circuit
operation to the maximum input voltage of 42V. In cases of less severe overload where the output voltage,
and the voltage at FB, is above ground the current limit off-time is less than 17 µs. The shorter off-times
reduces the amount of foldback, recovery time, and also reduces the startup time.
4
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Minimum Load Current
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The current limit off-time is calculated from Equation 7:
10
tOFF =
0.59 +
-5
VFB
-6
7.22 x 10 x R5
(7)
The current limit off-time ranges from 4.3 µs to 17 µs as VFB varies from 2.5V to 0V, with R5 = 200 kΩ.
The guideline for selecting R5’s value is that the current limit off-time (at VFB = 2.5V) should be slightly
longer than the maximum off-time encountered in normal operation. Setting a shorter off-time could result
in inadequate overload protection, and setting a much longer off-time can affect the startup operation.
7
Minimum Load Current
The LM25007 requires a minimum load current of ≊500 µA to ensure the boost capacitor (C5) is
recharged sufficiently during each off-time. In this evaluation board, the minimum load current is provided
by the feedback resistors (R2, R3), allowing the board’s minimum load current to be specified at zero.
9V-42V
Input
C3
C1
1.0 PF
VCC
LM25007
VIN
8
Minimum
Off
Timer
On
Timer
R1 0.1 PF
115k
7
C4
0.1 PF
BST
V
IN
2
0.01 PF
L1 100 PH
C5
6
SW
Logic
RON/SD
1
2.5V
4
Current Limit
Detect and
Off-Timer
Regulation
Comparator
RTN
5
D1
C7
121k
2200
pF
C8
0.01 PF
RCL
3
R6
C6
R5
200k
C9
FB
5V
VOUT1 (V1)
R2
3k
R4
0
VOUT2 (V2)
R3
3k
C2
22 PF
GND
Figure 5. Complete Evaluation Board Schematic
Table 1. Bill of Materials (BOM)
Item
Description
Mfg., Part Number
Package
Value
C1
C2
Ceramic Capacitor
TDK C3225X7R2A105M
1210
1.0 µF, 100V
Ceramic Capacitor
TDK C3225X7R1C226M
1210
22 µF, 16V
C3, 4
Ceramic Capacitor
TDK C2012X7R2A104M
0805
0.1 µF, 100V
C5,8
Ceramic Capacitor
TDK C2012X7R2A103M
0805
0.01 µF, 100V
Unpopulated
0805
TDK C2012X7R2A222M
0805
Unpopulated
0805
C6
C7
Ceramic Capacitor
C9
2200 pF
D1
Schottky Diode
Diodes Inc. DFLS160
Power DI 123
60V, 1A
L1
Power Inductor
TDK SLF7045T-101MR50
7 mm x 7 mm
100 µH
R1
Resistor
Vishay CRCW08051153F
0805
115 kΩ
R2, 3
Resistor
Vishay CRCW08053011F
0805
3.01 kΩ
R4
Resistor
Vishay CRCW2010000Z
2010
0Ω
R5
Resistor
Vishay CRCW08052003F
0805
200 kΩ
R6
Resistor
Vishay CRCW08051213F
0805
121 kΩ
U1
Switching Regulator
LM25007
VSSOP-8
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5
Circuit Performance
8
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Circuit Performance
100
Vin = 9V
90
EFFICIENCY (%)
15V
80
42V
30V
70
60
50
0
50 100 150 200 250 300 350 400 450
LOAD CURRENT (mA)
Figure 6. Efficiency vs Load Current
100
450 mA
EFFICIENCY (%)
90
80
150 mA
IOUT = 50 mA
70
60
50
5
10
15
20
25
30
35
40
45
INPUT VOLTAGE (V)
Figure 7. Efficiency vs Input Voltage
6
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Circuit Performance
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120
OUTPUT RIPPLE (mVp-p)
100
Option C
80
60
Option B
40
20
Options A & D
0
5
10
15
20
25
30
35
40
45
INPUT VOLTAGE (V)
Figure 8. Output Voltage Ripple
SWITCHING FREQUENCY (kHz)
400
350
300
250
VIN = 15V
200
0
50 100 150 200 250 300 350 400 450
LOAD CURRENT (mA)
Figure 9. Switching Frequency vs. Load Current
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7
PCB Layout
9
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PCB Layout
Figure 10. Board Silkscreen
Figure 11. Board Top Layer
8
AN-1453 LM25007 Evaluation Board
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PCB Layout
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Figure 12. Board Bottom Layer (viewed from top)
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