LM25061PMME-2/NOPB

LM25061 www.ti.com SNVS611E – FEBRUARY 2011 – REVISED MARCH 2013 LM25061 Positive Low Voltage Power Limiting Hot Swap Controller Check for Samples: LM25061 FEATURES APPLICATIONS • • • • • 1 2 • • • • • • • • • • Operating Range: +2.9V to +17V In-rush Current Limit for Safe Board Insertion into Live Power Sources Programmable Maximum Power Dissipation in the External Pass Device Adjustable Current Limit Circuit Breaker Function for Severe OverCurrent Events Internal High Side Charge Pump and Gate Driver for External N-Channel MOSFET Adjustable Under-Voltage Lockout (UVLO) and Hysteresis Adjustable Output Voltage Monitoring and Hysteresis Initial Insertion Timer Allows Ringing and Transients to Subside After System Connection Programmable Fault Timer Avoids Nuisance Trips Active High Open Drain POWER GOOD Output Available in Latched Fault and Automatic Restart Versions Server Backplane Systems Base Station Power Distribution Systems Solid State Circuit Breaker PACKAGE • VSSOP-10 DESCRIPTION The LM25061 positive hot swap controller provides intelligent control of the power supply voltage to the load during insertion and removal of circuit cards from a live system backplane or other "hot" power sources. The LM25061 provides in-rush current control to limit system voltage droop and transients. The current limit and power dissipation in the external series pass NChannel MOSFET are programmable, ensuring operation within the Safe Operating Area (SOA). The POWER GOOD output indicates when the output voltage exceeds a programmable threshold. The input under-voltage level and hysteresis are programmable, as well as the initial insertion delay time and fault detection time. The LM25061-1 latches off after a fault detection, while the LM25061-2 automatically restarts at a fixed duty cycle. The LM25061 is available in a 10 pin VSSOP package. Typical Application VSYS VOUT GND VIN UVLO/EN SENSE GATE OUT VPGD FB LM25061 Power Good PGD TIMER GND PWR Figure 1. Positive Power Supply Control 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011–2013, Texas Instruments Incorporated LM25061 SNVS611E – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com Connection Diagram SENSE 1 10 VIN 2 9 UVLO/EN 3 8 PGD FB 4 7 PWR GND 5 6 TIMER GATE OUT Figure 2. Top View 10-Lead VSSOP PIN DESCRIPTIONS Pin # Name Description Applications Information 1 SENSE Current sense input The voltage across the current sense resistor (RS) is measured from VIN to this pin. If the voltage across RS reaches 50mV the load current is limited and the fault timer activates. 2 VIN Positive supply input A small ceramic bypass capacitor close to this pin is recommended to suppress transients which occur when the load current is switched off. 3 UVLO/EN Under-voltage lockout An external resistor divider from the system input voltage sets the under-voltage turnon threshold. An internal 20 µA current source provides hysteresis. The enable threshold at the pin is 1.17V. This pin can also be used for remote shutdown control. 4 FB Output feedback An external resistor divider from the output sets the output voltage at which the PGD pin switches. The threshold at the pin is 1.17V. An internal 22 µA current source provides hysteresis. 5 GND Circuit ground 6 TIMER Timing capacitor 7 PWR Power limit set 8 PGD Power Good indicator 9 OUT Output feedback Connect to the output rail (external MOSFET source). Internally used to determine the MOSFET VDS voltage for power limiting. 10 GATE Gate drive output Connect to the external MOSFET’s gate. This pin's voltage is limited at 19.5V above ground. An external capacitor connected to this pin sets the insertion time delay and the Fault Timeout Period. The capacitor also sets the restart timing of the LM25061-2. An external resistor connected to this pin, in conjunction with the current sense resistor (RS), sets the maximum power dissipation allowed in the external series pass MOSFET. An open drain output. This output is high when the voltages at the FB pin and at the UVLO pin are above their thresholds. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 2 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM25061 LM25061 www.ti.com SNVS611E – FEBRUARY 2011 – REVISED MARCH 2013 Absolute Maximum Ratings (1) (2) (3) VIN to GND (4) -0.3V to 20V SENSE, OUT, PGD to GND -0.3V to 20V UVLO to GND -0.3V to 20V FB to GND -0.3V to 20V VIN to SENSE -0.3V to +0.3V ESD Rating (5) Human Body Model 2kV Storage Temperature -65°C to +150°C Junction Temperature +150°C Lead Temperature (soldering 4 sec) +260°C (1) (2) (3) (4) (5) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications and conditions see the Electrical Characteristics. If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications. For detailed information on soldering plastic VSSOP packages refer to the Packaging Databook available from Texas Instruments. Current out of a pin is indicated as a negative number. The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. Operating Ratings VIN Supply Voltage +2.9V to 17V PGD Off Voltage 0V to 17V Junction Temp. Range −40°C to +85°C Electrical Characteristics Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +85°C. Minimum and Maximum limits are ensured through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: VIN = 12V. Symbol Parameter Conditions Min. Typ. Max. Units Input (VIN pin) IIN-EN Input Current, enabled UVLO = 2V, VIN = 14V 1.6 2.4 mA IIN-DIS Input Current, disabled UVLO = 0.7V 1.0 1.6 mA POR Power On Reset threshold at VIN VIN Increasing 2.6 2.8 V POR hysteresis VIN decreasing 150 mV OUT = VIN, Normal operation 0.30 µA Disabled, OUT = 0V, SENSE = VIN -12 PORHYS OUT pin IOUT-EN IOUT-DIS OUT bias current, enabled OUT bias current, disabled (1) UVLO pin UVLOTH UVLO threshold UVLOHYS UVLO hysteresis current UVLO = 1V UVLODEL UVLO delay Delay to GATE high 15 Delay to GATE low 8.3 UVLOBIAS UVLO bias current 1.154 1.17 1.183 V 15 20 26 µA UVLO = 3V µs 1 µA Power Limit (PWR pin) PWRLIM-1 Power limit sense voltage (VIN-SENSE) PWRLIM-2 IPWR RSAT(PWR) (1) SENSE-OUT = 12V, RPWR = 69.8 kΩ 19 25 31 mV SENSE-OUT = 6V, RPWR = 34.8 kΩ 19 25 31 mV PWR pin current VPWR = 2.5V -15 µA PWR pin impedance when disabled UVLO = 0.7V 140 Ω OUT bias current (disabled) due to leakage current through an internal 1.0 MΩ resistance from SENSE to VOUT. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM25061 3 LM25061 SNVS611E – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com Electrical Characteristics (continued) Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +85°C. Minimum and Maximum limits are ensured through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: VIN = 12V. Symbol Parameter Conditions Min. Typ. Max. Units Gate Control (GATE pin) IGATE Source current Normal Operation -27 -20 -13 µA Sink current UVLO = 1V 1.5 2 2.7 mA VIN - SENSE = 150 mV or VIN < POR, VGATE = 5V 160 260 375 mA Gate output voltage in normal operation GATE voltage with respect to ground 18 19.5 21 V VCL Threshold voltage VIN-SENSE voltage 45 50 55 mV tCL Response time VIN-SENSE stepped from 0 mV to 80 mV 15 µs SENSE input current Enabled, SENSE = OUT 23 µA Disabled, OUT = 0V 12 Enabled, OUT = 0V 62 VGATE Current Limit ISENSE Circuit Breaker VCB Threshold voltage VIN - SENSE tCB Response time VIN - SENSE stepped from 0 mV to 150 mV, time to GATE low, no load 75 95 110 mV 0.19 0.36 µs 1.60 1.72 1.85 V 0.9 1.0 1.1 V Timer (TIMER pin) VTMRH Upper threshold VTMRL Lower threshold ITIMER Restart cycles (LM25061-2) End of 8th cycle (LM25061-2) 0.3 Re-enable Threshold (LM25061-1) 0.3 Insertion time current -7.5 Sink current, end of insertion time TIMER pin = 2V Fault detection current Fault sink current DCFAULT Fault Restart Duty Cycle LM25061-2 only tFAULT Fault to GATE low delay TIMER pin reaches the upper threshold -5.5 V V -3.5 µA 1.5 2 2.5 mA -110 -80 -50 µA 1.6 2.5 3.4 µA 0.67 % 20 µs FB Pin FBTH FB threshold UVLO = 2V FBHYS FB hysteresis current FB = 2V FBDEL FB delay Delay to PGD high 100 Delay to PGD low 110 FBBIAS FB bias current 1.145 1.17 1.195 V -28 -22 -17 µA FB = 1V ns 1 µA 30 mV 1 µA Power Good (PGD pin) 4 PGDVOL Output low voltage ISINK = 2 mA PGDIOH Off leakage current VPGD = 17V Submit Documentation Feedback 15 Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM25061 LM25061 www.ti.com SNVS611E – FEBRUARY 2011 – REVISED MARCH 2013 Typical Performance Characteristics Unless otherwise specified the following conditions apply: TJ = 25°C, VIN = 12V VIN Pin Input Current vs. VIN SENSE Pin Input Current Figure 3. Figure 4. OUT Pin Input Current GATE Pin Voltage Figure 5. Figure 6. GATE Pin Source Current MOSFET Power Dissipation Limit Figure 7. Figure 8. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM25061 5 LM25061 SNVS611E – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified the following conditions apply: TJ = 25°C, VIN = 12V 6 PGD Pin Low Voltage vs. Sink Current Input Current, Enabled vs. Temperature Figure 9. Figure 10. UVLO Threshold vs. Temperature UVLO Hysteresis Current vs. Temperature Figure 11. Figure 12. FB Threshold vs. Temperature FB Hysteresis Current vs. Temperature Figure 13. Figure 14. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM25061 LM25061 www.ti.com SNVS611E – FEBRUARY 2011 – REVISED MARCH 2013 Typical Performance Characteristics (continued) Unless otherwise specified the following conditions apply: TJ = 25°C, VIN = 12V Current Limit Threshold vs. Temperature Circuit Breaker Threshold vs. Temperature Figure 15. Figure 16. Power Limit Threshold vs. Temperature GATE Output Voltage vs. Temperature Figure 17. Figure 18. GATE Source Current vs. Temperature PGD Low Voltage vs. Temperature Figure 19. Figure 20. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM25061 7 LM25061 SNVS611E – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com Block Diagram Q1 VSYS VOUT RS CIN CL R3 R1 VIN UVLO/EN SENSE GATE OUT VPGD FB R4 LM25061 R2 Power Good PGD TIMER CT GND RPG PWR RPWR Figure 21. Basic Application Circuit 8 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM25061 LM25061 www.ti.com SNVS611E – FEBRUARY 2011 – REVISED MARCH 2013 Functional Description The LM25061 is designed to control the in-rush current to the load upon insertion of a circuit card into a live backplane or other "hot" power source, thereby limiting the voltage sag on the backplane’s supply voltage, and the dV/dt of the voltage applied to the load. Effects on other circuits in the system are minimized, preventing possible unintended resets. A controlled shutdown when the circuit card is removed can also be implemented using the LM25061. In addition to a programmable current limit, the LM25061 monitors and limits the maximum power dissipation in the series pass device to maintain operation within the device Safe Operating Area (SOA). Either current limiting or power limiting for an extended period of time results in the shutdown of the series pass device. In this event, the LM25061-1 latches off until the circuit is re-enabled by external control, while the LM25061-2 automatically restarts with defined timing. The circuit breaker function quickly switches off the series pass device upon detection of a severe over-current condition. The Power Good (PGD) output pin indicates when the output voltage is above the programmed threshold. A programmable under-voltage lock-out (UVLO) circuit enables the LM25061 when the system input voltage is above the desired threshold. The typical configuration of a circuit card with LM25061 hot swap protection is shown in Figure 22. RS VSYS +12V LIVE POWER SOURCE VOUT Q1 VIN OUT LM25061 CL LOAD PGD GND GND PLUG - IN BOARD Figure 22. LM25061 Application Power Up Sequence The VIN operating range of the LM25061 is +2.9V to +17V, with a transient capability to 20V. Referring to the Block Diagram and Figure 21 and Figure 23, as the voltage at VIN initially increases, the external N-channel MOSFET (Q1) is held off by an internal 260 mA pull-down current at the GATE pin. The strong pull-down current at the GATE pin prevents an inadvertent turn-on as the MOSFET’s gate-to-drain (Miller) capacitance is charged. Additionally, the TIMER pin is initially held at ground. When the VIN voltage reaches the POR threshold the insertion time begins. During the insertion time, the capacitor at the TIMER pin (CT) is charged by a 5.5 µA current source, and Q1 is held off by a 2 mA pull-down current at the GATE pin regardless of the VIN voltage. The insertion time delay allows ringing and transients at VIN to settle before Q1 is enabled. The insertion time ends when the TIMER pin voltage reaches 1.72V. CT is then quickly discharged by an internal 2 mA pull-down current. The GATE pin then switches on Q1 when VSYS exceeds the UVLO threshold. If VSYS is above the UVLO threshold at the end of the insertion time, Q1 switches on at that time. The GATE pin charge pump sources 20 µA to charge Q1’s gate capacitance. The maximum voltage at the GATE pin is limited by an internal 19.5V zener diode. As the voltage at the OUT pin increases, the LM25061 monitors the drain current and power dissipation of MOSFET Q1. In-rush current limiting and/or power limiting circuits actively control the current delivered to the load. During the in-rush limiting interval (t2 in Figure 23) an internal 80 µA fault timer current source charges CT. If Q1’s power dissipation and the input current reduce below their respective limiting thresholds before the TIMER pin reaches 1.72V the 80 µA current source is switched off, and CT is discharged by the internal 2.5 µA current sink (t3 in Figure 23). The in-rush limiting interval is complete when the load current reduces to the normal operating level. The PGD pin switches high when the output voltage exceeds the threshold programmed at the FB pin. If the TIMER pin voltage reaches 1.72V before in-rush current limiting or power limiting ceases (during t2), a fault is declared and Q1 is turned off. See the Fault Timer & Restart section for a complete description of the fault mode. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM25061 9 LM25061 SNVS611E – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com VSYS UVLO V IN POR 5.5 PA TIMER Pin GATE Pin 1.72V 80 PA 2.5 PA 2 mA 260 mA pull-down 2 mA pull-down 20 PA source I LIMIT Load Current Output Voltage (OUT Pin) FB Threshold PGD t1 Insertion Time t2 In- rush Limiting t3 Normal Operation Figure 23. Power Up Sequence (Current Limit only) Gate Control A charge pump provides the voltage at the GATE pin to enhance the N-Channel MOSFET’s gate. During normal operating conditions (t3 in Figure 23) the gate of Q1 is held charged by an internal 20 µA current source. The voltage at the GATE pin (with respect to ground) is limited by an internal 19.5V zener diode. See the graph “ GATE Pin Voltage”. Since the gate-to-source voltage applied to Q1 could be as high as 19.5V during various conditions, a zener diode with the appropriate voltage rating must be added between the GATE and OUT pins if the maximum VGS rating of the selected MOSFET is less than 19.5V. The external zener diode must have a forward current rating of at least 260 mA. When the system voltage is initially applied, the GATE pin is held low by a 260 mA pull-down current. This helps prevent an inadvertent turn-on of the MOSFET through its drain-gate capacitance as the applied system voltage increases. During the insertion time (t1 in Figure 23) the GATE pin is held low by a 2 mA pull-down current. This maintains Q1 in the off-state until the end of t1, regardless of the voltage at VIN or UVLO. Following the insertion time, during t2 in Figure 23, the gate voltage of Q1 is modulated to keep the current or power dissipation level from exceeding the programmed levels. While in the current or power limiting mode the TIMER pin capacitor is charging. If the current and power limiting cease before the TIMER pin reaches 1.72V the TIMER pin capacitor then discharges, and the circuit enters normal operation. If the in-rush limiting condition persists such that the TIMER pin reached 1.72V during t2, the GATE pin is then pulled low by the 2 mA pull-down current. The GATE pin is then held low until either a power up sequence is initiated (LM25061-1), or until the end of the restart sequence (LM25061-2). See the Fault Timer & Restart section. If the system input voltage falls below the UVLO threshold, the GATE pin is pulled low by the 2 mA pull-down current to switch off Q1. 10 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM25061 LM25061 www.ti.com SNVS611E – FEBRUARY 2011 – REVISED MARCH 2013 Current Limit The current limit threshold is reached when the voltage across the sense resistor RS (VIN to SENSE) reaches 50 mV. In the current limiting condition, the GATE voltage is controlled to limit the current in MOSFET Q1. While the current limit circuit is active, the fault timer is active as described in the Fault Timer & Restart section. If the load current falls below the current limit threshold before the end of the Fault Timeout Period, the LM25061 resumes normal operation. For proper operation, the RS resistor value should be no larger than 200 mΩ. Higher values may result in instability in the current limit control loop. Circuit Breaker If the load current increases rapidly (e.g., the load is short-circuited) the current in the sense resistor (RS) may exceed the current limit threshold before the current limit control loop is able to respond. If the current exceeds approximately twice the current limit threshold (95 mV/RS), Q1 is quickly switched off by the 260 mA pull-down current at the GATE pin, and a Fault Timeout Period begins. When the voltage across RS falls below 95 mV the 260 mA pull-down current at the GATE pin is switched off, and the gate voltage of Q1 is then determined by the current limit or the power limit functions. If the TIMER pin reaches 1.72V before the current limiting or power limiting condition ceases, Q1 is switched off by the 2 mA pull-down current at the GATE pin as described in the Fault Timer & Restart section. Power Limit An important feature of the LM25061 is the MOSFET power limiting. The Power Limit function can be used to maintain the maximum power dissipation of MOSFET Q1 within the device SOA rating. The LM25061 determines the power dissipation in Q1 by monitoring its drain-source voltage (SENSE to OUT), and the drain current through the sense resistor (VIN to SENSE). The product of the current and voltage is compared to the power limit threshold programmed by the resistor at the PWR pin. If the power dissipation reaches the limiting threshold, the GATE voltage is modulated to regulate the current in Q1. While the power limiting circuit is active, the fault timer is active as described in the Fault Timer & Restart section. Fault Timer & Restart When the current limit or power limit threshold is reached during turn-on or as a result of a fault condition, the gate-to-source voltage of Q1 is modulated to regulate the load current and power dissipation in Q1. When either limiting function is activated, an 80 µA fault timer current source charges the external capacitor (CT) at the TIMER pin as shown in Figure 25 (Fault Timeout Period). If the fault condition subsides during the Fault Timeout Period before the TIMER pin reaches 1.72V, the LM25061 returns to the normal operating mode and CT is discharged by the 2.5 µA current sink. If the TIMER pin reaches 1.72V during the Fault Timeout Period, Q1 is switched off by a 2 mA pull-down current at the GATE pin. The subsequent restart procedure then depends on which version of the LM25061 is in use. The LM25061-1 latches the GATE pin low at the end of the Fault Timeout Period. CT is then discharged to ground by the 2.5 µA fault current sink. The GATE pin is held low by the 2 mA pull-down current until a power up sequence is externally initiated by cycling the input voltage (VSYS), or momentarily pulling the UVLO pin below its threshold with an open-collector or open-drain device as shown in Figure 24. The voltage at the TIMER pin must be less than 0.3V for the restart procedure to be effective. Figure 24. Latched Fault Restart Control Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM25061 11 LM25061 SNVS611E – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com The LM25061-2 provides an automatic restart sequence which consists of the TIMER pin cycling between 1.72V and 1V seven times after the Fault Timeout Period, as shown in Figure 25. The period of each cycle is determined by the 80 µA charging current, and the 2.5 µA discharge current, and the value of the capacitor CT. When the TIMER pin reaches 0.3V during the eighth high-to-low ramp, the 20 µA current source at the GATE pin turns on Q1. If the fault condition is still present, the Fault Timeout Period and the restart cycle repeat. The Fault Timeout Period during restart cycles is approximately 18% shorter than the initial fault timeout period which initiated the restart cycle. This is due to the fact that the TIMER pin transitions from 0.3V to 1.72V after each restart time, rather than from ground. Fault Detection ILIMIT Load Current 20 PA Gate Charge 2 mA pulldown GATE Pin 2.5 PA 1.72V 80 PA TIMER Pin 1V 1 Fault Timeout Period 2 3 7 8 0.3V tRESTART Figure 25. Restart Sequence (LM25061-2) Under-Voltage Lock-Out (UVLO) The series pass MOSFET (Q1) is enabled when the input supply voltage (VSYS) is greater than the programmable under-voltage lockout (UVLO) level. Typically the UVLO level at VSYS is set with a resistor divider (R1-R2) as shown in Figure 21. Refering to the Block Diagram when VSYS is below the UVLO level, the internal 20 µA current source at UVLO is enabled, and Q1 is held off by the 2 mA pull-down current at the GATE pin. As VSYS is increased, raising the voltage at UVLO above its threshold the 20 µA current source at UVLO is switched off, increasing the voltage at UVLO, providing hysteresis for this threshold. With the UVLO pin above its threshold, Q1 is switched on by the 20 µA current source at the GATE pin if the insertion time delay has expired. See the Applications Section for a procedure to calculate the values of the threshold setting resistors (R1-R2). The minimum possible UVLO level at VSYS can be set by connecting the UVLO pin to VIN. In this case Q1 is enabled after the insertion time. Shutdown Control The load current can be remotely switched off by taking the UVLO pin below its threshold with an open collector or open drain device, as shown in Figure 26. Upon releasing the UVLO pin the LM25061 switches on the load current with in-rush current and power limiting. Figure 26. Shutdown Control 12 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM25061 LM25061 www.ti.com SNVS611E – FEBRUARY 2011 – REVISED MARCH 2013 Power Good Pin The Power Good indicator pin (PGD) is connected to the drain of an internal N-channel MOSFET capable of sustaining 17V in the off-state, and transients up to 20V. An external pull-up resistor is required at PGD to an appropriate voltage to indicate the status to downstream circuitry. The off-state voltage at the PGD pin can be higher or lower than the voltages at VIN and OUT. The PGD pin switches high when the voltage at the FB pin exceeds its threshold. Typically the output voltage threshold is set with a resistor divider (R3-R4) as shown in Figure 21, although the monitored voltage need not be the output voltage. Any other voltage can be monitored by connecting R3 to that voltage as long as the voltage at the FB pin does not exceed its maximum rating. Referring to the Block Diagram, when the voltage at the FB pin is below its threshold, the internal 22 µA current source at FB is disabled. As the output voltage increases, taking FB above its threshold, the current source is enabled, sourcing current out of the pin, raising the voltage at FB to provide threshold hysteresis. The PGD output is low when the UVLO pin is below its threshold. The PGD output is high when the voltage at VIN is less than 1.6V. APPLICATION INFORMATION (Refer to Figure 21) CURRENT LIMIT, RS The LM25061 monitors the current in the external MOSFET (Q1) by measuring the voltage across the sense resistor (RS), connected from VIN to SENSE. The required resistor value is calculated from: RS = 50 mV ILIM where • ILIM is the desired current limit threshold (1) If the voltage across RS reaches 50 mV, the current limit circuit modulates the gate of Q1 to regulate the current at ILIM. While the current limiting circuit is active, the fault timer is active as described in the Fault Timer & Restart section. For proper operation, RS must be no larger than 200 mΩ. While the maximum load current in normal operation can be used to determine the required power rating for resistor RS, basing it on the current limit value provides a more reliable design since the circuit can operate near the current limit threshold continuously. The resistor’s surge capability must also be considered since the circuit breaker threshold is approximately twice the current limit threshold. Connections from RS to the LM25061 should be made using Kelvin techniques. In the suggested layout of Figure 27 the small pads at the lower corners of the sense resistor connect only to the sense resistor terminals, and not to the traces carrying the high current. With this technique, only the voltage across the sense resistor is applied to VIN and SENSE, eliminating the voltage drop across the high current solder connections. HIGH CURRENT PATH FROM SYSTEM INPUT VOLTAGE TO MOSFET'S DRAIN SENSE RESISTOR RS SENSE VIN 3 4 LM25061 5 10 9 8 7 6 Figure 27. Sense Resistor Connections Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM25061 13 LM25061 SNVS611E – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com POWER LIMIT THRESHOLD The LM25061 determines the power dissipation in the external MOSFET (Q1) by monitoring the drain current (the current in RS), and the VDS of Q1 (SENSE to OUT pins). The resistor at the PWR pin (RPWR) sets the maximum power dissipation for Q1, and is calculated from the following equation: RPWR = 2.32 x 105 x RS x PFET(LIM) where • • PFET(LIM) is the desired power limit threshold for Q1 RS is the current sense resistor described in the Current Limit section (2) For example, if RS is 10 mΩ , and the desired power limit threshold is 20W, RPWR calculates to 46.4 kΩ. If Q1’s power dissipation reaches the threshold Q1’s gate is modulated to regulate the load current, keeping Q1’s power from exceeding the threshold. For proper operation of the power limiting feature, RPWR must be ≤150 kΩ. While the power limiting circuit is active, the fault timer is active as described in the Fault Timer & Restart section. Typically, power limit is reached during startup, or if the output voltage falls due to a severe overload or short circuit. The programmed maximum power dissipation should have a reasonable margin from the maximum power defined by the FET's SOA chart if the LM25061-2 is used since the FET will be repeatedly stressed during fault restart cycles. The FET manufacturer should be consulted for guidelines. If the application does not require use of the power limit function the PWR pin can be left open. The accuracy of the power limit function at turn-on may degrade if a very low value power dissipation limit is set. The reason for this caution is that the voltage across the sense resistor, which is monitored and regulated by the power limit circuit, is lowest at turn-on when the regulated current is at minimum. The voltage across the sense resistor during power limit can be expressed as follows: RS x PFET(LIM) RPWR VSENSE = IL x RS = = 5 VDS 2.32 x 10 x VDS where • • IL is the current in RS VDS is the voltage across Q1 (3) For example, if the power limit is set at 20W with RS = 10 mohms, and VDS = 15V the sense resistor voltage calculates to 13.3 mV, which is comfortably regulated by the LM25061. However, if a lower power limit is set lower (e.g., 2W), the sense resistor voltage calculates to 1.33 mV. At this low level noise and offsets within the LM25061 may degrade the power limit accuracy. To maintain accuracy, the sense resistor voltage should not be less than 5 mV. TURN-ON TIME The output turn-on time depends on whether the LM25061 operates in current limit, or in both power limit and current limit, during turn-on. A) Turn-on with current limit only: The current limit threshold (ILIM) is determined by the current sense resistor (RS). If the current limit threshold is less than the current defined by the power limit threshold at maximum VDS the circuit operates at the current limit threshold only during turn-on. Referring to Figure 30a, as the load current reaches ILIM, the gate-to-source voltage is controlled at VGSL to maintain the current at ILIM. As the output voltage reaches its final value, (VDS ≊ 0V) the drain current reduces to its normal operating value. The time for the OUT pin voltage to transition from zero volts to VSYS is equal to: VSYS x CL tON = ILIM where • 14 CL is the load capacitance (4) Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM25061 LM25061 www.ti.com SNVS611E – FEBRUARY 2011 – REVISED MARCH 2013 For example, if VSYS = 12V, CL = 1000 µF, and ILIM = 1A, tON calculates to 12 ms. The maximum instantaneous power dissipated in the MOSFET is 12W. This calculation assumes the time from t1 to t2 in Figure 30a is small compared to tON, and the load does not draw any current until after the output voltage has reached its final value, (Figure 28). If the load draws current during the turn-on sequence (Figure 29), the turn-on time is longer than the above calculation, and is approximately equal to: tON = -(RL x CL) x In (ILIM x RL) - VSYS (ILIM x RL) where • RL is the load resistance (5) The Fault Timeout Period must be set longer than tON to prevent a fault shutdown before the turn-on sequence is complete. RS Q1 VSYS OUT PGD VIN LM25061 CL RL GND GND Figure 28. No Load Current During Turn-On RS Q1 VSYS OUT VIN CL PGD LM25061 RL GND GND Figure 29. Load Draws Current During Turn-On B) Turn-on with power limit and current limit: The maximum allowed power dissipation in Q1 (PFET(LIM)) is defined by the resistor at the PWR pin, and the current sense resistor RS. See the Power Limit Threshold section. If the current limit threshold (ILIM) is higher than the current defined by the power limit threshold at maximum VDS (PFET(LIM)/VSYS) the circuit operates initially in the power limit mode when the VDS of Q1 is high, and then transitions to current limit mode as the current increases to ILIM and VDS decreases. See Figure 30b. Assuming the load (RL) is not connected during turn-on, the time for the output voltage to reach its final value is approximately equal to: tON = CL x VSYS2 2 x PFET(LIM) + CL x PFET(LIM) 2 x ILIM2 (6) For example, if VSYS = 12V, CL = 1000 µF, ILIM = 1A, and PFET(LIM) = 10W, tON calculates to ≊12.2 ms, and the initial current level (IP) is approximately 0.83A. The Fault Timeout Period must be set longer than tON. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM25061 15 LM25061 SNVS611E – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com VSYS VSYS VDS VDS Drain Current ILIM Drain Current ILIM IP 0 0 VGATE VGATE Gate- to - Source Voltage VGSL VGSL VTH VTH t ON 0 0 t3 t1 t2 a) Current Limit Only t ON 0 0 b) Power Limit and Current Limit Figure 30. MOSFET Power Up Waveforms MOSFET SELECTION It is recommended that the external MOSFET (Q1) selection be based on the following criteria: • The BVDSS rating should be greater than the maximum system voltage (VSYS), plus ringing and transients which can occur at VSYS when the circuit card, or adjacent cards, are inserted or removed. • The maximum continuous current rating should be based on the current limit threshold (50 mV/RS), not the maximum load current, since the circuit can operate near the current limit threshold continuously. • The Pulsed Drain Current spec (IDM) must be greater than the current threshold for the circuit breaker function (95 mV/RS). • The SOA (Safe Operating Area) chart of the device, and the thermal properties, should be used to determine the maximum power dissipation threshold set by the RPWR resistor. The programmed maximum power dissipation should have a reasonable margin from the maximum power defined by the FET's SOA chart if the LM25061-2 is used since the FET will be repeatedly stressed during fault restart cycles. The FET manufacturer should be consulted for guidelines. • RDS(on) should be sufficiently low that the power dissipation at maximum load current (IL(max)2 x RDS(on)) does not raise its junction temperature above the manufacturer’s recommendation. If the circuit’s input voltage is at the low end of the LM25061’s operating range (14V), the gate-to-source voltage applied to the MOSFET by the LM25061 is less than 5V, and can approach 1V in a worst case situation. See the graph “ GATE Pin Voltage”. The selected device must have a suitable Gate-to-Source Threshold Voltage. The gate-to-source voltage provided by the LM25061 can be as high as 19.5V at turn-on when the output voltage is zero. At turn-off the reverse gate-to-source voltage will be equal to the output voltage at the instant the GATE pin is pulled low. If the device chosen for Q1 is not rated for these voltages, an external zener diode must be added from its gate to source, with the zener voltage less than the device maximum VGS rating. The zener diode’s working voltage protects the MOSFET during turn-on, and its forward voltage protects the MOSFET during shutoff. The zener diode’s forward current rating must be at least 260 mA to conduct the GATE pull-down current when a circuit breaker condition is detected. TIMER CAPACITOR, CT The TIMER pin capacitor (CT) sets the timing for the insertion time delay, fault timeout period, and restart timing of the LM25061-2. A) Insertion Delay - Upon applying the system voltage (VSYS) to the circuit, the external MOSFET (Q1) is held off during the insertion time (t1 in Figure 23) to allow ringing and transients at VSYS to settle. Since each backplane’s response to a circuit card plug-in is unique, the worst case settling time must be determined for each application. The insertion time starts when VIN reaches the POR threshold, at which time the internal 5.5 µA current source charges CT from 0V to 1.72V. The required capacitor value is calculated from: 16 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM25061 LM25061 www.ti.com CT = SNVS611E – FEBRUARY 2011 – REVISED MARCH 2013 t1 x 5.5 PA = t1 x 3.2 x 10-6 1.72V (7) For example, if the desired insertion delay is 250 ms, CT calculates to 0.8 µF. At the end of the insertion delay, CT is quickly discharged by a 2 mA current sink. B) Fault Timeout Period - During in-rush current limiting or upon detection of a fault condition where the current limit and/or power limit circuits regulate the current through Q1, the fault timer current source (80 µA) switches on to charge CT. The Fault Timeout Period is the time required for the voltage at the TIMER pin to transition from ground to 1.72V, at which time Q1 is switched off. If the LM25061-1 is in use, the required capacitor value is calculated from: tFAULT x 80 PA = tFAULT x 4.65 x 10-5 CT = 1.72V (8) For example, if the desired Fault Timeout Period is 17 ms, CT calculates to 0.8 µF. When the Fault Timeout Period expires, the LM25061-1 latches the GATE pin low until a power-up sequence is initiated by external circuitry. If the LM25061-2 is in use, the Fault Timeout Period during restart cycles is approximately 18% shorter than the initial fault timeout period which initiated the restart cycles since the voltage at the TIMER pin transitions from 0.3V to 1.72V. Since the Fault Timeout Period must always be longer than the turn-on-time, the required capacitor value for the LM25061-2 is calculated using this shorter time period: CT = tFAULT x 80 PA 1.42V = tFAULT x 5.63 x 10 -5 (9) For example, if the desired Fault Timeout Period is 17 ms, CT calculates to 0.96 µF. When the Fault Timeout Period of the LM25061-2 expires, a restart sequence starts as described below (Restart Timiing). Since the LM25061 normally operates in power limit and/or current limit during a power-up sequence, the Fault Timeout Period MUST be longer than the time required for the output voltage to reach its final value. See the Turn-on Time section C) Restart Timing For the LM25061-2, after the Fault Timeout Period described above, CT is discharged by the 2.5 µA current sink to 1.0V. The TIMER pin then cycles through seven additional charge/discharge cycles between 1V and 1.72V as shown in Figure 25. The restart time ends when the TIMER pin voltage reaches 0.3V during the final high-to-low ramp. The restart time, after the Fault Timeout Period, is equal to: tRESTART = CT x 7 x 0.72V 7 x 0.72V 1.42V + + 2.5 PA 80 PA 2.5 PA = CT x 2.65 x 106 (10) For example, if CT = 0.8 µF, tRESTART = 2.12 seconds. At the end of the restart time, Q1 is switched on. If the fault is still present, the fault timeout and restart sequence repeats. The on-time duty cycle of Q1 is approximately 0.67% in this mode. UVLO Programming the UVLO thresholds sets the minimum system voltage to enable the series pass device (Q1). If VSYS is below the UVLO thresholds, Q1 is switched off, denying power to the load. Programmable hysteresis is provided. Option A: The UVLO thresholds are set with two resistors (R1, R2) as shown in Figure 31. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM25061 17 LM25061 SNVS611E – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com VPWR VIN R1 20 PA LM25061 UVLO/ EN 1.17V TIMER AND GATE LOGIC CONTROL R2 GND Figure 31. Programming the UVLO Thresholds The two resistor values are calculated as follows: • Choose the upper and lower UVLO thresholds (VUVH) and (VUVL). R1 = VUVH - VUVL VUV(HYS) = 20 PA 20 PA (11) 1.17V x R1 R2 = VUVL - 1.17V (12) As an example, assume the application requires the following thresholds: VUVH = 8V, VUVL = 7V.Therefore VUV(HYS) = 1V. The resistor values are: R1 = 50 kΩ, R2 = 10 kΩ (13) Where the resistor values are known, the threshold voltages and hysteresis are calculated from the following: VUVH = 1.17V + [R1 x (1.17V + 20 PA)] R2 (14) 1.17V x (R1 + R2) VUVL = R2 (15) (16) VUV(HYS) = R1 x 20 µA Option B: The minimum UVLO level is obtained by connecting the UVLO pin to VIN as shown in Figure 32. Q1 is switched on when the VIN voltage reaches the POR threshold (≊2.6V). VPWR VIN 20 PA LM25061 UVLO/ EN 1.17V TIMER AND GATE LOGIC CONTROL GND Figure 32. UVLO = POR 18 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM25061 LM25061 www.ti.com SNVS611E – FEBRUARY 2011 – REVISED MARCH 2013 POWER GOOD and FB PINS During turn-on, the Power Good pin (PGD) is high until the voltage at VIN increases above ≊1.6V. PGD then switches low, remaining low as the VIN voltage increases. When the voltage at the FB pin increases above its threshold PGD switches high. PGD switches low when the voltage at the FB pin is below the programmed threshold, or if the UVLO pin is taken below its threshold. Setting the output threshold for the PGD pin requires two resistors (R3, R4) as shown in Figure 33. While monitoring the output voltage is shown in Figure 33 , R3 can be connected to any other voltage which requires monitoring. Q1 VOUT OUT SENSE R3 LM25061 1.17V FB R4 22 PA PGD from UVLO GND Figure 33. Programming the PGD Threshold The resistor values are calculated as follows: • Choose the upper and lower threshold (VPGDH) and (VPGDL) at VOUT. R3 = R4 = VPGDH - VPGDL VPGD(HYS) = 22 PA 22 PA (17) 1.17V x R3 (VPGDH - 1.17V) (18) As an example, assume the application requires the following thresholds: VPGDH = 11V, and VPGDL = 10.5V. Therefore VPGD(HYS) = 0.5V. The resistor values are: R3 = 22.7 kΩ, R4 = 2.68 kΩ (19) Where the R3 and R4 resistor values are known, the threshold voltages and hysteresis are calculated from the following: VPGDH = 1.17V x (R3 + R4) R4 VPGDL = 1.17V + [R3 x (20) (1.17V - 22 PA)] R4 (21) (22) VPGD(HYS) = R3 x 22 µA A pull-up resistor is required at PGD as shown in Figure 34. The pull-up voltage (VPGD) can be as high as 17V, and can be higher or lower than the voltages at VIN and OUT. VPGD R PG LM25061 Power Good PGD GND Figure 34. Power Good Output Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM25061 19 LM25061 SNVS611E – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com If a delay is required at PGD, suggested circuits are shown in Figure 35. In Figure 35a, capacitor CPG adds delay to the rising edge, but not to the falling edge. In Figure 35b, the rising edge is delayed by RPG1 + RPG2 and CPG, while the falling edge is delayed a lesser amount by RPG2 and CPG. Adding a diode across RPG2 (Figure 35c) allows for equal delays at the two edges, or a short delay at the rising edge and a long delay at the falling edge. Design-in Procedure The recommended design-in procedure is as follows: • Determine the current limit threshold (ILIM). This threshold must be higher than the normal maximum load current, allowing for tolerances in the current sense resistor value and the LM25061 Current Limit threshold voltage. Use Equation 1 to determine the value for RS. • Determine the maximum allowable power dissipation for the series pass FET (Q1), using the device’s SOA information. Use Equation 2 to determine the value for RPWR. • Determine the value for the timing capacitor at the TIMER pin (CT) using Equation 8 or Equation 9. The fault timeout period (tFAULT) must be longer than the circuit’s turn-on-time. The turn-on time can be estimated using the equations in the TURN-ON TIME section of this data sheet, but should be verified experimentally. Review the resulting insertion time, and restart timing if the LM25061-2 is used. • Choose option A or B from the UVLO section of the Application Information for setting the UVLO threshold and hysteresis. Use the procedure for the appropriate option to determine the resistor values at the UVLO pin. • Choose the appropriate voltage, and pull-up resistor, for the Power Good output. • Determine the resistor values for the FB pin. PC Board Guidelines The following guidelines should be followed when designing the PC board for the LM25061: • Place the LM25061 close to the board’s input connector to minimize trace inductance from the connector to the FET. • Place a small capacitor (1000 pF) directly adjacent to the VIN and GND pins of the LM25061 to help minimize transients which may occur on the input supply line. Transients of several volts can easily occur when the load current is shut off. • The sense resistor (RS) should be close to the LM25061, and connected to it using the Kelvin techniques shown in Figure 27. • The high current path from the board’s input to the load (via Q1), and the return path, should be parallel and close to each other to minimize loop inductance. • The ground connection for the various components around the LM25061 should be connected directly to each other, and to the LM25061’s GND pin, and then connected to the system ground at one point. Do not connect the various component grounds to each other through the high current ground line. • Provide adequate heat sinking for the series pass device (Q1) to help reduce stresses during turn-on and turn-off. • The board’s edge connector can be designed to shut off the LM25061 as the board is removed, before the supply voltage is disconnected from the LM25061. In Figure 36 the voltage at the UVLO pin goes to ground before VSYS is removed from the LM25061 due to the shorter edge connector pin. When the board is inserted into the edge connector, the system voltage is applied to the LM25061’s VIN pin before the UVLO voltage is taken high. 20 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM25061 LM25061 www.ti.com SNVS611E – FEBRUARY 2011 – REVISED MARCH 2013 VPGD VPGD VPGD R PG1 LM25061 LM25061 LM25061 R PG2 Power Good PGD R PG1 R PG1 Power Good PGD CPG GND CPG GND Power Good C PG GND c) Short Delay at Rising Edge and Long Delay at Falling Edge or Equal Delays b) Long delay at rising edge, short delay at falling edge a) Delay Rising Edge Only PGD R PG2 Figure 35. Adding Delay to the Power Good Output Pin GND To Load VSYS Q1 RS LM25061 CIN R1 R2 SENSE GATE VIN OUT UVLO PGD PWR FB GND TIMER To System Ground R4 R3 CARD EDGE CONNECTOR PLUG-IN CARD Figure 36. Recommended Board Connector Design System Considerations 1. Continued proper operation of the LM25061 hot swap circuit requires capacitance be present on the supply side of the connector into which the hot swap circuit is plugged in, as depicted in Figure 22. The capacitor in the “Live Power Source” section is necessary to absorb the transient generated whenever the hot swap circuit shuts off the load current. If the capacitance is not present, inductance in the supply lines will generate a voltage transient at shut-off which can exceed the absolute maximum rating of the LM25061, resulting in its destruction. 2. If the load powered by the LM25061 hot swap circuit has inductive characteristics, a Schottky diode is required across the LM25061’s output, along with some load capacitance. The capacitance and the diode are necessary to limit the negative excursion at the OUT pin when the load current is shut off. If the OUT pin transitions more than 0.3V negative the LM25061 will internally reset, interfering with the latch-off feature of the LM25061-1, or the restart cycle of the LM25061-2. See Figure 37. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM25061 21 LM25061 SNVS611E – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com RS VSYS VOUT Q1 +12V LIVE POWER SOURCE VIN SENSE OUT CL Inductive Load LM25061 GND GND PLUG-IN BOARD Figure 37. Output Diode Required for Inductive Loads 22 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM25061 LM25061 www.ti.com SNVS611E – FEBRUARY 2011 – REVISED MARCH 2013 REVISION HISTORY Changes from Revision D (March 2013) to Revision E • Page Changed layout of National Data Sheet to TI format .......................................................................................................... 22 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM25061 23 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) LM25061PMM-1/NOPB ACTIVE VSSOP DGS 10 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 SXSB LM25061PMM-2/NOPB ACTIVE VSSOP DGS 10 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 SXRB LM25061PMME-1/NOPB ACTIVE VSSOP DGS 10 250 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 SXSB LM25061PMME-2/NOPB ACTIVE VSSOP DGS 10 250 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 SXRB LM25061PMMX-1/NOPB ACTIVE VSSOP DGS 10 3500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 SXSB LM25061PMMX-2/NOPB ACTIVE VSSOP DGS 10 3500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 SXRB (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of