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LM25117, LM25117-Q1
SNVS714F – APRIL 2011 – REVISED AUGUST 2015
LM25117/Q1 Wide Input Range Synchronous Buck Controller With Analog Current
Monitor
1 Features
3 Description
•
The LM25117 is a synchronous buck controller
intended for step-down regulator applications from a
high voltage or widely varying input supply. The
control method is based upon current mode control
utilizing an emulated current ramp. Current mode
control provides inherent line feed-forward, cycle-bycycle current limiting and ease of loop compensation.
The use of an emulated control ramp reduces noise
sensitivity of the pulse-width modulation circuit,
allowing reliable control of very small duty cycles
necessary in high input voltage applications.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
LM25117-Q1 is Qualified for Automotive
Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: -40°C to 125°C
Ambient Operating Temperature Range
Emulated Peak Current Mode Control
Wide Operating Range from 4.5 V to 42 V
Robust 3.3 A Peak Gate Drives
Adaptive Dead-time Output Driver Control
Free-run or Synchronizable Clock up to 750 kHz
Optional Diode Emulation Mode
Programmable Output from 0.8 V
Precision 1.5% Voltage Reference
Analog Current Monitor
Programmable Current Limit
Hiccup Mode Over Current Protection
Programmable Soft-start and Tracking
Programmable Line Undervoltage Lockout
Programmable Switch-over to External Bias
Supply
Thermal Shutdown
The operating frequency is programmable from 50
kHz to 750 kHz. The LM25117 drives external highside and low-side NMOS power switches with
adaptive dead-time control. A user-selectable diode
emulation mode enables discontinuous mode
operation for improved efficiency at light load
conditions. A high voltage bias regulator that allows
external bias supply further improves efficiency. The
LM25117’s unique analog telemetry feature provides
average output current information. Additional
features include thermal shutdown, frequency
synchronization, hiccup mode current limit and
adjustable line undervoltage lockout.
Device Information(1)
PART NUMBER
2 Applications
•
•
•
•
Automotive Infotainment
Industrial DC-DC Motor Drivers
Automotive USB Power
Telecom Server
PACKAGE
BODY SIZE (NOM)
LM25117
HTSSOP (20) PWP
6.50 mm x 4.40 mm
LM25117-Q1
WQFN (24) RTW
4.00 mm x 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Typical Application
VIN
SW
UVLO
VIN
DEMB
VCC
HB
RAMP
LM25117
HO
VOUT
VOUT
VCCDIS
SW
COMP
FB
CM
RT
LO
CS
CSG
RES
SS AGND PGND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM25117, LM25117-Q1
SNVS714F – APRIL 2011 – REVISED AUGUST 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
5
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
5
5
5
6
6
7
8
9
Absolute Maximum Ratings ......................................
ESD Ratings (LM25117) ...........................................
ESD Ratings (LM25117-Q1) .....................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 11
7.1 Overview ................................................................. 11
7.2 Functional Block Diagram ....................................... 12
7.3 Feature Description................................................. 13
7.4 Device Functional Modes........................................ 21
8
Application and Implementation ........................ 22
8.1
8.2
8.3
8.4
Application Information............................................
Typical Applications ...............................................
Detailed Design Procedure .....................................
Application Curves ..................................................
22
22
22
32
9 Power Supply Recommendations...................... 35
10 Layout................................................................... 35
10.1 Layout Guideline ................................................... 35
11 Device and Documentation Support ................. 36
11.1
11.2
11.3
11.4
11.5
Community Resources..........................................
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
36
36
36
36
36
12 Mechanical, Packaging, and Orderable
Information ........................................................... 36
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (March 2013) to Revision F
Page
•
Added Device Information and Pin Configuration and Functions sections, ESD Rating table, Feature Description,
Device Functional Modes, Application and Implementation, Power Supply Recommendations, Layout, Device and
Documentation Support , and Mechanical, Packaging, and Orderable Information sections ................................................ 1
•
Changed µH to µF ................................................................................................................................................................ 29
Changes from Revision D (March 2013) to Revision E
•
2
Page
Changed layout of National Data Sheet to TI format ........................................................................................................... 34
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Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: LM25117 LM25117-Q1
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SNVS714F – APRIL 2011 – REVISED AUGUST 2015
5 Pin Configuration and Functions
PWP Package
20-Pin HTSSOP
Top View
UVLO
1
20
VIN
DEMB
2
19
HB
RES
3
18
HO
SS
4
17
SW
RT
5
16
VCC
15
LO
EP
AGND
6
VCCDIS
7
14
PGND
FB
8
13
CSG
COMP
9
12
CS
CM
10
11
RAMP
UVLO
NC
VIN
NC
HB
HO
RTW Package
24-Pin WQFN
Top View
24
23
22
21
20
19
DEMB
1
18
SW
RES
2
17
NC
SS
3
16
VCC
EP
14
PGND
NC
6
13
CSG
7
8
9
10
11
12
CS
5
RAMP
AGND
CM
LO
COMP
15
FB
4
VCCDIS
RT
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LM25117, LM25117-Q1
SNVS714F – APRIL 2011 – REVISED AUGUST 2015
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Pin Functions
PIN
WQFN
NO.
NAME
TYPE (1)
DESCRIPTION
1
24
UVLO
I
Undervoltage lockout programming pin. If the UVLO pin voltage is below 0.4V, the regulator is
in the shutdown mode with all functions disabled. If the UVLO pin voltage is greater than 0.4V
and less than 1.25V, the regulator is in standby mode with the VCC regulator operational, the
SS pin grounded, and no switching at the HO and LO outputs. If the UVLO pin voltage is above
1.25 V, the SS pin is allowed to ramp and pulse width modulated gate drive signals are
delivered to the HO and LO pins. A 20μA current source is enabled when UVLO exceeds 1.25V
and flows through the external UVLO resistors to provide hysteresis.
2
1
DEMB
I
Optional logic input that enables diode emulation when in the low state. In diode emulation
mode, the low-side NMOS is latched off for the remainder of the PWM cycle after detecting
reverse current flow (current flow from output to ground through the low-side NMOS). When
DEMB is high, diode emulation is disabled allowing current to flow in either direction through the
low-side NMOS. A 50kΩ pull-down resistor internal to the LM25117 holds DEMB pin low and
enables diode emulation if the pin is left floating.
3
2
RES
O
The restart timer pin that configures the hiccup mode current limiting. A capacitor on the RES
pin determines the time the controller remains off before automatically restarting. The hiccup
mode commences when the controller experiences 256 consecutive PWM cycles of cycle-bycycle current limiting. After this occurs, an 10μA current source charges the RES pin capacitor
to the 1.25V threshold and restarts LM25117.
4
3
SS
I
An external capacitor and an internal 10μA current source set the ramp rate of the error
amplifier reference during soft-start. The SS pin is held low when VCC< 4V, UVLO < 1.25V or
during thermal shutdown.
5
4
RT
I
The internal oscillator is programmed with a single resistor between RT and the AGND. The
recommended maximum oscillator frequency is 750kHz. The internal oscillator can be
synchronized to an external clock by coupling a positive pulse into the RT pin through a small
coupling capacitor.
6
5
AGND
G
Analog ground. Return for the internal 0.8V voltage reference and analog circuits.
7
7
VCCDIS
I
Optional input that disables the internal VCC regulator. If VCCDIS>1.25V, the internal VCC
regulator is disabled. VCCDIS has an internal 500kΩ pull-down resistor to enable the VCC
regulator when the pin is left floating. The internal 500kΩ pull-down resistor can be overridden
by pulling VCCDIS above 1.25V with a resistor divider connected to an external bias supply.
8
8
FB
I
Feedback. Inverting input of the internal error amplifier. A resistor divider from the output to this
pin sets the output voltage level. The regulation threshold at the FB pin is 0.8V.
9
9
COMP
O
Output of the internal error amplifier. The loop compensation network should be connected
between this pin and the FB pin.
10
10
CM
O
Current monitor output. Average of the sensed inductor current is provided. Monitor directly
between CM and AGND. CM should be left floating when the pin is not used.
11
11
RAMP
I
PWM ramp signal. An external resistor and capacitor connected between the SW pin, the
RAMP pin and the AGND pin sets the PWM ramp slope. Proper selection of component values
produces a RAMP signal that emulates the AC component of the inductor with a slope
proportional to input supply voltage.
12
12
CS
I
Current sense amplifier input. Connect to the high-side of the current sense resistor.
13
13
CSG
I
Kelvin ground connection to the current sense resistor. Connect directly to the low-side of the
current sense resistor.
14
14
PGND
G
Power ground return pin for low-side NMOS gate driver. Connect directly to the low-side of the
current sense resistor.
15
15
LO
O
Low-side NMOS gate drive output. Connect to the gate of the low-side synchronous NMOS
transistor through a short, low inductance path.
16
16
VCC
P/O/I
Bias supply pin. Locally decouple to PGND using a low ESR/ESL capacitor located as close to
controller as possible.
17
18
SW
I/O
Switching node of the buck regulator. Connect to the bootstrap capacitor, the source terminal of
the high-side NMOS transistor and the drain terminal of the low-side NMOS through a short,
low inductance path.
18
19
HO
O
High-side NMOS gate drive output. Connect to the gate of the high-side NMOS transistor
through a short, low inductance path.
19
20
HB
P
High-side driver supply for the bootstrap gate drive. Connect to the cathode of the external
bootstrap diode and to the bootstrap capacitor. The bootstrap capacitor supplies current to
charge the high-side NMOS gate and should be placed as close to controller as possible.
HTSSO
P NO.
(1)
4
I = Input, O = Output, G = Ground, P = Power
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SNVS714F – APRIL 2011 – REVISED AUGUST 2015
Pin Functions (continued)
PIN
WQFN
NO.
NAME
TYPE (1)
20
22
VIN
P/I
EP
EP
EP
-
Exposed pad of the package. Electrically isolated. Should be soldered to the ground plane to
reduce thermal resistance.
HTSSO
P NO.
DESCRIPTION
Supply voltage input source for the VCC regulator.
6
NC
-
No electrical contact.
17
NC
-
No electrical contact.
21
NC
-
No electrical contact.
23
NC
-
No electrical contact.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
VIN to AGND
-0.3
45
V
SW to AGND
-3.0
45
V
HB to SW
-0.3
15
V
VCC to AGND
(2)
-0.3
15
V
HO to SW
-0.3
HB+0.3
V
LO to AGND
-0.3
VCC+0.3
V
FB, DEMB, RES, VCCDIS, UVLO to AGND
-0.3
15
V
CM, COMP to AGND
(3)
-0.3
7
V
SS, RAMP, RT to AGND
-0.3
7
V
CS, CSG, PGND, to AGND
-0.3
0.3
V
Storage temperature, Tstg
-55
150
°C
Junction Temperature
-40
150
°C
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
See Application and Implementation when input supply voltage is less than the VCC voltage.
These pins are output pins. As such they are not specified to have an external voltage applied.
6.2 ESD Ratings (LM25117)
V(ESD)
(1)
(2)
Electrostatic discharge
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
V
Charged-device model (CDM), per JEDEC specification JESD22- V
C101 (2)
±750
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 ESD Ratings (LM25117-Q1)
V(ESD)
(1)
Human-body model (HBM), per AEC Q100-002
Electrostatic discharge
(1)
Charged-device model (CDM), per AEC Q100-011
VALUE
UNIT
±2000
V
±750
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VIN
(1)
(2)
MIN
MAX
UNIT
4.5
42
V
VCC
4.5
14
V
HB to SW
4.5
14
V
Junction
Temperature
-40
125
°C
(1)
(2)
Recommended Operating Conditions are conditions under which operation of the device is intended to be functional, but does not
ensure specific performance limits. For specifications and test conditions see .Electrical Characteristics
Minimum VIN operating voltage is defined with VCC supplied by the internal HV startup regulator and no external load on VCC. When
VCC is supplied by an external source, minimum VIN operating voltage is 4.5 V.
6.5 Thermal Information
LM25117, LM25117-Q1
THERMAL METRIC (1)
PWP (HTSSOP)
RTW (WQFN)
20 PINS
24 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
40
40
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
4
6
°C/W
(1)
6
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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SNVS714F – APRIL 2011 – REVISED AUGUST 2015
6.6 Electrical Characteristics
Typical limits are for TJ = 25°C only; typical values represent the most likely parametric norm at TJ = 25°C, and are provided
for reference purposes only. Minimum and maximum limits apply over the junction temperature range of –40°C to +125°C.
Unless otherwise specified, the following conditions apply: VVIN = 24 V, VVCCDIS = 0 V, RT = 25 kΩ, no load on LO & HO.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN SUPPLY
IBIAS
VIN Operating Current
ISHUTDOWN
VIN Shutdown Current
(1)
VSS = 0V
4.8
6.2
mA
VSS = 0V, VVCCDIS = 2V
0.4
0.55
mA
VSS = 0V, VUVLO = 0V
16
40
µA
VCC Regulator
VCC(REG)
VCC Regulation
No Load
7.6
8.2
V
VCC Dropout (VIN to VCC)
VVIN = 4.5V, No external load
0.05
0.14
V
VVIN = 5.0V, ICC = 20mA
0.4
0.5
VCC Sourcing Current Limit
IVCC
VCC Operating Current
VVCC = 0V
(1)
VCC Under-voltage Threshold
6.85
30
42
V
mA
VSS = 0V, VVCCDIS = 2V
4.0
5.0
mA
VSS = 0V, VVCCDIS = 2V, VVCC = 14V
5.8
7.3
mA
4.0
4.15
V
VCC Rising
3.75
VCC Under-voltage Hysteresis
0.2
V
VCC Disable
VCCDIS Threshold
VCCDIS Rising
1.22
VCCDIS Hysteresis
VCCDIS Input Current
VVCCDIS = 0V
VCCDIS Pull-down Resistance
1.25
1.29
V
0.06
V
-20
nA
500
kΩ
UVLO
UVLO Threshold
UVLO Rising
1.22
1.25
1.29
V
UVLO Hysteresis Current
VUVLO = 1.4V
15
20
25
µA
UVLO Shutdown Threshold
UVLO Falling
0.23
0.3
V
0.1
V
UVLO Shutdown Hysteresis
Soft Start
ISS
SS Current Source
VSS = 0V
7
SS Pull-down Resistance
10
12
µA
13
24
Ω
800
812
mV
Error Amplifier
VREF
FB Reference Voltage
Measured at FB, FB = COMP
FB Input Bias Current
VFB = 0.8V
788
VOH
COMP Output High Voltage
ISOURCE = 3mA
VOL
COMP Output Low Voltage
ISINK = 3mA
AOL
DC Gain
80
dB
fBW
Unity Gain Bandwidth
3
MHz
1
nA
2.8
V
0.26
V
PWM Comparator
tHO(OFF)
Forced HO Off-time
tON(MIN)
Minimum HO On-time
260
VVIN = 42V
COMP to PWM comparator offset
320
440
ns
100
ns
1.2
V
Oscillator
fSW1
Frequency 1
RT = 25kΩ
180
fSW2
Frequency 2
RT = 10kΩ
430
RT Output Voltage
(1)
200
220
kHz
480
530
kHz
1.25
RT Sync Positive Threshold
2.6
Sync Pulse Width
100
3.2
V
3.95
V
ns
Operating current does not include the current into the RT resistor.
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Electrical Characteristics (continued)
Typical limits are for TJ = 25°C only; typical values represent the most likely parametric norm at TJ = 25°C, and are provided
for reference purposes only. Minimum and maximum limits apply over the junction temperature range of –40°C to +125°C.
Unless otherwise specified, the following conditions apply: VVIN = 24 V, VVCCDIS = 0 V, RT = 25 kΩ, no load on LO & HO.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Current Limit
VCS(TH)
Cycle-by-cycle Sense Voltage
Threshold
VRAMP = 0, CSG to CS
106
120
135
mV
CS Input Bias Current
VCS = 0V
-100
-66
µA
CSG Input Bias Current
VCSG = 0V
-100
-66
µA
Current Sense Amplifier Gain
10
V/V
Hiccup Mode Fault Timer
256
Cycles
IRES
RES Current Source
10
µA
VRES
RES Threshold
RES
RES Rising
1.22
1.25
1.285
V
2.0
1.65
V
Diode Emulation
VIL
DEMB Input Low Threshold
VIH
DEMB Input High Threshold
2.5
V
SW Zero Cross Threshold
2.95
-5
mV
DEMB Input Pull-down Resistance
50
kΩ
Current Monitor
Current Monitor Amplifier Gain
CS to CM
Current Monitor Amplifier Gain
Drift over Temperature
17.5
20.5
23.5
-2
0
+2
%
25
120
mV
Zero Input Offset
V/V
HO Gate Driver
VOHH
HO High-state Voltage Drop
IHO = –100mA, VOHH = VHB - VHO
0.17
0.3
V
VOLH
HO Low-state Voltage Drop
IHO = 100mA, VOLH = VHO - VSW
0.1
0.2
V
HO Rise Time
C-load = 1000pF
(2)
HO Fall Time
C-load = 1000pF
(2)
IOHH
Peak HO Source Current
VHO = 0V, SW = 0V, HB = 7.6V
IOLH
Peak HO Sink Current
VHO = VHB = 7.6V
ns
5
ns
2.2
A
3.3
HB to SW Under-voltage
HB DC Bias Current
6
2.56
HB - SW = 7.6V
A
2.9
3.32
V
65
100
µA
V
LO Gate Driver
VOHL
LO High-state Voltage Drop
ILO = –100mA, VOHL = VCC-VLO
0.17
0.27
VOLL
LO Low-state Voltage Drop
ILO = 100mA, VOLL = VLO
0.1
0.2
LO Rise Time
C-load = 1000pF
(2)
LO Fall Time
C-load = 1000pF
(2)
IOHL
Peak LO Source Current
VLO = 0V
IOLL
Peak LO Sink Current
VLO = 7.6V
3.3
A
Thermal Shutdown
Temperature Rising
165
°C
25
°C
V
6
ns
5
ns
2.5
A
Thermal
TSD
Thermal Shutdown Hysteresis
(2)
High and low reference are 80% and 20% of the pulse amplitude respectively.
6.7 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TDLH
LO fall to HO rise delay
TDHL
HO fall to LO rise delay
8
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TEST CONDITIONS
MIN
No load
TYP
MAX
UNIT
72
ns
71
ns
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6.8 Typical Characteristics
Figure 1. HO Peak Driver Current Vsoutput Voltage
Figure 2. LO Peak Driver Current vs Output Voltage
Figure 3. Driver Dead Time vs VVCC
Figure 4. Driver Dead Time vs Temperature
Figure 5. Forced Ho Off-Time vs Temperature
Figure 6. Switching Frequency vs RT
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Typical Characteristics (continued)
Figure 7. VVCC vs IVCC
Figure 8. VVCC vs VVIN
Figure 9. VCS(TH) vs Temperature
Figure 10. VREF vs Temperature
Figure 12. Error Amp Gain And Phase vs Frequency
Figure 11. VVCC vs Temperature
10
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Typical Characteristics (continued)
Figure 13. VCM vs IOUT
Figure 14. VCM vs VCSG-CS
7 Detailed Description
7.1 Overview
The LM25117 high voltage switching controller features all of the functions necessary to implement an efficient
high voltage buck regulator that operates over a very wide input voltage range. This easy to use controller
integrates high-side and low-side NMOS drivers. The regulator control method is based upon peak current mode
control utilizing an emulated current ramp. Peak current mode control provides inherent line feed-forward, cycleby-cycle current limiting and ease of loop compensation. The use of an emulated control ramp reduces noise
sensitivity of the PWM circuit, allowing reliable processing of the very small duty cycles necessary in high input
voltage applications.
The switching frequency is user programmable up to 750 kHz. The RT pin allows the switching frequency to be
programmed by a single resistor or synchronized to an external clock. Fault protection features include cycle-bycycle and hiccup mode current limiting, thermal shutdown and remote shutdown capability by pulling down UVLO
pin. The UVLO input enables the regulator when the input voltage reaches a user selected threshold and
provides a very low quiescent shutdown current when pulled low. A unique analog telemetry feature provides
averaged output current information, allowing various applications that need either a current monitor or current
control. The functional block diagram and typical application circuit of the LM25117 are shown in Functional
Block Diagram
The device is available in HTSSOP-20 and WQFN-24 (4mm×4mm) package featuring an exposed pad to aid in
thermal dissipation.
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11
12
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SYNC
CSYNC
CSS
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CRES
CHF
RT
RUV1
RUV2
RCOMP CCOMP
CFT
CIN
REF
RES
RES
Current
COMP
FB
SS
RT
+
+
ERR
+ AMP
-
+
+
-
RESTART
TIMER
-
1.2V
+
STANDBY
REF
STANDBY
SS Current
OSCILLATOR/
SYNC DETECTOR
UVLO
Shutdown
Threshold
UVLO
UVLO
Threshold
UVLO Hysteresis
Current
LM25117
+
AGND
CLK
Q
Q
R
S
STANDBY
VCC OFF
HO_ENABLE
+
PGND
HICCUP MODE
FAULT TIMER
256 CYCLES
C/L
Comparator
RES RESET
HICCUP
10uVCS(TH)
+
500 k:
VCCDIS
Threshold
THERMAL
SHUTDOWN
PWM
Comparator
DE_ENABLE
CLK
STANDBY
VCC OFF
RES RESET
STANDBY
VCCDIS
+
50 k:
DE_ENABLE
DIODE
EMULATION
CONTROL
HB
UVLO
-5 mV
CONDITIONER
VCC
CSG
A=2
RAMP
40 k:
CM
CCM
RCM
RCS2
CCS
RCS1
CS
RGH
RGL
CHB
DHB
RS
CVCC
LO
SW
HO
HB
DEMB
VCC
UVLO
VCC
Current Monitor
Amplifier
Current Sense
Amplifier
A=10
LO Driver
+
-
HO Driver
DISABLE
STANDBY
ZCD
Comparator
2.0/2.5V
VCC Regulator
CVIN
LEVEL SHIFT/
ADAPTIVE
TIMER
VCC OFF
LO_ENABLE
HO_ENABLE
DE_ENABLE
VCC OFF
VIN
RVIN
+
-
VIN
QL
QH
CSNB
RSNB
CRAMP
RRAMP
COUT1
LO
RFB1
RFB2
COUT2
VOUT
LM25117, LM25117-Q1
SNVS714F – APRIL 2011 – REVISED AUGUST 2015
www.ti.com
7.2 Functional Block Diagram
Copyright © 2011–2015, Texas Instruments Incorporated
LM25117, LM25117-Q1
www.ti.com
SNVS714F – APRIL 2011 – REVISED AUGUST 2015
7.3 Feature Description
7.3.1 High Voltage Startup Regulator and VCC Disable
The LM25117 contains an internal high voltage bias regulator that provides the VCC bias supply for the PWM
controller and NMOS gate drivers. The VIN pin can be connected to an input voltage source as high as 42V. The
output of the VCC regulator is set to 7.6V. When the input voltage is below the VCC set-point level, the VCC
output tracks the VIN with a small dropout voltage. The output of the VCC regulator is current limited at 30mA
minimum.
Upon power-up, the regulator sources current into the capacitor connected to the VCC pin. The recommended
capacitance range for the pin VCC is 0.47µF to 10µF. When the VCC pin voltage exceeds the VCC UV threshold
and the UVLO pin is greater than UVLO threshold, the HO and LO drivers are enabled and a soft-start sequence
begins. The HO and LO drivers remain enabled until either the VCC pin voltage falls below VCC UV threshold,
the UVLO pin voltage falls below UVLO threshold, hiccup mode is activated or the die temperature exceeds the
thermal shutdown threshold. Enabling/Disabling the IC by controlling UVLO is recommended in most of cases.
An output voltage derived bias supply can be applied to the VCC pin to reduce the controller power dissipation at
higher input voltage. The VCCDIS input can be used to disable the internal VCC regulator when external biasing
is supplied. The externally supplied bias should be coupled to the VCC pin through a diode, preferably a
Schottky diode. If the VCCDIS pin voltage exceeds the VCCDIS threshold, the internal VCC regulator is disabled.
VCCDIS has a 500kΩ internal pull-down resistor to ground for normal operation with no external bias.
The VCC regulator series pass transistor includes a diode between VCC (Anode) and VIN (Cathode) that should
not be forward biased in normal operation. If the voltage of the external bias supply is greater than the VIN pin
voltage, an external blocking diode is required from the input power supply to the VIN pin to prevent the external
bias supply from passing current to the input supply through VCC.
VIN
VIN
LM25117
External
VCC Supply
VCC
Figure 15. VIN Configuration For VVIN
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