LM25143
SNVSC10 – MARCH 2022
LM25143 3.5-V to 42-V Dual Synchronous Buck DC/DC Controller With Ultra-Low IQ
1 Features
2 Applications
•
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Functional Safety-Capable
– Documentation available to aid functional safety
system design
Versatile synchronous buck DC/DC controller
– Wide input voltage range of 3.5 V to 42 V
– 1% accurate, fixed 3.3-V, 5-V, or adjustable
outputs from 0.6 V to 36 V
– 150°C maximum junction temperature
– 4-µA typical shutdown mode current
– 15-µA typical no-load standby current
Two interleaved synchronous buck channels
– Dual channel or single-output multiphase
– 65-ns tON(min) for high VIN/VOUT ratio
– 60-ns tOFF(min) for low dropout
Inherent protection features for robust design
– Shunt or inductor DCR current sensing
– Hiccup mode overcurrent protection
– Independent ENABLE and PGOOD functions
– Adjustable output voltage soft start
– VCC, VDDA, and gate-drive UVLO protection
– Thermal shutdown protection with hysteresis
Optimized for CISPR 11 and CISPR 32 class B
conducted and radiated EMI requirements
– Slew-rate controlled adaptive gate drivers
– Spread spectrum reduces peak emissions
100-kHz to 2.2-MHz switching frequency
– SYNC in and SYNC out capability
– Selectable diode emulation or FPWM modes
6-mm × 6-mm VQFN-40 package
Create a custom design using the LM25143 with
WEBENCH® Power Designer
Personal electronics: computer peripherals
Industrial: 24-V bus systems, factory automation
and control, robotics, power delivery
Enterprise systems: high-performance computing
•
3 Description
The LM25143 is a 42-V DC/DC synchronous buck
controller for high-current single or dual outputs.
Deriving from a family of wide-VIN range controllers,
the device uses an interleaved, stackable, peak
current-mode control architecture for easy loop
compensation, fast transient response, excellent load
and line regulation, and accurate current sharing with
paralleled phases for higher output current. A highside switch minimum on time of 65 ns provides large
step-down ratios, enabling the direct conversion from
12-V or 24-V inputs to low-voltage rails for reduced
system complexity and cost. The LM25143 continues
to operate during input voltage dips as low as 3.5 V, at
nearly 100% duty cycle if needed.
The 15-μA no-load quiescent current with the output
voltage in regulation extends operating run-time in
battery-powered systems. Power the LM25143 from
the output of the switching regulator or another
available source for even lower input quiescent
current and power loss.
Device Information
PART NUMBER
PACKAGE(1)
BODY SIZE (NOM)
LM25143
VQFN (40)
6.00 mm × 6.00 mm
(1)
For all available packages, see the orderable addendum at
the end of the data sheet.
VIN = 3.5 V...42 V
VDDA
CIN
HB1
VOUT1 = 3.3 V
IOUT1 = 12 A
RS1
CO1
VCC
VIN FB1 FB2 MODE
HB2
QH1
QH2
LO1
HO1
HO2
HOL1
HOL2
SW1
SW2
LO1
LOL1
LO2
LOL2
QL1
PGND1
VIN
LM25143
RS2
VOUT2 = 5 V
IOUT2 = 10 A
CO2
QL2
PGND2
EN1
EN2
RT
PG2
PG1
LO2
VIN
SYNCOUT
CS1
VOUT1
DEMB
CS2
VOUT2
COMP1
COMP2
VCCX
AGND SS1 RES SS2 VDDA DITH
* VOUT1 tracks VIN if VIN < 3.7 V
VOUT2 tracks VIN if VIN < 5.4 V
High-Efficiency Dual Step-Down Regulator
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM25143
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SNVSC10 – MARCH 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Description (continued).................................................. 3
6 Device Comparison Table...............................................3
7 Pin Configuration and Functions...................................4
8 Specifications.................................................................. 7
8.1 Absolute Maximum Ratings........................................ 7
8.2 ESD Ratings............................................................... 7
8.3 Recommended Operating Conditions.........................8
8.4 Thermal Information....................................................8
8.5 Electrical Characteristics.............................................9
8.6 Switching Characteristics..........................................12
8.7 Typical Characteristics.............................................. 13
9 Detailed Description......................................................18
9.1 Overview................................................................... 18
9.2 Functional Block Diagram......................................... 19
9.3 Feature Description...................................................20
9.4 Device Functional Modes..........................................32
10 Application and Implementation................................ 33
10.1 Application Information........................................... 33
10.2 Typical Applications................................................ 40
11 Power Supply Recommendations..............................53
12 Layout...........................................................................54
12.1 Layout Guidelines................................................... 54
12.2 Layout Example...................................................... 57
13 Device and Documentation Support..........................59
13.1 Device Support....................................................... 59
13.2 Documentation Support.......................................... 60
13.3 Receiving Notification of Documentation Updates..61
13.4 Support Resources................................................. 61
13.5 Trademarks............................................................. 61
13.6 Electrostatic Discharge Caution..............................61
13.7 Glossary..................................................................61
14 Mechanical, Packaging, and Orderable
Information.................................................................... 61
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
March 2022
*
Initial release
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5 Description (continued)
Several features are included to simplify compliance with CISPR 11 and CISPR 32 EMI requirements. Adaptively
timed, high-current MOSFET gate drivers with adjustable slew rate control minimize body diode conduction
during switching transitions, reducing switching losses and improving thermal and EMI performance at high
input voltage and high switching frequency. To reduce input capacitor ripple current and EMI filter size, 180°
interleaved operation is provided for two outputs. A 90° out-of-phase clock output works well for cascaded,
multi-channel, or multiphase power stages. Resistor-adjustable switching frequency as high as 2.2 MHz can
be synchronized to an external clock source up to 2.5 MHz to eliminate beat frequencies in noise-sensitive
applications. Optional triangular spread spectrum modulation further improves the EMI signature.
Additional features of the LM25143 include 150°C maximum junction temperature operation, user-selectable
diode emulation for lower current consumption at light-load conditions, configurable soft-start functions, opendrain power-good flags for fault reporting and output monitoring, independent enable inputs, monotonic start-up
into prebiased loads, an integrated VCC bias supply regulator with automatic changeover to an external bias
connected at VCCX, programmable hiccup-mode overload protection, and thermal shutdown protection with
automatic recovery. Current is sensed using the inductor DCR for highest efficiency or an optional shunt resistor
for high accuracy.
The LM25143 controller comes in a 6-mm × 6-mm thermally enhanced, 40-pin VQFN package. The wide input
voltage range, low quiescent current consumption, high-temperature operation, cycle-by-cycle current limit, low
EMI signature, and small solution size provide an ideal point-of-load regulator solution for applications requiring
enhanced reliability and durability.
6 Device Comparison Table
Device
Orderable Part Number
Package Drawing
Package Type
Wettable Flanks
Maximum VIN
LM25143
LM25143RHAR
RHA
VQFN
No
42 V
LM5143
LM5143RHAR
RHA
VQFN
No
65 V
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EN2
SYNCOUT
DITH
RT
VDDA
AGND
MODE
DEMB
RES
EN1
40
39
38
37
36
35
34
33
32
31
7 Pin Configuration and Functions
SS2
1
30
SS1
COMP2
2
29
COMP1
FB2
3
28
FB1
CS2
4
27
CS1
VOUT2
5
26
VOUT1
Exposed Pad (EP) on Bottom
Connect to Ground
21
SW1
HB1
HB2
20
10
19
SW2
LOL1
HO1
18
22
LO1
9
17
HO2
PGND1
HOL1
16
23
VCC
8
15
HOL2
VCC
PG1
14
24
PGND2
7
13
PG2
LO2
VIN
12
25
LOL2
6
11
VCCX
Connect the exposed pad on the bottom to AGND and PGND on the PCB.
Figure 7-1. 40-Pin VQFN RHA Package (Top View)
4
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Table 7-1. Pin Functions
PIN
I/O(1)
DESCRIPTION
NAME
NO.
SS2
1
I
Channel 2 soft-start programming pin. An external ceramic capacitor and an internal 20-μA current source
set the ramp rate of the internal error amplifier reference during soft start. Pulling SS2 below 150 mV turns
off the channel 2 gate driver outputs, but all the other functions remain active.
COMP2
2
O
Output of the channel 2 transconductance error amplifier. COMP2 is high impedance in single-output
interleaved or single-output multiphase operation.
FB2
3
I
Feedback input of channel 2. Connect FB2 to VDDA for a 3.3-V output or connect FB2 to AGND for a fixed
5-V output. A resistive divider from VOUT2 to FB2 sets the output voltage level between 0.6 V and 55 V.
The regulation threshold at FB2 is 0.6 V.
CS2
4
I
Channel 2 current sense amplifier input. Connect CS2 to the inductor side of the external current sense
resistor (or to the relevant sense capacitor terminal if inductor DCR current sensing is used) using a
low-current Kelvin connection.
VOUT2
5
I
Output voltage sense and the current sense amplifier input of channel 2. Connect VOUT2 to the output side
of the channel 2 current sense resistor (or to the relevant sense capacitor terminal if inductor DCR current
sensing is used).
VCCX
6
P
Optional input for an external bias supply. If VVCCX > 4.3 V, VCCX is internally connected to VCC and the
internal VCC regulator is disabled. Connect a ceramic capacitor between VCCX and PGND.
PG2
7
O
An open-collector output that goes low if VOUT2 is outside a specified regulation window
HOL2
8
O
Channel 2 high-side gate driver turn-off output
HO2
9
O
Channel 2 high-side gate driver turn-on output
SW2
10
P
Switching node of the channel 2 buck regulator. Connect to the bootstrap capacitor, the source terminal of
the high-side MOSFET, and the drain terminal of the low-side MOSFET.
HB2
11
P
Channel 2 high-side driver supply for the bootstrap gate drive
LOL2
12
O
Channel 2 low-side gate driver turn-off output
LO2
13
O
Channel 2 low-side gate driver turn-on output
PGND2
14
G
Power-ground connection pin for the low-side NMOS gate driver
VCC
15, 16
P
VCC bias supply pin. Pins 15 and 16 must to be connected together on the PCB. Connect ceramic
capacitors between VCC and PGND1 and between VCC and PGND2.
PGND1
17
G
Power-ground connection pin for the low-side NMOS gate driver
LO1
18
O
Channel 1 low-side gate driver turn-on output
LOL1
19
O
Channel 1 low-side gate driver turn-off output
HB1
20
P
Channel 1 high-side driver supply for the bootstrap gate drive
SW1
21
P
Switching node of the channel 1 buck regulator. Connect to the channel 1 bootstrap capacitor, the source
terminal of the high-side MOSFET, and the drain terminal of the low-side MOSFET.
HO1
22
O
Channel 1 high-side gate driver turn-on output
HOL1
23
O
Channel 1 high-side gate driver turn-off output
PG1
24
O
An open-collector output that goes low if VOUT1 is outside a specified regulation window
VIN
25
P
Supply voltage input source for the VCC regulators
VOUT1
26
I
Output voltage sense and the current sense amplifier input of channel 1. Connect VOUT1 to the output side
of the channel 1 current sense resistor (or to the relevant sense capacitor terminal if inductor DCR current
sensing is used).
CS1
27
I
Channel 1 current sense amplifier input. Connect CS1 to the inductor side of the external current sense
resistor (or to the relevant sense capacitor terminal if inductor DCR current sensing is used) using a
low-current Kelvin connection.
FB1
28
I
Feedback input of channel 1. Connect the FB1 pin to VDDA for a 3.3-V output or connect FB1 to AGND for
a 5-V output. A resistive divider from VOUT1 to FB1 sets the output voltage level between 0.6 V and 55 V.
The regulation threshold at FB1 is 0.6 V.
COMP1
29
O
Output of the channel 1 transconductance error amplifier (EA)
SS1
30
I
Channel 1 soft-start programming pin. An external capacitor and an internal 20-μA current source set the
ramp rate of the internal error amplifier reference during soft start. Pulling the SS1 voltage below 150 mV
turns off the channel 1 gate driver outputs, but all the other functions remain active.
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Table 7-1. Pin Functions (continued)
PIN
NO.
EN1
31
I/O(1)
DESCRIPTION
I
An active high input (VEN1 > 2 V) enables output 1. If outputs 1 and 2 are disabled, the LM25143 is in
shutdown mode unless a SYNC signal is present at DEMB. EN1 must never be floating.
RES
32
O
Restart timer pin. An external capacitor configures the hiccup-mode current limiting. A capacitor at the
RES pin determines the time the controller remains off before automatically restarting in hiccup mode. The
two regulator channels operate independently. One channel can operate in normal mode while the other
is in hiccup-mode overload protection. Hiccup mode commences when either channel experiences 512
consecutive PWM cycles with cycle-by-cycle current limiting. Connect RES to VDDA during power up to
disable hiccup-mode protection.
DEMB
33
I
Diode emulation pin. Connect DEMB to AGND to enable diode emulation mode. Connect DEMB to VDDA
to operate the LM25143 in forced PWM (FPWM) mode with continuous conduction at light loads. DEMB can
also be used as a synchronization input to synchronize the internal oscillator to an external clock.
MODE
34
I
Connect MODE to AGND or VDDA for dual-output or interleaved single-output operation, respectively.
This also configures the LM25143 with an EA transconductance of 1200 µS. Connecting a 10-kΩ resistor
between MODE and AGND sets the LM25143 for dual-output operation with an ultra-low IQ mode and an
EA transconductance of 60 µS.
AGND
35
G
Analog ground connection. Ground return for the internal voltage reference and analog circuits
VDDA
36
O
Internal analog bias regulator output. Connect a ceramic decoupling capacitor from VDDA to AGND.
RT
37
I
Frequency programming pin. A resistor from RT to AGND sets the oscillator frequency between 100 kHz
and 2.2 MHz.
DITH
38
I
A capacitor connected between the DITH pin and AGND is charged and discharged with a 20-µA current
source. If dithering is enabled, the voltage on the DITH pin ramps up and down modulating the oscillator
frequency between –5% and +5% of the internal oscillator. Connecting DITH to VDDA during power up
disables the dither feature. DITH is ignored if an external synchronization clock is used.
SYNCOUT
39
O
SYNCOUT is a logic level signal with a rising edge approximately 90° lagging HO2 (or 90° leading HO1).
When the SYNCOUT signal is used to synchronize a second LM25143 controller, all phases are 90° out of
phase.
EN2
40
I
An active high input (VEN2 > 2 V) enables output 2. If outputs 1 and 2 are disabled, the LM25143 is in
shutdown mode unless a SYNC signal is present on DEMB. EN2 must never be floating.
(1)
6
NAME
P = Power, G = Ground, I = Input, O = Output
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8 Specifications
8.1 Absolute Maximum Ratings
Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise noted)(1)
MIN
MAX
VIN to PGND
–0.3
47
SW1, SW2 to PGND
–0.3
47
SW1, SW2 to PGND (20-ns transient)
–5
HB1 to SW1, HB2 to SW1
–0.3
HB1 to SW1, HB2 to SW1 (20-ns transient)
HO1 to SW1, HOL1 to SW1, HO2 to SW2, HOL2 to SW2
Input voltage
UNIT
6.5
–5
–0.3
HO1 to SW1, HOL1 to SW1, HO2 to SW2, HOL2 to SW2 (20-ns transient)
VHB + 0.3
–5
–0.3
LO1, LOL1, LO2, LOL2 to PGND (20-ns transient)
–1.5
VVCC + 0.3
SS1, SS2, COMP1, COMP2, RES, RT, DITH, MODE to AGND
–0.3
VVDDA + 0.3
EN1, EN2 to PGND
–0.3
47
VCC, VCCX, VDDA, PG1, PG2, DEMB, FB1, FB2 to AGND
–0.3
6.5
VOUT1, VOUT2, CS1, CS2
–0.3
47
VOUT1 to CS1, VOUT2 to CS2
–0.3
0.3
PGND to
AGND
–0.3
0.3
V
Operating junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–40
150
°C
(1)
VVCC + 0.3
V
LO1, LOL1, LO2, LOL2 to PGND
Operation outside the Absolute Maximum Ratings may cause permanent damage to the device. Absolute Maximum Ratings do
not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operation
Condition. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be
fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
8.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±1000
Charged-device model (CDM), per ANSI/ESDA/JESD22 JS-002 (2)
±750
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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8.3 Recommended Operating Conditions
Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise noted).
MIN
Input voltage
range
VIN
TJ
VIN to PGND
–0.3
SW1, SW2 to PGND
–0.3
HB1 to SW1, HB2 to SW1
–0.3
HO1 to SW1, HOL1 to SW1, HO2 to SW2, HOL2 to SW2
–0.3
LO1, LOL1, LO2, LOL2 to PGND
–0.3
FB1, FB2, SS1, SS2, COMP1, COMP2, RES, DEMB,
RT, MODE, DITH to AGND
–0.3
EN1, EN2 to PGND
–0.3
VCC, VDDA to PGND
–0.3
VOUT1, VOUT2, CS1, CS2 to PGND
NOM
MAX
UNIT
42
42
5
5.25
VHB + 0.3
5
5.25
5.25
V
42
5
5.25
–0.3
37
PGND to AGND
–0.3
0.3
Operating
junction
temperature
–40
150
°C
8.4 Thermal Information
THERMAL METRIC(1)
40 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
34.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
22.8
°C/W
RθJB
Junction-to-board thermal resistance
9.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.3
°C/W
ΨJB
Junction-to-board characterization parameter
9.4
°C/W
ΨJT
Junction-to-top characterization parameter
0.3
°C/W
(1)
8
RHA (VQFNP)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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8.5 Electrical Characteristics
Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise noted), typical values
correspond to TJ = 25℃, VVIN = 12 V, VVCCX = 5 V, VVOUT1 = 3.3 V, VVOUT2 = 5 V, VEN1 = VEN2 = 5 V, RRT = 10 kΩ, FSW = 2.2
MHz, no load on the drive outputs (HO1, HOL1, LO1, LOL1, HO2, HOL2, LO2, and LOL2).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
7
UNIT
INPUT VOLTAGE (VIN)
ISHUTDOWN
Shutdown mode current
VEN1 = VEN2 = 0 V
3.5
µA
ISTANDBY1
Standby current, channel 1
VEN1 = 5 V, VEN2 = 0 V, VVOUT1 = 3.3 V, in
regulation, no load, not switching, DEMB =
MODE = GND
24
µA
ISTANDBY2
Standby current, channel 2
VEN1 = 0 V, VEN2 = 5 V, VVOUT2 = 5 V, in
regulation, no load, not switching, DEMB =
MODE = GND
25
µA
ISTANDBY3
VEN1 = 5 V, VEN2 = 0 V, VVOUT1 = 3.3 V, in
Standby current, channel 1, ultra-low
regulation, no load, not switching, DEMB =
IQ mode
GND, RMODE = 10 kΩ to GND
16.5
µA
ISTANDBY4
VEN1 = 0 V, VEN2 = 5 V, VVOUT2 = 5 V, in
Standby current, channel 2, ultra-low
regulation, no load, not switching, DEMB =
IQ mode
GND, RMODE = 10 kΩ to GND
21
µA
BIAS REGULATOR (VCC)
VVCC-REG
VCC regulation voltage
IVCC = 100 mA, VVCCX = 0 V
4.7
5
5.3
3.3
3.4
V
VCC-UVLO
VCC UVLO rising threshold
VVCC rising
3.2
VVCC-HYST
VCC UVLO hysteresis
182
mV
IVCC-LIM
VCC sourcing current limit
235
mA
V
ANALOG BIAS (VDDA)
VVDDA-REG
VDDA regulation voltage
VVDDA-UVLO
VDDA UVLO rising threshold
VVCC rising, VVCCX = 0 V
4.75
5
5.25
V
3.1
3.2
3.3
V
VVDDA-HYST
VDDA UVLO hysteresis
VVCCX = 0 V
90
mV
RVDDA
VDDA resistance
VVCCX = 0 V
20
Ω
EXTERNAL BIAS (VCCX)
VVCCX-ON
VCCX(ON) rising threshold
RVCCX
VCCX resistance
VVCCX-HYST
VCCX hysteresis voltage
4.1
VVCCX = 5 V
4.3
4.4
V
1.2
Ω
130
mV
CURRENT LIMIT (CS1, CS2)
VCS1
Current limit threshold 1
Measured from CS1 to VOUT1
66
73
82
mV
VCS2
Current limit threshold 2
Measured from CS2 to VOUT2
66
73
82
mV
tCS-DELAY
CS delay to output
GCS
CS amplifier gain
ICS-BIAS
CS amplifier input bias current
40
11.25
12
ns
12.6
V/V
15
nA
POWER GOOD (PG1, PG2)
PG1UV
PG1 UV trip level
Falling with respect to the regulation voltage
89.5%
92%
94%
PG2UV
PG2 UV trip level
Falling with respect to the regulation voltage
89.5%
PG2OV
PG2 OV trip level
Rising with respect to the regulation voltage
107.5%
110% 112.5%
92%
94%
PG2OV
PG2 OV trip level
Rising with respect to the regulation voltage
107.5%
110% 112.5%
PG1UV-HYST
PG1 UV hysteresis
Rising with respect to the regulation voltage
3.4%
PG1OV-HYST
PG1 OV hysteresis
Rising with respect to the regulation voltage
3.4%
PG2UV-HYST
PG2 UV hysteresis
Rising with respect to the regulation voltage
3.4%
PG2OV-HYST
PG2 OV hysteresis
Rising with respect to the regulation voltage
3.4%
VOL-PG1
PG1 voltage
Open collector, IPG1 = 2 mA
0.4
V
VOL-PG2
PG2 voltage
Open collector, IPG2 = 2 mA
0.4
V
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Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise noted), typical values
correspond to TJ = 25℃, VVIN = 12 V, VVCCX = 5 V, VVOUT1 = 3.3 V, VVOUT2 = 5 V, VEN1 = VEN2 = 5 V, RRT = 10 kΩ, FSW = 2.2
MHz, no load on the drive outputs (HO1, HOL1, LO1, LOL1, HO2, HOL2, LO2, and LOL2).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPG-RISE-DLY
OV filter time
VOUT rising
25
µs
tPG-FALL-DLY
UV filter time
VOUT falling
22
µs
HIGH-SIDE GATE DRIVER (HO1, HO2, HOL1, HOL2)
VHO-LOW
HO low-state output voltage
IHO = 100 mA
0.04
V
VHO-HIGH
HO high-state output voltage
IHO = –100 mA, VHO-HIGH = VHB – VHO
0.09
V
tHO-RISE
HO rise time (10% to 90%)
CLOAD = 2.7 nF
24
ns
tHO-FALL
HO fall time (90% to 10%)
CLOAD = 2.7 nF
24
ns
IHO-SRC
HO peak source current
VHO = VSW = 0 V, VHB = 5 V, VVCCX = 5 V
3.25
A
IHO-SINK
HO peak sink current
VVCCX = 5 V
4.25
A
VBT-UV
BOOT UVLO
VVCC falling
2.45
V
VBT-UV-HYS
BOOT UVLO hysteresis
113
mV
IBOOT
BOOT quiescent current
1.25
µA
LOW-SIDE GATE DRIVER (LO1, LO2, LOL1, LOL2)
VLO-LOW
LO low-state output voltage
ILO = 100 mA
0.04
V
VLO-HIGH
LO high-state output voltage
ILO = –100 mA
0.07
V
tLO-RISE
LO rise time (10% to 90%)
CLOAD = 2.7 nF
4
ns
tLO-FALL
LO fall time (90% to 10%)
CLOAD = 2.7 nF
3
ns
ILO-SOURCE
LO peak source current
VHO = VSW = 0 V, VHB = 5 V, VVCCX = 5 V
3.25
A
ILO-SINK
LO peak sink current
VVCCX = 5 V
4.25
A
20
µA
RESTART (RES)
IRES-SRC
RES current source
VRES-TH
RES threshold
1.2
V
HICCYCLES
HICCUP mode fault
512
cycles
RRES-PD
RES pulldown resistance
5.7
Ω
OUTPUT VOLTAGE SETPOINT (VOUT1, VOUT2)
VOUT33
3.3-V output voltage setpoint
FB = VDDA, VIN = 3.5 V to 65 V
3.267
3.3
3.335
V
VOUT50
5-V output voltage setpoint
FB = AGND, VIN = 5.5 V to 65 V
4.95
5
5.05
V
FEEDBACK (FB1, FB2)
VFB-3V3-SEL
VOUT select threshold 3.3-V output
4.6
V
RFB-5V
Resistance FB to AGND for 5-V
output
VMODE = 0 V or RMODE = 10 kΩ
RFB-EXTRES
Thevenin equivelent resistance
VMODE = 0 V or RMODE = 10 kΩ, VFB < 2 V
VFB2-LOW
Primary mode select logic level low
MODE = VDDA
VFB2-HIGH
Primary mode select logic level high
MODE = VDDA
VFB1-LOW
Diode emulation logic level low
in secondary mode
MODE = FB2 = VDDA
VFB1-HIGH
FPWM logic level high in secondary
mode
MODE = FB2 = VDDA
VFB-REG
Regulated feedback voltage
TJ = –40°C to 125°C
0.594
0.6
1020
1200
500
5
Ω
kΩ
0.8
2
V
V
0.8
2
V
V
0.606
V
ERROR AMPLIFIER (COMP1, COMP2)
gm1
EA transconductance
FB to COMP, RMODE < 5 kΩ to AGND
gm2
EA transconductance, ultra-low IQ
mode
MODE = GND, RMODE = 10 kΩ
IFB
Error amplifier input bias current
VCOMP-CLMP
COMP clamp voltage
10
µs
µs
65
30
VFB = 0 V
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nA
V
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Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise noted), typical values
correspond to TJ = 25℃, VVIN = 12 V, VVCCX = 5 V, VVOUT1 = 3.3 V, VVOUT2 = 5 V, VEN1 = VEN2 = 5 V, RRT = 10 kΩ, FSW = 2.2
MHz, no load on the drive outputs (HO1, HOL1, LO1, LOL1, HO2, HOL2, LO2, and LOL2).
PARAMETER
ICOMP-
TEST CONDITIONS
MIN
TYP
MAX
UNIT
COMP leakage, secondary mode
VCOMP = 1 V, MODE = FB2 = VDDA
10
nA
ICOMP-INTLV
COMP2 leakage, interleaved mode
VCOMP = 1 V, MODE = VDDA, VFB2 = 0 V
10
nA
ICOMP-SRC1
EA source current
VCOMP = 1 V, VFB = 0.4 V, VMODE = 0 V
190
µA
ICOMP-SINK1
EA sink current
VCOMP = 1 V, VFB = 0.8 V, VMODE = 0 V
160
µA
ICOMP-SRC2
EA source current, ultra-low IQ mode
VCOMP = 1 V, VFB = 0.4 V,
RMODE = 10 kΩ to AGND
10
µA
ICOMP-SINK2
EA sink current, ultra-low IQ mode
VCOMP = 1 V, VFB = 0.8 V,
RMODE = 10 kΩ to AGND
12
µA
VSS-OFFSET
EA SS offset with VFB = 0 V
Raise VSS until VCOMP > 300 mV
36
mV
VGS falling, no load
SECOND
ADAPTIVE DEADTIME CONTROL
VGS-DET
VGS detection threshold
2.1
V
tDEAD1
HO off to LO on dead time
22
ns
tDEAD2
LO off to HO on dead time
20
ns
DIODE EMULATION (DEMB)
VDEMB-LOW
DEMB input low threshold
VDEMB_Rising
DEMB input high threshold
0.8
VZC-SW
Zero-cross threshold
VDEMB = 0 V
VZC-SS
Zero-cross threshold soft start
VZC-DIS
Zero-cross threshold disabled
2
V
V
–7
mV
DEMB = VDDA,
50 SW cycles after first HO pulse
–6.1
mV
DEMB = VDDA,
1000 SW cycles after first HO pulse
210
mV
ENABLE (EN1, EN2)
VEN-LOW
EN1/2 low threshold
VVCCX = 0 V
VEN-HIGH-TH
EN1/2 high threshold
VVCCX = 0 V
IEN-LEAK
EN1/2 leakage currernt
EN1, EN2 logic inputs only
0.8
2
V
V
0.05
µA
0.8
V
SWITCHING FREQUENCY (RT)
VRT
RT regulation voltage
10 kΩ < RRT < 220 kΩ
MODE
RMODE-HIGH
Resistance to AGND for ultra-low IQ
5
kΩ
RMODE-LOW
Resistance to AGND for normal IQ
0.5
kΩ
VMODE-LOW
Non-interleaved mode input low
threshold
0.8
V
VMODE-HIGH
Interleaved mode input high
threshold
2
V
SYNCHRONIZATION INPUT (SYNCIN)
VDEMB-LOW
DEMB input low threshold
VDEMB-HIGH
DEMB input high threshold
tSYNC-MIN
DEMB minimum pulse width
VMODE = 0 V or RMODE = 10 kΩ
FSYNCIN
External SYNC frequency range
VIN = 8 V to 18 V, % of the nominal frequency
set by RRT
tSYNCIN-HO1
Delay from DEMB rising to HO1
rising edge
tSYNCINSECOND
tDEMB-FILTER
0.8
V
20
250
ns
–20%
20%
2
Delay from DEMB falling edge to
HO2 rising edge
Secondary mode, MODE = FB2 = VDDA
Delay from DEMB low to diode
emulation enable
VMODE = 0 V or RMODE = 10 kΩ
15
V
120
ns
100
ns
50
µs
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Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise noted), typical values
correspond to TJ = 25℃, VVIN = 12 V, VVCCX = 5 V, VVOUT1 = 3.3 V, VVOUT2 = 5 V, VEN1 = VEN2 = 5 V, RRT = 10 kΩ, FSW = 2.2
MHz, no load on the drive outputs (HO1, HOL1, LO1, LOL1, HO2, HOL2, LO2, and LOL2).
PARAMETER
tAWAKE-FILTER
Maximum SYNC period to maintain
standby state
TEST CONDITIONS
MIN
VEN1 = VEN2 = 0 V
TYP
MAX
27
UNIT
µs
SYNCHRONIZATION OUTPUT (SYNCOUT)
VSYNCOUT-LO SYNCOUT low-state voltage
ISYNCOUT = 16 mA
FSYNCOUT
SYNCOUT frequency
MODE = FB2 = VDDA
0.8
V
0
Hz
tSYNCOUT1
Delay from HO2 rising edge to
SYNCOUT rising edge
VDEMB = 0 V, TS = 1/FSW, FSW set by RRT = 220
kΩ
2.5
µs
tSYNCOUT2
Delay from HO2 rising edge to
SYNCOUT falling edge
VDEMB = 0 V, TS = 1/FSW, FSW set by RRT =
220 kΩ
7.5
µs
DITHER (DITH)
IDITH
Dither source/sink current
21
µA
VDITH-HIGH
Dither high-level threshold
1.25
V
VDITH-LOW
Dither low-level threshold
1.15
V
SOFT START (SS1, SS2)
ISS
Soft-start current
VMODE = 0 V
16
RSS-PD
Soft-start pulldown resistance
VMODE = 0 V
VSS-FB
SS to FB clamp voltage
VCS – VVOUT > 73 mV
ISS-SECOND
SS leakage, secondary mode
ISS-INTLV
SS2 leakage, interleaved mode
21
28
3
µA
Ω
130
mV
VSS = 0.8 V, MODE = FB2 = VDDA
30
nA
VSS = 0.8 V, MODE = VDDA, VFB2 = 0 V
21
nA
175
°C
15
°C
THERMAL SHUTDOWN
TSHD
Thermal shutdown
TSHD-HYS
Thermal shutdown hysteresis
8.6 Switching Characteristics
Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise noted). Typical values
correspond to TJ = 25℃, VVIN = 12 V, VVCCX = 5 V, VVOUT1 = 3.3 V, VVOUT2 = 5 V, VEN1 = VEN2 = 5 V, RRT = 10 kΩ, FSW = 2.2
MHz, no load on the gate driver outputs (HO1, HOL1, LO1, LOL1, HO2, HOL2, LO2, and LOL2).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
195
220
245
UNIT
FSW1
Switching frequency 1
RRT = 100 kΩ
FSW2
Switching frequency 2
RRT = 10 kΩ
2.2
FSW3
Switching frequency 3
RRT = 220 kΩ
100
kHz
SLOPE1
Internal slope compensation 1
RRT = 10 kΩ
557
mV/µs
SLOPE2
Internal slope compensation 2
RRT = 100 kΩ
tOFF(min)
Minimum off time
PHHO1-HO2
Phase between HO1 and HO2
12
64
80
DEMB = MODE = AGND
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180
kHz
MHz
mV/µs
105
ns
°
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8.7 Typical Characteristics
100
100
95
95
90
90
Efficiency (%)
Efficiency (%)
VIN = VEN1 = VEN2 = 12 V, TJ = 25°C, unless otherwise stated
85
80
75
85
80
75
70
70
VIN = 8V
VIN = 12V
VIN = 18V
65
VIN = 8V
VIN = 12V
VIN = 18V
65
60
60
0
1
2
3
4
Load Current (A)
See Figure 10-4.
VOUT = 5 V
5
6
0
7
FSW = 2.1 MHz
1
2
See Figure 10-4.
Figure 8-1. Efficiency Versus Load
3
4
Load Current (A)
VOUT = 3.3 V
5
6
7
FSW = 2.1 MHz
Figure 8-2. Efficiency Versus Load
VIN 2V/DIV
VOUT2 1V/DIV
SW1 5V/DIV
VOUT1 1V/DIV
SW2 5V/DIV
IOUT1 5A/DIV
1ms/DIV
80 ns/DIV
See Figure 10-4.
See Figure 10-4.
Figure 8-4. Start-Up Characteristic
Figure 8-3. Switch Node Voltages
Shutdown Quiescent Current (PA)
6
VOUT1 100mV/DIV
IOUT1 2A/DIV
100Ps/DIV
5
4
3
2
1
0
-50
-25
See Figure 10-4.
Figure 8-5. Load Transient Response
0
25
50
75
100
Junction Temperature (qC)
125
150
D001
VEN1 = VEN2 = 0 V
Figure 8-6. Shutdown Current Versus Temperature
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30
Standby Quiescent Current (PA)
Sleep Quiescent Current (PA)
10
8
6
4
2
0
0
10
20
30
40
Input Voltage (V)
50
60
28
26
24
22
20
-50
70
-25
0
25
50
75
100
Junction Temperature (qC)
D002
VEN1 = VEN2 = 0 V
3.33
Fixed 3.3V Output Voltage Setting (V)
ULIQ Mode Standby Quiescent Current (PA)
D003
Figure 8-8. Channel 1 Standby Current Versus
Temperature
30
25
20
15
10
5
Channel 1
Channel 2
0
-50
-25
0
25
50
75
100
Junction Temperature (qC)
125
D004
3.32
3.31
3.3
3.29
3.28
3.27
-50
150
Figure 8-9. ULIQ Mode Standby Current Versus
Temperature
5.06
0.606
5.04
0.604
5.02
0.602
5
4.98
0
25
50
75
100
Junction Temperature (qC)
125
150
D014
0.6
0.598
0.596
4.96
4.94
-50
-25
Figure 8-10. Fixed 3.3-V Output Voltage (VOUT1)
Versus Temperature
FB Voltage (V)
Fixed 5V Output Voltage Setting (V)
150
VEN2 = 0 V
Figure 8-7. Shutdown Current Versus Input Voltage
-25
0
25
50
75
100
Junction Temperature (qC)
125
150
D013
Figure 8-11. Fixed 5-V Output Voltage (VOUT1)
Versus Temperature
14
125
0.594
-50
-25
0
25
50
75
100
Junction Temperature (qC)
125
150
D015
Figure 8-12. Feedback Voltage Versus Temperature
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100
114
98
112
PG OV Thresholds (%)
PG UV Thresholds (%)
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96
94
92
90
88
86
-50
0
25
50
75
100
Junction Temperature (qC)
125
-25
0
25
50
75
100
Junction Temperature (qC)
125
150
D016
3.4
VCC UVLO Thresholds (V)
VCC Voltage (V)
Rising
Falling
Figure 8-14. PG OV Thresholds Versus
Temperature
5.2
5.1
5
4.9
4.8
3.3
3.2
3.1
3
Rising
Falling
IVCC = 0mA
IVCC = 100mA
-25
0
25
50
75
100
Junction Temperature (qC)
125
2.9
-50
150
-25
0
D005
25
50
75
100
Junction Temperature (qC)
125
150
D007
Figure 8-16. VCC UVLO Thresholds Versus
Temperature
Figure 8-15. VCC Regulation Voltage Versus
Temperature
5.3
350
5.2
300
VDDA Voltage (V)
VCC Current Limit (mA)
104
D016
5.3
250
200
150
100
-50
106
100
-50
150
Figure 8-13. PG UV Thresholds Versus
Temperature
4.7
-50
108
102
Rising
Falling
-25
110
5.1
5
4.9
4.8
-25
0
25
50
75
100
Junction Temperature (qC)
125
150
4.7
-50
D010
Figure 8-17. VCC Current Limit Versus
Temperature
-25
0
25
50
75
100
Junction Temperature (qC)
125
150
D008
Figure 8-18. VDDA Regulation Voltage Versus
Temperature
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4.6
3.3
VCCX Thresholds (V)
VDDA UVLO Thresholds (V)
3.4
3.2
3.1
3
4.4
4.2
4
Rising
Falling
2.9
-50
-25
0
25
50
75
100
Junction Temperature (qC)
125
Rising
Falling
2.5
76
CS Threshold Voltage (V)
77
2
1.5
1
0.5
-25
0
25
50
75
100
Junction Temperature (qC)
125
150
D011
74
73
72
-25
0
D012
25
50
75
100
Junction Temperature (qC)
125
150
D019
Figure 8-22. Current Sense (CS1) Threshold Versus
Temperature
100
Min On and Off Times (ns)
12.4
CS Amplifier Gain (V/V)
125
75
70
-50
150
12.6
12.2
12
11.8
11.6
80
60
40
20
Min On Time
Min Off Time
-25
0
25
50
75
100
Junction Temperature (qC)
125
150
0
-50
D018
Figure 8-23. Current Sense (CS1) Amplifier Gain
Versus Temperature
16
25
50
75
100
Junction Temperature (qC)
71
Figure 8-21. VCCX Switch Resistance Versus
Temperature
11.4
-50
0
Figure 8-20. VCCX On/Off Thresholds Versus
Temperature
3
0
-50
-25
D009
Figure 8-19. VDDA UVLO Thresholds Versus
Temperature
VCCX Switch Rds-on (:)
3.8
-50
150
-25
0
25
50
75
100
Junction Temperature (qC)
125
150
D020
Figure 8-24. Minimum On Time and Off Time (HO1)
Versus Temperature
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2.8
24
2.6
22
SS Current (PA)
BOOT UVLO Thresholds (V)
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2.4
2.2
20
18
Rising
Falling
2
-50
-25
0
25
50
75
100
Junction Temperature (qC)
125
150
16
-50
-25
D021
Figure 8-25. BOOT (HB1) UVLO Thresholds Versus
Temperature
0
25
50
75
100
Junction Temperature (qC)
125
150
D022
Figure 8-26. Soft-Start (SS1) Current Versus
Temperature
250
RT Resistance (k:)
200
150
100
50
0
0
400
800
1200
1600
Switching Frquency (kHz)
2000
D023
Figure 8-27. RT Resistance Versus Switching Frequency
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9 Detailed Description
9.1 Overview
The LM25143 is a dual-phase or dual-channel switching controller that features all of the functions necessary
to implement a high-efficiency synchronous buck power supply operating over a wide input voltage range from
3.5 V to 42 V. The LM25143 is configured to provide a fixed 3.3-V or 5-V output, or an adjustable output
between 0.6 V to 36 V. This easy-to-use controller integrates high-side and low-side MOSFET drivers capable of
sourcing 3.25-A and sinking 4.25-A peak current. Adaptive dead-time control is designed to minimize body diode
conduction during switching transitions.
Current-mode control using a shunt resistor or inductor DCR current sensing provides inherent line feedforward,
cycle-by-cycle peak current limiting, and easy loop compensation. It also supports a wide duty cycle range for
high input voltage and low dropout applications as well as when a high voltage conversion ratio (for example,
10-to-1) is required. The oscillator frequency is user-programmable between 100 kHz to 2.2 MHz, and the
frequency can be synchronized as high as 2.5 MHz by applying an external clock to DEMB.
An external bias supply can be connected to VCCX to maximize efficiency in high input voltage applications.
A user-selectable diode emulation feature enables discontinuous conduction mode (DCM) operation to further
improve efficiency and reduce power dissipation during light-load conditions. Fault protection features include
the following:
•
•
•
•
Current limiting
Thermal shutdown
UVLO
Remote shutdown capability
The LM25143 incorporates features to simplify the compliance with CISPR 11 and CISPR 32 EMI requirements.
An optional spread spectrum frequency modulation (SSFM) technique reduces the peak EMI signature, while
the adaptive gate drivers with slew rate control minimize high-frequency emissions. Finally, 180° out-of-phase
interleaved operation of the two controller channels reduces input filtering and capacitor requirements.
The LM25143 is provided in a 40-pin VQFN package with an exposed pad to aid in thermal dissipation.
18
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9.2 Functional Block Diagram
VIN
SYNCOUT
COMMON
VCCX
BIAS
VREF 0.6V
DEMB/
SYNCIN
CLK1
VCC
PLL &
OSCILLATORS
CLK2
DEM/FPWM
VDDA
22PA
VOUT1
VDDA
CONTROL
`
DITH
DITHER
22PA
20PA
RT amp
HICCUP FAULT
TIMER
512 CYCLES
RESTART
LOGIC
RES
ILIM1/2
800mV
AGND
+
INTERLEAVE
-
ULIQ
DECODER
MODE
RT
HICCUP1/2
CHANNEL 1/2
EN1/2
ILIM1/2
+
CURRENT
LIMIT
75mV
CS1/2
+
VOUT1/2
-
+
GAIN = 12
-
HB1/2
UVLO
SLOPE COMP
3.3V
HB1
RAMP
5V
FB
DECODER
/MUX
DEM/FPWM
COMP1/2 ENABLE
FB1/2
HO1/2
HOL1/2
HICCUP1/2
INTERLEAVE
ERROR
FB1/2
0.660V
+
R
Q
S
Q
SW1/2
VCC
CLK1/2
LEVEL SHIFT
ADAPTIVE
DEADTIME
ULIQ
-
PG
DELAY
25Ps
PWM1/2
+
-
+
+
PGOV
PG1/2
AMPLIFER
-
VREF
PGUV
0.552V
LO1/2
LOL1/2
+
COMP1/2
21PA
_
SS1/2
STANDBY
ILIM1/2
PGND1/2
-
+
125mV
+
±
-
GM
150mV
+
SS1/2
+
SS1/2
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9.3 Feature Description
9.3.1 Input Voltage Range (VIN)
The LM25143 operational input voltage range is from 3.5 V to 42 V. The device is intended for step-down
conversions from 12-V and 24-V supply rails. The application circuit in Figure 9-1 shows all the necessary
components to implement an LM25143-based wide-VIN dual-output step-down regulator using a single supply.
The LM25143 uses an internal LDO subregulator to provide a 5-V VCC bias rail for the gate drive and control
circuits (assuming the input voltage is higher than 5 V plus the necessary subregulator dropout specification).
VIN
CIN
CVCC2
CVCC1
HB1
VCC
VIN
FB1 FB2 MODE
HB2
RHO2
RHO1
VOUT1
RS1
LO1
CO1
HO1
HO2
HOL1
HOL2
SW1
SW2
LO1
LOL1
LO2
LOL2
VOUT2
CO2
LM25143
EN1
EN2
RT
PG2
PG1
SYNC In (optional)
CCOMP1 RCOMP1
RS2
PGND2
PGND1
RRT
LO2
SYNCOUT
CS1
VOUT1
DEMB
CS2
VOUT2
COMP1
COMP2
VCCX
SYNC Out
RCOMP2 CCOMP2
AGND SS1 RES SS2 VDDA DITH
CHF1
CHF2
CSS1 CRES CSS2 CVDD CDITH
Figure 9-1. Dual-Output Regulator Schematic Diagram With an Input Voltage Range of 3.5 V to 42 V
In high input voltage applications, make sure the VIN and SW pins do not exceed their absolute maximum
voltage rating of 47 V during line or load transient events. Voltage excursions that exceed the Absolute Maximum
Ratings can damage the IC. Proceed carefully during PCB layout and use high-quality input bypass capacitors to
minimize voltage overshoot and ringing.
9.3.2 High-Voltage Bias Supply Regulator (VCC, VCCX, VDDA)
The LM25143 contains an internal high-voltage VCC bias regulator that provides the bias supply for the PWM
controller and the gate drivers for the external MOSFETs. The input voltage pin (VIN) can be connected directly
to an input voltage source up to 42 V. However, when the input voltage is below the VCC setpoint level, the VCC
voltage tracks VIN minus a small voltage drop.
The VCC regulator output current limit is 170 mA (minimum). At power up, the regulator sources current into the
capacitors connected at the VCC pin. When the VCC voltage exceeds 3.3 V, both output channels are enabled
(if EN1 and EN2 are connected to a voltage greater than 2 V) and the soft-start sequence begins. Both channels
remain active unless the VCC voltage falls below the VCC falling UVLO threshold of 3.1 V (typical) or EN1 or
EN2 is switched to a low state. The LM25143 has two VCC pins that must be connected together on the PCB.
TI recommends that two VCC capacitors are connected from VCC1 to PGND1 and from VCC2 to PGND2. The
recommended range for each VCC capacitor is from 2.2 µF to 10 µF.
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An internal 5-V linear regulator generates the VDDA bias supply. Bypass VDDA with a 470-nF ceramic capacitor
to achieve a low-noise internal bias rail. Normally, VDDA is 5 V, but there are two operating conditions where it
regulates at 3.3 V. The first is in skip cycle mode when VOUT1 is set to 3.3 V and VOUT2 is disabled. The second
is in a cold-crank start-up where VIN is 3.8 V and VOUT1 is 3.3 V.
Internal power dissipation of the VCC regulator can be minimized by connecting VCCX to a 5-V output at VOUT1
or VOUT2 or to an external 5-V supply. If the VCCX voltage is above 4.3 V, VCCX is internally connected to VCC
and the internal VCC regulator is disabled. Tie VCCX to AGND if it is unused. Never connect VCCX to a voltage
greater than 6.5 V or less than –0.3 V. If an external supply is connected to VCCX to power the LM25143, VIN
must be greater than the external bias voltage during all conditions to avoid damage to the controller.
9.3.3 Enable (EN1, EN2)
The LM25143 contains two enable inputs. EN1 and EN2 facilitate independent start-up and shutdown control of
VOUT1 and VOUT2. The enable pins can be connected to a voltage as high as 70 V. If an enable input is greater
than 2 V, its respective output is enabled. If an enable pin is pulled below 0.4 V, the output is shut down. If both
outputs are disabled, the LM25143 is in a low-IQ shutdown mode with a 4-µA typical current drawn from VIN. TI
does not recommend leaving EN1 or EN2 floating.
9.3.4 Power-Good Monitor (PG1, PG2)
The LM25143 includes output voltage monitoring signals for VOUT1 and VOUT2 to simplify sequencing and
supervision. The power-good function can be used to enable circuits that are supplied by the corresponding
voltage rail or to turn on sequenced supplies. Each power-good output (PG1 and PG2) switches to a high
impedance open-drain state when the corresponding output voltage is in regulation. Each output switches low
when the corresponding output voltage drops below the lower power-good threshold (92% typical) or rises above
the upper power-good threshold (110% typical). A 25-µs deglitch filter prevents false tripping of the power-good
signals during transients. TI recommends pullup resistors of 100 kΩ from PG1 and PG2 to the relevant logic rail.
PG1 and PG2 are asserted low during soft start and when the corresponding buck regulator is disabled by EN1
or EN2.
If the LM25143 is in diode emulation mode (VDEMB = 0 V) and enters sleep mode, the power-good comparators
are turned off to reduce quiescent current consumption. When this occurs, PG1 and PG2 are open or pulled high
(if a pullup resistor is connected) such that output undervoltage or overvoltage events are not detected.
9.3.5 Switching Frequency (RT)
The LM25143 oscillator is programmed by a resistor between RT and AGND to set an oscillator frequency
between 100 kHz to 2.2 MHz. CLK1 is the clock for channel 1 and CLK2 is for channel 2. CLK1 and CLK2 are
180° out of phase. Use Equation 1 to calculate the RT resistance for a given switching frequency.
RRT ª¬k: º¼
22
FSW ª¬MHz º¼
(1)
Under low VIN conditions when either of the on times of the high-side MOSFETs exceeds the programmed
oscillator period, the LM25143 extends the switching period of that channel until the PWM latch is reset by
the current sense ramp exceeding the controller compensation voltage. In such an event, the oscillators (CLK1
and CLK2) operate independently and asynchronously until both channels can maintain output regulation at the
programmed frequency.
The approximate input voltage level where this occurs is given by Equation 2.
VIN(min)
VOUT ˜
t SW
t SW
t OFF(min)
(2)
where
•
tSW is the switching period.
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•
tOFF(min) is the minimum off time of 60 ns.
9.3.6 Clock Synchronization (DEMB)
To synchronize the LM25143 to an external source, apply a logic-level clock signal (greater than 2 V) to DEMB.
The LM25143 can be synchronized to ±20% of the programmed frequency up to a maximum of 2.5 MHz. If there
is an RT resistor and a synchronization signal, the LM25143 ignores the RT resistor and synchronizes to the
external clock. Under low VIN conditions when the minimum off time is reached, the synchronization signal is
ignored, allowing the switching frequency to reduce to maintain output voltage regulation.
9.3.7 Synchronization Out (SYNCOUT)
The SYNCOUT voltage is a logic level signal with a rising edge approximately 90° lagging HO2 (or 90° leading
HO1). When the SYNCOUT signal is used to synchronize a second LM25143 controller, all four phases are 90°
out of phase.
9.3.8 Spread Spectrum Frequency Modulation (DITH)
The LM25143 provides a frequency dithering option that is enabled by connecting a capacitor from DITH to
AGND. This generates a triangular voltage centered at 1.2 V at DITH. See Figure 9-2. The triangular waveform
modulates the oscillator frequency by ±5% of the nominal frequency set by the RT resistance. Use Equation 3
to calculate the required DITH capacitance to set the modulating frequency, FMOD. For the dithering circuit to
effectively attenuate the peak EMI, the modulation rate must be less than 20 kHz for proper operation of the
clock circuit.
(3)
1.25 V
1.2 V
DITH
1.15 V
CDITH
AGND
Figure 9-2. Switching Frequency Dithering
If DITH is connected to VDDA during power up, the dither feature is disabled and cannot be enabled unless VCC
is recycled below the VCC UVLO threshold. If DITH is connected to AGND on power up, CDITH is prevented from
charging, disabling dither. Also, dither is disabled when the LM25143 is synchronized to an external clock.
9.3.9 Configurable Soft Start (SS1, SS2)
The soft-start feature allows the regulator to gradually reach the steady-state operating point, thus reducing
start-up stresses and surges.
The LM25143 features an adjustable soft start that determines the charging time of the output or outputs.
Soft-start limits inrush current as a result of high output capacitance to avoid an overcurrent condition. Stress on
the input supply rail is also reduced.
The LM25143 regulates the FB voltage to the SS voltage or the internal 600-mV reference, whichever is lower.
At the beginning of the soft-start sequence when the SS voltage is 0 V, the internal 21-μA soft-start current
source gradually increases the voltage on an external soft-start capacitor connected to the SS pin, resulting in a
gradual rise of the relevant FB and output voltages. Use Equation 4 to calculate the soft-start capacitance.
22
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CSS (nF)
35 ˜ t SS (ms)
(4)
where
•
tSS is the required soft-start time.
SS can be pulled low with an external circuit to stop switching, but this is not recommended. When the controller
is in FPWM mode (set by connecting DEMB to VDDA), pulling SS low results in COMP being pulled down
internally as well. LO remains on and the low-side MOSFET discharges the output capacitor, resulting in large
negative inductor current. In contrast, the LO gate driver is disabled when the LM25143 internal logic pulls SS
low due to a fault condition.
9.3.10 Output Voltage Setpoint (FB1, FB2)
The LM25143 outputs can be independently configured for one of the two fixed output voltages with no external
feedback resistors, or adjusted to the desired voltage using an external resistor divider. VOUT1 or VOUT2 can be
configured as a 3.3-V output by connecting the corresponding FB pin to VDDA, or a 5-V output by connecting
FB to AGND. The FB1 and FB2 connections (either VDDA or GND) are detected during power up. The
configuration settings are latched and cannot be changed until the LM25143 is powered down with the VCC
voltage decreasing below its falling UVLO threshold, and then powered up again.
Alternatively, the output voltage can be set using external resistive dividers from the output to the relevant
FB pin. The output voltage adjustment range is between 0.6 V and 36 V. The regulation threshold at FB is
0.6 V (VREF). Use Equation 5 to calculate the upper and lower feedback resistors, designated RFB1 and RFB2,
respectively. See Figure 9-3.
RFB1
§ VOUT
¨
© VREF
·
1¸ ˜ RFB2
¹
(5)
The recommended starting value for RFB2 is between 10 kΩ and 20 kΩ.
VIN
LO
VOUT1
VREF
+
SS
+
FB1
CO
RFB1
–
COMP1
RCOMP
RFB2
gm = 1200 S
CCOMP
AGND
CHF
Figure 9-3. Control Loop Error Amplifier
The Thevenin equivalent impedance of the resistive divider connected to the FB pin must be greater than 5 kΩ
for the LM25143 to detect the divider and set the channel to the adjustable output mode.
RTH
RFB1 ˜ RFB2
! 5k:
RFB1 RFB2
(6)
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If a low IQ mode is required, take care when selecting the external resistors. The extra current drawn from the
external divider is added to the LM25143 ISTANDBY current (15 µA typical). The divider current reflected to VIN is
divided down by the ratio of VOUT/VIN. For example, if VOUT is set to 5.55 V with RFB1 equal to 82.5 kΩ and RFB2
equal to 10 kΩ, use Equation 7 to calculate the input current from a 12-V input required to supply the current in
the feedback resistors.
IVIN(DIVIDER)
IVIN
VOUT
V
˜ OUT
RFB1 RFB2 K ˜ VIN
ISTANDBY
IVIN(DIVIDER)
15 $
5.55 V
5.55 V
˜
| 35 $
82.5k: 10k: 80% ˜ 12 V
$
$
(7)
If one output is enabled and the other disabled, the VCC output is in regulation. The HB voltage of the disabled
channel charges to VCC through the bootstrap diode. As a result, the HO driver bias current (approximately 1.5
µA) can increase the output voltage of the disabled channel to approximately 2.2 V. If this is not desired, add a
load resistor (100 kΩ) to the output that is disabled to maintain a low-voltage OFF state.
9.3.11 Minimum Controllable On Time
There are two limitations to the minimum output voltage adjustment range: the LM25143 voltage reference of 0.6
V and the minimum controllable switch-node pulse width, tON(min).
tON(min) effectively limits the voltage step-down conversion ratio of VOUT/VIN at a given switching frequency. For
fixed-frequency PWM operation, the voltage conversion ratio must satisfy Equation 8.
VOUT
! t ON(min) ˜ FSW
VIN
(8)
where
•
•
tON(min) is 65 ns (typical).
FSW is the switching frequency.
If the desired voltage conversion ratio does not meet the above condition, the LM25143 transitions from fixed
switching frequency operation to a pulse-skipping mode to maintain output voltage regulation. For example, if
the desired output voltage is 5 V with an input voltage is 24 V and switching frequency of 2.1 MHz, the voltage
conversion ratio test in Equation 9 is satisfied.
5V
! 65ns ˜ 2.1 MHz
24 V
0.208 ! 0.137
(9)
For wide VIN applications and low output voltages, an alternative is to reduce the LM25143 switching frequency
to meet the requirement of Equation 8.
9.3.12 Error Amplifier and PWM Comparator (FB1, FB2, COMP1, COMP2)
Each channel of the LM25143 has an independent high-gain transconductance amplifier that generates an
error current proportional to the difference between the feedback voltage and an internal precision reference
(0.6 V). The output of the transconductance amplifier is connected to the COMP pin, allowing the user to
provide external control loop compensation. A type-II compensation network is generally recommended for peak
current-mode control.
The amplifier has two gain settings, one is for normal operation with a gm of 1200 µS and the other is for
ultra-low IQ with a gm of 60 µS. For normal operation, connect MODE to AGND. For ultra-low operation IQ,
connect MODE to AGND through a 10-kΩ resistor.
24
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9.3.13 Slope Compensation
The LM25143 provides internal slope compensation for stable operation with peak current-mode control and a
duty cycle greater than 50%. Use Equation 10 to calculate the buck inductance to provide a slope compensation
contribution equal to one times the inductor downslope.
LO-IDEAL ( +
•
•
VOUT (V) ˜ RS (m:)
24 ˜ FSW (MHz)
(10)
A lower inductance value generally increases the peak-to-peak inductor current, which minimizes size and
cost, and improves transient response at the cost of reduced light-load efficiency due to higher cores losses
and peak currents.
A higher inductance value generally decreases the peak-to-peak inductor current, which increases the fullload efficiency by reducing switch peak and RMS currents at the cost of requiring larger output capacitors to
meet load-transient specifications.
9.3.14 Inductor Current Sense (CS1, VOUT1, CS2, VOUT2)
There are two methods to sense the inductor current of the buck power stage. The first uses a current sense
resistor (also known as a shunt) in series with the inductor, and the second avails of the DC resistance of the
inductor (DCR current sensing).
9.3.14.1 Shunt Current Sensing
Figure 9-4 illustrates inductor current sensing using a shunt resistor. This configuration continuously monitors the
inductor current to provide accurate overcurrent protection across the operating temperature range. For optimal
current sense accuracy and overcurrent protection, use a low inductance ±1% tolerance shunt resistor between
the inductor and the output, with a Kelvin connection to the LM25143 current sense amplifier.
If the peak differential current signal sensed from CS to VOUT exceeds the current limit threshold of 73 mV, the
current limit comparator immediately terminates the applicable HO output for cycle-by-cycle current limiting. Use
Equation 11 to calculate the shunt resistance.
RS
VCS
IOUT(CL)
'IL
2
(11)
where
•
•
•
VCS is current sense threshold of 73 mV.
IOUT(CL) is the overcurrent setpoint that is set higher than the maximum load current to avoid tripping the
overcurrent comparator during load transients.
ΔIL is the peak-to-peak inductor ripple current.
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VIN
LO
RS
VOUT1
CO
Current sense
amplifier
VOUT1
CS1
+
CS gain = 12
Figure 9-4. Shunt Current Sensing Implementation
The respective SS voltage is clamped 150 mV above FB during an overcurrent condition for each channel.
Sixteen overcurrent events must occur before the SS clamp is enabled. This makes sure that SS can be pulled
low during brief overcurrent events, preventing output voltage overshoot during recovery.
9.3.14.2 Inductor DCR Current Sensing
For high-power applications that do not require accurate current-limit protection, inductor DCR current sensing
is preferable. This technique provides lossless and continuous monitoring of the inductor current using an RC
sense network in parallel with the inductor. Select an inductor with a low DCR tolerance to achieve a typical
current limit accuracy within the range of 10% to 15% at room temperature. Components RCS and CCS in Figure
9-5 create a low-pass filter across the inductor to enable differential sensing of the voltage drop across the
inductor DCR.
VIN
LO
RDCR
VOUT1
CO
RCS
CCS
Current sense
amplifier
VOUT1
CS1
+
CS gain = 12
Figure 9-5. Inductor DCR Current Sensing Implementation
Use Equation 12 to calculate the voltage drop across the sense capacitor in the s-domain. When the RCSCCS
time constant is equal to LO/RDCR, the voltage developed across the sense capacitor, CCS, is a replica of the
inductor DCR voltage and accurate current sensing is achieved. If the RCSCCS time constant is not equal to the
LO/RDCR time constant, there is a sensing error as follows:
•
•
26
RCSCCS > LO/RDCR → the DC level is correct, but the AC amplitude is attenuated.
RCSCCS < LO/RDCR → the DC level is correct, but the AC amplitude is amplified.
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LO
RDCR
§
˜ RDCR ˜ ¨ IOUT(CL)
1 s ˜ RCS ˜ CCS
©
1 s˜
VCS (s)
'IL ·
¸
2 ¹
(12)
Choose the CCS capacitance greater than or equal to 0.1 μF to maintain a low-impedance sensing network,
thus reducing the susceptibility of noise pickup from the switch node. Carefully observe the guidelines found in
Section 12.1 to make sure that noise and DC errors do not corrupt the differential current sense signals applied
between the CS and VOUT pins.
9.3.15 Hiccup Mode Current Limiting (RES)
The LM25143 includes an optional hiccup mode protection function that is enabled when a capacitor is
connected to the RES pin. In normal operation, the RES capacitor is discharged to ground. If 512 cycles of
cycle-by-cycle current limiting occurs, SS is pulled low and the HO and LO outputs are disabled (see Figure 9-6).
A 20-μA current source begins to charge the RES capacitor. When the RES voltage increases to 1.2 V, RES
is pulled low and the SS capacitor begins to charge. The 512-cycle hiccup counter is reset if four consecutive
switching cycles occur without exceeding the current limit threshold. Separate hiccup counters are provided for
each channel, but the RES pin is shared by both channels. One channel can be in hiccup protection while
the other operates normally. In the event that both channels are in an overcurrent condition triggering hiccup
protection, the last hiccup counter to expire pulls RES low and starts the RES capacitor charging cycle. Both
channels then restart together when V RES = 1.2 V. If RES is connected to VDDA at power up, the hiccup function
is disabled for both channels.
1.2 V RES threshold
Current Limit
detected
RES
IRES = 20 A
0V
SS
ISS = 21 A
VREF = 0.6 V
VFB + 150 mV
tRES
Current Limit persists
during 512 consecutive
clock cycles
Hiccup delay
– no switching
tSS
Soft-start time
Figure 9-6. Hiccup Mode Timing Diagram
Use Equation 13 to calculate the RES capacitance.
CRES (nF) 17 ˜ tRES (ms)
(13)
where
•
tRES is the specified hiccup delay as shown in Figure 9-6.
9.3.16 High-Side and Low-Side Gate Drivers (HO1/2, LO1/2, HOL1/2, LOL1/2)
The LM25143 contains N-channel MOSFET gate drivers and an associated high-side level shifter to drive the
external N-channel MOSFET. The high-side gate driver works in conjunction with an external bootstrap diode,
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DBST, and bootstrap capacitor, CBST. See Figure 9-7. During the conduction interval of the low-side MOSFET, the
SW voltage is approximately 0 V and CBST is charged from VCC through DBST. TI recommends a 0.1-μF ceramic
capacitor connected with short traces between the applicable HB and SW pins.
The LO and HO outputs are controlled with an adaptive dead-time methodology so that both outputs (HO and
LO) are never enabled at the same time, preventing cross conduction. When the controller commands LO to be
enabled, the adaptive dead-time logic first disables HO and waits for the HO-SW voltage to drop below 2.5 V
(typical). LO is then enabled after a small delay (HO fall to LO rising delay). Similarly, the HO turn-on is delayed
until the LO voltage has dropped below 2.5 V. HO is then enabled after a small delay (LO falling to HO rising
delay). This technique ensures adequate dead time for any size N-channel MOSFET component or parallel
MOSFET configurations.
Caution is advised when adding series gate resistors, as this can decrease the effective dead time. Each of
the high-side and low-side drivers has an independent driver source and sink output pins. This allows the
user to adjust drive strength to optimize the switching losses for maximum efficiency and control the slew rate
for reduced EMI signature. The selected N-channel high-side MOSFET determines the appropriate bootstrap
capacitance values, CBST, in Figure 9-7 according to Equation 14.
CBST
QG
'VBST
(14)
where
•
•
QG is the total gate charge of the high-side MOSFET at the applicable gate drive voltage.
ΔVBST is the voltage variation of the high-side MOSFET driver after turn-on.
To determine CBST, choose ΔVBST so that the available gate drive voltage is not significantly impacted. An
acceptable range of ΔVBST is 100 mV to 300 mV. The bootstrap capacitor must be a low-ESR ceramic capacitor,
typically 0.1 µF. Use high-side and low-side MOSFETs with logic level gate threshold voltages.
VCC
DBST
VIN
HB
CIN
HO
High-side
gate driver
HOL
RHO
CBST
Q1
RHOL
LO
SW
VOUT
VCC
LO
Low-side
gate driver
RLO
CVCC
Q2
CO
LOL
PGND
GND
Figure 9-7. Integrated MOSFET Gate Drivers
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9.3.17 Output Configurations (MODE, FB2)
9.3.17.1 Independent Dual-Output Operation
The LM25143 has two outputs that can operate independently. Both VOUT1 and VOUT2 can be set at 3.3 V or 5
V without installing external feedback resistors. Alternatively, set the output voltages between 0.6 V and 36 V
using external feedback resistors based on Equation 5. See Table 9-1 and Figure 9-8. Connect MODE directly to
AGND for independent outputs.
Table 9-1. Output Voltage Settings
Mode
FB1
FB2
VOUT1
AGND
AGND
AGND
AGND
VDDA
VDDA
AGND
VDDA
AGND
AGND
AGND
VDDA
VOUT2
Error Amplifier, gm
5V
5V
1200 µS
3.3 V
3.3 V
1200 µS
3.3 V
5V
1200 µS
5V
3.3 V
1200 µS
AGND
Rdivider
Rdivider
0.6 V to 36 V
0.6 V to 36 V
1200 µS
10 kΩ to AGND
AGND
AGND
5V
5V
60 µS
10 kΩ to AGND
VDDA
VDDA
3.3 V
3.3 V
60 µS
10 kΩ to AGND
VDDA
AGND
3.3 V
5V
60 µS
10 kΩ to AGND
AGND
VDDA
5V
3.3 V
60 µS
10 kΩ to AGND
Rdivider
Rdivider
0.6 V to 36 V
0.6 V to 36 V
60 µS
VIN
CIN
CVCC2
CVCC1
HB1
VCC
VIN
FB1 FB2 MODE
HB2
RHO2
RHO1
VOUT1
RS1
LO1
CO1
HO1
HO2
HOL1
HOL2
SW1
SW2
LO1
LOL1
LO2
LOL2
VOUT2
CO2
LM25143
EN1
EN2
RT
PG2
PG1
SYNC In (optional)
CCOMP1 RCOMP1
RS2
PGND2
PGND1
RRT
LO2
SYNCOUT
CS1
VOUT1
DEMB
SYNC Out
CS2
VOUT2
VCCX
COMP1
RCOMP2 CCOMP2
COMP2
AGND SS1 RES SS2 VDDA DITH
CHF1
CHF2
CSS1 CRES CSS2 CVDD CDITH
Figure 9-8. Regulator Schematic Configured for Independent Dual Outputs
9.3.17.2 Single-Output Interleaved Operation
Connect the MODE to VDDA and FB2 to AGND to configure the LM25143 for interleaved operation. This
disables the channel 2 error amplifier and places it in a high impedance state. The controller is then in a
primary and secondary configuration. Connect COMP1 to COMP2 and SS1 to SS2. Connect FB1 to VDDA for a
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3.3-V output and to AGND for a 5-V output. Connect FB1 to an external feedback divider for an output voltage
between 0.6 V to 36 V. See Table 9-2 and Figure 9-9.
The LM25143 in single-output interleaved operation does not support phase shedding when the output voltage is
set between 0.6 V to 1.5 V.
Table 9-2. Single-Output Interleaved Operation
Mode
FB1
FB2
Output Setpoint
VDDA
AGND
AGND
5V
VDDA
VDDA
AGND
3.3 V
VDDA
Rdivider
AGND
0.6 V to 36 V
VIN
CIN
VDDA
VDDA
CVCC2
CVCC1
VCC
VIN FB1
FB2
MODE
HB1
HB2
HO1
HO2
HOL1
HOL2
SW1
SW2
LO1
LOL1
LO2
LOL2
RHO2
RHO1
RS1
LO1
CO1
VOUT
RS2
CO2
PGND2
PGND1
LM25143
EN1
EN2
RT
RRT
LO2
PG2
PG1
SYNCOUT
CS1
VOUT1
SYNC Out
CS2
VOUT2
DEMB
VCCX
CCOMP RCOMP
COMP1
COMP2
CVCCX
AGND SS1 SS2 RES VDDA DITH
CHF
CSS
CDITH
CRES CVDD
Figure 9-9. Two-Phase Regulator Schematic Configured for Single-Output Interleaved Operation
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9.3.17.3 Single-Output Multiphase Operation
To configure the LM25143 for multiphase operation (three or four phases), two LM25143 controllers are required.
See Figure 9-10. Configure the first controller (CNTRL1) as a primary and the second controller (CNTRL2) as
a secondary. To configure the second controller as a secondary, connect the MODE and FB2 pins to VDDA.
This disables both feedback error amplifiers of the secondary controller, placing them in a high-impedance state.
Connect COMP1 and COMP2 of the primary and secondary together. Connect SS1 and SS2 of the primary
and secondary together. Connect SYNCOUT of the primary controller to DEMB (SYNCIN) of the secondary. The
SYNCOUT of the primary controller is 90° out-of-phase and facilitates interleaved operation. RT is not used for
the oscillator when the LM25143 is in secondary mode but instead used for slope compensation. Therefore,
select the RT resistance to be the same as that of the primary. The oscillator is derived from the primary
controller. FPWM or DEM mode for the secondary is set by connecting its FB1 to VDDA or AGND, respectively.
FPWM or DEM mode of the primary controller is set by its DEMB pin. See Table 9-3.
The LM25143 in single-output multiphase operation does not support phase shedding when the output voltage is
set between 0.6 V to 1.5 V.
See the Benefits of a Multiphase Buck Converter White Paper and Multiphase Buck Design From Start to Finish
Application Report for more information.
Table 9-3. Single-Output Multiphase Operation
Mode
FB1 (Secondary)
FB2 (Secondary)
DEM or FPWM (Secondary)
VDDA
AGND
VDDA
DEM
VDDA
VDDA
VDDA
FPWM
VIN
VIN
CIN
VDDA
CIN
VDDA
HB1
VCC
VIN FB1
FB2
MODE
LO1
CO1
RHO2
VCC
VIN FB1
FB2
MODE
HB2
RHO4
RHO3
HO1
HO2
HO1
HO2
HOL1
HOL2
HOL1
HOL2
SW1
SW2
SW1
SW2
LO1
LOL1
LO2
LOL2
LO1
LOL1
LO2
LOL2
PGND1
LM25143
RT
RS3
RS2
LO3
CO2 CO3
PGND1
RT
PG2
RRT2
SYNCOUT
CS1
VOUT1
DEMB
CS2
VOUT2
COMP1
COMP2
VCCX
CCOMP RCOMP
CVCCX1
PG1
LO4
RS4
VOUT
CO4
PGND2
LM25143
EN1
EN2
CNTRL1
Primary/Secondary
PG1
LO2
PGND2
EN1
RRT1
CVCC4
HB1
HB2
RHO1
RS1
VDDA VDDA VDDA
CVCC3
CVCC2
CVCC1
EN2
CNTRL2
Secondary
PG2
SYNCOUT
CS1
VOUT1
DEMB
CS2
VOUT2
COMP1
COMP2
VCCX
CVCCX2
AGND SS1 SS2 RES VDDA DITH
AGND SS1 SS2 RES VDDA DITH
CHF
CSS
CRES1 CVDD1 CDITH
CRES2 CVDD2
Figure 9-10. Multiphase Regulator Schematic Configured for Single-Output Interleaved Operation
Note
A design with five or more phases (using three or more LM25143 controllers) is feasible when
appropriately phase-shifted clock signals are available. For example, a 6-phase design requires
three LM25143 controllers with 0°, 60°, and 120° external SYNC signals to achieve the ideal phase
separation of 360° divided by the total number of phases.
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9.4 Device Functional Modes
9.4.1 Standby Modes
The LM25143 operates with peak current-mode control such that the compensation voltage is proportional to the
peak inductor current. During no-load or light-load conditions, the output capacitor discharges very slowly. As
a result, the compensation voltage does not demand driver output pulses on a cycle-by-cycle basis. When the
LM25143 controller detects 16 missed switching cycles, it enters standby mode and switches to a low IQ state
to reduce the current drawn from the input. For the LM25143 to go into standby mode, the controller must be
programmed for diode emulation (VDEMB < 0.4 V).
There are two standby modes: ultra-low IQ and normal mode. To enter ultra-low IQ mode, connect MODE to
AGND through a 10-kΩ resistor. In ultra-low IQ mode, the transconductance amplifier gain is reduced from 1200
µS to 60 µS. The typical ultra-low IQ is 15 μA with channel 1 set to 3.3 V and the channel 2 disabled. If ultra-low
IQ is not required, connect MODE to AGND. In normal mode, the IQ is 25 μA with channel 1 set to 3.3 V and the
second channel disabled.
9.4.2 Diode Emulation Mode
A fully synchronous buck regulator implemented with a low-side synchronous MOSFET rather than a diode
has the capability to sink negative current from the output during light-load, overvoltage, and prebias start-up
conditions. The LM25143 provides a diode emulation feature that can be enabled to prevent reverse (drainto-source) current flow in the low-side MOSFET. When configured for diode emulation (DEM), the low-side
MOSFET is switched off when reverse current flow is detected by sensing of the applicable SW voltage using
a zero-cross comparator. The benefit of this configuration is lower power loss at light-load conditions; the
disadvantage being slower light-load transient response.
The diode emulation feature is configured with the DEMB pin. To enable diode emulation and thus achieve
discontinuous conduction mode (DCM) operation at light loads, connect DEMB to AGND. If FPWM or continuous
conduction mode (CCM) operation is desired, tie DEMB to VDDA. See Table 9-4. Note that diode emulation is
automatically engaged to prevent reverse current flow during a prebias start-up in FPWM. A gradual change
from DCM to CCM operation provides monotonic start-up performance.
Table 9-4. DEMB Settings
DEMB
FPWM/DEM
VDDA
FPWM
AGND
DEM
External clock
FPWM
9.4.3 Thermal Shutdown
The LM25143 includes an internal junction temperature monitor. If the temperature exceeds 175°C (typical),
thermal shutdown occurs. When entering thermal shutdown, the device:
1.
2.
3.
4.
Turns off the high-side and low-side MOSFETs
Pulls SS1/2 and PG1/2 low
Turns off the VCC regulator
Initiates a soft-start sequence when the die temperature decreases by the thermal shutdown hysteresis of
15°C (typical)
This is a non-latching protection, and as such, the device cycles into and out of thermal shutdown if the fault
persists.
32
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10 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
10.1 Application Information
The LM25143 is a synchronous buck controller used to convert a higher input voltage to two lower output
voltages. The following sections discuss the design procedure for a dual-output implementation using a specific
circuit design example. To expedite and streamline the process of designing of a LM25143-based regulator, a
comprehensive LM25143 Quickstart Calculator is available for download to assist the designer with component
selection for a given application.
10.1.1 Power Train Components
A comprehensive understanding of the buck regulator power train components is critical to successfully
completing a synchronous buck regulator design. The subsequent subsections discuss the following:
•
•
•
•
Output inductor
Input and output capacitors
Power MOSFETs
EMI input filter
10.1.1.1 Buck Inductor
For most applications, choose a buck inductance such that the inductor ripple current, ΔIL, is between 30% to
50% of the maximum DC output current at nominal input voltage. Choose the inductance using Equation 15
based on a peak inductor current given by Equation 16.
LO
IL(peak)
VOUT §
VOUT ·
˜ ¨1
¸
'IL ˜ FSW ©
VIN ¹
IOUT
(15)
'IL
2
(16)
Check the inductor data sheet to make sure that the saturation current of the inductor is well above the peak
inductor current of a particular design. Ferrite designs have very low core loss and are preferred at high
switching frequencies, so design goals can then concentrate on copper loss and preventing saturation. Low
inductor core loss is evidenced by reduced no-load input current and higher light-load efficiency. However, ferrite
core materials exhibit a hard saturation characteristic and the inductance collapses abruptly when the saturation
current is exceeded. This results in an abrupt increase in inductor ripple current and higher output voltage ripple,
not to mention reduced efficiency and compromised reliability. Note that the saturation current of an inductor
generally decreases as its core temperature increases. Of course, accurate overcurrent protection is key to
avoiding inductor saturation.
10.1.1.2 Output Capacitors
Ordinarily, the output capacitor energy store of the regulator combined with the control loop response are
prescribed to maintain the integrity of the output voltage within the dynamic (transient) tolerance specifications.
The usual boundaries restricting the output capacitor in power management applications are driven by finite
available PCB area, component footprint and profile, and cost. The capacitor parasitics – equivalent series
resistance (ESR) and equivalent series inductance (ESL) – take greater precedence in shaping the load
transient response of the regulator as the load step amplitude and slew rate increase.
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The output capacitor, COUT, filters the inductor ripple current and provides a reservoir of charge for step-load
transient events. Typically, ceramic capacitors provide extremely low ESR to reduce the output voltage ripple
and noise spikes, while tantalum and electrolytic capacitors provide a large bulk capacitance in a relatively
compact footprint for transient loading events.
Based on the static specification of peak-to-peak output voltage ripple denoted by ΔVOUT, choose an output
capacitance that is larger than that given by Equation 17.
'IL
COUT t
8 ˜ FSW 'VOUT
2
RESR ˜ 'IL
2
(17)
Figure 10-1 conceptually illustrates the relevant current waveforms during both load step-up and step-down
transitions. As shown, the large-signal slew rate of the inductor current is limited as the inductor current ramps
to match the new load-current level following a load transient. This slew-rate limiting exacerbates the deficit
of charge in the output capacitor, which must be replenished as quickly as possible during and after the load
step-up transient. Similarly, during and after a load step-down transient, the slew rate limiting of the inductor
current adds to the surplus of charge in the output capacitor that must be depleted as quickly as possible.
IOUT1
IOUT
Inductor current, iL(t)
QC
IOUT2
Load current, iOUT(t)
Inductor current, iL(t)
IOUT2
QC
IOUT
Load current, iOUT(t)
IOUT1
tramp
Figure 10-1. Load Transient Response Representation Showing COUT Charge Surplus or Deficit
In a typical regulator application of 12-V input to low output voltage (for example, 3.3 V), the load-off transient
represents the worst case in terms of output voltage transient deviation. In that conversion ratio application, the
steady-state duty cycle is approximately 28% and the large-signal inductor current slew rate when the duty cycle
collapses to zero is approximately –VOUT/L. Compared to a load-on transient, the inductor current takes much
longer to transition to the required level. The surplus of charge in the output capacitor causes the output voltage
to significantly overshoot. In fact, to deplete this excess charge from the output capacitor as quickly as possible,
the inductor current must ramp below its nominal level following the load step. In this scenario, a large output
capacitance can be advantageously employed to absorb the excess charge and minimize the voltage overshoot.
To meet the dynamic specification of output voltage overshoot during such a load-off transient (denoted as
ΔVOVERSHOOT with step reduction in output current given by ΔIOUT), the output capacitance must be larger than:
LO ˜ 'IOUT
COUT t
VOUT
34
2
'VOVERSHOOT
2
VOUT
2
(18)
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The ESR of a capacitor is provided in the manufacturer’s data sheet either explicitly as a specification or
implicitly in the impedance versus frequency curve. Depending on type, size, and construction, electrolytic
capacitors have significant ESR, 5 mΩ and above, and relatively large ESL, 5 nH to 20 nH. PCB traces
contribute some parasitic resistance and inductance as well. Ceramic output capacitors, on the other hand, have
low ESR and ESL contributions at the switching frequency, and the capacitive impedance component dominates.
However, depending on the package and voltage rating of the ceramic capacitor, the effective capacitance can
drop quite significantly with applied DC voltage and operating temperature.
Ignoring the ESR term in Equation 17 gives a quick estimation of the minimum ceramic capacitance necessary
to meet the output ripple specification. Two to four 47-µF, 10-V, X7R capacitors in 1206 or 1210 footprint is a
common choice for a 5-V output. Use Equation 18 to determine if additional capacitance is necessary to meet
the load-off transient overshoot specification.
A composite implementation of ceramic and electrolytic capacitors highlights the rationale for paralleling
capacitors of dissimilar chemistries yet complementary performance. The frequency response of each capacitor
is accretive in that each capacitor provides desirable performance over a certain portion of the frequency range.
While the ceramic provides excellent mid-frequency and high-frequency decoupling characteristics with its low
ESR and ESL to minimize the switching frequency output ripple, the electrolytic device with its large bulk
capacitance provides low-frequency energy storage to cope with load transient demands.
10.1.1.3 Input Capacitors
Input capacitors are necessary to limit the input ripple voltage to the buck power stage due to switchingfrequency AC currents. TI recommends using X7S or X7R dielectric ceramic capacitors to provide low
impedance and high RMS current rating over a wide temperature range. To minimize the parasitic inductance
in the switching loop, position the input capacitors as close as possible to the drain of the high-side MOSFET
and the source of the low-side MOSFET. Use Equation 19 to calculate the input capacitor RMS current for a
single-channel buck regulator.
ICIN,rms
§
2
D ˜ ¨ IOUT ˜ 1 D
¨
©
2
'IL ·
¸
12 ¸
¹
(19)
The highest input capacitor RMS current occurs at D = 0.5, at which point the RMS current rating of the input
capacitors is greater than half the output current.
Ideally, the DC component of input current is provided by the input voltage source and the AC component by the
input filter capacitors. Neglecting inductor ripple current, the input capacitors source current of amplitude (IOUT −
IIN) during the D interval and sink IIN during the 1−D interval. Thus, the input capacitors conduct a square-wave
current of peak-to-peak amplitude equal to the output current. It follows that the resultant capacitive component
of AC ripple voltage is a triangular waveform. Together with the ESR-related ripple component, use Equation 20
to calculate the peak-to-peak ripple voltage amplitude.
'VIN
IOUT ˜ D ˜ 1 D
FSW ˜ CIN
IOUT ˜ RESR
(20)
Use Equation 21 to calculate the input capacitance required for a particular load current, based on an input
voltage ripple specification of ΔVIN.
CIN t
D ˜ 1 D ˜ IOUT
FSW ˜ 'VIN RESR ˜ IOUT
(21)
Low-ESR ceramic capacitors can be placed in parallel with higher valued bulk capacitance to provide optimized
input filtering for the regulator and damping to mitigate the effects of input parasitic inductance resonating
with high-Q ceramics. One bulk capacitor of sufficiently high current rating and four 10-μF 50-V X7R ceramic
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decoupling capacitors are usually sufficient for 12-V battery automotive applications. Select the input bulk
capacitor based on its ripple current rating and operating temperature range.
Of course, a two-channel buck regulator with 180° out-of-phase interleaved switching provides input ripple
current cancellation and reduced input capacitor current stress. The previous equations represent valid
calculations when one output is disabled and the other output is fully loaded.
10.1.1.4 Power MOSFETs
The choice of power MOSFETs has significant impact on DC/DC regulator performance. A MOSFET with
low on-state resistance, RDS(on), reduces conduction loss, whereas low parasitic capacitances enable faster
transition times and reduced switching loss. Normally, the lower the RDS(on) of a MOSFET, the higher the gate
charge and output charge (QG and QOSS, respectively), and vice versa. As a result, the product of RDS(on) and
QG is commonly specified as a MOSFET figure-of-merit. Low thermal resistance of a given package ensures that
the MOSFET power dissipation does not result in excessive MOSFET die temperature.
The main parameters affecting power MOSFET selection in a LM25143 application are as follows:
•
•
•
•
•
•
RDS(on) at VGS = 5 V
Drain-source voltage rating, BVDSS, is typically 30 V, 40 V, or 60 V, depending on the maximum input voltage.
Gate charge parameters at VGS = 5 V
Output charge, QOSS, at the relevant input voltage
Body diode reverse recovery charge, QRR
Gate threshold voltage, VGS(th), derived from the Miller plateau evident in the QG versus VGS plot in the
MOSFET data sheet. With a Miller plateau voltage typically in the range of 2 V to 3 V, the 5-V gate drive
amplitude of the LM25143 provides an adequately-enhanced MOSFET when on and a margin against Cdv/dt
shoot-through when off.
The MOSFET-related power losses for one channel are summarized by the equations presented in Table 10-1,
where suffixes 1 and 2 represent high-side and low-side MOSFET parameters, respectively. While the influence
of inductor ripple current is considered, second-order loss modes, such as those related to parasitic inductances
and SW node ringing, are not included. Consult the LM25143 Quickstart Calculator. The calculator is available
for download from the LM25143 product folder to assist with power loss calculations.
Table 10-1. MOSFET Power Losses
Power Loss Mode
High-Side MOSFET
Pcond1
MOSFET conduction(2) (3)
MOSFET switching
Psw1
PCoss
Body diode
conduction
Body diode
reverse recovery(5)
(1)
(2)
(3)
(4)
36
VIN ˜ FSW
2
PGate1
MOSFET gate drive(1)
MOSFET output charge(4)
§
2
D ˜ ¨ IOUT
¨
©
ª§
Ǭ IOUT
©
Low-Side MOSFET
2
'IL ·
¸ ˜ RDS(on)1
12 ¸
¹
'IL ·
¸ ˜ tR
2 ¹
§
¨ IOUT
©
Pcond2
'IL · º
¸ ˜ tF »
2 ¹ ¼
PGate2
Eoss1 Eoss2
VCC ˜ FSW ˜ QG2
Negligible
N/A
PcondBD
PRR
2
'IL ·
¸ ˜ RDS(on)2
12 ¸
¹
Negligible
VCC ˜ FSW ˜ QG1
FSW ˜ VIN ˜ Qoss2
§
2
Dc ˜ ¨ IOUT
¨
©
ª§
VF ˜ FSW «¨ IOUT
©
'IL ·
§
¸ ˜ t dt1 ¨ IOUT
2 ¹
©
º
'IL ·
¸ ˜ t dt2 »
2 ¹
¼
VIN ˜ FSW ˜ QRR2
Gate drive loss is apportioned based on the internal gate resistance of the MOSFET, externally added series gate resistance, and the
relevant driver resistance of the LM25143.
MOSFET RDS(on) has a positive temperature coefficient of approximately 4500 ppm/°C. The MOSFET junction temperature, TJ, and its
rise over ambient temperature is dependent upon the device total power dissipation and its thermal impedance. When operating at or
near minimum input voltage, make sure that the MOSFET RDS(on) is rated for the available gate drive voltage.
D' = 1–D is the duty cycle complement.
MOSFET output capacitances, Coss1 and Coss2, are highly non-linear with voltage. These capacitances are charged losslessly by
the inductor current at high-side MOSFET turn-off. During turn-on, however, a current flows from the input to charge the output
capacitance of the low-side MOSFET. Eoss1, the energy of Coss1, is dissipated at turn-on, but this is offset by the stored energy Eoss2 on
Coss2. For more detail, refer to "Comparison of deadtime effects on the performance of DC-DC converters with GaN FETs and silicon
MOSFETs," ECCE 2016.
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MOSFET body diode reverse recovery charge, QRR, depends on many parameters, particularly forward current, current transition
speed, and temperature.
The high-side (control) MOSFET carries the inductor current during the PWM on time (or D interval) and
typically incurs most of the switching losses, so it is imperative to choose a high-side MOSFET that balances
conduction and switching loss contributions. The total power dissipation in the high-side MOSFET is the sum of
the following:
•
•
•
•
Losses due to conduction
Switching (voltage-current overlap)
Output charge
Typically two-thirds of the net loss attributed to body diode reverse recovery
The low-side (synchronous) MOSFET carries the inductor current when the high-side MOSFET is off (or 1–D
interval). The low-side MOSFET switching loss is negligible as it is switched at zero voltage – current just
commutates from the channel to the body diode or vice versa during the transition dead times. The LM25143,
with its adaptive gate drive timing, minimizes body diode conduction losses when both MOSFETs are off. Such
losses scale directly with switching frequency.
In high step-down ratio applications, the low-side MOSFET carries the current for a large portion of the switching
period. Therefore, to attain high efficiency, it is critical to optimize the low-side MOSFET for low RDS(on). In cases
where the conduction loss is too high or the target RDS(on) is lower than available in a single MOSFET, connect
two low-side MOSFETs in parallel. The total power dissipation of the low-side MOSFET is the sum of the losses
due to channel conduction, body diode conduction, and typically one-third of the net loss attributed to body diode
reverse recovery. The LM25143 is well suited to drive TI's portfolio of NexFET™ power MOSFETs.
10.1.1.5 EMI Filter
As expressed by Equation 22, switching regulators exhibit negative input impedance, which is lowest at the
minimum input voltage.
ZIN
VIN(min)
2
PIN
(22)
An underdamped LC filter exhibits a high output impedance at the resonant frequency of the filter. For stability,
the filter output impedance must be less than the absolute value of the converter input impedance.
LIN
Q1
VIN
LO
CD
VOUT
CIN
CF
Q2
RD
CO
GND
GND
Figure 10-2. Buck Regulator With π-Stage EMI Filter
Referencing the filter schematic in Figure 10-2, the EMI filter design steps are as follows:
•
Calculate the required attenuation of the EMI filter at the switching frequency, where CIN represents the
existing capacitance at the input of the switching converter.
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•
•
•
The input filter inductance, LIN, is usually selected between 1 μH and 10 μH, but it can be lower to reduce
losses in a high-current design.
Calculate input filter capacitance, CF.
Calculate damping capacitance, CD, and damping resistance, RD.
By calculating the first harmonic current from the Fourier series of the input current waveform and multiplying it
by the input impedance (the impedance is defined by the existing input capacitor CIN), a formula is derived to
obtain the required attenuation as shown by Equation 23.
Attn
§ IL(PEAK)
1 ·
¸ VMAX
20log ¨ 2
˜ sin S ˜ DMAX ˜
¨ S ˜F ˜ C
¸
1
9
SW
IN
©
¹
(23)
where
•
•
•
•
VMAX is the allowed dBμV noise level for the applicable conducted EMI specification (for example, CISPR 25
Class 5).
CIN is the existing input capacitance of the buck regulator.
DMAX is the maximum duty cycle.
IPEAK is the peak inductor current.
For filter design purposes, the current at the input can be modeled as a square-wave. Determine the EMI filter
capacitance CF from Equation 24.
CF
Attn
§
¨
1 10 40
¨
LIN ¨ 2S ˜ FSW
¨
©
·
¸
¸
¸
¸
¹
2
(24)
Adding an input filter to a switching regulator modifies the control-to-output transfer function. The output
impedance of the filter must be sufficiently small such that the input filter does not significantly affect the loop
gain of the buck converter. The impedance peaks at the filter resonant frequency. Use Equation 25 to calculate
the resonant frequency of the filter.
fres
1
2S ˜ LIN ˜ CF
(25)
The purpose of RD is to reduce the peak output impedance of the filter at its resonant frequency. Capacitor CD
blocks the DC component of the input voltage to avoid excessive power dissipation in RD. Capacitor CD must
have lower impedance than RD at the resonant frequency with a capacitance value greater than that of the input
capacitor CIN. This prevents CIN from interfering with the cutoff frequency of the main filter. Added damping is
needed when the output impedance of the filter is high at the resonant frequency (Q of the filter formed by LIN
and CIN is too high). An electrolytic capacitor CD can be used for damping with a value given by Equation 26.
CD t 4 ˜ CIN
(26)
Use Equation 27 to select the damping resistor RD.
RD
38
LIN
CIN
(27)
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10.1.2 Error Amplifier and Compensation
Figure 10-3 shows a Type-II compensator using a transconductance error amplifier (EA). The dominant pole of
the EA open-loop gain is set by the EA output resistance, RO-EA, and effective bandwidth-limiting capacitance,
CBW, as shown in Equation 28.
GEA(openloop) (s)
gm ˜ RO-EA
1 s ˜ RO-EA ˜ CBW
(28)
The EA high-frequency pole is neglected in Equation 28. The compensator transfer function from output voltage
to COMP node, including the gain contribution from the (internal or external) feedback resistor network, is
calculated in Equation 29.
Gc (s)
vÖ c (s)
vÖ out (s)
VREF
VOUT
§
s ·
gm ˜ RO-EA ˜ ¨ 1
¸
Zz1 ¹
©
˜
§
s · §
s ·
¨1
¸ ˜ ¨1
¸
¨ Zp1 ¸ ¨ Zp2 ¸
©
¹ ©
¹
(29)
where
•
•
•
VREF is the feedback voltage reference of 0.6 V.
gm is the EA gain transconductance of 1200 µS.
RO-EA is the error amplifier output impedance of 64 MΩ.
ZZ1
Zp1
Zp2
1
RCOMP ˜ CCOMP
(30)
1
RO-EA ˜ CCOMP CHF
CBW
1
#
1
RO-EA ˜ CCOMP
#
RCOMP ˜ CCOMP CHF
CBW
(31)
1
RCOMP ˜ CHF
(32)
The EA compensation components create a pole close to the origin, a zero, and a high-frequency pole. Typically,
RCOMP > CBW and CHF, so the approximations are valid.
VOUT
Error amplifier model
RFB1
FB
COMP
–
gm
VREF
+
p2
RO-EA
p1
z1
RCOMP
RFB2
CHF
CBW
CCOMP
AGND
Figure 10-3. Error Amplifier and Compensation Network
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10.2 Typical Applications
For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation, and test results of
an LM25143-powered implementation, see the TI Designs reference design library.
10.2.1 Design 1 – 5-V and 3.3-V Dual-Output Buck Regulator for Computing Applications
Figure 10-4 shows the schematic diagram of a dual-output synchronous buck regulator with output voltages
setpoints of 3.3 V and 5 V and a rated load current of 7 A for each output. In this example, the target half-load
and full-load efficiencies are 91% and 90%, respectively, based on a nominal input voltage of 12 V that ranges
from 3.5 V to 36 V. The switching frequency is set at 2.1 MHz by resistor RRT. The 5-V output is connected to
VCCX to reduce IC bias power dissipation and improve efficiency.
VIN = 3.5 V...36 V
(12 V nom)
4
8
VOUT1 = 3.3 V
IOUT1 = 7 A
CO1
4
CVCC1
2.2 F
CIN
10 F
10 nF
7 m
CBST1
0.1 F
LO1
VCC
VIN
FB1 FB2 MODE
0
Q2
RHO2
HO1
HO2
HOL1
HOL2
SW1
SW2
LO1
LOL1
LO2
LOL2
PGND1
RRT
VIN
10.5 k
CCOMP1 RCOMP1
1 nF 20 k
LM25143
Q3
LO2
0
RS2
0.68 H 7 m
Q4
VOUT2 = 5 V
IOUT2 = 7 A
CO2
4 47 F
PGND2
EN1
EN2
RT
VIN
PG2
PG1
SYNCOUT
CS1
VOUT1
DEMB
CS2
VOUT2
VCCX
COMP1
RCOMP2 CCOMP2
24.9 k
1 nF
CVCCX
2.2 F
COMP2
AGND SS1 RES
SS2 VDDA DITH
CHF1
15 pF
* VOUT1 tracks VIN if VIN < 3.7 V
VOUT2 tracks VIN if VIN < 5.4 V
CVCC2
2.2 F
DB2
HB2
RHO1
0.68 H
47 F
CBST2
0.1 F
VDDA
HB1
Q1
RS1
DB1
CDITH
10 nF
CHF2
15 pF
CSS1 CRES CSS2 CVDDA
68 nF 0.22 F 68 nF 0.47 F
Figure 10-4. Application Circuit 1 With LM25143 Dual-Output Buck Regulator at 2.1 MHz
Note
This and subsequent design examples are provided herein to showcase the LM25143 controller
in several different applications. Depending on the source impedance of the input supply bus, an
electrolytic capacitor can be required at the input to ensure stability, particularly at low input voltage
and high output current operating conditions. See Section 10 for more details.
40
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10.2.1.1 Design Requirements
Table 10-2 shows the intended input, output, and performance parameters for this design example.
Table 10-2. Design Parameters
Design Parameter
Value
Input voltage range (steady state)
8 V to 18 V
Min transient input voltage (cold crank)
3.5 V
Max transient input voltage (load dump)
36 V
Output voltages
3.3 V, 5 V
Output currents
7A
Switching frequency
2.1 MHz
Output voltage regulation
±1%
Standby current, output 1 enabled, no load
< 50 µA
Shutdown current
4 µA
The switching frequency is set at 2.1 MHz by resistor RRT. In terms of control loop performance, the target loop
crossover frequency is 60 kHz with a phase margin greater than 50°. The output voltage soft-start times are set
at 2 ms by 68-nF soft-start capacitors.
The selected buck regulator powertrain components are cited in Table 10-3, and many of the components are
available from multiple vendors. The MOSFETs in particular are chosen for both lowest conduction and switching
power loss, as discussed in detail in Section 10.1.1.4. This design uses a low-DCR, metal-powder composite
inductor, and ceramic output capacitor implementation.
Table 10-3. List of Materials for Application Circuit 1
Ref Des
Qty
Specification
10 µF, 50 V, X7R, 1210, ceramic
CIN
CO
4
8
10 µF, 50 V, X7S, 1210, ceramic
47 µF, 6.3 V, X7R, 1210, ceramic
47 µF, 6.3 V, X7S, 1210, ceramic
LO1, LO2
2
Manufacturer(1)
Part Number
Taiyo Yuden
UMJ325KB7106KMHT
Murata
GCM32EC71H106KA03
TDK
CGA6P3X7S1H106M
Murata
GCM32ER70J476KE19L
Taiyo Yuden
JMK325B7476KMHTR
TDK
CGA6P1X7S0J476M
0.68 µH, 4.8 mΩ, 25 A, 7.3 × 6.6 × 2.8 mm
Würth Elektronik
744373460068
0.68 µH, 4.5 mΩ, 22 A, 6.95 × 6.6 × 2.8 mm
Cyntec
VCMV063T-R68MN2T
0.68 µH, 3.1 mΩ, 20 A, 7 × 6.9 × 3.8 mm
0.68 µH, 7.4 mΩ, 12.2 A, 5.4 × 5.0 × 3 mm
Würth Elektronik
744311068
TDK
SPM5030VT-R68-D
0.68 µH, 2.9 mΩ, 15.3 A, 6.7 × 6.5 × 3.1 mm
Coilcraft
XGL6030-681
Q1, Q2, Q3, Q4
4
40 V, 5.7 mΩ, 9 nC, SON 5 × 6
Infineon
IPC50N04S5L-5R5
RS1, RS2
2
Shunt, 7 mΩ, 0508, 1 W
Susumu
KRL2012E-M-R007
U1
1
LM25143 42-V dual-channel/phase synchronous buck controller
Texas Instruments
LM25143RHAR
(1)
See the Third Party Products Disclaimer.
10.2.1.2 Detailed Design Procedure
10.2.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM25143 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
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In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
10.2.1.2.2 Custom Design With Excel Quickstart Tool
Select components based on the regulator specifications using the LM25143 Quickstart Calculator available for
download from the LM25143 product folder.
10.2.1.2.3 Inductor Calculation
1. Use Equation 33 to calculate the required buck inductance for each channel based on a 30% inductor ripple
current at nominal input voltages.
LO1
VOUT1
VIN(nom)
§ VIN(nom) VOUT1 ·
˜ ¨¨
¸¸
'IL ˜ FSW
©
¹
3.3 V § 12 V 3.3 V ·
˜¨
¸
12 V © 2.1A ˜ 2.1MHz ¹
0.54 +
LO2
VOUT2
VIN(nom)
§ VIN(nom) VOUT2
˜ ¨¨
'IL ˜ FSW
©
5 V § 12 V 5 V ·
˜¨
¸
12 V © 2.1A ˜ 2.1MHz ¹
0.66 +
·
¸¸
¹
(33)
2. Select a standard inductor value of 0.68 µH for both channels. Use Equation 34 to calculate the peak
inductor currents at maximum steady-state input voltage. Subharmonic oscillation occurs with a duty cycle
greater than 50% for peak current-mode control. For design simplification, the LM25143 has an internal
slope compensation ramp proportional to the switching frequency that is added to the current sense signal to
damp any tendency toward subharmonic oscillation.
ILO1(PK)
IOUT1
'ILO1
2
IOUT1
VOUT1
2 ˜ LO1 ˜ FSW
ILO2(PK)
IOUT2
'ILO2
2
IOUT2
VOUT2
2 ˜ LO2 ˜ FSW
§
VOUT1
˜ ¨1
¨
VIN(max)
©
·
¸
¸
¹
§
VOUT2
˜ ¨1
¨
VIN(max)
©
·
¸
¸
¹
7A
7A
3.3 V
2 ˜ 0.68 + ˜
§ 3.3 V ·
˜ ¨1
¸
0+] ©
9 ¹
7.94 A
5V
2 ˜ 0.68 + ˜
§
5V ·
˜ ¨1
¸
0+] © 18 V ¹
8.27 A
(34)
3. Based on Equation 10, use Equation 35 to cross-check the inductance to set a slope compensation equal to
the ideal one times the inductor current downslope.
LO1(sc)
VOUT (V) ˜ RS (m:)
24 ˜ FSW (MHz)
3.3 V ˜ 7m :
24 ˜ 2.1 MHz
0.46 +
LO2(sc)
VOUT (V) ˜ RS (m:)
24 ˜ FSW (MHz)
5 V ˜ 7m:
24 ˜ 2.1 MHz
0.69 +
(35)
10.2.1.2.4 Current-Sense Resistance
1. Calculate the current-sense resistance based on a maximum peak current capability of at least 20% higher
than the peak inductor current at full load to provide sufficient margin during start-up and load-on transients.
Calculate the current sense resistances using Equation 36.
42
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RS1
RS2
SNVSC10 – MARCH 2022
VCS(th)
1.2 ˜ ILO1(PK)
VCS(th)
1.2 ˜ ILO2(PK)
73mV
1.2 ˜ 7.94 A
7.66m :
73mV
1.2 ˜ 8.27 A
7.36m :
(36)
where
• VCS(th) is the 73-mV current limit threshold.
2. Select a standard resistance value of 7 mΩ for both shunts. A 0508 footprint component with wide aspect
ratio termination design provides 1-W power rating, low parasitic series inductance, and compact PCB
layout. Carefully observe the layout guidelines to make sure that noise and DC errors do not corrupt the
differential current-sense voltages measured at [CS1, VOUT1] and [CS2, VOUT2].
3. Place the shunt resistor close to the inductor.
4. Use Kelvin-sense connections, and route the sense lines differentially from the shunt to the LM25143.
5. The CS-to-output propagation delay (related to the current limit comparator, internal logic and power
MOSFET gate drivers) causes the peak current to increase above the calculated current limit threshold. For
a total propagation delay of tCS-DELAY of 40 ns, use Equation 37 to calculate the worst-case peak inductor
current with the output shorted.
ILO1(PK-SC)
ILO2(PK-SC)
VCS(th)
VIN(max) ˜ tCS-DELAY
RS1
LO1
73mV
7m:
18 V ˜ 40ns
0.68 +
11.49 A
(37)
6. Based on this result, select an inductor for each channel with saturation current greater than 12 A across the
full operating temperature range.
10.2.1.2.5 Output Capacitors
1. Use Equation 38 to estimate the output capacitance required to manage the output voltage overshoot during
a load-off transient (from full load to no load) assuming a load transient deviation specification of 1.5% (50
mV for a 3.3-V output).
2
0.68 + ˜
LO1 ˜ 'IOUT1
COUT1 t
VOUT1
LO2 ˜ 'IOUT2
COUT2 t
VOUT2
2
'VOVERSHOOT1
2
VOUT1
3.3 V
2
'VOVERSHOOT2
50mV
0.68 + ˜
2
VOUT2
2
5V
75mV
$
2
$
2
2
3.3 V
2
100.2 )
2
5V
44.1 )
2
(38)
2. Noting the voltage coefficient of ceramic capacitors where the effective capacitance decreases significantly
with applied voltage, select four 47-µF, 6.3-V, X7R, 1210 ceramic output capacitors for each channel.
Generally, when sufficient capacitance is used to satisfy the load-off transient response requirement, the
voltage undershoot during a no-load to full-load transient is also satisfactory.
3. Use Equation 39 to estimate the peak-peak output voltage ripple of channel 1 at nominal input voltage.
'VOUT1
§
·
'ILO1
¨
¸
© 8 ˜ FSW ˜ COUT1 ¹
2
RESR ˜ 'ILO1
2
§
·
1.89A
¨
¸
© 8 ˜ 2.1MHz ˜ 130 ) ¹
2
1m: ˜ 1.89 A
2
| 2mV
(39)
where
•
•
RESR is the effective equivalent series resistance (ESR) of the output capacitors.
130 µF is the total effective (derated) ceramic output capacitance at 3.3 V.
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4. Use Equation 40 to calculate the output capacitor RMS ripple current using and verify that the ripple current
is within the capacitor ripple current rating.
ICO1(RMS)
ICO2(RMS)
'ILO1
1.89 A
12
12
'ILO2
2.53 A
12
12
0.55 A
0.73 A
(40)
10.2.1.2.6 Input Capacitors
A power supply input typically has a relatively high source impedance at the switching frequency. Good-quality
input capacitors are necessary to limit the input ripple voltage. As mentioned earlier, dual-channel interleaved
operation significantly reduces the input ripple amplitude. In general, the ripple current splits between the input
capacitors based on the relative impedance of the capacitors at the switching frequency.
1. Select the input capacitors with sufficient voltage and RMS ripple current ratings.
2. Worst case input ripple for a two-channel buck regulator typically corresponds to when one channel operates
at full load and the other channel is disabled or operates at no load. Use Equation 41 to calculate the input
capacitor RMS ripple current assuming a worst-case duty-cycle operating point of 50%.
ICIN(RMS)
IOUT1 ˜ D ˜ 1 D
7 A ˜ 0.5 ˜ 1 0.5
3.5 A
(41)
3. Use Equation 42 to find the required input capacitance.
CIN t
D ˜ 1 D ˜ IOUT1
0.5 ˜ 1 0.5 ˜ 7 A
FSW ˜ 'VIN RESR ˜ IOUT1
2.1MHz ˜ 120mV 2m: ˜ 7 A
7.8 )
(42)
where
• ΔVIN is the input peak-to-peak ripple voltage specification.
• RESR is the input capacitor ESR.
4. Recognizing the voltage coefficient of ceramic capacitors, select two 10-µF, 50-V, X7R, 1210 ceramic input
capacitors for each channel. Place these capacitors adjacent to the relevant power MOSFETs.
5. Use four 10-nF, 50-V, X7R, 0603 ceramic capacitors near each high-side MOSFET to supply the high di/dt
current during MOSFET switching transitions. Such capacitors offer high self-resonant frequency (SRF)
and low effective impedance above 100 MHz. The result is lower power loop parasitic inductance, thus
minimizing switch-node voltage overshoot and ringing for lower EMI signature. Refer to Figure 12-2 in
Section 12.1 for more detail.
10.2.1.2.7 Compensation Components
Choose compensation components for a stable control loop using the procedure outlined as follows.
1. Based on a specified open-loop gain crossover frequency, fC, of 60 kHz, use Equation 43 to calculate
RCOMP1, assuming an effective output capacitance of 130 µF. Select RCOMP1 of 20 kΩ.
RCOMP1
2 ˜ S ˜ fC ˜
VOUT RS ˜ GCS
˜
˜ COUT
VREF
gm
2 ˜ S ˜ 60kHz ˜
3.3 V 7m: ˜ 12
˜
˜ 130 )
0.6 V 1200 6
N:
(43)
2. Calculate CCOMP1 to create a zero at the higher of (1) one tenth of the crossover frequency, or (2) the load
pole. Select a CCOMP1 capacitor of 1 nF.
CCOMP1
44
10
2 ˜ S ˜ fC ˜ RCOMP1
10
2 ˜ S ˜ 60kHz ˜ 20 k:
1.3nF
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3. Calculate CHF1 to create a pole at the ESR zero and to attenuate high-frequency noise at COMP. Select a
CHF1 capacitor of 15 pF.
CHF1
1
2 ˜ S ˜ fESR ˜ RCOMP1
1
2 ˜ S ˜ 500kHz ˜ 20 k:
15.9pF
(45)
Note
Set a fast loop with high RCOMP and low CCOMP values to improve the response when recovering from
operation in dropout.
WHITE SPACE
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100
100
95
95
90
90
Efficiency (%)
Efficiency (%)
10.2.1.3 Application Curves
85
80
75
85
80
75
70
70
VIN = 8V
VIN = 12V
VIN = 18V
65
VIN = 8V
VIN = 12V
VIN = 18V
65
60
60
0
1
2
3
4
Load Current (A)
5
6
0
7
1
Channels loaded equally
3
4
Load Current (A)
5
6
7
3.3-V output, channel 2 disabled
Figure 10-5. Efficiency Versus IOUT
Figure 10-6. Efficiency Versus IOUT
100
100
90
95
90
Efficiency (%)
80
Efficiency (%)
2
70
60
50
85
80
75
70
VIN = 8V
VIN = 12V
VIN = 18V
40
30
0.001
0.01
0.1
Load Current (A)
1
VIN = 8V
VIN = 12V
VIN = 18V
65
60
7
0
1
2
3
4
Load Current (A)
5
6
7
5-V output, channel 1 disabled
3.3-V output, channel 2 disabled
Figure 10-8. Efficiency Versus IOUT
Figure 10-7. Efficiency Versus IOUT, Log Scale
100
VIN 1V/DIV
90
VOUT2 1V/DIV
Efficiency (%)
80
VOUT1 1V/DIV
70
60
50
IOUT1 2A/DIV
VIN = 8V
VIN = 12V
VIN = 18V
40
30
0.001
0.01
0.1
Load Current (A)
1
5-V output, channel 1 disabled
2ms/DIV
7
1-A loads
Figure 10-10. Cold-Crank Response to VIN = 3.8 V
Figure 10-9. Efficiency Versus IOUT, Log Scale
46
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10.2.1.3 Application Curves (continued)
VIN 2V/DIV
VOUT2 1V/DIV
VOUT2 1V/DIV
EN 1V/DIV
VOUT1 1V/DIV
VOUT1 1V/DIV
IOUT1 5A/DIV
1ms/DIV
1ms/DIV
VIN step to 12 V
7-A resistive loads
Figure 10-11. Start-Up Characteristic
VIN = 12 V
Figure 10-12. ENABLE ON and OFF Characteristic
VOUT1 100mV/DIV
VOUT1 100mV/DIV
IOUT1 2A/DIV
IOUT1 2A/DIV
100Ps/DIV
VIN = 12 V
100Ps/DIV
FPWM
Figure 10-13. Load Transient, 3.3-V Output, 0 A to 7 A
VIN = 12 V
FPWM
Figure 10-14. Load Transient, 3.3-V Output, 3.5 A to 7 A
VOUT2 100mV/DIV
VOUT2 100mV/DIV
IOUT2 2A/DIV
IOUT2 2A/DIV
100Ps/DIV
100Ps/DIV
VIN = 12 V
7-A resistive loads
FPWM
Figure 10-15. Load Transient, 5-V Output, 0 A to 7 A
VIN = 12 V
FPWM
Figure 10-16. Load Transient, 5-V Output, 3.5 A to 7 A
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VIN = 12 V
Phase (°)
Gain (dB)
Gain (dB)
Phase (°)
10.2.1.3 Application Curves (continued)
VIN = 12 V
7-A resistive load
7-A resistive load
Figure 10-18. Bode Plot, 5-V Output
Figure 10-17. Bode Plot, 3.3-V Output
Margin
Margin
Start 150 kHz
VIN = 13.5 V
Stop 30 MHz
VOUT = 5 V
7-A resistive load
Figure 10-19. CISPR 25 Class 5 Conducted EMI, 150 kHz to 30
MHz
48
Start 30 MHz
VIN = 13.5 V
Stop 108 MHz
VOUT = 5 V
7-A resistive load
Figure 10-20. CISPR 25 Class 5 Conducted EMI, 30 MHz to 108
MHz
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10.2.2 Design 2 – Two-Phase, 15-A, 2.1-MHz Single-Output Buck Regulator for Server Applications
Figure 10-21 shows the schematic diagram of a single-output, two-phase synchronous buck regulator with an
output voltage of 5 V and rated load current of 15 A. In this example, the target half-load and full-load efficiencies
are 93% and 91%, respectively, based on a nominal input voltage of 12 V that ranges from 5 V to 36 V. The
switching frequency is set at 2.1 MHz by resistor RRT. The 5-V output is connected to VCCX to reduce IC
bias power dissipation and improve light-load efficiency. An output voltage of 3.3 V is also feasible simply by
connecting FB1 to VDDA.
Note
See the LM5143-Q1 4-phase Buck Regulator Design for Automotive ADAS Applications application
report for a four-phase, 30-A version of this design.
VIN = 5 V...36 V
(12 V nom)
4
8
VOUT = 5 V
IOUT = 15 A
RS1
47 F
7 m
DB1
CBST1
0.1 F
CBST2
0.1 F
VDDA
HB1
Q1
CO1
4
CVCC1
2.2
F
CIN
10 F
10 nF
VCC
VIN FB1
FB2 MODE
DB2
HB2
RHO2
RHO1
LO1
1
0.68 H
Q2
HO1
HO2
HOL1
HOL2
SW1
SW2
LM25143
PGND1
VIN
10.5 k
EN2
RT
PG2
RS2
0.68 H 7 m
Q4
CO2
4 47 F
VIN
SYNCOUT
CS1
VOUT1
DEMB
CS2
VOUT2
COMP1
COMP2
RCOMP
LO2
1
PGND2
EN1
PG1
CCOMP
VDDA
820 pF
Q3
LO2
LOL2
LO1
LOL1
RRT
CVCC2
2.2 F
CVCCX
2.2 F
VCCX
AGND SS1 SS2 RES VDDA DITH
30.1 k
CDITH
10 nF
CSS
68 nF
* VOUT tracks VIN if VIN < 5.4 V
CRES CVDDA
0.22 F 0.47 F
Figure 10-21. Application Circuit 2 With LM25143 Two-Phase Buck Regulator at 2.1 MHz
10.2.2.1 Design Requirements
Table 10-4 shows the intended input, output, and performance parameters for this automotive application design
example.
Table 10-4. Design Parameters
Design Parameter
Value
Input voltage range (steady state)
5 V to 18 V
Minimum transient input voltage
5V
Maximum transient input voltage
36 V
Output voltage
5V
Output current
15 A
Switching frequency
2.1 MHz
Output voltage regulation
±1%
Shutdown current
4 µA
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The switching frequency is set at 2.1 MHz by resistor RRT. In terms of control loop performance, the target loop
crossover frequency is 60 kHz with a phase margin greater than 50°. The output voltage soft-start time is set at 2
ms by a 68-nF soft-start capacitor.
The selected buck regulator powertrain components are cited in Table 10-5, and many of the components
are available from multiple vendors. Similar to design 1, this design uses a low-DCR, composite inductor and
ceramic output capacitor implementation.
Table 10-5. List of Materials for Application Circuit 2
Ref Des
Qty
Specification
10 µF, 50 V, X7R, 1210, ceramic
CIN
CO
4
8
10 µF, 50 V, X7S, 1210, ceramic
47 µF, 6.3 V, X7R, 1210, ceramic
47 µF, 6.3 V, X7S, 1210, ceramic
0.68 µH, 4.8 mΩ, 25 A, 7.3 × 6.6 × 2.8 mm
0.68 µH, 4.5 mΩ, 22 A, 6.95 × 6.6 × 2.8 mm
LO1, LO2
2
0.68 µH, 3.1 mΩ, 20 A, 7 × 6.9 × 3.8 mm
0.68 µH, 7.4 mΩ, 12.2 A, 5.4 × 5.0 × 3 mm
0.68 µH, 2.9 mΩ, 15.3 A, 6.7 × 6.5 × 3.1 mm
Manufacturer(1)
Part Number
Taiyo Yuden
UMJ325KB7106KMHT
Murata
GCM32EC71H106KA03
TDK
CGA6P3X7S1H106M
Murata
GCM32ER70J476KE19L
Taiyo Yuden
JMK325B7476KMHTR
TDK
CGA6P1X7S0J476M
Würth Elekronik
744373460068
Cyntec
VCMV063T-R68MN2T
Würth Elekronik
744311068
TDK
SPM5030VT-R68-D
Coilcraft
XGL6030-681
Q1, Q2, Q3, Q4
4
40 V, 5.7 mΩ, 9 nC, SON 5 × 6
Infineon
IPC50N04S5L-5R5
RS1, RS2
2
Shunt, 7 mΩ, 0508, 1 W
Susumu
KRL2012E-M-R007
U1
1
LM25143 42-V dual-channel/phase synchronous buck controller
Texas Instruments
LM25143RHAR
(1)
See the Third Party Products Disclaimer.
10.2.2.2 Detailed Design Procedure
See Section 10.2.1.2.
100
100
95
95
90
90
Efficiency (%)
Efficiency (%)
10.2.2.3 Application Curves
85
80
75
70
80
75
70
VIN = 8V
VIN = 12V
VIN = 18V
65
60
VIN = 8V
VIN = 12V
VIN = 18V
65
60
0
3
6
9
Load Current (A)
12
15
Figure 10-22. Efficiency Versus IOUT, 5-V Output
50
85
0
3
6
9
Load Current (A)
12
15
Configure the regulator as a 3.3-V output by tying FB1 to
VDDA.
Figure 10-23. Efficiency Versus IOUT, 3.3-V Output
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10.2.3 Design 3 – Two-Phase, 50-A, 300-kHz Single-Output Buck Regulator for ASIC Power Applications
Figure 10-24 shows the schematic diagram of a single-output, two-phase synchronous buck regulator with an
output voltage of 5 V. The expected DC load current is 35 A with transients up to 50 A. In this example, the
target efficiency at 35 A is 96% using a power stage optimized for a nominal input voltage of 24 V. The switching
frequency is set at 300 kHz by resistor RRT, and inductor DCR current sensing is used to mitigate shunt-related
losses at high current. The 5-V output is connected to VCCX to reduce IC bias power dissipation and improve
light-load efficiency. An output voltage of 3.3 V is also feasible simply by connecting FB1 to VDDA.
VIN = 18 V...36 V
(24 V nom)
LIN
1.5 H
CF
2
10 F
CVCC1
2.2
F
CIN
CIN(BULK)
100 F
6
6
10 F
10 nF
DB1
CBST1
0.1 F
HB1
Q1
LO1
VOUT = 5 V
IOUT = 35 A (TDC)
= 50 A (EDC)
1.5 H
CO1
4
Q2
47 F
VIN FB1
FB2 MODE
VIN
73.2 k
VDDA
RC1
4.99 k
CC1
6.8 nF
DB2
CVCC2
2.2 F
HB2
HO1
HO2
HOL1
HOL2
SW1
SW2
Q3
LO2
1.5 H
Q4
LO2
LOL2
LM25143
PGND1
RRT
CC2
150 pF
VCC
LO1
LOL1
RS1
CS1
0.1 F 10 k
CO(BULK)
220 F
CBST2
0.1
F
VDDA
EN1
EN2
RT
PG2
PG1
RS2
10 k
PGND2
CO2
4 47 F
CS2
0.1 F
VIN
SYNCOUT
CS1
VOUT1
DEMB
CS2
VOUT2
COMP1
COMP2
VCCX
CVCCX
2.2 F
AGND SS1 SS2 RES VDDA DITH
CDITH
10 nF
CSS
0.1 F
CRES
CVDDA
0.47 F 0.47 F
Figure 10-24. Application Circuit 3 With LM25143 Two-Phase Buck Regulator at 300 kHz
10.2.3.1 Design Requirements
Table 10-6 shows the intended input, output, and performance parameters for this design example.
Table 10-6. Design Parameters
Design Parameter
Value
Nominal input voltage
24 V
Input voltage range (steady state)
18 V to 36 V
Output voltage
5V
Thermal design current (TDC)
35 A
Electrical design current (EDC)
50 A
Switching frequency
300 kHz
Output voltage regulation
±1%
Shutdown current
4 µA
The switching frequency is set at 300 kHz by resistor RRT. In terms of control loop performance, the target loop
crossover frequency is 45 kHz with a phase margin greater than 50°. The output voltage soft-start time is set at
3 ms by a 100-nF soft-start capacitor. FPWM operation provides constant switching frequency over the full load
current range for predictable EMI performance and optimal load transient response.
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The selected buck regulator powertrain components are cited in Table 10-7, and many of the components are
available from multiple vendors. The MOSFETs in particular are chosen for both lowest conduction and switching
power loss, as discussed in detail in Section 10.1.1.4. This design uses a low-DCR composite inductor and
ceramic output capacitor implementation.
Table 10-7. List of Materials for Application Circuit 3
Ref Des
Qty
CIN
6
CO
CO(BULK)
Specification
10 µF, 50 V, X7R, 1210, ceramic
Part Number
TDK
CNA6P1X7R1H106K
AVX
12105C106K4T2A
10 µF, 50 V, X7R, 1206, ceramic
TDK
CGA5L1X7R1H106K
8
47 µF, 6.3 V, X7R, 1210, ceramic
Murata
GCM32ER70J476KE19L
6
100 µF, 6.3 V, X7S, 1210, ceramic
Murata
GRT32EC70J107ME13L
Kemet
T598D227M010ATE025
1
220 µF, 10 V, 25 mΩ, 7343, polymer tantalum
AVX
TCQD227M010R0025E
1.5 µH, 1.28 mΩ, 46.7 A, 13.3 × 12.8 × 8 mm
Cyntec
VCUD128T-1R5MS8
1.5 µH, 2.3 mΩ, 35 A, 13.5 × 12.6 × 6.5 mm
Cyntec
VCMV136E-1R5MN2
1.5 µH, 2.8 mΩ, 32.8 A, 13 × 12.5 × 6.5 mm
TDK
SPM12565VT-1R5M-D
LO1, LO2
2
Q1, Q3
2
60 V, 11 mΩ, 4.5 nC, DFN5
Q2, Q4
2
60 V, 2.6 mΩ, 24 nC, DFN5
U1
1
LM25143 42-V dual-channel/phase synchronous buck controller
1.5 µH, 2.3 mΩ, 55.3 A, 13.5 × 12.5 × 6.2 mm
(1)
Manufacturer(1)
Würth Elektronik
744373965015
Onsemi
NVMFS5C673NL
Onsemi
NVMFS5C628NL
Texas Instruments
LM25143RHAR
See the Third Party Products Disclaimer.
10.2.3.2 Detailed Design Procedure
See Section 10.2.1.2.
10.2.3.3 Application Curves
100
Efficiency (%)
95
VOUT 0.5 V/DIV
90
85
80
75
VIN = 24 V
70
0
10
20
30
Load Currrent (A)
40
50
IOUT 10 A/DIV
100 s/DIV
Figure 10-25. Efficiency Versus IOUT
52
Figure 10-26. Load Transient, 0 A to 15 A
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11 Power Supply Recommendations
The LM25143 buck controller is designed to operate over a wide input voltage range of 3.5 V to 42 V. The
characteristics of the input supply must be compatible with the Absolute Maxmimum Ratings and Recommended
Operating Conditions. In addition, the input supply must be capable of delivering the required input current to the
fully-loaded regulator. Use Equation 46 to estimate the average input current.
IIN
POUT
VIN ˜ K
(46)
where
•
η is the efficiency.
If the regulator is connected to an input supply through long wires or PCB traces with a large impedance,
take special care to achieve stable performance. The parasitic inductance and resistance of the input cables
may have an adverse effect on regulator operation. The parasitic inductance in combination with the low-ESR
ceramic input capacitors form an underdamped resonant circuit. This circuit can cause overvoltage transients
at VIN each time the input supply is cycled ON and OFF. The parasitic resistance causes the input voltage to
dip during a load transient. The best way to solve such issues is to reduce the distance from the input supply
to the regulator and use an aluminum or tantalum input capacitor in parallel with the ceramics. The moderate
ESR of the electrolytic capacitors helps to damp the input resonant circuit and reduce any voltage overshoots.
A capacitance in the range of 10 µF to 47 µF is usually sufficient to provide parallel input damping and helps to
hold the input voltage steady during large load transients.
An EMI input filter is often used in front of the regulator that, unless carefully designed, can lead to instability as
well as some of the affects mentioned above. The Simple Success with Conducted EMI for DC-DC Converters
Application Report provides helpful suggestions when designing an input filter for any switching regulator.
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12 Layout
12.1 Layout Guidelines
Proper PCB design and layout is important in a high-current, fast-switching circuits (with high current and voltage
slew rates) to achieve a robust and reliable design. As expected, certain issues must be considered before
designing a PCB layout using the LM25143. The high-frequency power loop of a buck regulator power stage is
denoted by loop 1 in the shaded area of Figure 12-1. The topological architecture of a buck regulator means
that particularly high di/dt current flows in the components of loop 1, and it becomes mandatory to reduce the
parasitic inductance of this loop by minimizing its effective loop area. Also important are the gate drive loops of
the low-side and high-side MOSFETs, denoted by 2 and 3, respectively, in Figure 12-1.
VCC
VIN
CIN
HB
CBST
High-side
gate driver
1
High frequency
power loop
HO
HOL
Q1
LO
2
VOUT
SW
VCC
CVCC
LO
Low-side
gate driver
Q2
LOL
CO
3
GND
PGND
Figure 12-1. DC/DC Regulator Ground System With Power Stage and Gate Drive Circuit Switching Loops
12.1.1 Power Stage Layout
•
•
54
Input capacitors, output capacitors, and MOSFETs are the constituent components of the power stage of a
buck regulator and are typically placed on the top side of the PCB (solder side). The benefits of convective
heat transfer are maximized because of leveraging any system-level airflow. In a two-sided PCB layout,
small-signal components are typically placed on the bottom side (component side). Insert at least one inner
plane, connected to ground, to shield and isolate the small-signal traces from noisy power traces and lines.
The DC/DC regulator has several high-current loops. Minimize the area of these loops in order to suppress
generated switching noise and optimize switching performance.
– Loop 1: The most important loop area to minimize is the path from the input capacitor or capacitors
through the high-side and low-side MOSFETs, and back to the capacitor or capacitors through the ground
connection. Connect the input capacitor or capacitors negative terminal close to the source of the low-side
MOSFET (at ground). Similarly, connect the input capacitor or capacitors positive terminal close to the
drain of the high-side MOSFET (at VIN). Refer to loop 1 in Figure 12-1.
– Another loop, not as critical as loop 1, is the path from the low-side MOSFET through the inductor and
output capacitor or capacitors, and back to source of the low-side MOSFET through ground. Connect the
source of the low-side MOSFET and negative terminal of the output capacitor or capacitors at ground as
close as possible.
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•
•
•
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The PCB trace defined as SW node, which connects to the source of the high-side (control) MOSFET, the
drain of the low-side (synchronous) MOSFET and the high-voltage side of the inductor, must be short and
wide. However, the SW connection is a source of injected EMI and thus must not be too large.
Follow any layout considerations of the MOSFETs as recommended by the MOSFET manufacturer, including
pad geometry and solder paste stencil design.
The SW pin connects to the switch node of the power conversion stage and acts as the return path for the
high-side gate driver. The parasitic inductance inherent to loop 1 in Figure 12-1 and the output capacitance
(COSS) of both power MOSFETs form a resonant circuit that induces high frequency (greater than 50 MHz)
ringing at the SW node. The voltage peak of this ringing, if not controlled, can be significantly higher than
the input voltage. Make sure that the peak ringing amplitude does not exceed the absolute maximum rating
limit for the SW pin. In many cases, a series resistor and capacitor snubber network connected from the SW
node to GND damps the ringing and decreases the peak amplitude. Provide provisions for snubber network
components in the PCB layout. If testing reveals that the ringing amplitude at the SW pin is excessive, then
include snubber components as needed.
12.1.2 Gate-Drive Layout
The LM25143 high-side and low-side gate drivers incorporate short propagation delays, adaptive dead-time
control, and low-impedance output stages capable of delivering large peak currents with very fast rise and
fall times to facilitate rapid turn-on and turn-off transitions of the power MOSFETs. Very high di/dt can cause
unacceptable ringing if the trace lengths and impedances are not well controlled.
Minimization of stray or parasitic gate loop inductance is key to optimizing gate drive switching performance,
whether it be series gate inductance that resonates with MOSFET gate capacitance or common source
inductance (common to gate and power loops) that provides a negative feedback component opposing the
gate drive command, thereby increasing MOSFET switching times. The following loops are important:
• Loop 2: high-side MOSFET, Q1. During the high-side MOSFET turn-on, high current flows from the bootstrap
(boot) capacitor through the gate driver and high-side MOSFET, and back to the negative terminal of the boot
capacitor through the SW connection. Conversely, to turn off the high-side MOSFET, high current flows from
the gate of the high-side MOSFET through the gate driver and SW, and back to the source of the high-side
MOSFET through the SW trace. Refer to loop 2 of Figure 12-1.
• Loop 3: low-side MOSFET, Q2. During the low-side MOSFET turn-on, high current flows from the VCC
decoupling capacitor through the gate driver and low-side MOSFET, and back to the negative terminal of the
capacitor through ground. Conversely, to turn off the low-side MOSFET, high current flows from the gate of
the low-side MOSFET through the gate driver and GND, and back to the source of the low-side MOSFET
through ground. Refer to loop 3 of Figure 12-1.
TI strongly recommends following circuit layout guidelines when designing with high-speed MOSFET gate drive
circuits.
• Connections from gate driver outputs, HO1/2, HOL1/2, LO1/2, and LOL1/2 to the respective gates of the
high-side or low-side MOSFETs must be as short as possible to reduce series parasitic inductance. Be aware
that peak gate drive currents can be as high as 4.25 A. Use 0.65-mm (25 mils) or wider traces. Use via or
vias, if necessary, of at least 0.5-mm (20 mils) diameter along these traces. Route HO and SW gate traces as
a differential pair from the LM25143 to the high-side MOSFET, taking advantage of flux cancellation.
• Minimize the current loop path from the VCC and HB pins through their respective capacitors as these
provide the high instantaneous current, up to 4.25 A, to charge the MOSFET gate capacitances. Specifically,
locate the bootstrap capacitor, CBST, close to the HB and SW pins of the LM25143 to minimize the area of
loop 2 associated with the high-side driver. Similarly, locate the VCC capacitor, CVCC, close to the VCC and
PGND pins of the LM25143 to minimize the area of loop 3 associated with the low-side driver.
12.1.3 PWM Controller Layout
With the provision to locate the controller as close as possible to the power MOSFETs to minimize gate driver
trace runs, the components related to the analog and feedback signals as well as current sensing are considered
in the following:
• Separate power and signal traces, and use a ground plane to provide noise shielding.
• Place all sensitive analog traces and components related to COMP1/2, FB1/2, CS1/2, SS1/2, RES, and RT
away from high-voltage switching nodes such as SW1/2, HO1/2, LO1/2, or HB1/2 to avoid mutual coupling.
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•
•
•
Use internal layer or layers as ground plane or planes. Pay particular attention to shielding the feedback (FB)
trace from power traces and components.
Locate the upper and lower feedback resistors (if required) close to the respective FB pins, keeping the FB
traces as short as possible. Route the trace from the upper feedback resistor or resistors to the required
output voltage sense point or points at the load or loads.
Route the CS1/2 and VOUT1/2 traces as differential pairs to minimize noise pickup and use Kelvin
connections to the applicable shunt resistor (if shunt current sensing is used) or to the sense capacitor
(if inductor DCR current sensing is used).
Minimize the loop area from the VCC1/2 and VIN pins through their respective decoupling capacitors to the
relevant PGND pins. Locate these capacitors as close as possible to the LM25143.
12.1.4 Thermal Design and Layout
The useful operating temperature range of a PWM controller with integrated gate drivers and bias supply LDO
regulator is greatly affected by the following:
•
•
•
•
Average gate drive current requirements of the power MOSFETs
Switching frequency
Operating input voltage (affecting bias regulator LDO voltage drop and hence its power dissipation)
Thermal characteristics of the package and operating environment
For a PWM controller to be useful over a particular temperature range, the package must allow for the efficient
removal of the heat produced while keeping the junction temperature within rated limits. The LM25143 controller
is available in a small 6-mm × 6-mm 40-pin VQFN (RHA) PowerPAD package to cover a range of application
requirements. The summarizes the thermal metrics of this package.
The 40-pin VQFNP package offers a means of removing heat from the semiconductor die through the exposed
thermal pad at the base of the package. While the exposed pad of the package is not directly connected to any
leads of the package, it is thermally connected to the substrate of the LM25143 device (ground). This allows a
significant improvement in heat sinking, and it becomes imperative that the PCB is designed with thermal lands,
thermal vias, and a ground plane to complete the heat removal subsystem. The exposed pad of the LM25143 is
soldered to the ground-connected copper land on the PCB directly underneath the device package, reducing the
thermal resistance to a very low value.
Numerous vias with a 0.3-mm diameter connected from the thermal land to the internal and solder-side ground
plane or planes are vital to help dissipation. In a multilayer PCB design, a solid ground plane is typically placed
on the PCB layer below the power components. Not only does this provide a plane for the power stage currents
to flow but it also represents a thermally conductive path away from the heat generating devices.
The thermal characteristics of the MOSFETs also are significant. The drain pads of the high-side MOSFETs are
normally connected to a VIN plane for heat sinking. The drain pads of the low-side MOSFETs are tied to the
respective SW planes, but the SW plane area is purposely kept as small as possible to mitigate EMI concerns.
12.1.5 Ground Plane Design
As mentioned previously, using one or more of the inner PCB layers as a solid ground plane is recommended. A
ground plane offers shielding for sensitive circuits and traces and also provides a quiet reference potential for the
control circuitry. Connect the PGND1 and PGND2 pins to the system ground plane using an array of vias under
the exposed pad. Also connect the PGND1 and PGND2 pins directly to the return terminals of the input and
output capacitors. The PGND nets contain noise at the switching frequency and can bounce because of load
current variations. The power traces for PGND1/2, VIN and SW1/2 can be restricted to one side of the ground
plane. The other side of the ground plane contains much less noise and is ideal for sensitive analog trace routes.
56
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12.2 Layout Example
Based on the LM5143-Q1EVM-2100 design, Figure 12-2 shows a single-sided layout of a dual-output
synchronous buck regulator. Each power stage is surrounded by a GND pad geometry to connect an EMI
shield if needed. The design uses layer 2 of the PCB as a power-loop return path directly underneath the top
layer to create a low-area switching power loop of approximately 2 mm². This loop area, and hence parasitic
inductance, must be as small as possible to minimize EMI as well as switch-node voltage overshoot and ringing.
Refer to the LM5143-Q1EVM-2100 Evaluation Module User's Guide for more detail.
Locate the controller close to the power stage ±
keep gate drive traces short and direct
Copper island
connected to AGND pin
GND
VIN
Keep the VCC and
BOOT caps close to
their respective pins
GND pad
geometry for EMI
shield connection
EMI S-filter with
electroytic cap for
parallel admping
GND
Use paralleled 0603
input capacitors close
to the FETs for VIN to
PGND decoupling
VOUT
Optional jumper to connect VOUT1 and
VOUT2 for a 2-phase implementation
Figure 12-2. PCB Top Layer
As shown in Figure 12-3, the high-frequency power loop current of one channel flows through MOSFETs Q2
and Q4, through the power ground plane on layer 2, and back to VIN through the 0603 ceramic capacitors
C16 through C19. The currents flowing in opposing directions in the vertical loop configuration provide field
self-cancellation, reducing parasitic inductance. Figure 12-4 shows a side view to illustrate the concept of
creating a low-profile, self-canceling loop in a multilayer PCB structure. The layer-2 GND plane layer, shown in
Figure 12-3, provides a tightly-coupled current return path directly under the MOSFETs to the source terminals of
Q2.
Four 10-nF input capacitors with small 0402 or 0603 case size are placed in parallel very close to the drain
of each high-side MOSFET. The low equivalent series inductance (ESL) and high self-resonant frequency
(SRF) of the small footprint capacitors yield excellent high-frequency performance. The negative terminals of
these capacitors are connected to the layer-2 GND plane with multiple 12-mil (0.3-mm) diameter vias, further
minimizing parasitic loop inductance.
Additional steps used in this layout example include:
•
•
Keep the SW connection from the power MOSFETs to the inductor (for each channel) at minimum copper
area to reduce radiated EMI.
Locate the controller close to the gate terminals of the MOSFETs such that the gate drive traces are routed
short and direct.
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•
Create an analog ground plane near the controller for sensitive analog components. The analog ground plane
for AGND and power ground planes for PGND1 and PGND2 must be connected at a single point directly
under the IC – at the die attach pad (DAP).
Optional high-side FET
gate resistors
High-frequency switching current
loop with reduced effective area
Input Caps
(1210)
Place four paralleled 0603
capacitors close the drain of the
high-side FET and connect with
vias to the GND plane on layer 2
High-side
FET
G
S
Optional low-side FET gate
resistor (typically not required)
G
Low-side
FET
S
VIN
PGND
SW
GND pad geometry for
EMI shield connection
Optional RC sense network for
inductor DCR current sensing
Inductor
Output
Caps (1210)
Keep the SW node copper
area as small as possible
Shunt
VOUT
Locate the output caps
close to the inductor
Shunt resistor for current sensing
with centrally located vias
Figure 12-3. Power Stage Component Layout
Tightly-coupled return path
minimizes power loop impedance
Q2
GND
SW
Q1
VIN
Cin1-4
GND
L1
0.15mm
L2
L3
0.3mm
vias
L4
Note
See the Improve High-current DC/DC Regulator Performance for Free with Optimized Power Stage
Layout application report for more detail.
Figure 12-4. PCB Stack-up Diagram With Low L1-L2 Intra-layer Spacing
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13 Device and Documentation Support
13.1 Device Support
13.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
13.1.2 Development Support
With an input operating voltage as low as 3.5 V and up to 100 V as specified in Table 13-1, the LM(2)514x
family of synchronous buck controllers from TI provides scalability and optimized solution size for a range of
applications. These controllers enable DC/DC solutions with high density, low EMI and increased flexibility.
Available EMI mitigation features include dual-random spread spectrum (DRSS) or triangular spread spectrum
(TRSS), split gate driver outputs for slew rate (SR) control, and integrated active EMI filtering (AEF).
Table 13-1. Synchronous Buck DC/DC Controller Family
DC/DC
Controller
Single or
Dual
VIN Range
Control Method
Gate Drive
Voltage
Sync Output
EMI Mitigation
LM25141
Single
3.8 V to 42 V
Peak current mode
5V
N/A
SR control, TRSS
LM25143
Dual
3.5 V to 42 V
Peak current mode
5V
90° phase shift
SR control, TRSS
LM25145
Single
6 V to 42 V
Voltage mode
7.5 V
180° phase shift
N/A
LM25148
Single
3.5 V to 42 V
Peak current mode
5V
180° phase shift
DRSS
LM25149
Single
3.5 V to 42 V
Peak current mode
5V
180° phase shift
DRSS, AEF
LM5141
Single
3.8 V to 65 V
Peak current mode
5V
N/A
SR control, TRSS
LM5143
Dual
3.5 V to 65 V
Peak current mode
5V
90° phase shift
SR control, TRSS
LM5145
Single
6 V to 75 V
Voltage mode
7.5 V
180° phase shift
N/A
LM5146
Single
5.5 V to 100 V
Voltage mode
7.5 V
180° phase shift
N/A
LM5148
Single
3.5 V to 80 V
Peak current mode
5V
180° phase shift
DRSS
LM5149
Single
3.5 V to 80 V
Peak current mode
5V
180° phase shift
DRSS, AEF
For development support, see the following:
•
•
•
•
•
•
•
LM25143 Quickstart Calculator
LM25143 Simulation Models
TI Reference Design Library
WEBENCH® Design Center
To design a low-EMI power supply, review TI's comprehensive EMI Training Series
TI Designs:
– Automotive wide VIN front-end reference design for digital cockpit processing units
Technical Articles:
– High-density PCB layout of DC/DC converters
– Synchronous buck controller solutions support wide VIN performance and flexibility
– How to use slew rate for EMI control
– How to reduce EMI and shrink power-supply size with an integrated active EMI filter
13.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM25143 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
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The WEBENCH Power Designer gives a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
13.2 Documentation Support
13.2.1 Related Documentation
For related documentation see the following:
•
•
•
•
•
User's Guides:
– LM5143-Q1 Synchronous Buck Controller EVM
– LM5140-Q1 Synchronous Buck Controller High Density EVM
– LM5141-Q1 Synchronous Buck Controller EVM
– LM5146-Q1 EVM User's Guide
– LM5145 EVM User's Guide
Application Reports:
– LM5143-Q1 Synchronous Buck Controller High-Density 4-Phase Design
– AN-2162 Simple Success with Conducted EMI from DC-DC Converters
– Maintaining Output Voltage Regulation During Automotive Cold-Crank with LM5140-Q1 Dual Synchronous
Buck Controller
Technical Briefs:
– Reduce Buck Converter EMI and Voltage Stress by Minimizing Inductive Parasitics
– EMI Filter Components And Their Nonidealities For Automotive DC/DC Regulators
White Papers:
– An Overview of Conducted EMI Specifications for Power Supplies
– An Overview of Radiated EMI Specifications for Power Supplies
– Valuing Wide VIN, Low EMI Synchronous Buck Circuits for Cost-driven, Demanding Applications
– Time-Saving and Cost-Effective Innovations for EMI Reduction in Power Supplies
E-Book:
– An Engineer's Guide To EMI In DC/DC Regulators
13.2.1.1 PCB Layout Resources
•
•
Application Reports:
– Improve High-current DC/DC Regulator Performance for Free with Optimized Power Stage Layout
– AN-1149 Layout Guidelines for Switching Power Supplies
– Low Radiated EMI Layout Made SIMPLE with LM4360x and LM4600x
Seminars:
– Constructing Your Power Supply – Layout Considerations
13.2.1.2 Thermal Design Resources
•
60
Application Reports:
– AN-2020 Thermal Design by Insight, Not Hindsight
– AN-1520 A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages
– Semiconductor and IC Package Thermal Metrics
– Thermal Design Made Simple with LM43603 and LM43602
– PowerPAD™Thermally Enhanced Package
– PowerPAD Made Easy
– Using New Thermal Metrics
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LM25143
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13.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
13.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.5 Trademarks
NexFET™ and TI E2E™ are trademarks of Texas Instruments.
PowerPAD™ is a trademark of Texas Instruments.
WEBENCH® is a registered trademark of Texas Instruments.
is a registered trademark of TI.
All trademarks are the property of their respective owners.
13.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages show mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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61
LM25143
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SNVSC10 – MARCH 2022
PACKAGE OUTLINE
RHA0040P
VQFN - 1 mm max height
SCALE 2.200
PLASTIC QUAD FLATPACK - NO LEAD
6.1
5.9
A
B
0.5
0.3
6.1
5.9
PIN 1 INDEX AREA
0.3
0.2
DETAIL
OPTIONAL TERMINAL
TYPICAL
C
1 MAX
SEATING PLANE
0.05
0.00
0.08 C
2X 4.5
(0.2) TYP
3.3 0.1
11
EXPOSED
THERMAL PAD
20
36X 0.5
10
21
2X
4.5
41
SYMM
1
SEE TERMINAL
DETAIL
PIN 1 ID
(OPTIONAL)
30
40
31
SYMM
40X
0.5
0.3
40X
0.3
0.2
0.1
0.05
C A
B
4226761/A 04/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RHA0040P
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(5.8)
( 3.3)
31
40
SEE SOLDER MASK
DETAIL
40X (0.6)
1
30
40X (0.25)
(
0.2) TYP
VIA
SYMM
41
(5.8)
(0.575)
(0.825)
36X (0.5)
21
10
(R0.05)
TYP
11
20
(0.575) TYP
(0.825)
SYMM
LAND PATTERN EXAMPLE
SCALE:15X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4226761/A 04/2021
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view.
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SNVSC10 – MARCH 2022
EXAMPLE STENCIL DESIGN
RHA0040P
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
(1.15)
40
31
40X (0.6)
1
30
40X (0.25)
(1.15)
TYP
SYMM
41
(5.8)
36X (0.5)
( 0.95)
21
10
(R0.05) TYP
20
11
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 41:
78.25% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:15X
4226761/A 04/2021
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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PACKAGE OPTION ADDENDUM
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26-Mar-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LM25143RHAR
ACTIVE
VQFN
RHA
40
2500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 150
LM25143R
HAR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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