LM25148
SNVSC05 – DECEMBER 2021
LM25148 42-V Synchronous Buck DC/DC Controller with Ultra-Low IQ and Dual
Random Spread Spectrum
1 Features
2 Applications
•
•
•
•
•
•
•
•
•
•
•
Functional Safety-Capable
– Documentation available to aid functional safety
system design
Integrated EMI mitigation
– Selectable dual random spread spectrum
(DRSS) feature for enhanced EMI performance
across low and high-frequency bands
– Optimized for CISPR 32 Class B requirements
Versatile synchronous buck DC/DC controller
– Wide input voltage range of 3.5 V to 42 V
– 1% accurate, fixed 3.3-V, 5-V, 12-V, or
adjustable output from 0.8 V to 36 V
– 150°C maximum junction temperature
– Lossless DCR or shunt current sensing
– Shutdown mode current: 2.3 µA
– No-load sleep current: 9.5 µA
– Internal 3-ms soft-start ramp
– Stackable up to two phases
– Advanced dropout with frequency foldback
– Internal bootstrap diode
Switching frequency from 100 kHz to 2.2 MHz
– SYNC in and SYNC out capability
– Selectable PFM or FPWM modes
Inherent protection features for robust design
– Internal hiccup mode overcurrent protection
– ENABLE and PGOOD functions
– VCC, VDDA, and gate-drive UVLO protection
– Internal or external loop compensation
– Thermal shutdown protection with hysteresis
Create a custom design using the LM25148 with
WEBENCH® Power Designer
Building automation
Industrial transport
Power delivery
Test and measurement
Aerospace and defense
3 Description
The LM25148 is a 42-V, ultra-low IQ synchronous
buck DC/DC controller for high-current, single-output
applications. The controller uses a peak current-mode
control architecture for easy loop compensation,
fast transient response, and excellent load and line
regulation. The LM25148 can be set up in interleaved
mode (paralleled output) with accurate current sharing
for high-current applications. It can operate at input
voltages as low as 3.5 V, at nearly 100% duty cycle if
needed.
The LM25148 has a unique EMI reduction
feature known as dual random spread spectrum
(DRSS). Combining low-frequency triangular and
high-frequency random modulations mitigates EMI
disturbances across lower and higher frequency
bands, respectively. This hybrid technique aligns with
the multiple resolution bandwidth (RBW) settings
specified in industry-standard EMC tests.
Device Information
PART NUMBER
PACKAGE(1)
BODY SIZE (NOM)
LM25148
VQFN (24)
3.5 mm × 5.5 mm
(1)
For all available packages, see the orderable addendum at
the end of the data sheet
VIN = 3.5 V...42 V
2
CVCC
CIN
4.7 F
VIN
EN
2.2 F
VCC
CBOOT
CNFG
HO
PFM/SYNC
PG/SYNCOUT
VDDA
CBOOT
0.1 F
Q1
LO
1.5 H
SW
Q2
LO
LM25148
RS
3 m
VOUT = 5 V
IOUT = 12 A
CO
4
47 F
PGND
RFB
24.9 k
CS
FB
ISNS+
EXTCOMP
AGND
VCCX
RT
* Tie to GND
if not used
VDDA
RRT
54.9 k
CVDDA
0.1 F
* VOUT tracks VIN if VIN < 5.4 V
Typical Application Schematic
CISPR 25 EMI Performance, 150 kHz to 30 MHz
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM25148
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SNVSC05 – DECEMBER 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Description (continued).................................................. 3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings............................................................... 5
7.3 Recommended Operating Conditions.........................5
7.4 Thermal Information....................................................6
7.5 Electrical Characteristics.............................................6
7.6 Typical Characteristics................................................ 9
8 Detailed Description......................................................13
8.1 Overview................................................................... 13
8.2 Functional Block Diagram......................................... 14
8.3 Feature Description...................................................15
8.4 Device Functional Modes..........................................24
9 Application and Implementation.................................. 25
9.1 Application Information............................................. 25
9.2 Typical Applications.................................................. 32
10 Power Supply Recommendations..............................47
11 Layout........................................................................... 48
11.1 Layout Guidelines................................................... 48
11.2 Layout Example...................................................... 51
12 Device and Documentation Support..........................53
12.1 Device Support....................................................... 53
12.2 Documentation Support.......................................... 54
12.3 Receiving Notification of Documentation Updates..55
12.4 Support Resources................................................. 55
12.5 Trademarks............................................................. 55
12.6 Electrostatic Discharge Caution..............................55
12.7 Glossary..................................................................55
13 Mechanical, Packaging, and Orderable
Information.................................................................... 55
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
December 2021
*
Initial release
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5 Description (continued)
Additional features of the LM25148 include 150°C maximum junction temperature operation, user-selectable
diode emulation for lower current consumption at light-load conditions, open-drain power-good flag for fault
reporting and output monitoring, precision enable input, monotonic start-up into prebiased load, integrated VCC
bias supply regulator, internal 3-ms soft-start time, and thermal shutdown protection with automatic recovery.
The LM25148 controller comes in a 3.5-mm × 5.5-mm thermally enhanced, 24-pin VQFN package.
NC
NC
1
24
6 Pin Configuration and Functions
NC
2
23
NC
CNFG
3
22
NC
RT
4
21
VOUT
EXTCOMP
5
20
ISNS+
19
EN
Exposed
Pad
(EP)
FB
6
AGND
7
18
PFM/SYNC
VDDA
8
17
PG/SYNCOUT
VCC
9
16
VCCX
15 CBOOT
PGND 10
11
12
13
HO
14
VIN
LO
SW
Connect the exposed pad to AGND and PGND on the PCB.
Figure 6-1. (Top View)
Table 6-1. Pin Functions
PIN
NO.
NAME
I/O(1)
DESCRIPTION
1
NC
̶
Connect to GND at the exposed pad to improve heat spreading.
2
NC
̶
Connect to GND at the exposed pad to improve heat spreading.
3
CNFG
I
Connect a resistor to ground to set primary/secondary, spread spectrum enable/disable, or interleaved
operation.
4
RT
I
Frequency programming pin. A resistor from RT to AGND sets the oscillator frequency between 100 kHz
and 2.2 MHz.
5
EXTCOMP
O
Transconductance error amplifier output. If used, connect the compensation network from EXTCOMP to
AGND.
6
FB
I
Connect FB to VDDA to set the output voltage to 3.3 V. Connect FB using a 24.9 kΩ or 49.9 kΩ to VDDA
to set the output voltage to 5 V or 12 V, respectively. Install a resistor divider from VOUT to AGND to set
the output voltage setpoint between 0.8 V and 36 V. The FB regulation voltage is 0.8 V.
7
AGND
G
Analog ground connection. Ground return for the internal voltage reference and analog circuits
8
VDDA
O
Internal analog bias regulator. Connect a ceramic decoupling capacitor from VDDA to AGND.
9
VCC
P
VCC bias supply pin. Connect a ceramic capacitor between VCC and PGND.
10
PGND
G
Power ground connection pin for low-side MOSFET gate driver
11
LO
O
Low-side power MOSFET gate driver output
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Table 6-1. Pin Functions (continued)
PIN
NO.
I/O(1)
DESCRIPTION
12
VIN
P
Supply voltage input source for the VCC regulator
13
HO
O
High-side power MOSFET gate driver output
14
SW
P
Switching node of the buck regulator and high-side gate driver return. Connect to the bootstrap capacitor,
the source terminal of the high-side MOSFET, and the drain terminal of the low-side MOSFET.
15
CBOOT
P
High-side driver supply for bootstrap gate drive
16
VCCX
P
Optional input for an external bias supply. If VVCCX > 4.3 V, VCCX is internally connected to VCC and the
internal VCC regulator is disabled.
17
PG/SYNCOUT
O
An open-collector output that goes low if VOUT is outside the specified regulation window. The PG/
SYNCOUT pin of the primary controller in dual-phase mode provides a 180° phase-shifted SYNCOUT
signal.
18
PFM/SYNC
I
Connect PFM/SYNC to VDDA to enable diode emulation mode. Connect PFM to AGND to operate the
LM25148 in forced PWM (FPWM) mode with continuous conduction at light loads. PFM can also be used
as a synchronization input to synchronize the internal oscillator to an external clock signal.
19
EN
I
An active-high precision input with rising threshold of 1 V and hysteresis current of 10 µA. If the EN
voltage is less than 0.5 V, the LM25148 is in shutdown mode, unless a SYNC signal is present on PFM/
SYNC.
20
ISNS+
I
Current sense amplifier input. Connect this pin to the inductor side of the external current sense resistor
(or to the relevant sense capacitor terminal if inductor DCR current sensing is used) using a low-current
Kelvin connection.
21
VOUT
I
Output voltage sense and the current sense amplifier input. Connect VOUT to the output side of the
current sense resistor (or to the relevant sense capacitor terminal if inductor DCR current sensing is
used).
22
NC
—
Connect to GND at the exposed pad to improve heat spreading.
23
NC
—
Connect to GND at the exposed pad to improve heat spreading.
24
NC
—
Connect to GND at the exposed pad to improve heat spreading.
(1)
4
NAME
P = Power, G = Ground, I = Input, O = Output
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7 Specifications
7.1 Absolute Maximum Ratings
Over the recommended operating junction temperature range of –40℃ to 150℃ (unless otherwise noted) (1)
Output voltage
MIN
MAX
VOUT, ISNS+ to AGND
–0.3
36
V
VOUT to ISNS+
–0.3
0.3
V
VIN to PGND
–0.3
47
V
SW to PGND
–0.3
47
V
SW to PGND, transient < 20 ns
–5
CBOOT to SW
V
–0.3
CBOOT to SW, transient < 20 ns
Input voltage
UNIT
6.5
V
–2
HO to SW
V
–0.3
HO to SW, transient < 20 ns
VHB + 0.3
V
–5
V
LO to PGND
–0.3
LO to PGND, transient < 20 ns
–1.5
EN to PGND
–0.3
47
V
VCC, VCCX, VDDA, PG, FB, PFM/SYNC, RT, EXTCOMP to AGND
–0.3
6.5
V
CNFG to AGND
–0.3
5.5
V
Operating junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–55
150
°C
(1)
VVCC + 0.3
V
V
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/
JEDEC JS-001 (1)
±2000
Charged device model (CDM), per ANSI/ESDA/
JEDEC JS-002 (2)
±750
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
Over the operating junction temperature range of –40℃ to 150℃ (unless otherwise noted). (1)
MIN
NOM
MAX
UNIT
VIN
Input supply voltage range
3.5
42
V
VOUT
Output voltage range
0.8
36
V
SW to PGND
–0.3
42
V
CBOOT to SW
–0.3
5.25
V
FB, EXTCOMP, RT, CNFG to AGND
–0.3
5.25
V
EN to PGND
–0.3
42
V
VCC, VCCX, VDDA, to PGND
–0.3
5.25
V
VOUT, ISNS+ to PGND
–0.3
36
V
PGND to AGND
–0.3
0.3
V
CNFG to AGND
–0.3
5.5
V
Operating junction temperature
–40
150
°C
TJ
(1)
5
5
Recommended operating conditions are conditions under which the device is intended to be functional. For specifications and test
conditions, see the Electrical Characteristics.
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7.4 Thermal Information
LM25148
THERMAL METRIC(1)
RGY (VQFN)
UNIT
24 PINS
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
37.3
°C/W
32
RθJB
°C/W
Junction-to-board thermal resistance
15.5
°C/W
ψJT
Junction-to-top characterization parameter
1.2
°C/W
ψJB
Junction-to-board characterization parameter
15.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
5.6
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
note
7.5 Electrical Characteristics
TJ = –40°C to 150°C. Typical values are at TJ = 25°C and VIN = 12 V (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
3.8
UNIT
SUPPLY (VIN)
IQ-VIN1
VIN shutdown current
VEN = 0 V
2.3
IQ-VIN2
VIN standby current
Non-switching, 0.5 V ≥ VEN ≤ 1 V
124
µA
ISLEEP1
Sleep current, 3.3 V
1.03 V ≤ VEN ≤ 42 V, VVOUT = 3.3 V, in
regulation, no-load, not switching, VPFM/SYNC
=0V
9.5
19.7
µA
ISLEEP2
Sleep current, 5 V
VEN = 5 V, VVOUT = 5 V, in regulation, noload, not switching, VPFM/SYNC = 0 V
9.9
19.9
µA
VSDN
Shutdown to standby threshold
VEN rising
0.5
VEN-HIGH
Enable voltage rising threshold
VEN rising, enable switching
0.95
1.0
1.05
V
IEN-HYS
Enable hysteresis
VEN = 1.1 V
–12
–10
–8
µA
IVCC = 0 mA to 100 mA
4.7
5
5.3
V
3.3
3.4
3.5
µA
ENABLE (EN)
V
INTERNAL LDO (VCC)
VVCC-REG
VCC regulation voltage
VVCC-UVLO
VCC UVLO rising threshold
VVCC-HYST
VCC UVLO hysteresis
IVCC-REG
Internal LDO short-circuit current limit
115
V
148
mV
170
mA
INTERNAL LDO (VDDA)
VVDDA-REG
VDDA regulation voltage
VVDDA-UVLO
VDDA UVLO rising
VVCC rising, VVCCX = 0 V
4.75
5
5.25
3
3.2
3.3
V
VVDDA-HYST
VDDA UVLO hysteresis
VVCCX = 0 V
120
mV
RVDDA
VDDA resistance
VVCCX = 0 V
5.5
Ω
V
EXTERNAL BIAS (VCCX)
VVCCX-ON
VCCX rising threshold
VVCCX-HYST
VCCX hysteresis voltage
VVCCX = 5 V
4.1
130
4.3
RVCCX
VCCX resistance
VVCCX = 5 V
2
4.4
V
mV
Ω
REFERENCE VOLTAGE
VREF
Regulated FB voltage
795
800
808
mV
OUTPUT VOLTAGE (VOUT)
6
VOUT-3.3V–INT
3.3-V output voltage setpoint
RFB = 0 Ω, VIN = 3.8 V to 42 V, internal
COMP
3.267
3.3
3.333
V
VOUT-3.3V–EXT
3.3-V output voltage setpoint
RFB = 0 Ω, VIN = 3.8 V to 42 V, external
COMP
3.267
3.3
3.333
V
VOUT-5V–INT
5-V output voltage setpoint
RFB = 24.9 kΩ, VIN = 5.5 V to 42 V, internal
COMP
4.95
5.0
5.05
V
VOUT-5V–EXT
5-V output voltage setpoint
RFB = 24.9 kΩ, VIN = 5.5 V to 42 V, external
COMP
4.95
5.0
5.05
V
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TJ = –40°C to 150°C. Typical values are at TJ = 25°C and VIN = 12 V (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOUT-12V–INT
12-V output setpoint
RFB = 48.7 kΩ, VIN = 24 V to 42 V, internal
COMP COMP
11.88
12
12.12
V
VOUT-12V-EXT
12-V output setpoint
RFB = 48.7 kΩ, VIN = 24 V to 42 V, external
COMP
11.88
12
12.12
V
RFB-OPT1
5-V output select
23
25
27
kΩ
RFB-OPT2
12-V output select
47
50
53
kΩ
1020
1200
µS
µS
ERROR AMPLIFIER (COMP)
gm-EXTERNAL
EA transconductance, external
compensation
FB to EXTCOMP
gm-INTERNAL
EA transconductance, internal
compensation
FB to EXTCOMP 100 kΩ to VDDA
30
IFB
Error amplifier input bias current
VCOMP-CLAMP
COMP clamp voltage
VFB = 0 V
2.1
V
ICOMP-SRC
EA source current
VEXTCOMP = 1 V, VFB = 0.6 V
180
µA
ICOMP-SINK
EA sink current
VEXTCOMP = 1 V, VFB = 1 V
180
µA
RCOMP
Internal compensation
EXTCOMP 100 kΩ to VDDA
400
kΩ
CCOMP
Internal compensation
EXTCOMP 100 kΩ to VDDA
50
pF
CCOMP-HF
Internal compensation
EXTCOMP 100 kΩ to VDDA
1
pF
75
nA
PULSE FREQUENCY MODULATION (PFM/SYNC)
VPFM-LO
PFM detection threshold low
VPFM-HI
PFM decection threshold high
0.8
VZC-SW
Zero-cross threshold
VZC-DIS
Zero-cross threshold disable
PFM = VDDA, 1000 SW cycles after first HO
pulse
FSYNCIN3
Frequency sync range
RRT = 9.53 kΩ, ±20% of the nominal
oscillator frequency
tSYNC-MIN3
Minimum pulse-width of external
synchronization signal
tSYNCIN-HO
Delay from PFM faling edge to HO rising
edge
tPFM-FILTER
SYNCIN to PFM mode
V
2.0
V
–5.5
mV
100
mV
1.74
2.7
MHz
20
250
ns
45
13
ns
45
µs
DUAL RANDOM SPREAD SPECTRUM (DRSS)
ΔfC
Modulation frequency percentage change
fm
Modulation frequency
7%
8.2
16.2
kHz
SWITCHING FREQUENCY
VRT
RT pin regulation voltage
10 kΩ < RRT < 100 kΩ
0.5
V
FSW1
Switching frequency 1
RRT = 97.6 kΩ to AGND
FSW2
Switching frequency 2
VIN = 12 V, RRT = 9.09 kΩ to AGND
FSW3
Switching frequency 3
RRT = 220 kΩ to AGND
100
kHz
SLOPE1
Internal slope compensation 1
RRT = 9.09 kΩ
600
mV/µs
SLOPE2
Internal slope compensation 2
RRT = 97.6 kΩ
50
mV/µs
tON(min)
Minimum on time
50
ns
tOFF(min)
Minimum off time
90
ns
0.22
1.98
2.2
MHz
2.42
MHz
POWER GOOD (PG)
VPG-UV
Power-good UV trip level
Falling with respect to the regulated voltage
90%
92%
94%
VPG-OV
Power-good OV trip level
Rising with respect to the regulation voltage
108%
110%
112%
VPG-UV-HYST
Power-good UV hysteresis
Falling with respect to the regulated output
3.6%
VPG-OV-HYST
Power-good OV hysteresis
Rising with respect to the regulation voltage
3.4%
tOV-DLY
OV filter time
VOUT rising
25
tUV-DLY
UV filter time
VOUT falling
25
VPG-OL
PG voltage
Open collector, PG/SYNC = 4 mA
µs
µs
0.8
V
SYNCHRONIZATION OUTPUT (PG/SYNCOUT)
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TJ = –40°C to 150°C. Typical values are at TJ = 25°C and VIN = 12 V (unless otherwise noted).
PARAMETER
TEST CONDITIONS
VSYNCOUT-LO
SYNCOUT-LO low-state voltage
RCNFG = 54.9 kΩ or 71.5 kΩ to VDDA
(primary), PFM/SYNC = 2 mA
VSYNCOUT-HO
SYNCO-HO high-state voltage
RCNFG = 54.9 kΩ, or 71.5 kΩ to VDDA
(primary) PFM/SYNC = 2 mA
tSYNCOUT
Delay from HO rising edge to SYNCOUT
(PG pin in primary mode)
VPFM = 0 V, FSW set by RRT = 100 kΩ
MIN
TYP
MAX
0.8
2.0
UNIT
V
V
2.1
µs
STARTUP (Soft Start)
tSS-INT
Internal fixed soft-start time
1.9
3
0.63
0.8
4.6
ms
BOOT CIRCUIT
VBOOT-DROP
Internal diode forward drop
ICBOOT = 20 mA, VCC to CBOOT
IBOOT
CBOOT to SW quiescent current, not
switching
VEN = 5 V, VCBOOT-SW = 5 V
VBOOT-SW-UV-R
CBOOT to SW UVLO rising threshold
VCBOOT-SW rising
VBOOT-SW-UV-F
CBOOT to SW UVLO falling threshold
VCBOOT-SW falling
VBOOT-SW-UV-HYS
CBOOT to SW UVLO hysteresis
3.0
V
4.2
µA
2.83
V
2.5
V
0.05
V
106
mV
50
mV
HIGH-SIDE GATE DRIVER (HO)
VHO-HIGH
HO high-state output voltage
IHO = –100 mA, VHO-HIGH = VCBOOT – VHO
VHO-LOW
HO low-state output voltage
IHO = 100 mA
tHO-RISE
HO rise time (10% to 90%)
CLOAD = 2.7 nF
7
ns
tHO-FALL
HO fall time (90% to 10%)
CLOAD = 2.7 nF
7
ns
IHO-SRC
HO peak source current
VHO = VSW = 0 V, VCBOOT = VVCCX = 5 V
2.2
A
IHO-SINK
HO peak sink current
VVCCX = 5 V
3.2
A
LOW-SIDE GATE DRIVER (LO)
VLO-LOW
LO low-state output voltage
ILO = 100 mA
50
mV
VLO-HIGH
LO high-state output voltage
ILO = –100 mA
130
mV
tLO-RISE
LO rise time (10% to 90%)
CLOAD = 2.7 nF
7
ns
tLO-FALL
LO fall time (90% to 10%)
CLOAD = 2.7 nF
7
ns
ILO-SRC
LO peak source current
VHO = VSW = 0 V, VCBOOT = VVCCX = 5 V
2.2
A
ILO-SINK
LO peak sink current
VVCCX = 5 V
3.2
A
ADAPTIVE DEADTIME CONTROL
tDEAD1
HO off to LO on deadtime
20
ns
tDEAD2
LO off to HO on deadtime
20
ns
INTERNAL HICCUP MODE
HICDLY
Hiccup mode activation delay
VISNS+ –VVOUT > 60 mV
512
cycles
HICCYCLES
HICCUP mode fault
VISNS+ –VVOUT > 60 mV
16384
cycles
OVERCURRENT PROTECTION
VCS-TH
Current limit threshold
tDELAY-ISNS+
ISNS+ delay to output
GCS
CS amplifier gain
IBIAS-ISNS+
CS amplifier input bias current
Measured from ISNS+ to VOUT
49
60
73
mV
10.8
V/V
65
9
10
ns
15
nA
CONFIGURATION
RCONF-OPT1
Primary, no spread spectrum
28.7
29.4
31
kΩ
RCONF-OPT2
Primary, with spread spectrum
40.2
41.2
43.2
kΩ
RCONF-OPT3
Primary, interleaved, no spread spectrum
53.6
54.9
57.6
kΩ
RCONF-OPT4
Primary, interleaved, with spread spectrum
69.8
71.5
73.2
kΩ
RCONF-OPT5
Secondary
87
90.9
93.1
kΩ
THERMAL SHUTDOWN
TJ-SD
Thermal shutdown threshold (1)
TJ-HYS
Thermal shutdown hysteresis (1)
(1)
8
Temperature rising
175
°C
15
°C
Specified by design. Not production tested.
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7.6 Typical Characteristics
100
100
95
90
Efficiency (%)
Efficiency (%)
VIN = 12 V, unless otherwise specified
90
85
VIN
VIN
VIN
VIN
80
75
0
1
2
3
4
5
6
Load Current (A)
VOUT = 5 V
7
8
=
=
=
=
8V
12 V
18 V
24 V
9
FSW = 440 kHz
0.1
Load Current (A)
=
=
=
=
8V
12 V
18 V
24 V
1
10
FSW = 440 kHz
Figure 7-2. Efficiency vs. Load, Log Scale
150
4
140
3
2
130
120
110
1
-25
0
25
50
75
100
Junction Temperature (C)
125
100
-50
150
-25
0
25
50
75
100
Junction Temperature (C)
125
150
0.5 V ≤ VEN ≤ 1 V
VEN = 0 V
Figure 7-4. Standby Current vs. Temperature
Figure 7-3. Shutdown Current vs. Temperature
15
12
12
Sleep Current (A)
15
9
6
3
0
-50
0.01
VOUT = 5 V
5
0
-50
VIN
VIN
VIN
VIN
50
0.001
10
Standby Current (A)
Shutdown Current (A)
70
60
Figure 7-1. Efficiency vs. Load
Sleep Current (A)
80
9
6
3
-25
0
25
50
75
100
Junction Temperature (C)
VVOUT = 3.3 V
125
1.03 V ≤ VEN ≤ 42 V
Figure 7-5. Sleep Current vs. Temperature
150
0
-50
-25
VVOUT = 5 V
0
25
50
75
100
Junction Temperature (C)
125
150
1.03 V ≤ VEN ≤ 42 V
Figure 7-6. Sleep Current vs. Temperature
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5.05
Output Voltage (V)
5.025
5
4.975
4.95
-50
812
PG OV Threshold (%)
Feedback Voltage (V)
804
800
796
150
110
109
108
107
106
105
-25
0
25
50
75
100
Junction Temperature (C)
125
104
-50
150
Figure 7-9. Feedback Voltage vs. Temperature
-25
0
25
50
75
100
Junction Temperature (C)
125
150
Figure 7-10. PG OV Thresholds vs. Temperature
98
5.2
Falling
Rising
97
IVCC = 0 mA
IVCC = 100 mA
5.15
5.1
96
VCC Voltage (V)
PG UV Threshold (%)
125
Rising
Falling
111
792
95
94
93
5.05
5
4.95
92
4.9
91
4.85
-25
0
25
50
75
100
Junction Temperature (C)
125
150
Figure 7-11. PG UV Thresholds vs. Temperature
10
25
50
75
100
Junction Temperature (C)
112
808
90
-50
0
Figure 7-8. Fixed 5-V Output Voltage vs.
Temperature
Figure 7-7. Fixed 3.3-V Output Voltage vs.
Temperature
788
-50
-25
4.8
-50
-25
0
25
50
75
100
Junction Temperature (C)
125
150
Figure 7-12. VCC Regulation Voltage vs.
Temperature
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3.6
250
3.5
VCC Current Limit (mA)
VCC UVLO Threshold (V)
Rising
Falling
3.4
3.3
3.2
3.1
-50
-25
0
25
50
75
100
Junction Temperature (C)
125
VDDA UVLO Threshold (V)
VDDA Voltage (V)
50
-25
0
25
50
75
100
Junction Temperature (C)
125
150
3.3
5.05
5
4.95
-25
0
25
50
75
100
Junction Temperature (C)
125
Rising
Falling
3.25
3.2
3.15
3.1
3.05
3
-50
150
-25
0
25
50
75
100
Junction Temperature (C)
125
150
Figure 7-16. VDDA UVLO Thresholds vs.
Temperature
Figure 7-15. VDDA Regulation Voltage vs.
Temperature
70
4.6
Rising
Falling
4.5
CS Threshold Voltage (mV)
VCCX On/Off Thresholds (V)
100
Figure 7-14. VCC Current Limit vs. Temperature
5.1
4.4
4.3
4.2
4.1
4
-50
150
0
-50
150
Figure 7-13. VCC UVLO Thresholds vs.
Temperature
4.9
-50
200
-25
0
25
50
75
100
Junction Temperature (C)
125
Figure 7-17. VCCX On/Off Thresholds vs.
Temperature
150
65
60
55
50
-50
-25
0
25
50
75
100
Junction Temperature (C)
125
150
Figure 7-18. Current Sense (CS) Threshold vs.
Temperature
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80
Minimum On Time (ns)
70
60
50
40
30
-50
5
2.5
4
2.4
3
2
1
0
-50
-25
0
25
50
75
100
Junction Temperature (C)
125
150
-25
0
25
50
75
100
Junction Temperature (C)
125
150
Figure 7-20. Minimum On Time (HO) vs.
Temperature
Oscillator Frequency (MHz)
Internal Soft-Start Time (ms)
Figure 7-19. Current Sense (CS) Amplifier Gain vs.
Temperature
2.3
2.2
2.1
2
-50
-25
0
25
50
75
100
Junction Temperature (C)
125
150
RRT = 9.09 kΩ
Figure 7-21. Soft-Start Time vs. Temperature
Figure 7-22. Switching Frequency vs. Temperature
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8 Detailed Description
8.1 Overview
The LM25148 is a switching DC/DC controller that features all of the functions necessary to implement a
high-efficiency synchronous buck power supply operating over a wide input voltage range from 3.5 V to 42 V.
The LM25148 is configured to provide a fixed 3.3-V, 5-V, or 12-V output, or an adjustable output from 0.8 V to 36
V. This easy-to-use controller integrates high-side and low-side MOSFET gate drivers capable of sourcing and
sinking peak currents of 2.2 A and 3.2 A, respectively. Adaptive dead-time control is designed to minimize body
diode conduction during switching transitions.
Current-mode control using a shunt resistor or inductor DCR current sensing provides inherent line feedforward,
cycle-by-cycle peak current limiting, and easy loop compensation. It also supports a wide duty cycle range for
high input voltage and low-dropout applications as well as when application require a high step-down conversion
ratio (for example, 10-to-1). The oscillator frequency is user-programmable between 100 kHz to 2.2 MHz, and
the frequency can be synchronized as high as 2.5 MHz by applying an external clock to the PFM/SYNC pin.
An external bias supply can be connected to VCCX to maximize efficiency in high input voltage applications.
A user-selectable diode emulation feature enables discontinuous conduction mode (DCM) operation to further
improve efficiency and reduce power dissipation during light-load conditions. Fault protection features include
current limiting, thermal shutdown, UVLO, and remote shutdown capability.
The LM25148 incorporates features to simplify the compliance with various EMI standards, for example CISPR
11 and CISPR 32 Class B requirements. DRSS techniques reduce the peak harmonic EMI signature.
The LM25148 is provided in a 24-pin VQFN package with an exposed pad to aid in thermal dissipation.
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8.2 Functional Block Diagram
CLK
VIN
VREF 0.8 V
BIAS
VCCX
HICCUP
FAULT TIMER
512 CYCLES
PLL &
OSCILLATORS
SYNCOUT
PFM/SYNC
DEM/FPWM
ILIM
VCC
VOUT
VDDA
CONTROL
VDDA
HICCUP
RT amp
DRSS
ENABLE
+
DUAL RANDOM
SPREAD SPECTURM
(DRSS)
800 mV
–
RT
SECONDARY
CONFG
DECODER
CNFG
INTERLEAVED
EN
–
CURRENT
LIMIT
60 mV +
GAIN = 10
ISNS+
+
VOUT
–
VCC
ILIM
+
-
SLOPE
COMP
RAMP
CBOOT
UVLO
CBOOT
SECONDARY
3.3 V
5V
FB
DECODE
R/MUX
12 V
INTERLEAVE
DEM/FPWM
DRIVER
HICCUP
COMP/ENABLE
HO
FB
SYNCOUT
SECONDARY
PG/SYNCOUT
–
PGO
VREF
PG
DELAY
25 ms
–
+
+
–
PGUV
+
–
+
PG
0.880 V
EXTERNAL EA
gm 1200 µS
–
+
+
CLK
INTERNAL EA
gm 30 µs
R
Q
S
Q
PWM
SW
LEVEL
SHIFT
ADAPTIVE
DEADTIME
VCC
DRIVER
LO
0.735 V
+
EXTCOMP
–
SOFT-START
PGND
STANDBY
+
AGND
150 mV
14
+
–
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8.3 Feature Description
8.3.1 Input Voltage Range (VIN)
The LM25148 operational input voltage range is from 3.5 V to 42 V. The device is intended for step-down
conversions from 12-V, 24-V, and 48-V supply rails. The application circuit in Figure 9-4 shows all the necessary
components to implement an LM25148 based wide-VIN single-output step-down regulator using a single supply.
The LM25148 uses an internal LDO to provide a 5-V VCC bias rail for the gate drive and control circuits
(assuming the input voltage is higher than 5 V with additional voltage margin necessary for the subregulator
dropout specification).
In high input voltage applications, take extra care to ensure that the VIN and SW pins do not exceed their
absolute maximum voltage rating of 47 V during line or load transient events. Voltage excursions that exceed the
applicable voltage specifications can damage the device.
Care should be taken in applications where there are fast input transients that cause the voltage at VIN to
suddenly drop more than 2 V below the VOUT setpoint. The LM25148 has an internal ESD diode from the VOUT
to the VIN pins that can conduct under such conditions causing the output to discharge. To prevent damage to
the internal ESD diode under the said conditions, TI recommends adding a Schottky diode in series with the VIN
pin of the LM25148 to prevent reverse current flow from VOUT to VIN.
8.3.2 High-Voltage Bias Supply Regulator (VCC, VCCX, VDDA)
The LM25148 contains an internal high-voltage VCC bias regulator that provides the bias supply for the PWM
controller and the gate drivers for the external MOSFETs. The input voltage pin (VIN) can be connected directly
to an input voltage source up to 42 V. However, when the input voltage is below the VCC setpoint level, the VCC
voltage tracks VIN minus a small voltage drop.
The VCC regulator output current limit is 115 mA (minimum). At power up, the controller sources current into the
capacitor connected at the VCC pin. When the VCC voltage exceeds 3.3 V and the EN pin is connected to a
voltage greater than 1 V, the soft-start sequence begins. The output remains active unless the VCC voltage falls
below the VCC UVLO falling threshold of 3.1 V (typical) or EN is switched to a low state. Connect a ceramic
capacitor from VCC to PGND. The recommended range of the VCC capacitor is from 2.2 µF to 10 µF.
An internal 5-V linear regulator generates the VDDA bias supply. Bypass VDDA with a 100-nF or higher ceramic
capacitor to achieve a low-noise internal bias rail. Normally, VDDA is 5 V. However, there is one condition where
VDDA regulates at 3.3 V. This is in PFM mode with a light or no-load on the output.
Minimize the internal power dissipation of the VCC regulator by connecting VCCX to a 5-V output or to an
external 5-V supply. If the VCCX voltage is above 4.3 V, VCCX is internally connected to VCC and the internal
VCC regulator is disabled. Tie VCCX to PGND if it is unused. Never connect VCCX to a voltage greater than 6.5
V. If an external supply is connected to VCCX to power the LM25148, VIN must be greater than the external bias
voltage during all conditions to avoid damage to the controller.
8.3.3 Precision Enable (EN)
The EN pin can be connected to a voltage as high as 42 V. The LM25148 has a precision enable. When the
EN voltage is greater than 1 V, controller switching is enabled. If the EN pin is pulled below 0.5 V, the LM25148
is in shutdown with an IQ of 2.3 μA (typical) current consumption from VIN. When the enable voltage is between
0.5 V and 1 V, the LM25148 is in standby mode with the VCC regulator active but the controller is not switching.
In standby mode, the non-switching input quiescent current is 124-μA typical. The LM25148 is enabled with a
voltage greater than 1.0 V. However, many applications benefit from using a resistor divider RUV1 and RUV2, as
shown in Figure 8-1, to establish a precision UVLO level. TI does not recommend leaving the EN pin floating.
When using precision enable and a VCCX supply, place a series diode with the cathode connected to the
LM25148 VCCX pin.
Use Equation 1 and Equation 2 to calculate the UVLO resistors given the required input turn-on and turn-off
voltages.
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RUV1
RUV2
VIN(on)
VIN(off)
IHYS
RUV1 ˜
(1)
VEN
VIN(on) VEN
(2)
VDDA
VIN
10 µA
RUV1
19
RUV2
EN
+
1V
Enable
comparator
Figure 8-1. Programmable Input Voltage UVLO Turn-On
8.3.4 Power-Good Monitor (PG)
The LM25148 includes an output voltage monitoring signal for VOUT to simplify sequencing and supervision.
The power-good signal is used for start-up sequencing of downstream converters, fault protection, and output
monitoring. The power-good output (PG) switches to a high impedance open-drain state when the output voltage
is in regulation. The PG switches low when the output voltage drops below the lower power-good threshold
(92% typical) or rises above the upper power-good threshold (110% typical). A 25-µs deglitch filter prevents false
tripping of the power-good signal during transients. TI recommends a pullup resistor of 100 kΩ (typical) from PG
to the relevant logic rail. PG is asserted low during soft start and when the buck regulator is disabled.
When the LM25148 is configured as a primary controller, the PG/SYNC pin becomes a synchronization clock
output for the secondary controller. The synchronization signal is 180° out-of-phase with the primary HO driver
output.
8.3.5 Switching Frequency (RT)
Program the LM25148 oscillator with a resistor from RT to AGND to set an oscillator frequency from 100 kHz
and 2.2 MHz. Calculate the RT resistance for a given switching frequency using Equation 3.
6
RT (k:)
10
FSW (kHz)
45
53
(3)
Under low V IN conditions when the on time of the high-side MOSFET exceeds the programmed oscillator period,
the LM25148 extends the switching period until the PWM latch is reset by the current sense ramp exceeding the
controller compensation voltage.
The approximate input voltage level at which this occurs is given by Equation 4.
VIN(min)
16
VOUT ˜
t SW
t SW
t OFF(min)
(4)
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where
•
•
tSW is the switching period.
tOFF(min) is the minimum off time of 90 ns.
8.3.6 Dual Random Spread Spectrum (DRSS)
The LM25148 provides a digital spread spectrum, which reduces the EMI of the power supply over a wide
frequency range. DRSS combines a low-frequency triangular modulation profile with a high frequency cycle-bycycle random modulation profile. The low-frequency triangular modulation improves performance in lower radiofrequency bands, while the high-frequency random modulation improves performance in higher radio frequency
bands.
Spread spectrum works by converting a narrowband signal into a wideband signal that spreads the energy
over multiple frequencies. Since industry standards require different EMI receiver resolution bandwidth (RBW)
settings for different frequency bands, the RBW has an impact on the spread spectrum performance. For
example, the CISPR 25 spectrum analyzer RBW in the frequency band from 150 kHz to 30 MHz is 9 kHz.
For frequencies greater than 30 MHz, the RBW is 120 kHz. DRSS is able to simultaneously improve the
EMI performance in the low and high RBWs using its low-frequency triangular modulation profile and at high
frequency cycle-by-cycle random modulation, respectively. DRSS can reduce conducted emissions up to 15
dBμV in the low-frequency band (150 kHz to 30 MHz) and 5 dBμV in the high-frequency band (30 MHz to 108
MHz).
To enable DRSS, connect either a 41.2-kΩ or 71.5-kΩ resistor from CNFG to AGND. DRSS is disabled when an
external clock is applied to the PFM/SYNC pin.
Frequency
(a) Low-frequency
triangular modulation
(b) High-frequency
randomized modulation
fs(t)
(c) Low-frequency triangular + highfrequency
randomized modulations
2¨Is
Low RBW
High RBW
t
Spread spectrum OFF
Spread spectrum ON
Figure 8-2. Dual Random Spread Spectrum Implementation
8.3.7 Soft Start
The LM25148 has an internal 3-ms soft-start timer (typical). The soft-start feature allows the regulator to
gradually reach the steady-state operating point, thus reducing start-up stresses and surges.
8.3.8 Output Voltage Setpoint (FB)
The LM25148 output can be independently configured for one of three fixed output voltages without external
feedback resistors, or adjusted to a desired voltage using an external resistor divider. Set the output to 3.3 V
by connecting FB directly to VDDA. Alternatively, set the output to either 5 V or 12 V by installing a 24.9-kΩ or
49.9-kΩ resistor between FB and VDDA, respectively. See Table 8-1.
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Table 8-1. Feedback Configuration Resistors
PULLUP RESISTOR TO VDDA
VOUT SETPOINT
0Ω
3.3 V
24.9 kΩ
5V
49.9 kΩ
12 V
Not installed
External FB divider setting
The configuration settings are latched and cannot be changed until the LM25148 is powered down (with the
VCC voltage decreasing below its falling UVLO threshold) and then powered up again (VCC rises above 3.4-V
typical). Alternatively, set the output voltage with an external resistor divider from the output to AGND. The
output voltage adjustment range is between 0.8 V and 36 V. The regulation voltage at FB is 0.8 V (VREF). Use
Equation 5 to calculate the upper and lower feedback resistors, designated as RFB1 and RFB2, respectively.
RFB1
§ VOUT
¨
© VREF
·
1¸ ˜ RFB2
¹
(5)
The recommended starting value for RFB2 is between 10 kΩ and 20 kΩ.
If low-IQ operation is required, take care when selecting the external feedback resistors. The current
consumption of the external divider adds to the LM25148 sleep current (9.5 µA typical). The divider current
reflected to VIN is scaled by the ratio of VOUT / VIN.
8.3.9 Minimum Controllable On Time
There are two limitations to the minimum output voltage adjustment range: the LM25148 voltage reference of
0.8 V and the minimum controllable switch-node pulse width, tON(min).
tON(min) effectively limits the voltage step-down conversion ratio VOUT / VIN at a given switching frequency. For
fixed-frequency PWM operation, the voltage conversion ratio must satisfy Equation 6.
VOUT
! t ON(min) ˜ FSW
VIN
(6)
where
•
•
tON(min) is 50 ns (typical).
FSW is the switching frequency.
If the desired voltage conversion ratio does not meet the above condition, the LM25148 transitions from fixed
switching frequency operation to a pulse-skipping mode to maintain output voltage regulation. For example, if the
desired output voltage is 5 V with an input voltage of 24 V and switching frequency of 2.1 MHz, use Equation 7
to check the conversion ratio.
(7)
For wide VIN applications and low output voltages, an alternative is to reduce the LM25148 switching frequency
to meet the requirement of Equation 6.
8.3.10 Error Amplifier and PWM Comparator (FB, EXTCOMP)
The LM25148 has a high-gain transconductance amplifier that generates an error current proportional to
the difference between the feedback voltage and an internal precision reference (0.8 V). The control loop
compensation is configured two ways. The first is using the internal compensation amplifier, which has a
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transconductance of 30 µS. Internal compensation is configured by connecting the EXTCOMP pin through a
100-kΩ resistance to VDDA. If a 100-kΩ resistor is not detected, the LM25148 defaults to the external loop
compensation network. The transconductance of the amplifier for external compensation is 1200 µS. This is
latched and cannot be reconfigured once programmed unless power to the device is recycled. Use an external
compensation network if higher performance is required to meet a stringent transient response specification. To
reconfigure the compensation (internal or external), remove power and allow VCC to drop below its VCCUVLO
threshold, which is 3.3 V (typical).
A type-II compensation network is generally recommended for peak current-mode control.
8.3.11 Slope Compensation
The LM25148 provides internal slope compensation for stable operation with peak current-mode control and a
duty cycle greater than 50%. Calculate the buck inductance to provide a slope compensation contribution equal
to one times the inductor downslope using Equation 8.
LO-IDEAL ( +
•
•
VOUT (V) ˜ RS (m:)
24 ˜ FSW (MHz)
(8)
A lower inductance value generally increases the peak-to-peak inductor current, which minimizes size and
cost, and improves transient response at the cost of reduced light-load efficiency due to higher cores losses
and peak currents.
A higher inductance value generally decreases the peak-to-peak inductor current, reducing switch peak and
RMS currents at the cost of requiring larger output capacitors to meet load-transient specifications.
8.3.12 Inductor Current Sense (ISNS+, VOUT)
There are two methods to sense the inductor current of the buck power stage. The first uses a current sense
resistor (also known as a shunt) in series with the inductor, and the second avails of the DC resistance of the
inductor (DCR current sensing).
8.3.12.1 Shunt Current Sensing
Figure 8-3 illustrates inductor current sensing using a shunt resistor. This configuration continuously monitors the
inductor current to provide accurate overcurrent protection across the operating temperature range. For optimal
current sense accuracy and overcurrent protection, use a low inductance ±1% tolerance shunt resistor between
the inductor and the output, with a Kelvin connection to the LM25148 current sense amplifier.
If the peak voltage signal sensed from ISNS+ to VOUT exceeds the current limit threshold of 60 mV, the current
limit comparator immediately terminates the HO output for cycle-by-cycle current limiting. Calculate the shunt
resistance using Equation 9.
RS
VCS-TH
IOUT(CL)
'IL
2
(9)
where
•
•
•
VCS-TH is current sense threshold of 60 mV.
IOUT(CL) is the overcurrent setpoint that is set higher than the maximum load current to avoid tripping the
overcurrent comparator during load transients.
ΔIL is the peak-to-peak inductor ripple current.
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VIN
LO
RS
VOUT
CO
Current sense
amplifier
VOUT
ISNS+
+
CS gain = 10
Figure 8-3. Shunt Current Sensing Implementation
The soft-start voltage is clamped 150 mV above FB during an overcurrent condition. Sixteen overcurrent events
must occur before the SS clamp is enabled. This ensures that SS can be pulled low during brief overcurrent
events, preventing output voltage overshoot during recovery.
8.3.12.2 Inductor DCR Current Sensing
For high-power applications that do not require accurate current-limit protection, inductor DCR current sensing
is preferable. This technique provides lossless and continuous monitoring of the inductor current using an RC
sense network in parallel with the inductor. Select an inductor with a low DCR tolerance to achieve a typical
current limit accuracy within the range of 10% to 15% at room temperature. Components RCS and CCS in Figure
8-4 create a low-pass filter across the inductor to enable differential sensing of the voltage across the inductor
DCR.
VIN
LO
RDCR
VOUT
CO
RCS
CCS
Current sense
amplifier
VOUT
ISNS+
+
CS gain = 10
Figure 8-4. Inductor DCR Current Sensing Implementation
The voltage drop across the sense capacitor in the s-domain is given by Equation 10. When the RCSCCS time
constant is equal to LO/RDCR, the voltage developed across the sense capacitor, CCS, is a replica of the inductor
DCR voltage and accurate current sensing is achieved. If the RCSCCS time constant is not equal to the LO/RDCR
time constant, there is a sensing error as follows:
• RCSCCS > LO/RDCR → the DC level is correct, but the AC amplitude is attenuated.
• RCSCCS < LO/RDCR → the DC level is correct, but the AC amplitude is amplified.
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LO
RDCR
§
˜ RDCR ˜ ¨ IOUT(CL)
1 s ˜ RCS ˜ CCS
©
1 s˜
VCS (s)
'IL ·
¸
2 ¹
(10)
Choose the CCS capacitance greater than or equal to 0.1 μF to maintain a low-impedance sensing network, thus
reducing the susceptibility of noise pickup from the switch node. Carefully observe Section 11.1 to make sure
that noise and DC errors do not corrupt the current sense signals applied between the ISNS+ and VOUT pins.
8.3.13 Hiccup Mode Current Limiting
The LM25148 includes an internal hiccup-mode protection function. After an overload is detected, 512 cycles
of cycle-by-cycle current limiting occurs. The 512-cycle counter is reset if four consecutive switching cycles
occur without exceeding the current limit threshold. Once the 512-cycle counter has expired, the internal soft
start is pulled low, the HO and LO driver outputs are disabled, and the 16384 counter is enabled. After the
counter reaches 16384, the internal soft start is enabled and the output restarts. The hiccup-mode current limit is
disabled during soft start until the FB voltage exceeds 0.4 V.
8.3.14 High-Side and Low-Side Gate Drivers (HO, LO)
The LM25148 contains gate drivers and an associated high-side level shifter to drive the external N-channel
power MOSFETs. The high-side gate driver works in conjunction with an internal bootstrap diode DBOOT
and bootstrap capacitor CBOOT. During the conduction interval of the low-side MOSFET, the SW voltage is
approximately 0 V and CBOOT charges from VCC through the internal DBOOT. TI recommends a 0.1-μF ceramic
capacitor connected with short traces between the CBOOT and SW pins.
The HO and LO outputs are controlled with an adaptive dead-time methodology so that both outputs (HO and
LO) are never on at the same time, preventing cross conduction. Before the LO driver output is allowed to turn
on, the adaptive dead-time logic first disables HO and waits for the HO-SW voltage to drop below 2 V typical. LO
is allowed to turn on after a small delay (HO fall to LO rising delay). Similarly, the HO turn-on is delayed until the
LO voltage has dropped below 2 V. This technique ensures adequate dead-time for any size N-channel power
MOSFET implementations, including parallel MOSFET configurations.
Caution is advised when adding series gate resistors, as this can impact the effective dead-time. The selected
high-side MOSFET determines the appropriate bootstrap capacitance value CBOOT in accordance with Equation
11.
CBOOT
QG
'VCBOOT
(11)
where
•
•
QG is the total gate charge of the high-side MOSFET at the applicable gate drive voltage.
ΔVCBOOT is the voltage variation of the high-side MOSFET driver after turn-on.
To determine CBOOT, choose ΔVCBOOT such that the available gate drive voltage is not significantly impacted.
An acceptable range of ΔVCBOOT is 100 mV to 300 mV. The bootstrap capacitor must be a low-ESR ceramic
capacitor, typically 0.1 µF. Use high-side and low-side MOSFETs with logic-level gate threshold voltages.
8.3.15 Output Configurations (CNFG)
The LM25148 can be configured as a primary controller (interleaved mode) or as a secondary controller for
paralleling the outputs for high-current applications with a resistor RCNFG. This resistor also configures if spread
spectrum is enabled or disabled. See Table 8-2. Once the VCC voltage is above 3.3 V (typical), the CNFG pin
voltage is monitored and latched. To change the configuration mode, the LM25148 must be powered down, and
VCC must drop below 3.3 V. Figure 8-5 shows the configuration timing diagram.
When the LM25148 is configured as a primary controller with spread spectrum enabled (RCNFG of 41.2 kΩ or
71.5 kΩ), the LM25148 cannot be synchronized to an external clock.
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Table 8-2. Configuration Modes
RCNFG
PRIMARY/
SECONDARY
SPREAD SPECTRUM
DUAL PHASE
29.9 kΩ
Primary
OFF
Disabled
41.2 kΩ
Primary
ON
Disabled
54.9 kΩ
Primary
OFF
Enabled
71.5 kΩ
Primary
ON
Enabled
90.9 kΩ
Secondary
N/A
Enabled
Figure 8-5. Configuration Timing
8.3.16 Single-Output Dual-Phase Operation
To configure for dual-phase operation, two LM25148 controllers are required. The LM25148 can only be
configured in a single or dual-phase configuration where both outputs are tied together. Additional phases
cannot be added. Refer to Figure 8-6. Configure the first controller (CNTRL1) as a primary controller and the
second controller (CNTRL2) as a secondary. To configure CNTRL1 as a primary controller, install a 54-kΩ or
a 71.5-kΩ resistor from CNFG to AGND. To configure the CNTRL2 as a secondary controller, install a 90.9-kΩ
resistor from CNFG to AGND. This disables the error amplifier of CNTRL2, placing it into a high-impedance
state. Connect the EXTCOMP pins of the primary and secondary controllers together. The internal compensation
amplifier feature is not supported when the controller is in dual-phase mode.
In dual-phase mode, the PG pin of the primary controller becomes a SYNCOUT. Refer to Electrical
Characteristics for voltage levels. Connect PG of the primary to PFM/SYNC (SYNCIN) of the secondary
controller. The PG/SYNCOUT signal of the primary controller is 180° out-of-phase and facilitates interleaved
operation. RT is not used for the oscillator when the LM25148 is in Secondary Controller mode, but instead
is used for slope compensation. Therefore, select the RT resistance to be the same as that of the primary
controller. The oscillator is derived from the primary controller. When in primary/secondary mode, enable both
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controllers simultaneously for start-up. After the regulator has started, pull the secondary EN pin low (< 0.8 V) for
phase shedding if needed at light load to increase the efficiency.
Configure PFM mode by connecting the PFM/SYNC of the primary to VDDA and the FB of the secondary to
VDDA as shown in Figure 8-6. Configure FPWM mode by connecting PFM/SYNC of the primary and FB of
the secondary both to AGND. An external synchronization signal can be applied to the primary PFM/SYNC
(SYNCIN), and the secondary FB must be configured for FPWM. If an external SYNCIN signal is applied after
start-up while in primary/secondary mode, there is a two-clock cycle delay before the LM25148 locks on to the
external synchronization signal.
VOUT
RPGOOD
20 k
SYNCOUT
VDDA
EN CH1
PFM/SYNC
PGOOD/
SYNCOUT
EN
VOUT
EN CH2
Primary
Controller
CNFG
RCNFG1
PFM/SYNC
EN
Secondary
Controller
RFB1
FB
CNFG
FB
RCNFG2
EXTCOMP
RFB2
54.9 k
System
PGOOD
PGOOD/
SYNCOUT
VDDA
EXTCOMP
90.9 k
Figure 8-6. Schematic Configured for Single-Output Dual-Phase Operation
In PFM mode, the controller enters pulse skipping to reduce the IQ current and improve the light-load efficiency.
When this occurs, the primary controller disables its synchronization clock output, so phase shedding is not
supported. In PFM mode connect the two enable pins together. Phase shedding is supported in FPWM only. In
FPWM, enable or disable the secondary controller as needed to support higher load current or better light-load
efficiency, respectively. When the secondary controller is disabled and then re-enabled, its internal soft start is
pulled low and the LM25148 goes through a normal soft-start turn-on.
When the LM25148 is configured for a single-output dual-phase operation using the internal 3.3-V feedback
resistor divider, the internal bootstrap UV circuit can source current out of the SW pin, charging up the output
capacitors approximately to 3.6 V. If this behavior is undesirable, you can add a 100-kΩ resistor from VOUT to
GND to bleed off the charge on the output capacitors.
For more information, see the Benefits of a Multiphase Buck Converter Technical Brief and Multiphase Buck
Design From Start to Finish Application Report.
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8.4 Device Functional Modes
8.4.1 Sleep Mode
The LM25148 operates with peak current-mode control such that the compensation voltage is proportional to the
peak inductor current. During no-load or light-load conditions, the output capacitor discharges very slowly. As
a result, the compensation voltage does not demand the driver output pulses on a cycle-by-cycle basis. When
the LM25148 controller detects 16 missed switching cycles, it enters sleep mode and switches to a low IQ state
to reduce the current drawn from the input. For the LM25148 to go into sleep mode, the controller must be
programmed for diode emulation (tie PFM/SYNC to VDDA).
The typical controller IQ in sleep mode is 9.5 μA with a 3.3-V output.
8.4.2 Pulse Frequency Modulation and Synchronization (PFM/SYNC)
A synchronous buck regulator implemented with a low-side synchronous MOSFET rather than a diode has
the capability to sink negative current from the output during conditions of, light-load, output overvoltage, and
pre-bias start-up conditions. The LM25148 provides a diode emulation feature that can be enabled to prevent
reverse (drain-to-source) current flow in the low-side MOSFET. When configured for Diode Emulation mode,
the low-side MOSFET is switched off when reverse current flow is detected by sensing the SW voltage using
a zero-cross comparator. The benefit of this configuration is lower power loss during light-load conditions. The
disadvantage of diode emulation mode is slower light-load transient response.
The PFM/SYNC pin configures diode emulation. To enable diode emulation and thus achieve low-IQ current
at light loads, connect PFM/SYNC to VDDA. If FPWM with continuous conduction mode (CCM) operation is
desired, tie PFM/SYNC to AGND. Note that diode emulation is automatically engaged to prevent reverse current
flow during a prebias start-up. A gradual change from DCM to CCM operation provides monotonic start-up
performance.
To synchronize the LM25148 to an external source, apply a logic-level clock to the PFM/SYNC pin. The
LM25148 can be synchronized to ±20% of the programmed frequency up to a maximum of 2.5 MHz. If there
is an RT resistor and a synchronization signal, the LM25148 ignores the RT resistor and synchronizes to the
external clock. Under low VIN conditions when the minimum off time is reached, the synchronization signal is
ignored, allowing the switching frequency to reduce to maintain output voltage regulation.
8.4.3 Thermal Shutdown
The LM25148 includes an internal junction temperature monitor. If the temperature exceeds 175°C (typical),
thermal shutdown occurs. When entering thermal shutdown, the device:
1. Turns off the high-side and low-side MOSFETs.
2. PG/SYNCOUT switches low.
3. Turns off the VCC regulator.
4. Initiates a soft-start sequence when the die temperature decreases by the thermal shutdown hysteresis of
15°C (typical).
This is a non-latching protection, and, as such, the device cycles into and out of thermal shutdown if the fault
persists.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
9.1.1 Power Train Components
A comprehensive understanding of the buck regulator power train components is critical to successfully
completing a synchronous buck regulator design. The following sections discuss the output inductor, input and
output capacitors, power MOSFETs, and EMI input filter.
9.1.1.1 Buck Inductor
For most applications, choose a buck inductance such that the inductor ripple current, ΔIL, is between 30% to
50% of the maximum DC output current at nominal input voltage. Choose the inductance using Equation 12
based on a peak inductor current given by Equation 13.
LO
IL(peak)
VOUT
'IL ˜ FSW
IOUT
§
VOUT ·
˜ ¨1
¸
VIN ¹
©
(12)
'IL
2
(13)
Check the inductor data sheet to make sure that the saturation current of the inductor is well above the peak
inductor current of a particular design. Ferrite designs have very low core loss and are preferred at high
switching frequencies, so design goals can then concentrate on copper loss and preventing saturation. Low
inductor core loss is evidenced by reduced no-load input current and higher light-load efficiency. However, ferrite
core materials exhibit a hard saturation characteristic and the inductance collapses abruptly when the saturation
current is exceeded. This results in an abrupt increase in inductor ripple current and higher output voltage ripple,
not to mention reduced efficiency and compromised reliability. Note that the saturation current of an inductor
generally decreases as its core temperature increases. Of course, accurate overcurrent protection is key to
avoiding inductor saturation.
9.1.1.2 Output Capacitors
Ordinarily, the output capacitor energy storage of the regulator combined with the control loop response are
prescribed to maintain the integrity of the output voltage within the dynamic (transient) tolerance specifications.
The usual boundaries restricting the output capacitor in power management applications are driven by finite
available PCB area, component footprint and profile, and cost. The capacitor parasitics – equivalent series
resistance (ESR) and equivalent series inductance (ESL) – take greater precedence in shaping the load
transient response of the regulator as the load step amplitude and slew rate increase.
The output capacitor, COUT, filters the inductor ripple current and provides a reservoir of charge for step-load
transient events. Typically, ceramic capacitors provide extremely low ESR to reduce the output voltage ripple
and noise spikes, while tantalum and electrolytic capacitors provide a large bulk capacitance in a relatively
compact footprint for transient loading events.
Based on the static specification of peak-to-peak output voltage ripple denoted by ΔVOUT, choose an output
capacitance that is larger than that given by Equation 14.
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'IL
COUT t
8 ˜ FSW 'VOUT
2
RESR ˜ 'IL
2
(14)
Figure 9-1 conceptually illustrates the relevant current waveforms during both load step-up and step-down
transitions. As shown, the large-signal slew rate of the inductor current is limited as the inductor current ramps
to match the new load-current level following a load transient. This slew-rate limiting exacerbates the deficit of
charge in the output capacitor, which must be replenished as fast as possible during and after the load step-up
transient. Similarly, during and after a load step-down transient, the slew rate limiting of the inductor current adds
to the surplus of charge in the output capacitor that must be depleted as quickly as possible.
IOUT1
diL
dt
'IOUT
VOUT
LF
inductor current, iL(t)
'QC
IOUT2
diOUT
dt
load current,
iOUT(t)
'IOUT
tramp
inductor current, iL(t)
IOUT2
'QC
diL
dt
'IOUT
VIN
VOUT
LF
load current, iOUT(t)
IOUT1
tramp
Figure 9-1. Load Transient Response Representation Showing COUT Charge Surplus or Deficit
In a typical regulator application of 12-V input to low output voltage (for example, 3.3 V), the load-off transient
represents the worst case in terms of output voltage transient deviation. In that conversion ratio application, the
steady-state duty cycle is approximately 28% and the large-signal inductor current slew rate when the duty cycle
collapses to zero is approximately –VOUT / L. Compared to a load-on transient, the inductor current takes much
longer to transition to the required level. The surplus of charge in the output capacitor causes the output voltage
to significantly overshoot. In fact, to deplete this excess charge from the output capacitor as quickly as possible,
the inductor current must ramp below its nominal level following the load step. In this scenario, a large output
capacitance can be advantageously employed to absorb the excess charge and minimize the voltage overshoot.
To meet the dynamic specification of output voltage overshoot during such a load-off transient (denoted as
ΔVOVERSHOOT with step reduction in output current given by ΔIOUT), the output capacitance should be larger
than:
LO ˜ 'IOUT
COUT t
VOUT
2
'VOVERSHOOT
2
VOUT
2
(15)
The ESR of a capacitor is provided in the manufacturer’s data sheet either explicitly as a specification or
implicitly in the impedance versus frequency curve. Depending on type, size, and construction, electrolytic
capacitors have significant ESR, 5 mΩ and above, and relatively large ESL, 5 nH to 20 nH. PCB traces
contribute some parasitic resistance and inductance as well. Ceramic output capacitors, on the other hand,
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have low-ESR and ESL contributions at the switching frequency, and the capacitive impedance component
dominates. However, depending on package and voltage rating of the ceramic capacitor, the effective
capacitance can drop quite significantly with applied DC voltage and operating temperature.
Ignoring the ESR term in Equation 14 gives a quick estimation of the minimum ceramic capacitance necessary
to meet the output ripple specification. Two to four 47-µF, 10-V, X7R capacitors in 1206 or 1210 footprint is a
common choice for a 5-V output. Use Equation 15 to determine if additional capacitance is necessary to meet
the load-off transient overshoot specification.
A composite implementation of ceramic and electrolytic capacitors highlights the rationale for paralleling
capacitors of dissimilar chemistries yet complementary performance. The frequency response of each capacitor
is accretive in that each capacitor provides desirable performance over a certain portion of the frequency range.
While the ceramic provides excellent mid- and high-frequency decoupling characteristics with its low ESR and
ESL to minimize the switching frequency output ripple, the electrolytic device with its large bulk capacitance
provides low-frequency energy storage to cope with load transient demands.
9.1.1.3 Input Capacitors
Input capacitors are necessary to limit the input ripple voltage to the buck power stage due to switchingfrequency AC currents. TI recommends using X7S or X7R dielectric ceramic capacitors to provide low
impedance and high RMS current rating over a wide temperature range. To minimize the parasitic inductance
in the switching loop, position the input capacitors as close as possible to the drain of the high-side MOSFET
and the source of the low-side MOSFET. The input capacitor RMS current for a single-channel buck regulator is
given by Equation 16.
ICIN,rms
§
2
D ˜ ¨ IOUT ˜ 1 D
¨
©
2
'IL ·
¸
12 ¸
¹
(16)
The highest input capacitor RMS current occurs at D = 0.5, at which point, the RMS current rating of the input
capacitors should be greater than half the output current.
Ideally, the DC component of input current is provided by the input voltage source and the AC component by the
input filter capacitors. Neglecting inductor ripple current, the input capacitors source current of amplitude (IOUT −
IIN) during the D interval and sinks IIN during the 1−D interval. Thus, the input capacitors conduct a square-wave
current of peak-to-peak amplitude equal to the output current. It follows that the resultant capacitive component
of AC ripple voltage is a triangular waveform. Together with the ESR-related ripple component, the peak-to-peak
ripple voltage amplitude is given by Equation 17.
'VIN
IOUT ˜ D ˜ 1 D
FSW ˜ CIN
IOUT ˜ RESR
(17)
The input capacitance required for a particular load current, based on an input voltage ripple specification of
ΔVIN, is given by Equation 18.
CIN t
D ˜ 1 D ˜ IOUT
FSW ˜ 'VIN RESR ˜ IOUT
(18)
Low-ESR ceramic capacitors can be placed in parallel with higher valued bulk capacitance to provide optimized
input filtering for the regulator and damping to mitigate the effects of input parasitic inductance resonating
with high-Q ceramics. One bulk capacitor of sufficiently high current rating and four 10-μF 50-V X7R ceramic
decoupling capacitors are usually sufficient for 12-V battery automotive applications. Select the input bulk
capacitor based on its ripple current rating and operating temperature range.
Of course, a two-channel buck regulator with 180° out-of-phase interleaved switching provides input ripple
current cancellation and reduced input capacitor current stress. The above equations represent valid calculations
when one output is disabled and the other output is fully loaded.
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9.1.1.4 Power MOSFETs
The choice of power MOSFETs has significant impact on DC/DC regulator performance. A MOSFET with
low on-state resistance, RDS(on), reduces conduction loss, whereas low parasitic capacitances enable faster
transition times and reduced switching loss. Normally, the lower the RDS(on) of a MOSFET, the higher the gate
charge and output charge (QG and QOSS, respectively), and vice versa. As a result, the product of RDS(on) and
QG is commonly specified as a MOSFET figure-of-merit. Low thermal resistance of a given package ensures that
the MOSFET power dissipation does not result in excessive MOSFET die temperature.
The main parameters affecting power MOSFET selection in a LM25148 application are as follows:
• RDS(on) at VGS = 5 V
• Drain-source voltage rating, BVDSS, typically 40 V or 60 V, depending on the maximum input voltage
• Gate charge parameters at VGS = 5 V
• Output charge, QOSS, at the relevant input voltage
• Body diode reverse recovery charge, QRR
• Gate threshold voltage, VGS(th), derived from the Miller plateau evident in the QG versus VGS plot in the
MOSFET data sheet. With a Miller plateau voltage typically in the range of 2 V to 3 V, the 5-V gate drive
amplitude of the LM25148 provides an adequately enhanced MOSFET when on and a margin against Cdv/dt
shoot-through when off.
The MOSFET-related power losses for one channel are summarized by the equations presented in Table 9-1,
where suffixes one and two represent high-side and low-side MOSFET parameters, respectively. While the
influence of inductor ripple current is considered, second-order loss modes, such as those related to parasitic
inductances and SW node ringing, are not included. Consult the LM25148 Quickstart Calculator to assist with
power loss calculations.
Table 9-1. MOSFET Power Losses
POWER LOSS MODE
HIGH-SIDE MOSFET
MOSFET conduction(2)
Pcond1
(3)
MOSFET switching
Psw1
MOSFET gate drive(1)
VIN ˜ FSW
2
§
2
D ˜ ¨ IOUT
¨
©
ª§
Ǭ IOUT
©
PGate1
Body diode
reverse recovery(5)
(1)
(2)
(3)
(4)
(5)
·
¸ ˜ RDS(on)1
12 ¸
¹
'IL ·
¸ ˜ tR
2 ¹
§
¨ IOUT
©
Pcond2
PCoss
§
2
Dc ˜ ¨ IOUT
¨
©
'IL · º
¸ ˜ tF »
2 ¹ ¼
PGate2
FSW ˜ VIN ˜ Qoss2
N/A
VCC ˜ FSW ˜ QG2
Eoss1 Eoss2
PcondBD
PRR
2
'IL ·
¸ ˜ RDS(on)2
12 ¸
¹
Negligible
VCC ˜ FSW ˜ QG1
MOSFET output
charge(4)
Body diode
conduction
LOW-SIDE MOSFET
2
'IL
ª§
VF ˜ FSW «¨ IOUT
©
'IL
2
·
§
¸ ˜ t dt1 ¨ IOUT
¹
©
'IL
2
º
·
¸ ˜ t dt2 »
¹
¼
VIN ˜ FSW ˜ QRR2
Gate drive loss is apportioned based on the internal gate resistance of the MOSFET, externally added series gate resistance and the
relevant driver resistance of the LM25148.
MOSFET RDS(on) has a positive temperature coefficient of approximately 4500 ppm/°C. The MOSFET junction temperature, TJ, and its
rise over ambient temperature is dependent upon the device total power dissipation and its thermal impedance. When operating at or
near minimum input voltage, make sure that the MOSFET RDS(on) is rated for the available gate drive voltage.
D' = 1–D is the duty cycle complement.
MOSFET output capacitances, Coss1 and Coss2, are highly non-linear with voltage. These capacitances are charged losslessly by
the inductor current at high-side MOSFET turn-off. During turn-on, however, a current flows from the input to charge the output
capacitance of the low-side MOSFET. Eoss1, the energy of Coss1, is dissipated at turn-on, but this is offset by the stored energy Eoss2 on
Coss2.
MOSFET body diode reverse recovery charge, QRR, depends on many parameters, particularly forward current, current transition
speed, and temperature.
The high-side (control) MOSFET carries the inductor current during the PWM on-time (or D interval) and typically
incurs most of the switching losses. It is, therefore, imperative to choose a high-side MOSFET that balances
conduction and switching loss contributions. The total power dissipation in the high-side MOSFET is the sum of
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the losses due to conduction, switching (voltage-current overlap), output charge, and typically two-thirds of the
net loss attributed to body diode reverse recovery.
The low-side (synchronous) MOSFET carries the inductor current when the high-side MOSFET is off (or 1–D
interval). The low-side MOSFET switching loss is negligible as it is switched at zero voltage – current just
commutates from the channel to the body diode or vice versa during the transition dead-times. LM25148, with its
adaptive gate drive timing, minimizes body diode conduction losses when both MOSFETs are off. Such losses
scale directly with switching frequency.
In high step-down ratio applications, the low-side MOSFET carries the current for a large portion of the switching
period. Therefore, to attain high efficiency, it is critical to optimize the low-side MOSFET for low RDS(on). In cases
where the conduction loss is too high or the target RDS(on) is lower than available in a single MOSFET, connect
two low-side MOSFETs in parallel. The total power dissipation of the low-side MOSFET is the sum of the losses
due to channel conduction, body diode conduction, and typically one-third of the net loss attributed to body diode
reverse recovery. The LM25148 is well suited to drive TI's portfolio of NexFET™ power MOSFETs.
9.1.1.5 EMI Filter
Switching regulators exhibit negative input impedance, which is lowest at the minimum input voltage. An
underdamped LC filter exhibits a high output impedance at the resonant frequency of the filter. For stability,
the filter output impedance must be less than the absolute value of the converter input impedance.
ZIN
VIN(min)
2
PIN
(19)
The passive EMI filter design steps are as follows:
• Calculate the required attenuation of the EMI filter at the switching frequency, where CIN represents the
existing capacitance at the input of the switching converter.
• Input filter inductor LIN is usually selected between 1 μH and 10 μH, but it can be lower to reduce losses in a
high-current design.
• Calculate input filter capacitor CF.
Figure 9-2. Passive π-Stage EMI Filter for Buck Regulator
By calculating the first harmonic current from the Fourier series of the input current waveform and multiplying it
by the input impedance (the impedance is defined by the existing input capacitor CIN), a formula is derived to
obtain the required attenuation as shown by Equation 20.
Attn
§ IL(PEAK)
1 ·
¸ VMAX
20log ¨ 2
˜ sin S ˜ DMAX ˜
¨ S ˜F ˜ C
¸
1
9
SW
IN
©
¹
(20)
where
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•
•
•
•
VMAX is the allowed dBμV noise level for the applicable conducted EMI specification, for example CISPR 32
Class B.
CIN is the existing input capacitance of the buck regulator.
DMAX is the maximum duty cycle.
IPEAK is the peak inductor current.
For filter design purposes, the current at the input can be modeled as a square-wave. Determine the passive
EMI filter capacitance CF from Equation 21.
CF
Attn
§
¨
1 10 40
¨
LIN ¨ 2S ˜ FSW
¨
©
·
¸
¸
¸
¸
¹
2
(21)
Adding an input filter to a switching regulator modifies the control-to-output transfer function. The output
impedance of the filter must be sufficiently small so that the input filter does not significantly affect the loop
gain of the buck converter. The impedance peaks at the filter resonant frequency. The resonant frequency of the
passive filter is given by Equation 22.
fres
1
2S ˜ LIN ˜ CF
(22)
The purpose of RD is to reduce the peak output impedance of the filter at the resonant frequency. Capacitor CD
blocks the DC component of the input voltage to avoid excessive power dissipation in RD. Capacitor CD should
have lower impedance than RD at the resonant frequency with a capacitance value greater than that of the input
capacitor CIN. This prevents CIN from interfering with the cutoff frequency of the main filter. Added input damping
is needed when the output impedance of the filter is high at the resonant frequency (Q of filter formed by LIN and
CIN is too high). An electrolytic capacitor CD can be used for input damping with a value given by Equation 23.
CD t 4 ˜ CIN
(23)
Select the input damping resistor RD using Equation 24.
RD
LIN
CIN
(24)
9.1.2 Error Amplifier and Compensation
Figure 9-3 shows a type-ll compensator using a transconductance error amplifier (EA). The dominant pole of the
EA open-loop gain is set by the EA output resistance, RO-EA, and effective bandwidth-limiting capacitance, CBW,
as shown by Equation 25.
GEA(openloop) (s)
gm ˜ RO-EA
1 s ˜ RO-EA ˜ CBW
(25)
The EA high-frequency pole is neglected in the above expression. Equation 26 calculates the compensator
transfer function from output voltage to COMP node, including the gain contribution from the (internal or external)
feedback resistor network.
30
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Gc (s)
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vÖ c (s)
Öv out (s)
VREF
VOUT
§
s ·
gm ˜ RO-EA ˜ ¨ 1
¸
Zz1 ¹
©
˜
§
s · §
s ·
¨1
¸ ˜ ¨1
¸
¨ Zp1 ¸ ¨ Zp2 ¸
©
¹ ©
¹
(26)
where
•
•
•
VREF is the feedback voltage reference of 0.8 V.
gm is the EA gain transconductance of 1200 µS.
RO-EA is the error amplifier output impedance of 64 MΩ.
ZZ1
Zp1
Zp2
1
RCOMP ˜ CCOMP
(27)
1
RO-EA ˜ CCOMP
CHF
CBW
1
#
RO-EA
#
RCOMP ˜ CCOMP CHF
CBW
1
˜ CCOMP
(28)
1
RCOMP ˜ CHF
(29)
The EA compensation components create a pole close to the origin, a zero, and a high-frequency pole. Typically,
RCOMP > CBW and CHF, so the approximations are valid.
VOUT
Error Amplifier Model
RFB1
FB
COMP
±
gm
+
VREF
Zp2
RO-EA
Zp1
Zz1
RCOMP
RFB2
CHF
CBW
CCOMP
AGND
Figure 9-3. Error Amplifier and Compensation Network
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9.2 Typical Applications
9.2.1 Design 1 – High Efficiency 2.1-MHz Synchronous Buck Regulator
Figure 9-4 shows the schematic diagram of a single-output synchronous buck regulator with an output voltage
of 5 V and a rated load current of 8 A. In this example, the target half-load and full-load efficiencies are 93.5%
and 92.5%, respectively, based on a nominal input voltage of 12 V that ranges from 5.5 V to 36 V. The switching
frequency is set at 2.1 MHz by resistor RRT. The 5-V output is connected to VCCX to reduce IC bias power
dissipation and improve efficiency. An output voltage of 3.3 V is also feasible simply by connecting FB to VDDA.
LIN
1 µH
VIN = 3.5 V...36 V
CF
2
CIN
10 µF
CDAMP
47 F
10
F
CVCC
VIN
2.2 F
VCC
EN
CBOOT
VDDA
RFB
FB
24.9 k
CCOMP
RCOMP
EXTCOMP
10 k
2.7 nF
CBOOT
0.1 F
LO
SW
0.68 H
LM25148
RS
5 m
Q2
LO
VOUT = 5 V
IOUT = 8 A
CO
4 47 F
PGND
CHF
ISNS+
N/A
Tie to VOUT
or GND
Q1
HO
VOUT
PG/SYNCOUT
VCCX
PFM/SYNC
CNFG
RT
VDDA
AGND
Tie to VDDA
or GND
* VOUT tracks VIN if VIN < 5.2 V
RCNFG
41.2 k
RRT
9.52 k
CVDDA
0.1 F
Figure 9-4. Application Circuit 1 With LM25148 Buck Regulator at 2.1 MHz
Note
This and subsequent design examples are provided herein to showcase the LM25148 controller
in several different applications. Depending on the source impedance of the input supply bus, an
electrolytic capacitor can be required at the input to ensure stability, particularly at low input voltage
and high output current operating conditions. See Section 10 for more details.
32
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9.2.1.1 Design Requirements
Table 9-2 shows the intended input, output, and performance parameters for this design example.
Table 9-2. Design Parameters
DESIGN PARAMETER
VALUE
Input voltage range (steady state)
8 V to 18 V
Min transient input voltage
5.5 V
Max transient input voltage
36 V
Output voltage
5V
Output current
8A
Switching frequency
2.1 MHz
Output voltage regulation
±1%
Standby current, no-load
9.9 µA
Shutdown current
2.3 µA
Soft-start time
3 ms
The switching frequency is set at 2.1 MHz by resistor RRT. In terms of control loop performance, the target loop
crossover frequency is 60 kHz with a phase margin greater than 50°.
The selected buck regulator powertrain components are cited in Table 9-3, and many of the components are
available from multiple vendors. The MOSFETs in particular are chosen for lowest total conduction and switching
power loss, as discussed in detail in Section 9.1.1.4. This design uses a low-DCR composite inductor, and
ceramic output capacitor implementation.
Table 9-3. List of Materials for Application Circuit 1
REFERENCE
QTY
DESIGNATOR
CIN
CO
2
4
SPECIFICATION
10 µF, 50 V, X7S, 1210, ceramic
47 µF, 6.3 V, X7R, 1210, ceramic
MANUFACTURER
PART NUMBER
Taiyo Yuden
UMJ325KB7106KMHT
Murata
GCM32EC71H106KA03
TDK
CGA6P3X7S1H106K250AB
Murata
GCM32ER70J476KE19L
Taiyo Yuden
JMK325B7476KMHTR
TDK
CGA6P1X7S1A476M250AC
0.56 μH, 3.6 mΩ, 13 A, 6.6 × 6.6 × 4.8 mm
Würth Electronik
744373490056
0.68 µH, 2.9 mΩ, 22 A, 6.7 × 6.5 × 3.1 mm
Colicraft
XGL6030-681
47 µF, 10 V, X7S, 1210, ceramic
LO
1
Q1
1
40 V, 4.7 mΩ, 12 nC, SON 5 × 6
Texas Instruments
CSD18503Q5A
Q2
1
40 V, 2.7 mΩ, 35 nC, SON 5 × 6
Texas Instruments
CSD18511Q5A
RS
1
Shunt, 5 mΩ, 0508, 1 W
Susumu
KRL2012E-M-R005-F-T5
U1
1
LM25148 42-V synchronous buck controller
Texas Instruments
LM25148RGYR
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9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM25148 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
9.2.1.2.2 Custom Design With Excel Quickstart Tool
Select components based on the regulator specifications using the LM25148 Quickstart Calculator available for
download from the LM25148 product folder.
9.2.1.2.3 Buck Inductor
1. Use Equation 30 to calculate the required buck inductance based on a 30% inductor ripple current at
nominal input voltages.
LO
§
VOUT
˜ ¨1
'ILO ˜ FSW ¨
©
VOUT ·
¸
VIN nom ¸
¹
§
5V
5V ·
˜ ¨1
¸
2.4 A ˜ 2.1 MHz © 12 V ¹
0.58 +
(30)
2. Select a standard inductor value of 0.56 µH or use a 0.68 µH to account for effective inductance derating
with current of molded inductors. Use Equation 31 to calculate the peak inductor currents at maximum
steady-state input voltage. Subharmonic oscillation occurs with a duty cycle greater than 50% for peak
current-mode control. For design simplification, the LM25148 has an internal slope compensation ramp
proportional to the switching frequency that is added to the current sense signal to damp any tendency
toward subharmonic oscillation.
ILO(PK)
IOUT
'ILO
2
IOUT
VOUT
2 ˜ LO ˜ FSW
§
VOUT
˜ ¨1
¨
VIN(max)
©
·
¸
¸
¹
8A
5V
0.56 + ˜
§
˜ ¨1
0+] ©
5V ·
¸
9¹
9.53 A
(31)
3. Based on Equation 8, use Equation 32 to cross-check the inductance to set a slope compensation close to
the ideal one times the inductor current downslope.
LO(sc)
VOUT ˜ RS
24 ˜ FSW
5 V ˜ 5m:
24 ˜ 2.1 MHz
0.5 +
(32)
9.2.1.2.4 Current-Sense Resistance
1. Calculate the current-sense resistance based on a maximum peak current capability of at least 25% higher
than the peak inductor current at full load to provide sufficient margin during start-up and load-on transients.
Calculate the current sense resistances using Equation 33.
RS
34
VCS-TH
1.25 ˜ ILO(PK)
60mV
1.25 ˜ 9.53 A
5.04m:
(33)
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where
• VCS-TH is the 60-mV current limit threshold.
2. Select a standard resistance value of 5 mΩ for the shunt. An 0508 footprint component with wide aspect
ratio termination design provides 1-W power rating, low parasitic series inductance, and compact PCB
layout. Carefully adhere to the layout guidelines in Section 11.1 to make sure that noise and DC errors do
not corrupt the differential current-sense voltages measured at the ISNS+ and VOUT pins.
3. Place the shunt resistor close to the inductor.
4. Use Kelvin-sense connections, and route the sense lines differentially from the shunt to the LM25148.
5. The CS-to-output propagation delay (related to the current limit comparator, internal logic, and power
MOSFET gate drivers) causes the peak current to increase above the calculated current limit threshold.
For a total propagation delay tDELAY-ISNS+ of 40 ns, use Equation 34 to calculate the worst-case peak inductor
current with the output shorted.
ILO-PK(SC)
VIN(max) ˜ tDELAY-ISNS+
VCS-TH
RS
60mV
5m:
LO
18 V ˜ 45ns
0.56 +
13.5 A
(34)
6. Based on this result, select an inductor with saturation current greater than 16 A across the full operating
temperature range.
9.2.1.2.5 Output Capacitors
1. Use Equation 35 to estimate the output capacitance required to manage the output voltage overshoot during
a load-off transient (from full load to no load) assuming a load transient deviation specification of 1.5% (75
mV for a 5-V output).
LO ˜ 'IOUT
COUT t
VOUT
2
'VOVERSHOOT
0.56 + ˜
2
VOUT
2
5 V 75mV
$
2
2
5V
47.4 )
2
(35)
2. Noting the voltage coefficient of ceramic capacitors where the effective capacitance decreases significantly
with applied voltage, select four 47-µF, 10-V, X7R, 1210 ceramic output capacitors. Generally, when
sufficient capacitance is used to satisfy the load-off transient response requirement, the voltage undershoot
during a no-load to full-load transient is also satisfactory.
3. Use Equation 36 to estimate the peak-peak output voltage ripple at nominal input voltage.
'VOUT
§
·
'ILO
¨
¸
© 8 ˜ FSW ˜ COUT ¹
2
RESR ˜ 'ILO
2
§
·
2.54A
¨
¸
˜
˜
8
2.1MHz
44
)
©
¹
2
1m: ˜ 2.54 A
2
4.3mV
(36)
where
• RESR is the effective equivalent series resistance (ESR) of the output capacitors.
• 44 µF is the total effective (derated) ceramic output capacitance at 5 V.
4. Use Equation 37 to calculate the output capacitor RMS ripple current using and verify that the ripple current
is within the capacitor ripple current rating.
ICO(RMS)
'ILO
2.54 A
12
12
0.73 A
(37)
9.2.1.2.6 Input Capacitors
A power supply input typically has a relatively high source impedance at the switching frequency. Good-quality
input capacitors are necessary to limit the input ripple voltage. As mentioned earlier, dual-channel interleaved
operation significantly reduces the input ripple amplitude. In general, the ripple current splits between the input
capacitors based on the relative impedance of the capacitors at the switching frequency.
1. Select the input capacitors with sufficient voltage and RMS ripple current ratings.
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2. Use Equation 38 to calculate the input capacitor RMS ripple current assuming a worst-case duty-cycle
operating point of 50%.
ICIN(RMS)
IOUT ˜ D ˜ 1 D
8A ˜ 0.5 ˜ 1 0.5
4A
(38)
3. Use Equation 39 to find the required input capacitance.
CIN t
D ˜ 1 D ˜ IOUT
0.5 ˜ 1 0.5 ˜ 8 A
FSW ˜ 'VIN RESR ˜ IOUT
2.1MHz ˜ 120mV 2m: ˜ 8 A
9.2 )
(39)
where
• ΔVIN is the input peak-to-peak ripple voltage specification.
• RESR is the input capacitor ESR.
4. Recognizing the voltage coefficient of ceramic capacitors, select two 10-µF, 50-V, X7R, 1210 ceramic input
capacitors. Place these capacitors adjacent to the power MOSFETs. See Section 11.1.1 for more details.
5. Use four 10-nF, 50-V, X7R, 0603 ceramic capacitors near the high-side MOSFET to supply the high di/dt
current during MOSFET switching transitions. Such capacitors offer high self-resonant frequency (SRF)
and low effective impedance above 100 MHz. The result is lower power loop parasitic inductance, thus
minimizing switch-node voltage overshoot and ringing for lower conducted and radiated EMI signature. Refer
to Section 11.1 for more details.
9.2.1.2.7 Frequency Set Resistor
Calculate the RT resistance for a switching frequency of 2.1 MHz using Equation 40. Choose a standard E96
value of 9.53 kΩ.
6
RT (k:)
10
FSW (kHz)
45
6
53
10
2100kHz
45
53
9.4k:
(40)
9.2.1.2.8 Feedback Resistors
If an output voltage setpoint other than 3.3 V or 5 V is required (or to measure a bode plot when using either of
the fixed output voltage options), determine the feedback resistances using Equation 41.
(41)
9.2.1.2.9 Compensation Components
Choose compensation components for a stable control loop using the procedure outlined as follows:
1. Based on a specified loop gain crossover frequency, fC, of 60 kHz, use Equation 42 to calculate RCOMP,
assuming an effective output capacitance of 100 µF. Choose a standard value for RCOMP of 10 kΩ.
RCOMP
2S ˜ fC ˜
VOUT RS ˜ GCS
˜
˜ COUT
VREF
gm
2S ˜ 60kHz ˜
5 V 5m: ˜ 10
˜
˜ 100 )
0.8 V 1200 6
N:
(42)
2. To provide adequate phase boost at crossover while also allowing a fast settling time during a load or line
transient, select CCOMP to place a zero at the higher of (1) one tenth of the crossover frequency, or (2) the
load pole. Choose a standard value for CCOMP of 2.7 nF.
CCOMP
36
10
2S ˜ fC ˜ RCOMP
10
2S ˜ 60kHz ˜ 10 k:
2.65 nF
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Such a low capacitance value also helps to avoid output voltage overshoot when recovering from dropout
(when the input voltage is less than the output voltage setpoint and VCOMP is railed high).
3. Calculate CHF to create a pole at the ESR zero and to attenuate high-frequency noise at COMP. CBW is the
bandwidth-limiting capacitance of the error amplifier. CHF may not be significant enough to be necessary in
some designs, like this one. CHF can be unpopulated, or used with a small 22 pF for more noise filtering.
CHF
1
2S ˜ fESR ˜ RCOMP
CBW
1
2S ˜ 500kHz ˜ 10 k:
31 pF
0.8 pF
(44)
Note
Set a fast loop with high RCOMP and low CCOMP values to improve the response when recovering from
operation in dropout.
For technical solutions, industry trends, and insights for designing and managing power supplies, please refer to
TI's technical articles.
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9.2.1.3 Application Curves
100
100
90
90
Efficiency (%)
Efficiency (%)
95
85
80
70
0
1
2
3
4
5
Load Current (A)
6
7
70
60
VIN = 8 V
VIN = 12 V
VIN = 18 V
75
80
8
VIN = 8 V
VIN = 12 V
VIN = 18 V
50
0.001
0.01
0.1
Load Current (A)
Figure 9-6. Efficiency vs IOUT, Log Scale
Figure 9-5. Efficiency vs IOUT
8-A resistive load
No load
Figure 9-7. Full Load Switching
5-A load
Figure 9-9. Line Transient
38
8
5-V output
5-V output
VIN ramps from 12 V to 36 V
1
Figure 9-8. PFM Switching
VIN falls to 3.8 V
5-A load
Figure 9-10. Cold-Crank Response to VIN = 3.8 V
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VIN step to 12 V
8-A resistive load
Figure 9-11. Start-Up Characteristic
VIN = 12 V
8-A resistive load
Figure 9-15. Bode Plot, 5-V Output
8-A resistive load
Figure 9-12. ENABLE ON and OFF Characteristic
VIN = 12 V
FPWM
Figure 9-13. Load Transient, 0 A to 8 A
VIN = 12 V
VIN = 12 V
FPWM
Figure 9-14. Load Transient, 4 A to 8 A
VIN = 13.8 V
150 kHz to 30 MHz
7-A resistive load
Figure 9-16. CISPR 25 Class 5 Conducted EMI
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9.2.2 Design 2 – High Efficiency 440-kHz Synchronous Buck Regulator
Figure 9-17 shows the schematic diagram of a single-output synchronous buck regulator with an output voltage
of 5 V and a rated load current of 10 A. In this example, the target half-load and full-load efficiencies are 97%
and 95%, respectively, based on a nominal input voltage of 12 V that ranges from 5.5 V to 36 V. The switching
frequency is set at 440 kHz by resistor RRT. The 5-V output is connected to VCCX to reduce IC bias power
dissipation and improve efficiency. An output voltage of 3.3 V is also feasible simply by connecting FB to VDDA
(tie VCCX to GND in this case).
LIN
VIN = 3.5 V...36 V 2.2 µH
4
CIN
10 µF
CDAMP
120 F
CF
10
F
VIN
CVCC
2.2 F
VCC
EN
CBOOT
VDDA
RFB
FB
CBOOT
0.1 F
Q1
HO
LO
SW
2.2 H
24.9 k
CCOMP
RCOMP
EXTCOMP
15 nF
4.22 k
LM25148
Q2
LO
VOUT = 5 V
IOUT = 10 A
CO
4 47 F
PGND
CHF
150 pF
Tie to VOUT
or GND
RS
4 m
ISNS+
VOUT
PG/SYNCOUT
VCCX
PFM/SYNC
CNFG
RT
VDDA
AGND
Tie to VDDA
or GND
* VOUT tracks VIN if VIN < 5.3 V
RCNFG
41.2 k
RRT
CVDDA
49.9 k 0.1 F
Figure 9-17. Application Circuit 2 With LM25148 Buck Regulator at 440 kHz
40
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9.2.2.1 Design Requirements
Table 9-4 shows the intended input, output, and performance parameters for this design example.
Table 9-4. Design Parameters
DESIGN PARAMETER
VALUE
Input voltage range (steady-state)
8 V to 36 V
Min transient input voltage
5.5 V
Max transient input voltage
40 V
Output voltage
5V
Output current
10 A
Switching frequency
440 kHz
Output voltage regulation
±1%
Standby current, no-load
12 µA
Shutdown current
2.3 µA
Soft-start time
3 ms
The switching frequency is set at 440 kHz by resistor RRT. The selected buck regulator powertrain components
are cited in Table 9-5, and many of the components are available from multiple vendors. The MOSFETs in
particular are chosen for both lowest conduction and switching power loss, as discussed in detail in Section
9.1.1.4.
Table 9-5. List of Materials for Application Circuit 2
REFERENCE
QTY
DESIGNATOR
CIN
CO
4
4
SPECIFICATION
10 µF, 50 V, X7R, 1210, ceramic
47 µF, 6.3 V, X7R, 1210, ceramic
47 µF, 10 V, X7S, 1210, ceramic
2.2 μH, 4.3 mΩ, 12.5 A, 6.7 × 6.5 × 6.1 mm
MANUFACTURER
PART NUMBER
AVX
12105C106K4Z2A
TDK
C3225X7R1H106K250AC
Murata
GRM32ER71H106KA12L
Murata
GCM32ER70J476KE19L
Taiyo Yuden
JMK325B7476KMHTR
TDK
CGA6P1X7S1A476M250AC
Coilcraft
XGL6060-222MEC
LO
1
Würth Electronik
74437368022
Q1
1
40 V, 4.7 mΩ, 12 nC, SON 5 × 6
Texas Instruments
CSD18503Q5A
Texas Instruments
CSD18511Q5A
Susumu
KRL2012E-M-R004-F-T5
Texas Instruments
LM25148RGYR
2.2 µH, 6.5 mΩ, 10 A, 10 × 11 × 3.8 mm
Q2
1
40 V, 2.7 mΩ, 35 nC, SON 5 × 6
RS
1
Shunt, 4 mΩ, 0508, 1 W
U1
1
LM25148 42-V synchronous buck controller
9.2.2.2 Detailed Design Procedure
See Section 9.2.1.2.
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100
100
95
90
Efficiency (%)
Efficiency (%)
9.2.2.3 Application Curves
90
85
VIN
VIN
VIN
VIN
80
75
0
1
2
3
4
5
6
Load Current (A)
7
8
=
=
=
=
8V
12 V
18 V
24 V
9
10
80
70
VIN
VIN
VIN
VIN
60
50
0.001
0.01
0.1
Load Current (A)
5-V output
=
=
=
=
8V
12 V
18 V
24 V
1
10
5-V output
Figure 9-18. Efficiency vs IOUT
Figure 9-19. Efficiency vs IOUT, Log Scale
VOUT 20mV/DIV
VOUT 50mV/DIV
SW 5V/DIV
SW 5V/DIV
100 ms/DIV
1 µs/DIV
No load
10-A resistive load
Figure 9-21. PFM Switching
Figure 9-20. Full Load Switching
VIN 1 V/DIV
VOUT 1 V/DIV
VIN 10 V/DIV
VOUT 50 mV/DIV
IOUT 1 A/DIV
PG 5 V/DIV
IOUT 5A/DIV
5 ms/DIV
VIN ramps from 12 to 40 V
5-A load
Figure 9-22. Line Transient Response to VIN = 40 V
42
20 ms/DIV
VIN falls to 4 V
1-A load
Figure 9-23. Cold-Crank Response to VIN = 4 V
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EN 2V/DIV
VIN 2V/DIV
VOUT 1V/DIV
VOUT 1V/DIV
IOUT 5A/DIV
IOUT 5A/DIV
1 ms/DIV
1 ms/DIV
VIN step to 12 V
VIN = 12 V
10-A resistive load
Figure 9-24. Start-Up Characteristic
10-A resistive load
Figure 9-25. ENABLE ON and OFF Characteristic
VOUT 500 mV/DIV
VOUT 500 mV/DIV
IOUT 5 A/DIV
IOUT 5 A/DIV
100 µs/DIV
VIN = 12 V
100 µs/DIV
FPWM
Figure 9-26. Load Transient, 0 A to 10 A
VIN = 12 V
FPWM
Figure 9-27. Load Transient, 5 A to 10 A
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9.2.3 Design 3 – Dual-Phase 400-kHz 20-A Synchronous Buck Regulator
Figure 9-28 shows the schematic diagram of a dual-phase synchronous buck regulator with output voltage of
3.3 V and a rated load current of 20 A. In this example, the target half-load and full-load efficiencies are 95%
and 92%, respectively, based on a nominal input voltage of 12 V that ranges from 4 V to 36 V. The switching
frequency is set at 400 kHz by resistors RRT1 and RRT2.
VIN = 4 V...36 V
Tie to 5 V
or GND
VIN
PFM / FPWM setting
or SYNCIN
VCCX
EN
CIN1
2 × 10 F
4 × 10 nF
CVCC1
2.2 F
VCC
CBOOT
PFM/SYNC
HO
VOUT
RFB1
100 k
CBOOT1
0.1 F
FB
LO1
CO1
4 × 47 F
Q2
LO
Primary
VOUT = 3.3 V
IOUT = 20 A
RS1
4 m
2.2 H
SW
LM25148
RFB2
31.6 k
Q1
PGND
RCOMP
CCOMP
5.23 k
8.2 nF
ISNS+
EXTCOMP
VOUT
PG/SYNCOUT
CHF
120 pF
CNFG
RCNFG1
71.5 k
RT
AGND
VDDA
RRT1
56.2 k
CVDDA1
0.1 F
VIN
Tie to 5 V
or GND
PFM/SYNC
VIN
EN
VCCX
CIN2
2 × 10 F
4 × 10 nF
CVCC2
2.2 F
VCC
CBOOT
HO
CBOOT2
0.1
F
LM25148
FB
Q4
LO
Secondary
LO2
2.2 H
SW
PFM / FPWM
setting
Q3
RS2
4 m
CO2
4 × 47
F
PGND
ISNS+
EXTCOMP
VOUT
PG/SYNCOUT
CNFG
RCNFG2
90.9 k
RT
RRT2
56.2 k
VDDA
System
PGOOD
AGND
CVDDA2
0.1 F
Figure 9-28. Application Circuit 3 With Two LM25148 Buck Regulators at 400 kHz
44
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9.2.3.1 Design Requirements
Table 9-6 shows the intended input, output, and performance parameters for this design example.
Table 9-6. Design Parameters
DESIGN PARAMETER
VALUE
Input voltage range (steady-state)
8 V to 36 V
Min transient input voltage
4V
Max transient input voltage
40 V
Output voltage
3.3 V
Output current
20 A
Switching frequency
400 kHz
Output voltage regulation
±1%
Standby current, no-load
44 µA
Shutdown current
4.6 µA
Soft-start time
3 ms
The switching frequency is set at 400 kHz by resistors RRT1 and RRT2. The selected buck regulator powertrain
components are cited in Table 9-7, and many of the components are available from multiple vendors. The
MOSFETs in particular are chosen for both lowest conduction and switching power loss, as discussed in detail in
Section 9.1.1.4.
Table 9-7. List of Materials for Application Circuit 3
REFERENCE
QTY
DESIGNATOR
CIN
CO
4
8
4
LO1, LO2
2
SPECIFICATION
10 µF, 50 V, X7R, 1210, ceramic
MANUFACTURER
PART NUMBER
AVX
12105C106K4Z2A
TDK
C3225X7R1H106K250AC
Murata
GRM32ER71H106KA12L
47 µF, 6.3 V, X7R, 1210, ceramic
Murata
GCM32ER70J476KE19L
47 µF, 10 V, X7S, 1210, ceramic
TDK
CGA6P1X7S1A476M250AC
100 µF, 6.3 V, X7S, 1210, ceramic
Murata
GRT32EC70J107ME13
2.2 μH, 4.5 mΩ, 32 A, 11.3 × 10 × 6 mm
Coilcraft
XKL1060-222MEC
2.2 μH, 4.3 mΩ, 12.5 A, 6.7 × 6.5 × 6.1 mm
2.2 µH, 6.5 mΩ, 10 A, 10 × 11 × 3.8 mm
Coilcraft
XGL6060-222MEC
Würth Electronik
74437368022
Q1, Q3
2
40 V, 4.7 mΩ, 12 nC, SON 5 × 6
Texas Instruments
CSD18503Q5A
Q2, Q4
2
40 V, 2.7 mΩ, 35 nC, SON 5 × 6
Texas Instruments
CSD18511Q5A
RS1, RS2
2
Shunt, 4 mΩ, 0508, 1 W
Susumu
KRL2012E-M-R004-F-T5
U1, U2
2
LM25148 42-V synchronous buck controller
Texas Instruments
LM25148RGYR
9.2.3.2 Detailed Design Procedure
See Section 9.2.1.2.
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9.2.3.3 Application Curves
100
100
95
95
Efficiency (%)
Efficiency (%)
90
90
85
80
VIN
VIN
VIN
VIN
75
70
0
2
4
6
8
10
12
Load Current (A)
14
16
=
=
=
=
8V
12 V
18 V
24 V
18
20
85
80
75
70
VIN
VIN
VIN
VIN
65
60
0.001
0.01
0.1
Load Current (A)
3.3-V output
=
=
=
=
1
8V
12 V
18 V
24 V
10 20
3.3-V output
Figure 9-29. Efficiency vs IOUT
Figure 9-30. Efficiency vs IOUT, Log Scale
VIN 5V/DIV
EN 2V/DIV
VOUT 1V/DIV
VOUT 1V/DIV
IOUT 10A/DIV
IOUT 10A/DIV
1 ms/DIV
VIN step to 12 V
1 ms/DIV
20-A load
Figure 9-31. VIN Start-Up Characteristic
VIN = 12 V
Figure 9-32. ENABLE ON and OFF Characteristic
VOUT 200 mV/DIV
VOUT 500 mV/DIV
IOUT 10 A/DIV
IOUT 10 A/DIV
100 µs/DIV
VIN = 12 V
100 µs/DIV
FPWM
Figure 9-33. Load Transient, 5 A to 15 A
46
20-A load
VIN = 12 V
FPWM
Figure 9-34. Load Transient, 0 A to 20 A
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10 Power Supply Recommendations
The LM25148 buck controller is designed to operate from a wide input voltage range of 3.5 V to 42 V. The
characteristics of the input supply must be compatible with the Absolute Maximum Ratings and Recommended
Operating Conditions. In addition, the input supply must be capable of delivering the required input current to the
fully loaded regulator. Estimate the average input current with Equation 45.
IIN
POUT
VIN ˜ K
(45)
where
•
η is the efficiency
If the regulator is connected to an input supply through long wires or PCB traces with a large impedance,
take special care to achieve stable performance. The parasitic inductance and resistance of the input cables
can have an adverse affect on converter operation. The parasitic inductance in combination with the low-ESR
ceramic input capacitors form an underdamped resonant circuit. This circuit can cause overvoltage transients
at VIN each time the input supply is cycled ON and OFF. The parasitic resistance causes the input voltage to
dip during a load transient. The best way to solve such issues is to reduce the distance from the input supply
to the regulator and use an aluminum or tantalum input capacitor in parallel with the ceramics. The moderate
ESR of the electrolytic capacitors helps damp the input resonant circuit and reduce any voltage overshoots. A
capacitance in the range of 10 µF to 47 µF is usually sufficient to provide parallel input damping and helps to
hold the input voltage steady during large load transients.
An EMI input filter is often used in front of the regulator that, unless carefully designed, can lead to instability as
well as some of the effects mentioned above. The Simple Success with Conducted EMI for DC-DC Converters
application report provides helpful suggestions when designing an input filter for any switching regulator.
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11 Layout
11.1 Layout Guidelines
Proper PCB design and layout is important in a high-current, fast-switching circuit (with high current and voltage
slew rates) to achieve a robust and reliable design. As expected, certain issues must be considered before
designing a PCB layout using the LM25148. The high-frequency power loop of a buck regulator power stage is
denoted by loop 1 in the shaded area of Figure 11-1. The topological architecture of a buck regulator means
that particularly high di/dt current flows in the components of loop 1, and it becomes mandatory to reduce the
parasitic inductance of this loop by minimizing its effective loop area. Also important are the gate drive loops of
the high-side and low-side MOSFETs, denoted by 2 and 3, respectively, in Figure 11-1.
VIN
CBOOT
VCC
CIN
CBOOT
High-side
gate driver
#1
High frequency
power loop
HO
SW
Q1
LO
#2
VOUT
VCC
CVCC
Low-side
gate driver
LO
PGND
Q2
COUT
#3
GND
Figure 11-1. DC/DC Regulator Ground System With Power Stage and Gate Drive Circuit Switching Loops
11.1.1 Power Stage Layout
•
•
48
Input capacitors, output capacitors, and MOSFETs are the constituent components of the power stage of a
buck regulator and are typically placed on the top side of the PCB (solder side). The benefits of convective
heat transfer are maximized because of leveraging any system-level airflow. In a two-sided PCB layout,
small-signal components are typically placed on the bottom side (component side). Insert at least one inner
plane, connected to ground, to shield and isolate the small-signal traces from noisy power traces and lines.
The DC/DC regulator has several high-current loops. Minimize the area of these loops in order to suppress
generated switching noise and optimize switching performance.
– Loop 1: The most important loop area to minimize is the path from the input capacitor or capacitors
through the high- and low-side MOSFETs, and back to the capacitor or capacitors through the ground
connection. Connect the input capacitor or capacitors negative terminal close to the source of the low-side
MOSFET (at ground). Similarly, connect the input capacitor or capacitors positive terminal close to the
drain of the high-side MOSFET (at VIN). Refer to loop 1 of Figure 11-1.
– Another loop, not as critical as loop 1, is the path from the low-side MOSFET through the inductor and
output capacitor or capacitors, and back to source of the low-side MOSFET through ground. Connect the
source of the low-side MOSFET and negative terminal of the output capacitor or capacitors at ground as
close as possible.
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•
•
•
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The PCB trace defined as SW node, which connects to the source of the high-side (control) MOSFET, the
drain of the low-side (synchronous) MOSFET and the high-voltage side of the inductor, must be short and
wide. However, the SW connection is a source of injected EMI and thus must not be too large.
Follow any layout considerations of the MOSFETs as recommended by the MOSFET manufacturer, including
pad geometry and solder paste stencil design.
The SW pin connects to the switch node of the power conversion stage and acts as the return path for the
high-side gate driver. The parasitic inductance inherent to loop 1 in Figure 11-1 and the output capacitance
(COSS) of both power MOSFETs form a resonant circuit that induces high frequency (greater than 50 MHz)
ringing at the SW node. The voltage peak of this ringing, if not controlled, can be significantly higher than
the input voltage. Make sure that the peak ringing amplitude does not exceed the absolute maximum rating
limit for the SW pin. In many cases, a series resistor and capacitor snubber network connected from the SW
node to GND damps the ringing and decreases the peak amplitude. Provide provisions for snubber network
components in the PCB layout. If testing reveals that the ringing amplitude at the SW pin is excessive, then
include snubber components as needed.
11.1.2 Gate-Drive Layout
The LM25148 high-side and low-side gate drivers incorporate short propagation delays, adaptive dead-time
control, and low-impedance output stages capable of delivering large peak currents with very fast rise and
fall times to facilitate rapid turn-on and turn-off transitions of the power MOSFETs. Very high di/dt can cause
unacceptable ringing if the trace lengths and impedances are not well controlled.
Minimization of stray or parasitic gate loop inductance is key to optimizing gate drive switching performance,
whether it be series gate inductance that resonates with MOSFET gate capacitance or common source
inductance (common to gate and power loops) that provides a negative feedback component opposing the
gate drive command, thereby increasing MOSFET switching times. The following loops are important:
• Loop 2: high-side MOSFET, Q1. During the high-side MOSFET turnon, high current flows from the bootstrap
(boot) capacitor through the gate driver and high-side MOSFET, and back to the negative terminal of the boot
capacitor through the SW connection. Conversely, to turn off the high-side MOSFET, high current flows from
the gate of the high-side MOSFET through the gate driver and SW, and back to the source of the high-side
MOSFET through the SW trace. Refer to loop 2 of Figure 11-1.
• Loop 3: low-side MOSFET, Q2. During the low-side MOSFET turnon, high current flows from the VCC
decoupling capacitor through the gate driver and low-side MOSFET, and back to the negative terminal of the
capacitor through ground. Conversely, to turn off the low-side MOSFET, high current flows from the gate of
the low-side MOSFET through the gate driver and GND, and back to the source of the low-side MOSFET
through ground. Refer to loop 3 of Figure 11-1.
TI strongly recommends following circuit layout guidelines when designing with high-speed MOSFET gate drive
circuits.
• Connections from gate driver outputs, HO and LO, to the respective gates of the high-side or low-side
MOSFETs must be as short as possible to reduce series parasitic inductance. Be aware that peak gate drive
currents can be as high as 3.3 A. Use 0.65 mm (25 mils) or wider traces. Use via or vias, if necessary, of at
least 0.5 mm (20 mils) diameter along these traces. Route HO and SW gate traces as a differential pair from
the LM25148 to the high-side MOSFET, taking advantage of flux cancellation.
• Minimize the current loop path from the VCC and HB pins through their respective capacitors as these
provide the high instantaneous current, up to 3.3 A, to charge the MOSFET gate capacitances. Specifically,
locate the bootstrap capacitor, CBST, close to the CBOOT and SW pins of the LM25149 to minimize the area
of loop 2 associated with the high-side driver. Similarly, locate the VCC capacitor, CVCC, close to the VCC and
PGND pins of the LM25148 to minimize the area of loop 3 associated with the low-side driver.
11.1.3 PWM Controller Layout
With the proviso to locate the controller as close as possible to the power MOSFETs to minimize gate driver
trace runs, the components related to the analog and feedback signals as well as current sensing are considered
in the following:
• Separate power and signal traces, and use a ground plane to provide noise shielding.
• Place all sensitive analog traces and components related to COMP, FB, ISNS+, and RT away from highvoltage switching nodes such as SW, HO, LO, or CBOOT to avoid mutual coupling. Use internal layer or
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•
•
•
layers as ground plane or planes. Pay particular attention to shielding the feedback (FB) and current sense
(ISNS+ and VOUT) traces from power traces and components.
Locate the upper and lower feedback resistors (if required) close to the FB pin, keeping the FB trace as short
as possible. Route the trace from the upper feedback resistor to the required output voltage sense point at
the load.
Route the ISNS+ and VOUT sense traces as differential pairs to minimize noise pickup and use Kelvin
connections to the applicable shunt resistor (if shunt current sensing is used) or to the sense capacitor (if
inductor DCR current sensing is used).
Minimize the loop area from the VCC and VIN pins through their respective decoupling capacitors to the
PGND pin. Locate these capacitors as close as possible to the LM25148.
11.1.4 Thermal Design and Layout
The useful operating temperature range of a PWM controller with integrated gate drivers and bias supply LDO
regulator is greatly affected by the following:
•
•
•
•
Average gate drive current requirements of the power MOSFETs
Switching frequency
Operating input voltage (affecting bias regulator LDO voltage drop and hence its power dissipation)
Thermal characteristics of the package and operating environment
For a PWM controller to be useful over a particular temperature range, the package must allow for the
efficient removal of the heat produced while keeping the junction temperature within rated limits. The LM25148
controller is available in a small 4-mm × 4-mm 24-pin VQFN PowerPAD package to cover a range of application
requirements. Section 11.1.4 summarizes the thermal metrics of this package.
The 24-pin VQFN package offers a means of removing heat from the semiconductor die through the exposed
thermal pad at the base of the package. While the exposed pad of the package is not directly connected to any
leads of the package, it is thermally connected to the substrate of the LM25149 device (ground). This allows a
significant improvement in heat sinking, and it becomes imperative that the PCB is designed with thermal lands,
thermal vias, and a ground plane to complete the heat removal subsystem. The exposed pad of the LM25148 is
soldered to the ground-connected copper land on the PCB directly underneath the device package, reducing the
thermal resistance to a very low value.
Numerous vias with a 0.3-mm diameter connected from the thermal land to the internal and solder-side ground
plane or planes are vital to help dissipation. In a multi-layer PCB design, a solid ground plane is typically placed
on the PCB layer below the power components. Not only does this provide a plane for the power stage currents
to flow but it also represents a thermally conductive path away from the heat generating devices.
The thermal characteristics of the MOSFETs also are significant. The drain pads of the high-side MOSFETs are
normally connected to a VIN plane for heat sinking. The drain pads of the low-side MOSFETs are tied to the SW
plane, but the SW plane area is purposely kept as small as possible to mitigate EMI concerns.
11.1.5 Ground Plane Design
As mentioned previously, TI recommends using one or more of the inner PCB layers as a solid ground plane. A
ground plane offers shielding for sensitive circuits and traces and also provides a quiet reference potential for the
control circuitry. In particular, a full ground plane on the layer directly underneath the power stage components
is essential. Connect the source terminal of the low-side MOSFET and return terminals of the input and output
capacitors to this ground plane. Connect the PGND and AGND pins of the controller at the DAP and then
connect to the system ground plane using an array of vias under the DAP. The PGND nets contain noise at the
switching frequency and can bounce because of load current variations. The power traces for PGND, VIN, and
SW can be restricted to one side of the ground plane, for example on the top layer. The other side of the ground
plane contains much less noise and is ideal for sensitive analog trace routes.
50
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11.2 Layout Example
Figure 11-2 shows a single-sided layout of a synchronous buck regulator with discrete power MOSFETs, Q1 and
Q2, in SON 5-mm × 6-mm case size. The power stage is surrounded by a GND pad geometry to connect an
EMI shield if needed. The design uses layer 2 of the PCB as a power-loop return path directly underneath the
top layer to create a low-area switching power loop of approximately 2 mm². This loop area, and hence parasitic
inductance, must be as small as possible to minimize EMI as well as switch-node voltage overshoot and ringing.
The high-frequency power loop current flows through MOSFETs Q1 and Q2, through the power ground plane
on layer 2, and back to VIN through the 0603 ceramic capacitors C15 through C18. The currents flowing in
opposing directions in the vertical loop configuration provide field self-cancellation, reducing parasitic inductance.
Figure 11-4 shows a side view to illustrate the concept of creating a low-profile, self-canceling loop in a multilayer
PCB structure. The layer-2 GND plane layer, shown in Figure 11-3, provides a tightly-coupled current return path
directly under the MOSFETs to the source terminals of Q2.
Four 10-nF input capacitors with small 0402 or 0603 case size are placed in parallel very close to the drain
of Q1. The low equivalent series inductance (ESL) and high self-resonant frequency (SRF) of the small
footprint capacitors yield excellent high-frequency performance. The negative terminals of these capacitors are
connected to the layer-2 GND plane with multiple 12-mil (0.3-mm) diameter vias, further minimizing parasitic
loop inductance.
Use PGND keep-out to
minimize eddy currents
Locate controller close
to the power stage
Place PGND vias close to the
source of the low-side FET
Output Caps
PGND
VIN
SW
HO
GND
LO
VCC
GS
Input Caps G S
AGND
VIN
VOUT
Low-side
FET
Inductor
SW
Shunt
High-side
FET
GND
GND
Copper island
connected to AGND pin
Use paralleled 0402/0603 input capacitors close
to the FETs for VIN to PGND decoupling
Figure 11-2. PCB Top Layer – High Density, Single-sided Design
Additional guidelines to improve noise immunity and reduce EMI are as follows:
•
•
Make the ground connections to the LM25148-Q1 controller as shown in Figure 11-2. Create a power
ground directly connected to all high-power components and an analog ground plane for sensitive analog
components. The analog ground plane for AGND and power ground plane for PGND must be connected at a
single point directly under the IC – at the die attach pad (DAP).
Connect the MOSFETs (switch node) directly to the inductor terminal with short copper connections (without
vias) as this net has high dv/dt and contributes to radiated EMI. The single-layer routing of the switch-node
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•
connection means that switch-node vias with high dv/dt do not appear on the bottom side of the PCB. This
avoids e-field coupling to the reference ground plane during the EMI test. VIN and PGND plane copper
pours shield the polygon connecting the MOSFETs to the inductor terminal, further reducing the radiated EMI
signature.
Place the EMI filter components on the bottom side of the PCB so that they are shielded from the power
stage components on the top side.
Figure 11-3. Layer 2 Full Ground Plane Directly Under the Power Components
Tightly-coupled return path
minimizes power loop impedance
Q2
GND
SW
Q1
VIN
Cin1-4
GND
L1
0.15mm
L2
L3
0.3mm
vias
L4
Figure 11-4. PCB Stack-up Diagram With Low L1-L2 Intra-layer Spacing 1
1
52
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
With an input operating voltage as low as 3.5 V and up to 100 V as specified in Table 12-1, the LM(2)514x family
of synchronous buck controllers from TI provides flexibility, scalability and optimized solution size for a range
of applications. These controllers enable DC/DC solutions with high density, low EMI and increased flexibility.
Available EMI mitigation features include dual-random spread spectrum (DRSS) or triangular spread spectrum
(TRSS), split gate driver outputs for slew rate (SR) control, and integrated active EMI filtering (AEF).
Table 12-1. Synchronous Buck DC/DC Controller Family
DC/DC
CONTROLLER
SINGLE or
DUAL
VIN RANGE
CONTROL METHOD
GATE DRIVE
VOLTAGE
SYNC OUTPUT
EMI MITIGATION
LM25141
Single
3.8 V to 42 V
Peak current mode
5V
N/A
SR control, TRSS
LM25143
Dual
3.5 V to 42 V
Peak current mode
5V
90° phase shift
SR control, TRSS
LM25145
Single
6 V to 42 V
Voltage mode
7.5 V
180° phase shift
N/A
LM25148
Single
3.5 V to 42 V
Peak current mode
5V
180° phase shift
DRSS
LM25149
Single
3.5 V to 42 V
Peak current mode
5V
180° phase shift
AEF, DRSS
LM5141
Single
3.8 V to 42 V
Peak current mode
5V
N/A
SR control, TRSS
LM5143
Dual
3.5 V to 65 V
Peak current mode
5V
90° phase shift
SR control, TRSS
LM5145
Single
6 V to 75 V
Voltage mode
7.5 V
180° phase shift
N/A
LM5146
Single
5.5 V to 100 V
Voltage mode
7.5 V
180° phase shift
N/A
LM5148
Single
3.5 V to 80 V
Peak current mode
5V
180° phase shift
DRSS
LM5149
Single
3.5 V to 80 V
Peak current mode
5V
180° phase shift
AEF, DRSS
For development support see the following:
•
•
•
•
•
•
•
LM25148 Quickstart Calculator
LM25148 Simulation Models
For TI's reference design library, visit TI Designs
For TI's WEBENCH Design Environment, visit the WEBENCH® Design Center
TI Designs:
– ADAS 8-Channel Sensor Fusion Hub Reference Design with Two 4-Gbps Quad Deserializers
– Automotive EMI and Thermally Optimized Synchronous Buck Converter Reference Design
– Automotive High Current, Wide VIN Synchronous Buck Controller Reference Design Featuring LM5141Q1
– 25W Automotive Start-Stop Reference Design Operating at 2.2 MHz
– Synchronous Buck Converter for Automotive Cluster Reference Design
– 137W Holdup Converter for Storage Server Reference Design
– Automotive Synchronous Buck With 3.3V @ 12.0A Reference Design
– Automotive Synchronous Buck Reference Design
– Wide Input Synchronous Buck Converter Reference Design With Frequency Spread Spectrum
– Automotive Wide VIN Front-end Reference Design for Digital Cockpit Processing Units
Technical Articles:
– High-Density PCB Layout of DC/DC Converters
– Synchronous Buck Controller Solutions Support Wide VIN Performance and Flexibility
– How to Use Slew Rate for EMI Control
To view a related device of this product, see the LM25141
12.1.1.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM25148 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
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3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer gives a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
•
•
•
•
User's Guides:
– LM25149-Q1 Synchronous Buck Controller High Density EVM
– LM5141-Q1 Synchronous Buck Controller EVM
– LM5143-Q1 Synchronous Buck Controller EVM
– LM5146-Q1 EVM User's Guide
– LM5145 EVM User's Guide
Application Reports:
– Improve High-current DC/DC Regulator Performance for Free with Optimized Power Stage Layout
Application Report
– AN-2162 Simple Success with Conducted EMI from DC-DC Converters
– Maintaining Output Voltage Regulation During Automotive Cold-Crank with LM5140-Q1 Dual Synchronous
Buck Controller
Technical Briefs:
– Reduce Buck Converter EMI and Voltage Stress by Minimizing Inductive Parasitics
White Papers:
– An Overview of Conducted EMI Specifications for Power Supplies
– An Overview of Radiated EMI Specifications for Power Supplies
– Valuing Wide VIN, Low EMI Synchronous Buck Circuits for Cost-driven, Demanding Applications
12.2.1.1 PCB Layout Resources
•
•
Application Reports:
– Improve High-current DC/DC Regulator Performance for Free with Optimized Power Stage Layout
– AN-1149 Layout Guidelines for Switching Power Supplies
– AN-1229 Simple Switcher PCB Layout Guidelines
– Low Radiated EMI Layout Made SIMPLE with LM4360x and LM4600x
Seminars:
– Constructing Your Power Supply – Layout Considerations
12.2.1.2 Thermal Design Resources
•
54
Application Reports:
– AN-2020 Thermal Design by Insight, Not Hindsight
– AN-1520 A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages
– Semiconductor and IC Package Thermal Metrics
– Thermal Design Made Simple with LM43603 and LM43602
– PowerPAD™Thermally Enhanced Package
– PowerPAD Made Easy
– Using New Thermal Metrics
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Product Folder Links: LM25148
LM25148
www.ti.com
SNVSC05 – DECEMBER 2021
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 Trademarks
NexFET™ and TI E2E™ are trademarks of Texas Instruments.
PowerPAD™ is a trademark of Texas Instruments.
WEBENCH® is a registered trademark of Texas Instruments.
is a registered trademark of TI.
All trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages show mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Product Folder Links: LM25148
55
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2023
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
LM25148RGYR
ACTIVE
VQFN
RGY
24
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 150
LM25148
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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