LM26001EVAL

User's Guide SNVA153B – May 2006 – Revised April 2013 AN-1454 LM26001 Evaluation Board 1 Introduction The LM26001 evaluation board is designed to demonstrate the capabilities of the LM26001 switching regulator. The LM26001 board, schematic shown in Figure 1, is configured to provide an output of 3.3V at up to 1.5A from an input range of 3.5V to 38V (a minimum of 4.5V is required for startup). The nominal operating frequency is 305 kHz and can be synchronized from +30% to -20% of nominal using the SYNC connection post. The evaluation board is designed to operate at ambient temperatures up to 75°C. Typical evaluation board waveforms and performance curves are shown in Figure 2 through Figure 7. Figure 8 and Figure 9 show the pcb trace layout. To aid in the design and evaluation of dc/dc buck converters based on the LM26001 regulator, the evaluation board can be re-configured for different output voltages and operating frequencies. Test points are also provided to enable easy connection and monitoring of critical signals. Table 2 shows the Bill of Materials (BOM) for a second example circuit for 1.5V output and 480 kHz switching frequency. This design operates from an input voltage of 3.5V to 38V and enters pulse skipping mode at approximately 24Vin, depending on loading. For more information about device function and circuit design, see the LM26001/LM26001Q 1.5A Switching Regulator with High Efficiency Sleep Mode Data Sheet (SNVS430). 2 Jumper Settings The FPWM jumper is used to disable the sleep mode function. For normal operation, select ‘off’, which connects FPWM to GND. For FPWM operation (sleep mode disabled), select ‘on’. The Vbias jumper connects the VBIAS pin to Vout. When Vout is greater than 3V, the VBIAS function will be activated for improved efficiency. To disable VBIAS, or if Vout is set to less than 3V, set the jumper to ‘GND’. 3 Optional Components Before changing the default components, see the device-specific data sheet for information regarding the component selection. Output voltage and frequency are easily adjustable with single resistors, R1 and R3, respectively. However, large changes to the default settings may require other changes to the inductor, output capacitor, and compensation network. Several optional component pads have been provided for application flexibility. The C7 pad is provided for an additional ceramic output capacitor. This capacitor can be used to lower the total ESR at the output. D2 blocks reverse current to the input supply during low input voltage and light load conditions. This diode may not be necessary in all applications and can be replaced with a jumper. C10 is a phase lead capacitor that can be installed to increase phase and gain margin. For more detailed information, see the compensation section of the device-specific data sheet. All trademarks are the property of their respective owners. SNVA153B – May 2006 – Revised April 2013 Submit Documentation Feedback AN-1454 LM26001 Evaluation Board Copyright © 2006–2013, Texas Instruments Incorporated 1 Powering Up 4 www.ti.com Powering Up Before powering up the LM26001 evaluation board, all external connections should be verified. The power supply input must be turned off and connected with proper polarity to the VIN and GND posts. The load should be connected between the VOUT post and GND post. Both the VIN and VOUT connections should use the GND post closest to the VIN post. Output voltage can be monitored with a DVM or oscilloscope at the VOUT post. The second GND post, close to the IC, is provided primarily for small signal measurements, such as softstart voltage, or PGOOD. This GND post should also be used when applying optional external signals such as EN and SYNC. Once all connections have been verified, input power can be applied. The input voltage must be set between 4.5V and 38V. The load can be on or off at startup. If the EN post is left open, the output voltage will ramp up when VIN is applied VIN: 3.5V ± 38V D2 2A + C1 3.3 PF C2 47 PF VDD 1 R4 200k 2 3 PGOOD 4 EN 11 SYNC 5 R6 10k C5 10 nF GND 6 C9 47 pF R5 15k 7 C8 4.7 nF VIN SW VIN SW 14 R1 56k C4 BOOT 13 EN D1 3A + VDD 0.1PF LM26001 VBIAS SS FPWM COMP FB FREQ EP GND C7 ** C3 10 PF 12 SYNC C6 100 PF GND VDD 17 R2 33k 22 PH 15 PGOOD VOUT: 3.3V/1.5A L1 16 10 J-Vbias 9 8 R3 120k VDD J-FPWM C10 ** ** Component not installed Figure 1. Evaluation Board Schematic 2 AN-1454 LM26001 Evaluation Board SNVA153B – May 2006 – Revised April 2013 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Powering Up www.ti.com Table 1. LM26001 Bill of Materials (BOM) for VO = 3.3V, 1.5A, 305kHz Ref No Value Footprint C1 3.3µF 50V X7R ceramic 1210 C2 47µF 50V low ESR electrolytic Supplier TDK Panasonic C3 10µF 10V B ceramic 1206 Murata C4 0.1µF 50V COG ceramic 1206 Murata C5 10nF 50V X7R ceramic 0603 Murata C6 100µF 8V 12mohm SP C7 not installed 1206 - C8 4.7nF 50V COG ceramic 0603 Murata Murata Panasonic C9 47pF 50V COG ceramic 0603 C10 not installed 0603 - D1 60V 3A NSQ03A06 SMC NIEC D2 60V 2A EC21QS06 SMA NIEC L1 22µH 3.5A SLF12565T-220M3R5 R1 56kΩ 1% 0603 TDK - R2 33kΩ 1% 0603 - R3 120kΩ 1% 0603 - R4 200kΩ 5% 0603 - R5 15kΩ 1% 0603 - R6 10kΩ 5% 0603 - SNVA153B – May 2006 – Revised April 2013 Submit Documentation Feedback AN-1454 LM26001 Evaluation Board Copyright © 2006–2013, Texas Instruments Incorporated 3 Performance Characteristics 5 www.ti.com Performance Characteristics Unless otherwise specified, VIN = 12V, TA = 25°C. VOUT 10 mV/DIV VOUT 1V/DIV PGOOD 5V/DIV SS 1V/DIV IL 500 mA/DIV SW 5V/DIV EN 10V/DIV 2 Ps/DIV 2 ms/DIV Figure 2. Start-Up Waveforms (IOUT = 1A) Figure 3. PWM Waveforms (IOUT = 1A) VOUT 50 mV/DIV VOUT 50 mV/DIV IL 200 mA/DIV SW 5V/DIV 4 IOUT 500 mA/DIV 100 Ps/DIV 400 Ps/DIV Figure 4. Sleep Mode Waveforms (IOUT = 25mA) Figure 5. Load Transient Response (IOUT = 0.25A to 1.5A step) AN-1454 LM26001 Evaluation Board SNVA153B – May 2006 – Revised April 2013 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated PCB Layout Diagram(s) 90 160 85 140 80 120 75 100 IOUT (mA) EFFICIENCY (%) www.ti.com 70 FPWM MODE 65 80 60 60 40 55 20 50 0 1 10 100 1k 10k 0 IOUT (mA) 10 15 20 25 30 35 40 VIN (V) Figure 6. Efficiency vs IOUT (VBIAS = VOUT) 6 5 Figure 7. Sleep Mode Threshold Load Current vs Input Voltage PCB Layout Diagram(s) Figure 8. Top Side Layout SNVA153B – May 2006 – Revised April 2013 Submit Documentation Feedback AN-1454 LM26001 Evaluation Board Copyright © 2006–2013, Texas Instruments Incorporated 5 PCB Layout Diagram(s) www.ti.com Figure 9. Bottom Side Layout 6 AN-1454 LM26001 Evaluation Board SNVA153B – May 2006 – Revised April 2013 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated PCB Layout Diagram(s) www.ti.com Table 2. LM26001 Bill of Materials (BOM) for VO = 1.5V, 1.5A, 480kHz Ref No Value Footprint C1 3.3µF 50V X7R ceramic 1210 C2 47µF 50V electrolytic Supplier TDK Panasonic C3 10µF 10V B ceramic 1206 Murata C4 0.1µF 50V COG ceramic 1206 Murata C5 10nF 50V X7R ceramic 0603 Murata C6 100µF 8V 12mohm SP C7 10µF 6.3V X7R ceramic 1206 Panasonic Murata C8 6.8nF 16V COG ceramic 0603 Murata Murata C9 68pF 25V COG ceramic 0603 C10 not installed 0603 - D1 60V 3A NSQ03A06 SMC NIEC D2 60V 2A EC21QS06 SMA NIEC L1 3.3µH 4.1A RLF7030T-3R3M4R1 R1 8.2kΩ 1% 0603 TDK - R2 39kΩ 1% 0603 - R3 75kΩ 1% 0603 - R4 200kΩ 5% 0603 - R5 20kΩ 1% 0603 - R6 10kΩ 5% 0603 - SNVA153B – May 2006 – Revised April 2013 Submit Documentation Feedback AN-1454 LM26001 Evaluation Board Copyright © 2006–2013, Texas Instruments Incorporated 7 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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