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LM26003EVAL

LM26003EVAL

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    -

  • 描述:

    BOARD EVAL FOR LM26003

  • 数据手册
  • 价格&库存
LM26003EVAL 数据手册
User's Guide SNVA360B – August 2008 – Revised April 2013 AN-1884 LM26003 Evaluation Board 1 Introduction The LM26003 evaluation board is designed to demonstrate the capabilities of the LM26003 switching regulator. The LM26003 board schematic, shown in Figure 1, is configured to provide an output of 3.3V at up to 3A from an input range of 4V to 38V. The nominal operating frequency is 300 kHz and can be synchronized from +30% to -20% of nominal using the SYNC connection post. The evaluation board is designed to operate at ambient temperatures up to 75°C. Typical evaluation board waveforms and performance curves are shown in Section 6. The PCB trace layout is shown in Section 7. To aid in the design and evaluation of dc/dc buck converters based on the LM26003 regulator, the evaluation board can be re-configured for different output voltages and operating frequencies. Test points are also provided to enable easy connection and monitoring of critical signals. For more information about device function and circuit design, refer to LM26003/LM26003Q 3A Switching Regulator with High Efficiency Sleep Mode (SNVS576). VIN: 4V - 38V C9 6.8 PF + C10 100 PF R7 0: 1 2 VDD C2 100 nF R4 200 k: 3 4 5 PGOOD 6 EN 14 SYNC 7 R6 10 k: C3 22 nF GND 8 C4 220 pF R3 12.1 k: C5 4.7 nF R2 33.2 k: 9 R1 56.2 k: SW 20 L1 19 SW VIN 15 PH 18 D1 VIN SW C6 5A VDD 17 BOOT AVIN 16 0.1 PF VDD C1 PGOOD 10 PF 15 EN VBIAS 13 FPWM SYNC J-Vbias 12 VDD SS FREQ R5 J-FPWM 11 C8 124 PGND COMP 10 PF k: 10 FB EP AGND 21 VIN VOUT: 3.3V/3A + C7 120 PF + C12 ** R8 20: C11 ** Figure 1. Evaluation Board Schematic All trademarks are the property of their respective owners. SNVA360B – August 2008 – Revised April 2013 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated AN-1884 LM26003 Evaluation Board 1 Jumper Settings 2 www.ti.com Jumper Settings The FPWM jumper is used to disable the sleep mode function. For normal operation, select ‘off’ which connects FPWM to GND. For FPWM operation (sleep mode disabled), select ‘on’. The Vbias jumper connects the VBIAS pin to Vout. When Vout is greater than 3V, the VBIAS function will be activated for improved efficiency. To disable VBIAS, or if Vout is set to less than 3V, set the jumper to ‘GND’. 3 Optional Components Before changing the default components, please refer to the product datasheet for information regarding component selection. Output voltage and frequency are easily adjustable with single resistors R2 and R5, respectively. However, large changes to the default settings may require other changes to the inductor, output capacitor and compensation network. Several optional component pads have been provided for application flexibility. The C8 pad is provided for an additional ceramic output capacitor, This capacitor is used to filter noise on the output line to prevent noise from coupling into the Vbias line when the IC is supplied by Vout. If the Vbias function is not used, C8 is not necessary. C11 is a phase lead capacitor which can be installed to increase phase and gain margin. See the compensation section of the datasheet for more detailed information. The resistor R8 can be used as an injection point for a loop stability measurement. R7 is populated with a 0Ω resistor. A higher resistor value can be used on this location to build an RC filter in combination with C2 bypass capacitor. 4 Powering Up Before powering up the LM26003 evaluation board, all external connections should be verified. The power supply input must be turned off and connected with proper polarity to the VIN and GND posts. The load should be connected between the VOUT post and GND post. Both the VIN and VOUT connections should use the GND post closest to VIN or VOUT. Output voltage can be monitored with a DVM or oscilloscope at the VOUT post. Once all connections have been verified, input power can be applied. The load can be on or off at startup. If the EN post is left open, the output voltage will ramp up when VIN is applied. 2 AN-1884 LM26003 Evaluation Board SNVA360B – August 2008 – Revised April 2013 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Bill of Materials www.ti.com 5 Bill of Materials Table 1. LM26003 Bill of Materials Ref # Value Footprint Supplier Part Number C1 10 µF 10V ceramic 1206 (inch) TDK C3216X5R1A106M C2 100 nF 50V ceramic 0603 (inch) TDK C1608X7R1H104K C3 22 nF 10V ceramic 0603 (inch) TDK C1608SL1A223J C4 220 pF 10V ceramic 0603 (inch) TDK VJ0603A221JXQCW1BC C5 4.7 nF 10V ceramic 0603 (inch) TDK VJ0603Y472JXQCW1BC C6 100 nF 50V ceramic 0603 (inch) TDK C1608X7R1H104K C7 120 µF 6.3V 24 mΩ ESR 5.3 × 5.3mm Nippon Chemi-Con APXE6R3ARA121ME61G C8 10 µF 10V ceramic 1206 (inch) TDK C3216X5R1A106M C9 6.8 µF 50V ceramic 1812 (inch) TDK C4532X7R1H685M C10 100 µF 63V 10.3x10.3mm Panasonic EEE-FK1J101P C11 Not installed - - C12 Not installed - - D1 40V 5A Schottky SMC Central Semiconductor CMSH 5-40 L1 15 µH 5.0A WE-PD XL 12x12mm Wurth 744770115 R1 56.2 kΩ 0603 (inch) - CRCW060356K2FKEA R2 33.2 kΩ 0603 (inch) - CRCW060333K2FKEA R3 12.1 kΩ 0603 (inch) - CRCW060312K1FKEA R4 200 kΩ 0603 (inch) - CRCW0603200KJNEA R5 124 kΩ 0603 (inch) - CRCW0603124KFKEA R6 10 kΩ 0603 (inch) - CRCW060310K0JNEA R7 0Ω 0603 (inch) - CRCW06030000Z0EA R8 20Ω 0603 (inch) - CRCW060320R0JNEA U1 LM26003 TSSOP-20 Texas Instruments LM26003 SNVA360B – August 2008 – Revised April 2013 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated AN-1884 LM26003 Evaluation Board 3 Performance Characteristics 6 www.ti.com Performance Characteristics Unless otherwise specified, VIN = 12V, TA = 25°C Figure 2. Load Transient Response (IOUT = 0.4A to 3A step) Figure 3. Efficiency vs IOUT (VBIAS = VOUT) Figure 4. Sleep Mode Threshold Load Current vs Input Voltage 4 AN-1884 LM26003 Evaluation Board SNVA360B – August 2008 – Revised April 2013 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated PC Board Layout www.ti.com 7 PC Board Layout Figure 5. Top Side Layout Figure 6. Bottom Side Layout SNVA360B – August 2008 – Revised April 2013 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated AN-1884 LM26003 Evaluation Board 5 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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