LM2650M-ADJ

LM2650 www.ti.com SNVS133C – JUNE 1999 – REVISED APRIL 2013 LM2650 Synchronous Step-Down DC/DC Converter Check for Samples: LM2650 FEATURES DESCRIPTION • • The LM2650 is a step-down DC/DC converter featuring high efficiency over a 3A to milliamperes load range. This feature makes the LM2650 an ideal fit in battery-powered applications that demand long battery life in both run and standby modes. 1 2 • • • • • • • • • • • Ultra High Efficiencies (95% possible) High Efficiency Over a 3A to Milliamperes Load Range Synchronous Switching of Internal NMOS Power FETs Wide Input Voltage Range (4.5V to 18V) Output Voltage Adjustable from 1.5V to 16V Automatic Low-Power Sleep Mode Logic-Controlled Micropower Shutdown (IQSD ≤ 25 µA) Frequency Adjustable up to 300 kHz Frequency Synchronization with External Signal Programmable Soft-Start Short-Circuit Current Limiting Thermal Shutdown Available in 24-lead Small-Outline Package APPLICATIONS • • • • • • Notebook and Palmtop Personal Computers Portable Data Terminals Modems Portable Instruments Global Positioning Devices (GPSs) Battery-Powered Digital Devices The LM2650 also features a logic-controlled shutdown mode in which it draws at most 25μA from the input power supply. The LM2650 employs a fixed-frequency pulse-width modulation (PWM) and synchronous rectification to achieve very high efficiencies. In many applications, efficiencies reach 95%+ for loads around 1A and exceed 90% for moderate to heavy loads from 0.2A to 2A. A low-power hysteretic or "sleep" mode keeps efficiencies high at light loads. The LM2650 enters and exits sleep mode automatically as the load crosses "sleep in" and "sleep out" thresholds. The LM2650 provides nodes for programming both thresholds via external resistors. A logic input allows the user to override the automatic sleep feature and keep the LM2650 in PWM mode regardless of the load level. An optional soft-start feature limits current surges from the input power supply at start up and provides a simple means of sequencing multiple power supplies. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1999–2013, Texas Instruments Incorporated LM2650 SNVS133C – JUNE 1999 – REVISED APRIL 2013 www.ti.com Typical Application Figure 1. Converting a Four-Cell Li Ion Battery to 5V LM2650-ADJ Efficiency Figure 2. Connection Diagram Figure 3. Top View 24-Lead Small Outline Package (DW) See Package Number DW0024B 2 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LM2650 LM2650 www.ti.com SNVS133C – JUNE 1999 – REVISED APRIL 2013 PIN DESCRIPTIONS (1) Pins Description 1, 12 SUB: These pins make electrical contact with the substrate of the die. Ground them. For best thermal performance, ground them to the same large, uninterrupted copper plane as the PGND pins. 2 SLEEP LOGIC: Use this logic input to select the conversion mode; low selects PWM, high selects sleep, and high impedance (open) permits the LM2650 to move freely and automatically between the modes, using PWM for moderate to heavy loads and sleep for light loads. 3, 4, 9, 10 PGND: The ground return of the power stage. The power stage consists of the two power switches Q1 and Q2, the gate drivers DH and DL, and the linear voltage regulators VRegH and VRegL. For best electrical and thermal performance, ground these pins to a large, uninterrupted copper plane. 5, 8 SW: The output node of the power stage. It swings from slightly below ground to slightly below the voltage to PVIN. To minimize the effects of switching noise on nearby circuitry, keep all traces originating from SW short and to the point. Route all traces carrying signals well away from the SW traces. 6, 7 PVIN: The positive supply rail of the power stage. Bypass each PVIN pin to PGND with a 0.1 μF capacitor. Use capacitors having low ESL and low ESR, and locate them close to the IC. 11 BOOT: The positive supply rail of the high-side gate driver DH. Connect a 0.1 μF capacitor from this node to SW. Bootstrapping action creates a supply rail about 9V above that at PVIN, and DH uses this rail to override the gate of the NMOS power FET Q1. Overriding ensures low RDS(on). 13 FB: The feedback input. 14 VDD: An internal regulator steps the input voltage down to a 4V rail used by the signal-level circuitry. VDD is the output node of this regulator. Bypass VDD to GND close to the IC with a 0.2 μF capacitor. 15 COMP: The inverting input of the error amplifier EA. 16 EA OUT: The output node of the error amplifier EA. 17 SS: The soft start node. Connect a capacitor from SS to GND. 18 GND: The ground return of the signal-level circuitry. 19 VIN: The positive supply rail of the internal 4V regulator. Bypass VIN to GND close to the IC with a 0.1 μF capacitor. 20 FREQ ADJ: The LM2650 switches at a nominal 90 kHz. Connect a resistor between FREQ ADJ and GND to adjust the frequency up from the nominal. Use the graph under Typical performance Characteristics to select the resistor. 21 SYNC: The synchronization input. If the switching frequency is to be synchronized with an external clock signal, apply the clock signal here. Ground if not used. 22 SD: Use this logic input to control shutdown; pull low for operation, high for shutdown. 23 SLEEP OUT ADJ (SOA): The value of the resistor connected between SIA and ground programs the sleep-in threshold. Higher values program lower thresholds. 24 SLEEP IN ADJ (SIA): The value of the resistor connected between SIA and ground programs the sleep-in threshold. Higher values program lower thresholds. (1) Refer to the Block Diagrams. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LM2650 3 LM2650 SNVS133C – JUNE 1999 – REVISED APRIL 2013 www.ti.com Absolute Maximum Ratings (1) (2) (All voltages are referenced to the PGND and GND pins.) DC Voltage at PVIN and VIN 20V DC Voltage at SD, SLEEP LOGIC and SYNC 15V DC current into SW ±7.5A Junction Temperature Limited by the IC DC Power Dissipation (3) 1.28W −65°C to +150°C Storage Temperature Soldering Time, Temperature (4) ESD Susceptibility (1) (2) (3) (4) (5) Wave (4 seconds) 260°C Infrared (10 seconds) 240°C Vapor Phase (75 seconds) 219°C (5) 1.3 kV Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which the device operates correctly. Operating ratings do not imply performance limits. For performance limits and associated test conditions, see the Electrical Characteristics. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. This rating is calculated using the formula PDCmax = (TJmax − TA) / θJA, where PDCmax is the absolute maximum power dissipation, TJmax is the maximum junction temperature, and θJA is the junction ot ambient thermal resistance of the package. The PDCmax rating of 1.28W results from substituting 170°C, 70°C and 78°C/W for TJmax, TA and θJA respectively. A θJAof 78°C represents the worst condition of no heat sinking of the DW0024B small-outline package. Heat sinking allows the safe dissipation of more power. See Application Notes on thermal management. The LM2650 actively limits its junction temperature to about 170°C. For detailed information on soldering plastic small-outline packages, refer to the Packaging Databook published by Texas Instruments. ESD is applied using the human-body model, a 100pF capacitor discharged through a 1.5kΩ resistor. Operating Ratings (1) Supply Voltage Range (PVIN and VIN) 4.5V to 18V −40°C to +125°C Junction Temperature Range (1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which the device operates correctly. Operating ratings do not imply performance limits. For performance limits and associated test conditions, see the Electrical Characteristics. Electrical Characteristics VPVIN = 15V, VSLEEP LOGIC = 0V and VSD = 0V unless superseded under Conditions. Typicals and limits appearing in plain type apply for TA = TJ = +25°C. Limits appearing in boldface type apply over the full junction temperature range shown under Operating Ratings. Symbol VOUT Parameter Output Voltage Conditions R1 = 75 kΩ, 1%, R2 = 25 kΩ, 1%, 7.5V ≤ VPVIN ≤ 18V 0.12A ≤ ILOAD ≤ 3A Typ (1) Limit (2) Units 4.80/4.75 5.20/5.25 V V(min) V(max) 5.00 η1 System Efficiency ILOAD = 1A, TA = 25°C, FOSC Not Adjusted 94 % η2 System Efficiency ILOAD = 3A, TA = 25°C, FOSC Not Adjusted 89 % (3) VREF Reference Voltage VSLEEPLOGIC = 3V IQ Quiescent Current in PWM mode VFB = VREF −20mV (4) 4.0 IVFB = VREF −20mV, VSLEEPLOGIC = 3V (4) 850 IQS (1) (2) (3) (4) 4 Quiescent Current in Sleep mode 1.25 1.281/1.294 1.219/1.206 V(min) V(max) 6.50/7.0 mA mA(max) 1.35/1.60 μA mA(max) A typical is the center of characterization data taken at TA = TJ = 25°C. Tested at TA = TJ = 125°C and statistical correlation for room temperature and cold limits. VREF is measured at SLEEP OUT ADJ. Quiescent current is the total current flowing into the PVIN and VIN pins. IQ includes the current used to drive the gates of the two NMOS power FETs at the nominal switching frequency. IQS includes no such current. Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LM2650 LM2650 www.ti.com SNVS133C – JUNE 1999 – REVISED APRIL 2013 Electrical Characteristics (continued) VPVIN = 15V, VSLEEP LOGIC = 0V and VSD = 0V unless superseded under Conditions. Typicals and limits appearing in plain type apply for TA = TJ = +25°C. Limits appearing in boldface type apply over the full junction temperature range shown under Operating Ratings. Symbol IQSD RDS(on) HS RDS(on) LS Parameter Conditions (5) Typ (1) Quiescent Current in Shutdown mode VSD = 3V DC On-Resistance Drain-to-Source of the High-Side Power Switch IDS = 1A, VSLEEPLOGIC = 3V, VFB = 3V, VBOOT = 24V 130 DC On-Resistance Drain-to-Source of the Low-Side Power Switch IDS = 1A, VFB = 3V 125 HS Leakage current of the High-Side Power Switch VPVIN = 18V, VSW = 0V, VSD = 3V 100 IL LS Leakage current of the Low-Side Power Switch VPVIN = 18V, VSW = 18V, VSD = 3V 95 Active Current Limit of the HighSide Power Switch VPVIN = 15V, VBOOT = 24V, VFB = 3V, VSLEEPLOGIC = 3V, 5.5 Oscillator Frequency VFB = VREF −20 mV 90 FOSC FMAX DMAX DMIN VDD ISS TSD (5) (6) μA μA(max) 170/245 mΩ mΩ(max) 175/245 mΩ mΩ(max) 10 nA μA(max) 210 μA μA(max) A A(min) A(max) 80/75 100/105 kHz kHz(min) kHz(max) 270/260 360/370 kHz kHz(min) kHz(max) 94/93 % %(min) 5 % %(min) 3.6/3.4 4.2/4.3 V V(min) V(max) 6.5/6.0 V V(min) 13.5/20.0 μA μA(max) 10 50 mV mV(min) mV(max) VIL of SD 0.95 V(max) VIH of SD 2.10 V(min) VIL of SLEEP LOGIC 0.9 V(max) VIH of SLEEP LOGIC 2.0 V(min) VIL of SYNC 0.50 V(max) VIH of SYNC 1.45 V(min) Maximum Oscillator Frequency Maximum Duty Cycle Minimum Duty Cycle Bootstrap Regulator Voltage (VRegH) IFREQ ADJ = 100μA, (6) VFB = VREF −20 mV 315 VFB = VREF −20 mV, FOSC Not Adjusted 97 VFB = VREF +50 mV, FOSC Not Adjusted 2.8 IVDD = 1 mA 4.0 IBOOT = 1 mA Soft Start Current VHYST 20/25 3.5 7.5 Internal Rail Voltage VBOOT Units 9 IL ILIMIT Limit (2) Hysteresis of the Sleep Comparator (C2 Figure 16) 7.5 10 VSLEEPLOGIC = 3V TJ for Thermal Shutdown 30 170 °C Quiescent current is the total current flowing into the PVIN and VIN pins. IQ includes the current used to drive the gates of the two NMOS power FETs at the nominal switching frequency. IQS includes no such current. Pulling 100μA out of FREQ ADJ simulates adjusting the oscillator frequency with a 12.5 kΩ resistor connected from FREQ ADJ to GND. The sleep mode cannot be used at switching frequencies above 250 kHz. Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LM2650 5 LM2650 SNVS133C – JUNE 1999 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics 6 IQSD vs Input Voltage IQS vs Input Voltage Figure 4. Figure 5. IQ vs Input Voltage IQ vs Oscillator Frequency Figure 6. Figure 7. RDS(on) Low-Side vs Input Voltage RDS(on) High-Side vs Input Voltage Figure 8. Figure 9. Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LM2650 LM2650 www.ti.com SNVS133C – JUNE 1999 – REVISED APRIL 2013 Typical Performance Characteristics (continued) RDS(on) Low-Side vs Junction Temperature RDS(on) High-Side vs Junction Temperature Figure 10. Figure 11. Oscillator Frequency vs Junction Temperature Oscillator Frequency vs Adjusting Resistor Figure 12. Figure 13. Current Limit vs Junction Temperature Figure 14. Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LM2650 7 LM2650 SNVS133C – JUNE 1999 – REVISED APRIL 2013 www.ti.com Block Diagrams Figure 15. The PWM Circuit with External Components in a Closed Control Loop Figure 16. The Hysteretic or "Sleep" Circuit with External Components in a Closed Control Loop Figure 17. The Internal Voltage Regulator and Voltage Reference used by Both the PWM and Hysteretic Circuits 8 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LM2650 LM2650 www.ti.com SNVS133C – JUNE 1999 – REVISED APRIL 2013 OPERATION OVERVIEW The LM2650 uses two step-down conversion modes: fixed-frquency pulse-width modulation (PWM) and hysteretic. It moves freely and automatically between them, using PWM for moderate to heavy loads and hysteretic for light loads. For clarity, separate block diagrams for each conversion mode have been included. See Figure 15 and Figure 16. Blocks used in both modes appear in both diagrams with the same label. For example, both modes use the input buffer B. To keep the diagrams simple, most power supply rails have been omitted. R3, C10, RC, CC, CB, L1, R1, R2, and COUT are outside the IC. THE PWM CIRCUIT (Figure 15) The PWM is a fixed-frequency, voltage-mode pulse-width modulator. It consists of four functional blocks: an input buffer, an error amplifier, a modulator, and a power stage. 1. The input buffer B: B is a voltage follower. A fraction of the output voltage is fed back to its noninverting input FB. Circumventing B by using the COMP input as the feedback input will cause the IC to malfunction. 2. The error amplifier EA: EA is a voltage amplifier. It subtracts the feedback voltage from the 1.25V reference and amplifies the difference to produce an error voltage for the control loop. For the purpose of loop compensation, EA is typically configured as an integrator. In this configuration, a capacitor CC and a resistor RC are connected in series between the inverting input COMP and the output terminal EA OUT. The capacitor and the internal 6.5kΩ resistor create a pole, while the capacitor and series resistor create a zero. 3. The modulator: The modulator is the heart of the PWM circuit. It consists of the 90 kHz oscillator, the voltage comparator C1, and output logic represented here as a simple SR latch. – The modulator generates a continuous stream of rectangular, signal-level. It generates the pulses at a fixed frequency, and it modulates or varies their widths in response to variations in the error voltage. The pulses appear at Q, the output of the SR latch. An increase in the error voltage results in a proportional increase in the pulse widths, and, conversely, a decrease in the error voltage results in a proportional decrease in the pulse widths. – The oscillator produces a 90 kHz sawtooth that ramps between 1V and 2V. At the beginning of each ramp, the oscillator sets the SR latch sending Q high. As the ramp voltage surpasses the error voltage, C1 resets the SR latch sending Q low. An increase in the error voltage increases the time between the setting and the resetting of the SR latch which , in turn, results in an equal increase in pulse widths: that is, an equal increase in the time Q spends high in each cycle. A decrease in the error voltage has the opposite effect on the pulse widths as it decreases the time between the setting and resetting of the SR latch. 4. The power stage: The power stage puts some punch between the output of the modulator by translating the stream of signal-level pulses generated by the modulator into a stream of power pulses that swing from ground up to the input voltage while sinking and sourcing as much as 3.5A. The power stage consists of two gate drivers DH and DL, two linear voltage regulators VRegH and VRegL, and two NMOS power FETs Q1 and Q2. – The power pulses appear at the SW mode. When Q goes high, DL drives the gate of Q2 low turning Q23 off. While Q2 turns off, the SW potential may remain at just below ground as the body diode of Q2 conducts what was previously reverse current (source-to-drain) in Q2, or the SW potential may swing up to just above the input voltage as the body diode of Q1 conducts what was previously forward current (drain-to-source) in Q2. About 50 ns after Q goes high, DH drives the gate of Q1 high turning Q1 on. If the task remains, Q1 pulls the SW potential up, if not, Q1 simply takes over the conduction responsibility from its own body diode. When Q goes low, the inverse action occurs resulting in the SW potential swinging from the input voltage to the ground. The 50 ns delay between one switch beginning to turn off and the other switch beginning to turn on prevents the switches from "shooting through" directly from the input supply to the ground. Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LM2650 9 LM2650 SNVS133C – JUNE 1999 – REVISED APRIL 2013 www.ti.com – The PWM circuit drives the pulse stream into the low-pass filter made up of L1 and COUT. The filter passed the DC component of the stream and attenuates the AC components. The output of the filter is the DC voltage VOUT superimposed with a small ripple voltage. Since the DC component of any periodic waveforms the average value of the waveform, VOUT can be found using: (1) – Here T is the switching period in seconds V(t) is the pulse stream. Under DC steady-state conditions, (1) yields (2) – Here VIN is the input voltage, and therefore the height of the pulses, in volts, is the width of the pulses in seconds, and D is the ratio of tON to T, the duty or the duty cycle. – The output voltage is programmed using the resistive divider made up for R1 and R2, (3) – As Q1 turns on, its source voltage swings up to just below the input voltage. The LM2650 uses a simple technique called "bootstrapping" to pull the positive supply rail of DH (at BOOT) up along with the source voltage of Q1, but to a voltage above the input voltage. Because the source of Q1 and the positive supply rail of DH make the same voltage swing together, DH maintains the positive gate-to-source voltage required to turn Q1 on. Q12 plays an active role in pulling the supply rail of DH up and is therefore said to pull itself up by its "bootstraps", thus the name of the technique and of the BOOT pin. – In the typical application, a capacitor CB is connected outside the IC between the BOOT and SW pins. When Q2 is on, the input supply charges CB through VRegH and the internal diode D. THE HYSTERETIC CIRCUIT AND LOOP (Figure 16) Except for C2, the hysteretic circuit borrows all its circuit blocks from the PWM circuit. The hysteretic comparator C2 is a voltage comparator with built-in hysteresis VHYST of typically 30mV centered at 1.25V. The diode D2 is the body diode of Q2. The hysteretic circuit uses D2 as a rectifier instead of switching Q2 as a synchronous rectifier. When the load current drops below the prescribed sleep-in threshold, the LM2650 shuts down the PWM loop and starts up the hysteretic loop. The hysteretic loop supports light loads more efficiently because it uses less power to support its own operation; it uses less bias power because it's a simpler loop having less circuit blocks to bias, and it switches slower, so it incurs lower switching losses. The hysteretic control loop does not switch at a constant frequency. Instead, it monitors VOUT and switches only when VOUT reaches either side of a narrow window centered on the desired output voltage. C2 directs the switching based on its reading of the feedback voltage. Switching in this manner yields a regulated voltage consisting of the desired output voltage and an AC ripple voltage. The magnitude of the AC component can be approximated using (4) For example, with VOUT set to 5V, VOUT_PP is approximately 120mV, (5) When it starts up, the hysteretic loop turns Q1 on. While Q1 is on, the input power supply charges COUT and supplies current to the load. Current from the supply reaches C and the load via the series path provided by Q1 and L1. As the feedback voltage just surpasses the upper hysteretic threshold of C2, the output of C2 changes from high to low, and HD responds by pulling the gate of Q1 down turning Q1 off. As Q1 turns off, L1 generates a negative-going voltage transient that D2 clamps at just below ground. D2 remains on only briefly as the current in L1 runs out. While both Q1 and D2 are off, COUT alone supplies current to the load. As the feedback voltage just surpasses the lower hysteretic threshold of C2, the output of C2 changes states from low to high, and DH responds by pulling the gate of Q1 up turning Q1 on and starting the hysteretic cycle over. 10 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LM2650 LM2650 www.ti.com SNVS133C – JUNE 1999 – REVISED APRIL 2013 Note that as the load current decreases, it takes increasingly longer periods for the load current to discharge COUT through the hysteretic window, and as the load current increases, the periods become even shorter. It can be seen from the above observation that the switching frequency of the hysteretic loop varies as the load varies. The switching frequency can be approximated using (6) Here f is the switching frequency in hertz, I is the load current in amperes, COUT is the value of the capacitor in farads, and VOUT_PP is the magnitude of the AC ripple voltage in volts. Typical switching frequencies range anywhere from a few hertz for very light loads to a few thousand hertz for light loads bordering on the moderate level. Application Circuits Figure 18 is a schematic of the typical application circuit. use the component values shown in the figure and those contained in Table 1 to build a 5V, 3A, or 3.3V, 3A step-down DC/DC converter. As with the design of any DC/DC converter, the design of these circuits involved tradeoffs between efficiency, size, and cost. Here more weight was given to efficiency than to size as evidenced by the low switching frequency which keeps switching losses low but pushes the value and size of the inductor up. From a smaller circuit, use the component values shown in Figure 18 and those contained in Table 3. These circuits trade slightly higher switching losses for a much smaller inductor. Note, Figure 18 does not show RFA, the resistor required to adjust the switching frequency from 90 kHz up to 200 kHz. Connect RFA between the FREQ ADJ pin and ground. Figure 18. The Typical 90 kHz Application Circuit Table 1. Components for the Typical 90 kHz Application Circuit Input Voltage 7V to 18V IN Applicable Cell Stacks 8 to 12 Cell NiCd or NiMh, 3 to 4 Cell Li Ion, 8 to 11 Cell Alkaline, 6 Cell Lead Acid Output 5V, 3A Out 3.3V, 3A out Input Capacitor CIN 2 x 22 μF, 35V AVX TPS Series or Sprague 593D Series 2 x 22 μF, 35V AVX TPS Series or Sprague 593D Series Inductor L1 40μH (See Table 2) 33μH (See Table 2) Output Capacitor COUT 3x220 μF, 10V AVX TPS Series or Sprague 593D Series 3x220 μF, 10V AVX TPS Series or Sprague 593D Series Feedback Resistors R1 and R2 R1 = 75kΩ, 1%, R2 = 24.9kΩ, 1%, R1 = 41.2kΩ, 1%, R2 = 24.9kΩ, 1%, Compensation Components RC, CC, R3, and C10 RC = 37.4 kΩ, CC = 4.7 nF, R3 = 3.57 kΩ, C10 = 5.6 nF RC = 23.2 kΩ, CC = 8.2 nF, R3 = 2.0 kΩ, C10 = 10 nF Sleep Resistors RSIA and RSOA RSIA = 33 kΩ, RSOA = 200 kΩ RSIA = 39 kΩ, RSOA = 130 kΩ Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LM2650 11 LM2650 SNVS133C – JUNE 1999 – REVISED APRIL 2013 www.ti.com Table 2. Toroidal Inductors Using Cores from MICROMETALS, INC. Core Number Core Material Wire Gauge Number of Strands Number of Turns 15μH T38 −52 AWG # 23 1 21 20μH T38 −52 AWG # 23 1 25 33μH T50 −52 AWG # 21 1 41 40μH T50 (B) −18 AWG # 21 1 41 Table 3. Components for Typical 200 kHz Applications Input Voltage 7V to 18V IN Applicable Cell Stacks 8 to 12 Cell NiCd or NiMh, 3 to 4 Cell Li Ion, 8 to 11 Cell Alkaline, 6 Cell Lead Acid Output 5V, 3A Out 3.3V, 3A out Input Capacitor CIN 2 x 22 μF, 35V AVX TPS Series or Sprague 593D Series 2 x 22 μF, 35V AVX TPS Series or Sprague 593D Series Inductor L1 20μH (See Table 2) 15μH (See Table 2) Output Capacitor COUT 3x220 μF, 10V AVX TPS Series or Sprague 593D Series 3x220 μF, 10V AVX TPS Series or Sprague 593D Series Feedback Resistors R1 and R2 R1 = 75kΩ, 1%, R2 = 24.9kΩ, 1%, R1 = 41.2kΩ, 1%, R2 = 24.9kΩ, 1%, Compensation Components RC, CC, R3, and C10 RC = 53.6 kΩ, CC = 2.7 nF, R3 = 4.02 kΩ, C10 = 4.7 nF RC = 33.2 kΩ, CC = 3.9 nF, R3 = 3.01 kΩ, C10 = 6.8 nF Sleep Resistors RSIA and RSOA RSIA = 33 kΩ, RSOA = 200 kΩ RSIA = 47 kΩ, RSOA = 91 kΩ Frequency Adjusting Resistor RFA RFA = 24.9 kΩ RFA = 24.9 kΩ Figure 19. An Efficient, 2% Accurate 5V to 3.3V Converter 12 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LM2650 LM2650 www.ti.com SNVS133C – JUNE 1999 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision B (April 2013) to Revision C • Page Changed layout of National Data Sheet to TI format .......................................................................................................... 12 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LM2650 13 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) LM2650M-ADJ/NOPB ACTIVE SOIC DW 24 30 RoHS & Green SN Level-3-260C-168 HR -40 to 125 LM2650M -ADJ LM2650MX-ADJ/NOPB ACTIVE SOIC DW 24 1000 RoHS & Green SN Level-3-260C-168 HR -40 to 125 LM2650M -ADJ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of