LM2657
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SNVS342B – JANUARY 2005 – REVISED MARCH 2013
LM2657 Dual Synchronous Buck Regulator Controller
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FEATURES
DESCRIPTION
•
•
The LM2657 is an adjustable 200kHz-500kHz dual
channel
voltage-mode
controlled
high-speed
synchronous buck regulator controller ideally suited
for high current applications. The LM2657 requires
only N-channel FETs for both the upper and lower
positions of each stage. It features line feedforward to
improve the response to input transients. At very light
loads, the user can choose between the highefficiency Pulse-skip mode or the constant frequency
Forced-PWM mode. Lossless current limiting without
the use of external sense resistors is made possible
by sensing the voltage drop across the bottom FET.
A unique adaptive duty cycle clamping technique is
incorporated to significantly reduce peak currents
under abnormal load conditions. The two
independently programmable outputs switch 180° out
of phase (interleaved switching) reducing the input
capacitor and filter requirements. The input voltage
range is 4.5V to 28V while the output voltages are
adjustable down to 0.6V.
1
2
•
•
•
•
•
•
•
•
•
•
•
•
•
Input Voltage Range from 4.5V to 28V
Synchronous Dual-Channel Interleaved
Switching
Forced-PWM or Pulse-Skip Modes
Lossless Bottom-Side FET Current Sensing
Adaptive Duty Cycle Clamp
High Current N-Channel FET Drivers
Low Shutdown Supply Current
Reference Voltage Accurate to within ±1.5%
Output Voltage Adjustable Down to 0.6V
Power Good Flag and Chip Enable
Under-Voltage Lockout
Over-Voltage/Under-Voltage Protection
Soft-Start
Switching Frequency Adjustable 200kHz500kHz
28-Pin TSSOP Package
APPLICATIONS
•
Standard supervisory and control features include
Soft-start, Power Good, output Under-voltage and
Over-voltage protection, Under-voltage Lockout, and
chip Enable.
Low Output Voltage High-Efficiency Buck
Regulators
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2013, Texas Instruments Incorporated
LM2657
SNVS342B – JANUARY 2005 – REVISED MARCH 2013
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Typical Application (Channel 2 in parenthesis)
VIN
5V
D2
(D1)
VIN
Q1
(Q4)
BOOT1 (2)
VRON
LM2657
FPWM
C30
(C28)
C32
(C1)
HDRV1 (2)
L1
(L2)
Vo1
(Vo2)
SW1 (2)
R8 (R7)
ILIM1 (2)
C25
(C22)
R18
FPWM
LDRV1 (2)
Q2
(Q5)
R17
EN
POK
C26
(C23)
PGND1 (2)
SENSE1 (2)
C31
R20
PGOOD
V5
C6 (C5)
R9 (R6)
C17
(C14)
COMP1 (2)
VDD
R1
C7 (C4)
FB1 (2)
FREQ
R21
(R15)
SS1 (2)
SGND
C16
(C15)
C29
R19
R23
(R14)
R22
(R16)
Connection Diagram
SENSE1
1
28
ILIM1
FB1
2
27
SW1
COMP1
3
26
HDRV1
SS1
4
25
BOOT1
VDD
5
24
PGND1
FREQ
6
23
LDRV1
SGND
7
22
VIN
EN
8
21
V5
PGOOD
9
20
LDRV2
FPWM
10
19
PGND2
SS2
11
18
BOOT2
COMP2
12
17
HDRV2
FB2
13
16
SW2
SENSE2
14
15
ILIM2
Figure 1. 28-Pin TSSOP (Top View)
See PW Package
PIN DESCRIPTION
Pin 1, SENSE1: Output voltage sense pin for Channel 1. It is tied directly to the output rail. The SENSE pin voltage is used by the IC,
together with the VIN voltage (Pin 22) to calculate the CCM (continuous conduction mode) duty cycle. This is used by the
IC to set the minimum duty cycle in the SKIP mode to 85% of the CCM value. It is also used to set the adaptive duty
cycle clamp (see Pin 3).
Pin 2, FB1:
2
Feedback pin for Channel 1. This is the inverting input of the channel’s error amplifier. The voltage on this pin under
regulation is nominally at 0.6V. A ‘Power Good window’ on this pin determines if the output voltage is within regulation
limits (±13%). If the voltage (on either channel) falls outside this window for more than 7µs, ‘Power Not Good’ is signaled
on the PGOOD pin (Pin 9). Additionally, if the FB voltage is above the upper limit, an over-voltage fault condition occurs
which turns on the low-side FET. The part will resume normal operation on the next high side cycle in which no fault is
detected. When single channel operation is desired (one channel is used, the other is disabled), the feedback pins of
both channels must be connected together, near the IC. All other pins specific to the unused channel should be left
floating (not connected to each other, either).
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PIN DESCRIPTION (continued)
Pin 3, COMP1:
Compensation pin for Channel 1. This is the output of the error amplifier. The voltage level on this pin is compared with
an internally generated ramp signal to set the duty cycle for normal regulation. Since the Feedback pin is the inverting
input of the same error amplifier, the appropriate control loop compensation components are placed between this pin and
the Feedback pin. The COMP pin is internally pulled low during Soft-start to limit the duty cycle. Once Soft-start is
completed, the voltage on this pin can take up the value required to maintain output regulation. Note that an internal
voltage clamp does not allow the pin to go much higher than the steady-state requirement. This forms the ‘adaptive duty
cycle clamp’ circuit, which serves to limit the maximum allowable duty cycle and peak currents under sudden overloads.
Also note that this clamp has been designed with enough ‘headroom’ to permit an adequate response to step loads
within normal operating range.
Pin 4, SS1:
Channel 1 Soft-start pin. A Soft-start capacitor is placed between this pin and ground. A typical capacitance of 0.1µF is
recommended. During startup using chip Enable/power-up, soft-start is reset by connecting an internal 1.8 kΩ resistor
between this pin and ground (RSS_DCHG, see ELECTRICAL CHARACTERISTICS table). It discharges any remaining
charge on the Soft-start capacitors to ensure that the voltage on both Soft-start pins is below 100mV. Reset having thus
been obtained, an 11µA current source at this pin charges up the Soft-start capacitor. The voltage on this pin controls the
maximum duty cycle, and this produces a gradual ramp-up of the output voltage, thereby preventing large inrush currents
into the output capacitors. The voltage on this pin finally clamps close to 5V. During current limit, VDD UVLO, or VIN
UVLO this pin is connected to an internal 115µA current sink whenever a current limit event is in progress. This sink
current quickly discharges the Soft-start capacitor and forces the duty cycle low to protect the power components.
Pin 5, VDD:
5V supply rail for the control and logic sections of both channels. For normal operation to start, the voltage on this pin
must be brought above 4.5V. Subsequently, the voltage on this pin (including any ripple component) should not be
allowed to fall below 4V for a duration longer than 7µs. Since this pin is also the supply rail for the internal control
sections, it should be well-decoupled particularly at high frequencies. A minimum 0.1µF-0.47µF (ceramic) capacitor
should be placed on the component side very close to the IC with no intervening vias between this capacitor and the
VDD/SGND pins. If the voltage on Pin 5 falls below the lower UVLO threshold, the upper and lower FETs are both turned
OFF. ‘Power Not Good’ is also signaled immediately (on Pin 9.) Normal operation will resume once the fault condition
has cleared. Additionally if the voltage on this pin falls below the minimum voltage required for logic operation (about
1.8V typ) the part will shutdown identically to enable (see pin 8) being pulled low.
Pin 6, FREQ:
Frequency adjust pin. The switching frequency (for both channels) is set by a resistor connected between this pin and
ground. A value of 22.1kΩ sets the frequency to 300kHz (nominal). If the resistance is increased, the switching frequency
falls. An approximate relationship is that for every 7.3kΩ increase (or decrease) in the value of the frequency adjust
resistance, the time period (1/f) increases (or decreases) by about 1µs.
Pin 7, SGND:
Signal Ground pin. This is the lower rail for the control and logic sections of both channels. SGND should be connected
on the PCB to the system ground, which in turn is connected to PGND1 and PGND2. The layout is important and the
recommendations in the section LAYOUT GUIDELINES should be followed.
Pin 8, EN:
IC Enable pin. When EN is taken high, both channels are enabled by means of a Soft-start power-up sequence (see Pin
4). When EN is brought low, ‘Power Not Good’ is signaled within 100ns. The Soft-start capacitor is then discharged by an
internal 1.8kΩ resistor (RSS_DCHG, see ELECTRICAL CHARACTERISTICS table) to ground.
Pin 9, PGOOD:
Power Good output pin. An open-Drain logic output that is pulled high with an external pull-up resistor, indicating that
both output voltages are within a pre-defined ‘Power Good’ window, VIN and VDD are within required operating range, and
enable is high. Outside this window, this pin is internally pulled low (‘Power Not Good’ signaled) provided the output error
lasts for more than 7µs. The pin also goes low within 100ns of the Enable pin being taken low, or VDD going below
UVLO, or VIN going below UVLO irrespective of the output voltage level. Regulation on both channels must be achieved
first before fault monitoring becomes active (i.e. PGOOD must have been high prior to occurrence of the fault condition
for a fault to be asserted). For correct signaling on this pin under single-channel operation, see description of Pin 2.
Pin 10, FPWM:
Logic input for selecting either the Forced PWM (‘FPWM’) Mode or Pulse-skip Mode (‘SKIP’) for both channels (together).
When the pin is driven high, the IC operates in the FPWM mode, and when pulled low or left floating, the SKIP mode is
enabled. In FPWM mode, the lower FET of a given channel is always ON whenever the upper FET is OFF (except for a
narrow shoot-through protection deadband). This leads to continuous conduction mode of operation, which has a fixed
frequency and (almost) fixed duty cycle down to very light loads. But this does reduce efficiency at light loads. The
alternative is the SKIP mode, where the lower FET remains ON only till the voltage on the Switch pin (see Pin 27 or Pin
16) goes above -2.2mV (typical). So for example, for a 21mΩ FET, this translates to a current threshold of 2.2/21 = 0.1A.
Therefore if the (instantaneous) inductor current falls below this value, the lower FET will turn OFF every cycle at this
point (when operated in SKIP mode). This threshold is set by the ‘Zero-cross Comparator’ in the Block Diagram. Note
that if the inductor current waveform is high enough to cause the SW pin to be always below this ‘zero-cross threshold’
(see ELECTRICAL CHARACTERISTICS table), there will be no observable difference between FPWM and SKIP mode
settings (in steady-state). SKIP mode, when it occurs, is clearly a discontinuous mode of operation. However, in
conventional discontinuous mode, the duty cycle keeps falling (towards zero) as the load decreases. But the LM2657
does not ‘allow’ the duty cycle to fall by more than 15% of its original value (at the CCM-DCM boundary). This leads to
pulse-skipping, and so the average frequency decreases as the load decreases. This mode of operation improves
efficiency at light loads, but the frequency is effectively no longer a constant. Note that a minimum preload of 0.1mA
should be maintained on the output of each channel to ensure regulation in SKIP mode. The resistive divider from output
to ground used to set the output voltage could be designed to serve as this preload.
Pin 11, SS2:
Soft-start pin for Channel 2. See Pin 4.
Pin 12, COMP2: Compensation pin for Channel 2. See Pin 3.
Pin 13, FB2:
Feedback pin for Channel 2. See Pin 2.
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PIN DESCRIPTION (continued)
Pin 14,
SENSE2:
Output voltage sense pin for Channel 2. See Pin 1.
Pin 15, ILIM2:
Channel 2 Current Limit pin. When the bottom FET is ON, a 62µA (typical) current flows out of this pin into an external
current limit setting resistor connected to the drain of the lower FET. This is a current source so the drop across this
resistor tries to push the voltage on this pin to a more positive value. However, the drain of the lower FET, which is
connected to the other side of the same resistor, is trying to go more negative as the load current increases. Therefore at
some value of current, the voltage on this pin will cross zero and start to go negative. This is the current limiting condition
and it is detected by the ‘Current Limit Comparator’ seen in the BLOCK DIAGRAM. When a current limit condition has
been detected, the next ON-pulse of the upper FET will be omitted. The lower FET will again be monitored to determine if
the current has fallen below the threshold. If it has, the next ON-pulse will be permitted. If not, the upper FET will stay
OFF, and remain so for several cycles if necessary, until the current returns to normal. Eventually, if the overcurrent
condition persists and the upper FET has not been turned ON, the output will start to fall eventually triggering “Power not
Good”.
Pin 16, SW2:
The Switching node of the buck regulator of Channel 2. Also serves as the lower rail of the floating driver of the upper
FET.
Pin 17, HDRV2: Gate drive pin for the upper FET of Channel 2 (High-side drive). The top gate driver is interlocked with the bottom gate
driver to prevent shoot-through/cross-conduction.
Pin 18, BOOT2: Bootstrap pin for Channel 2. This is the upper supply rail for the floating driver of the upper FET. It is bootstrapped by
means of a ceramic capacitor connected to the channel Switching node. This capacitor is charged up by the IC to a value
of about 5V as derived from the V5 pin (Pin 21).
Pin 19, PGND2: Power Ground pin of Channel 2. This is the return path for the bottom FET gate drive. Both the PGND's are to be
connected on the PCB to the system ground and also to the Signal ground (Pin 7) in accordance with the recommended
Layout Guidelines .
Pin 20, LDRV2:
Gate drive pin for the Channel 2 bottom FET (Low-side drive). The bottom gate driver is interlocked with the top gate
driver to prevent shoot-through/cross-conduction.
Pin 21, V5:
Upper rail of the lower FET drivers of both channels. Also used to charge up the bootstrap capacitors of the upper FET
drivers. This is connected to an external 5V supply. The 5V rail may be the same as the rail used to provide power to the
VDD pin (Pin 5). If these rails are connected, the VDD pin must be well-decoupled so that it does not interact with the V5
pin. A minimum 0.1µF (ceramic) capacitor should be placed on the component side very close to the IC with no
intervening vias between this capacitor and the V5/PGND pins.
Pin 22, VIN:
The input that powers both the buck regulator channels. It also is used by the internal ramp generator to implement the
line ‘feedforward’ feature. The VIN pin is also used with the SENSE pin voltage to predict the CCM (continuous
conduction mode) duty cycle and to thereby set the minimum allowed DCM duty cycle to 85% of the CCM value (in SKIP
mode, see Pin 10). This is a high input impedance pin, drawing only about 115µA from the input rail. A fault condition will
occur if this voltage drops below its UVLO threshold.
Pin 23, LDRV1:
LDRV pin of Channel 1. See Pin 20.
Pin 24, PGND1: PGND pin for Channel 1.See Pin 19.
Pin 25, BOOT1: Boot pin of Channel 1. See Pin 18.
Pin 26, HDRV1: HDRV pin of Channel 1. See Pin 17.
Pin 27, SW1:
SW pin of Channel 1. See Pin 16.
Pin 28, ILIM1:
Channel 1 Current Limit pin. See Pin 15.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
4
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ABSOLUTE MAXIMUM RATINGS (1) (2)
Voltages from the indicated pins to GND unless otherwise indicated (3):
VIN
-0.3V to 30V
V5
-0.3V to 7V
VDD
-0.3V to 7V
BOOT1, BOOT2
-0.3V to 36V
BOOT1 to SW1, BOOT2 to SW2
-0.3V to 7V
SW1, SW2
-0.3V to 30V
ILIM1, ILIM2
-0.3V to 30V
SENSE1, SENSE2, FB1, FB2
-0.3V to 7V
PGOOD
-0.3V to 7V
EN
-0.3V to 7V
Junction Temperature
+150°C
ESD Rating (4)
2kV
Ambient Storage Temperature Range
Soldering Dwell Time, Temperature
(1)
-65°C to +150°C
Wave
4 sec, 260°C
Infrared
10 sec, 240°C
Vapor Phase
75 sec, 219°C
Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is specified. For specified performance limits and associated test conditions, see the Electrical Characteristics
table.
If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
PGND1, PGND2 and SGND are all electrically connected together on the PCB.
ESD is applied by the human body model, which is a 100pF capacitor discharged through a 1.5 kΩ resistor into each pin.
(2)
(3)
(4)
OPERATING RATINGS (1)
VIN
4.5V to 28V
VDD, V5
4.5V to 5.5V
Junction Temperature
(1)
-40°C to +125°C
Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is specified. For specified performance limits and associated test conditions, see the Electrical Characteristics
table.
ELECTRICAL CHARACTERISTICS
Specifications with standard typeface are for TJ = 25°C, and those with boldface apply over full Operating Junction
Temperature range. VDD = V5 = 5V, VSGND = VPGND = 0V, VIN = 15V, VEN = 3V, RFADJ = 22.1kΩ unless otherwise stated (1).
Datasheet min/max specification limits are specified by design, test, or statistical analysis.
Symbol
Parameter
Conditions
Min
Typical (2)
Max
Units
591
600
609
mV
Reference
VFB
FB Pin Voltage at
Regualtion (either FB Pin)
VDD = 4.5V to 5.5V,
VIN = 4.5V to 28V
VFB_LINE REG
VFB Line Regulation (ΔVFB)
VDD = 4.5V to 5.5V,
VIN = 4.5V to 28V
0.5
IFB
FB Pin Current (sourcing)
VFB at regulation
20
100
nA
IQ_VIN
VIN Quiescent Current
VFB1 = VFB2 = 0.7V
100
200
µA
ISD_VIN
VIN Shutdown Current
VEN = 0V
0
5
µA
IQ_VDD
VDD Quiescent Current
VFB1 = VFB2 = 0.7V
2.5
4
mA
ISD_VDD
VDD Shutdown Current
VEN = 0V
6
15
µA
IQ_V5
V5 Normal Operating
Current
VFB1 = VFB2 = 0.7V
0.3
0.5
mA
VFB1 = VFB2 = 0.5V
1
1.5
Chip Supply
(1)
(2)
RFADJ is the frequency adjust resistor between FREQ pin and SGND pin.
Typical numbers are at 25°C and represent the most likely norm.
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ELECTRICAL CHARACTERISTICS (continued)
Specifications with standard typeface are for TJ = 25°C, and those with boldface apply over full Operating Junction
Temperature range. VDD = V5 = 5V, VSGND = VPGND = 0V, VIN = 15V, VEN = 3V, RFADJ = 22.1kΩ unless otherwise stated(1).
Datasheet min/max specification limits are specified by design, test, or statistical analysis.
Symbol
Conditions
Min
Typical (2)
Max
Units
ISD_V5
V5 Shutdown Current
VEN = 0V
0
5
µA
IQ_BOOT
BOOT Quiescent Current
VFB1 = VFB2 = 0.7V
2
5
µA
VFB1 = VFB2 = 0.5V
300
500
ISD_BOOT
BOOT Shutdown Current
VEN = 0V
VDD_UVLO
VDD UVLO Threshold
VDD rising up to VUVLO
VDD UVLO Hysteresis
VIN UVLO Threshold
VIN UVLO Hysteresis
VIN falling from VUVLO
IEN
EN Input Current
VEN = 0 to 5V
VEN_HI
Minimum EN Input Logic
High
VEN_LO
Maximum EN Input Logic
Low
RFPWM
FPWM Pull-down
VFPWM_HI
Minimum FPWM Input
Logic High
VFPWM_LO
Maximum FPWM Input
Logic Low
VIN_UVLO
Parameter
1
5
µA
3.9
4.2
4.5
V
VDD = V5 falling from VUVLO
0.5
0.7
0.9
V
VIN rising up to VUVLO
3.9
4.2
4.5
V
0.1
0.3
V
Logic
0
µA
2
VFPWM = 2V
100
V
200
0.8
V
1000
kΩ
2
V
0.8
V
Power Good and OVP
VPGOOD_HI
Power Good Upper
Threshold as a Percentage
of Internal Reference
FB voltage rising above VFB
110
113
116
%
VPGOOD_LOW
Power Good Lower
Threshold as a Percentage
of Internal Reference
FB voltage falling below VFB
84
87
90
%
HYSPGOOD
Power Good Hysteresis
ΔtPG_OK
Power Good Delay
ΔtPG_NOK
ΔtSD
7
%
From both output voltages
“good” to PGOOD assertion.
10
20
30
From the first output voltage
“bad” to PGOOD de-assertion
4
7
10
µs
From Enable low to PGOOD low
0.03
0.1
VPGOOD_SAT
PGOOD Saturation Voltage
PGOOD de-asserted (Power
Not Good) and sinking 1.5mA
0.12
0.4
V
IPGOOD_LEAK
PGOOD Leakage Current
PGOOD = 5V and asserted
0
1
µA
ISS_CHG
Soft-start Charging Current
VSS = 1V
11
14
µA
RSS_DCHG
Soft-shutdown Resistance
(SS pin to SGND, either
channel)
VEN = 0V, VSS = 1V
ISS_DCHG
Soft-start Discharge Current In Current Limit
VSS_RESET
Soft-start pin reset
voltage (3)
VOS
SS to COMP Offset Voltage VSS = 0.5V and 1V, VFB1 = VFB2
= 0V
Soft-start
(3)
6
SS charged to 0.5V, EN low to
high
8
Ω
1800
80
115
160
µA
100
mV
600
mV
If the LM2657 starts up with a pre-charged soft start capacitor, it will first discharge the capacitor to VSS_RESET and then begin the
normal Soft-start process.
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ELECTRICAL CHARACTERISTICS (continued)
Specifications with standard typeface are for TJ = 25°C, and those with boldface apply over full Operating Junction
Temperature range. VDD = V5 = 5V, VSGND = VPGND = 0V, VIN = 15V, VEN = 3V, RFADJ = 22.1kΩ unless otherwise stated(1).
Datasheet min/max specification limits are specified by design, test, or statistical analysis.
Symbol
Parameter
Conditions
Min
Typical (2)
Max
Units
Error Amplifier
GAIN
DC Gain
VSLEW
Voltage Slew Rate
BW
70
dB
COMP rising
4.45
V/µs
COMP falling
2.25
Unity Gain Bandwidth
6.5
MHz
ICOMP_SOURCE COMP Source Current
VFB = lower COMP = 0.5V
2
5
mA
ICOMP_SINK
VFB = higher than internal
reference
COMP = 5V
7
14
mA
VILIM1 = VILIM2 = 0V
46
62
76
µA
-10
0
10
mV
COMP Sink Current
Current Limit and Zero-Cross
IILIM
ILIM Pin Current (sourcing,
either ILIM pin)
VILIM_TH
ILIM Threshold Voltage
VSW_ZERO
Zero-cross Threshold (SW
Pin)
LDRV goes low
PWM Frequency
RFADJ = 22.1kΩ
-2.2
mV
Oscillator
FOSC
VRAMP
PWM Ramp Peak-to-peak
Amplitude
VVALLEY
PWM Ramp Valley
ΔFOSC_VIN
ΔFOSC_VDD
255
300
RFADJ = 12.4kΩ
500
RFADJ = 30.9kΩ
200
VIN = 4.5V
0.48
VIN = 15V
1.6
VIN = 28V
3.0
345
kHz
V
0.8
V
Frequency Change with VIN VIN = 4.5V to 28V
±1
%
Frequency Change with
VDD
VDD = 4.5V to 5.5V
±2
%
øCH
Phase Shift Between
Channels
Phase from HDRV1 to HDRV2
VFREQ_VIN
FREQ Pin Voltage vs. VIN
165
180
195
deg
0.107
V/V
System
ton-min
Minimum ON Time
DMAX
Maximum Duty Cycle
VFPWM = 3V
30
ns
VIN = 4.5V
60
70
%
VIN = 15V
40
50
%
VIN = 28V, VDD= 4.5V
24
30
%
Gate Drivers
HDRV Source Impedance
HDRV Pin Current (sourcing)=
1.2A
7
Ω
RHDRV_SINK
HDRV Sink Impedance
HDRV Pin Current (sinking) =
1A
2
Ω
RLDRV_SOURC
LDRV Source Impedance
LDRV Pin Current (sourcing) =
1.2A
7
Ω
RLDRV_SINK
LDRV Sink Impedance
LDRV Pin Current (sinking) =
2A
1
Ω
tDEAD
Cross-conduction Protection HDRV Falling to LDRV Rising
Delay (deadtime)
LDRV Falling to HDRV Rising
40
ns
RHDRV_SOURC
E
E
70
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BLOCK DIAGRAM
SENSE1
1
VDD
Controller 1
SKIP
CMP
HS_ON
+
PWM
LOGI
C
RAMP1
VDD
SW1
27
+
-
+
-
EN
CURRENT
LIMIT CMP
PWM
CMP
E.A.
ILIM1
28
CL1
V5
LS_ON
+
-
V5
85%Ton
ZERO
CROSS CMP
SENSE1
+
-
COMP1
3
HDRV1
26
IN
+
-
0.35V
Vref1
BOOT1
25
6
PA
2
21
EN
LDRV1
23
IN
PGND1
24
FB1
2
+
-
PGOOD1
SW2
CONTROL
LOGIC
FB2
16
Controller2
13
+
ILIM2
15
Supervisory 2
SS2
0.87 x Vref1
HDRV2
17
COMP2
12
OVP
1.13 x Vref1
BOOT2
18
SENSE2
14
Supervisory 1
11
+
-
VDD
V5
11 PA
SS1
4
LDRV2
20
PGND2
19
VDD
COMP1
+
4.2V
RAMP1
200k
Vref1
VDD
SGND
7
8
BIAS/
REFERENCES
VDD UV
UVLO
VDD
5
CL1
Vref2
115 PA
PGOOD
9
EN
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RAMP/
TIMING
VIN
FPWM
8
CLK1
RAMP2
CLK2
1.8k
10
22
FREQ
6
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SNVS342B – JANUARY 2005 – REVISED MARCH 2013
TYPICAL PERFORMANCE CHARACTERISTICS
The system efficiency plots below were measured using input voltages of 15V, 20V, 24V, 28V. These input voltages
correspond with the uppermost curve to lowermost curve, respectively. The output current (IO) refers to simultaneous loading
of both channels.
System Efficiency for 2.5V/3.3V Outputs
100
95
95
90
90
85
85
EFFICIENCY (%)
EFFICIENCY (%)
System Efficiency for 5V/3.3V Outputs
100
80
75
80
75
70
70
65
65
60
0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3
60
0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3
IO (A)
IO (A)
Figure 2.
Figure 3.
System Efficiency for 1.8V/1.2V Outputs
System Max VOUT For A Given VIN
TJ = 25°C
100
6
95
90
MAX VOUT
EFFICIENCY (%)
5
85
80
75
70
4
3
65
2
60
4
0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3
6
8
10
12
14
VIN (V)
IO (A)
Figure 4.
Figure 5.
Modulator (Plant) Gain
40
5 PH
GAIN (dB)
16
3.3 PH
-8
-32
10 PH
-56
-80
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 6.
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LM2657
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OPERATION DESCRIPTIONS
GENERAL
The LM2657 provides two identical synchronously switched buck regulator channels that operate 180° out of
phase. A voltage-mode control topology was selected to provide fixed-frequency PWM regulation at very low
duty cycles, in preference to current-mode control, because the latter has inherent limitations in being able to
achieve low pulse widths due to blanking time requirements. Because of a minimum pulse width of about 30ns
for the LM2657, very low duty cycles (low output, high input) are possible. The main advantage of current-mode
control is the fact that the slope of its ramp (derived from the switch current), automatically increases with an
increase in input voltage. This leads to improved line rejection and fast response to line variations. In typical
voltage-mode control, the ramp is derived from the clock, not from the switch current. But by using the input
voltage together with the clock signal to generate the ramp as in the LM2657, this advantage of current-mode
control can in fact be completely replicated. The technique is called line feedforward. In addition, the LM2657
features a user-selectable Pulse-skip mode that significantly improves efficiency at light loads by reducing
switching losses and driver consumption, both of which are proportional to switching frequency.
INPUT VOLTAGE FEEDFORWARD
The feedforward circuit of the LM2657 adjusts the slope of the internal PWM ramp in proportion to the regulator
input voltage. See Figure 7 for an illustration of how the duty cycle changes as a result of the change in the slope
of the ramp, even though the error amplifier output has not had time to react to the line disturbance. The almost
instantaneous duty cycle correction provided by the feedforward circuit significantly improves line transient
rejection.
RAMP
Error Amp O/P
VIN = Low
PWM
RAMP
Error Amp O/P
PWM
VIN = High
Figure 7. Voltage Feedforward
FORCED-PWM MODE AND PULSE-SKIP MODE
Forced-PWM mode (FPWM) leads to Continuous Conduction Mode (CCM) even at very light loads. It is one of
two user-selectable modes of operation provided by the LM2657. When FPWM is chosen (FPWM pin high), the
bottom FET will always be turned ON whenever the top FET is OFF. See Figure 8 for a typical FPWM plot.
10
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SNVS342B – JANUARY 2005 – REVISED MARCH 2013
CH1: HDRV, CH2: LDRV, CH3: SW, CH4: IL (0.2A/div)
Output 1V @ 0.04A, VIN = 10V, FPWM, L = 10µH, f = 300kHz
Figure 8. Normal FPWM Mode Operation at Light Loads
In a conventional converter, as the load is decreased to about 10-30% of maximum load current, DCM
(Discontinuous Conduction Mode) occurs. In this condition the inductor current falls to zero during the OFF-time,
and stays there until the start of the next switching cycle. In this mode, if the load is decreased further, the duty
cycle decreases (pinches off), and ultimately may decrease to the point where the required pulse width becomes
less than the minimum ON-time achievable by the converter (controller + FETs). Then a sort of random skipping
behavior occurs as the error amplifier struggles to maintain regulation. There are two ways to prevent random
pulse skipping from occuring.
One way is to keep the lower FET ON until the start of the next cycle (as in the LM2657 operated in FPWM
mode). This allows the inductor current to drop to zero and then actually reverse direction (negative direction
through inductor, passing from drain to source of lower FET, see Channel 4 in Figure 8). Now the current can
continue to flow continuously until the end of the switching cycle. This maintains CCM and the duty cycle does
not start to pinch off as in typical DCM. Nor does it lead to the undesirable random skipping described above.
Note that the pulse width (duty cycle) for CCM is virtually constant for any load and therefore does not usually
run into the minimum ON-time restriction. But it can happen, especially when the application consists of a very
high input voltage, a low output voltage rail, and the switching frequency is set high. Let us check the LM2657 to
rule out this remote possibility. For example, with an input of 24V, an output of 1V, the duty cycle is 1/24 = 4.2%.
This leads to a required ON-time of 0.042* 3.3µs = 0.14 µs at a switching frequency of 300kHz (T=3.3 µs). Since
140ns exceeds the minimum ON-time of 30ns of the LM2657, normal constant frequency CCM mode of
operation is assured in FPWM mode at virtually any load.
The second way to prevent random pulse skipping in discontinuous mode is the Pulse-skip (SKIP) Mode. In SKIP
Mode, a zero-cross detector at the SW pin turns off the bottom FET when the inductor current decays to zero
(actually at VSW_ZERO, see ELECTRICAL CHARACTERISTICS table). This, however, would still amount to
conventional DCM, with its attendant idiosyncrasies at extremely light loads as described earlier. The LM2657
avoids the random skipping behavior and replaces it with a more consistent SKIP mode. In conventional DCM, a
converter would try to reduce its duty cycle from the CCM value as the load decreases, as explained previously.
So it would start with the CCM duty cycle value (at the CCM-DCM boundary), but as the load decreases, the
duty cycle would try to shrink to zero. However, in the LM2657, the DCM duty cycle is not allowed to fall below
85% of the CCM value. So when the theoretically required DCM duty cycle value falls below what the LM2657 is
allowed to deliver (in this mode), pulse-skipping starts. It will be seen that several of these excess pulses may be
delivered until the output capacitors charge up enough to notify the error amplifier and cause its output to
reverse. Thereafter, several pulses could be skipped entirely until the output of the error amplifier again reverses.
The SKIP mode therefore leads to a reduction in the average switching frequency. Switching losses and FET
driver losses, both of which are proportional to frequency, are significantly reduced at very light loads and
efficiency is boosted. SKIP mode also reduces the circulating currents and energy associated with the FPWM
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mode. See Figure 9 for a typical plot of SKIP mode at very light loads. Note the bunching of several fixed-width
pulses followed by skipped pulses. The average frequency can actually fall very low at very light loads. When
this happens the inductor core is seeing only very mild flux excursions, and no significant audible noise is
created. But if EMI is a particularly sensitive issue for the particular application, the user can simply opt for the
slightly less efficient, constant frequency FPWM mode.
CH1: HDRV, CH2: LDRV, CH3: SW, CH4: IL (0.2A/div)
Output 1V @ 0.04A, VIN = 10V, SKIP, L = 10µH, f = 300kHz
Figure 9. Normal SKIP Mode Operation at Light Loads
The SKIP mode is enabled when the FPWM pin is held low (or left floating). At higher loads, and under steady
state conditions (above CCM-DCM boundary), there will be absolutely no difference in the behavior of the
LM2657 or the associated converter waveforms based on the voltage applied on the FPWM pin. The differences
show up only at light loads.
Also, under startup, since the currents are high until the output capacitors have charged up, there will be no
observable difference in the shape of the ramp-up of the output rails in either SKIP mode or FPWM mode. The
design has thus forced the startup waveforms to be identical irrespective of whether the FPWM mode or the
SKIP mode has been selected.
The designer must realize that even at zero load condition, there is circulating current when operating in FPWM
mode. This is illustrated in Figure 10. Since duty cycle is the same as for conventional CCM, from V = L* ΔI / Δt it
can be seen that ΔI (or Ipp in Figure 10) must remain constant for any load, including zero. At zero load, the
average current through the inductor is zero, so the geometric center of the sawtooth waveform (the center being
always equal to load current) is along the x-axis. At critical conduction (boundary between conventional CCM and
what should have been DCM were it not in FPWM mode), the load current is equal to Ipp/2. Note that
excessively low values of inductance will produce much higher current ripple and this will lead to higher
circulating currents and dissipation.
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CRITICAL CONDUCTION
Io = Ipp/2
Ipp/2 > Io > 0
NO LOAD
Io = 0
LDRV
HDRV
Figure 10. Inductor Current in FPWM Mode
START-UP AND STATE-TRANSITIONS AT LIGHT LOADS
During startup the LM2657 is allowed to operate in SKIP mode regardless of the voltage on the FPWM pin.
Starting in SKIP mode prevents the low-side FET from having to sink excessive amounts of negative current
during start-up. This would occur if the output was pre-biased and the converter operated in FPWM mode. The
FB pin would sense that the output was high and force a very low duty cycle, which would keep the low-side FET
on longer than it should be in steady state. Without a load on the output the inductor current will reverse and
become negative. This negative inductor current can be quite large depending on the voltage on the output and
the size of the output capacitor.
A similar situation can occur if the converter transitions from SKIP mode to FPWM mode under a light load
condition (converter is operating below the DCM boundary). This can occur after startup if FPWM mode is
selected for use in a light load condition or if the FPWM pin is toggled high during normal operation at light load.
The problem occurs because in SKIP mode the converter is operating at a set duty cycle and a lower average
frequency. When the converter is forced into FPWM mode, this represents a change to the system. The pulse
widths and frequency need to readjust suddenly and in the process momentary imbalances can be created. Like
the case of a pre-biased load, there can be negative surge current passing from drain to source of the lower
FET. It must be kept in mind that though the LM2657 has current limiting for current passing in the ‘positive’
direction (positive with regards to the inductor, i.e. passing from source to drain of the lower FET), there is no
limit for reverse currents. The amount of reverse current when the FPWM pin is toggled ‘on the fly’ can be very
high. This current is determined by several factors. One key factor is the output capacitance. Large output
capacitances will lead to higher peak reverse currents. The reverse swing will be higher for lighter loads because
of the bigger difference between the duty cycles/average frequency in the two modes. See Figure 11 for a plot of
what happened in going from SKIP to FPWM mode at 0A load (worst case). The peak reverse current was as
high as 3A, lasting about 0.1ms. The inductor could also saturate severely at this point if designed for light loads.
In general, if the designer wants to toggle the FPWM pin while the converter is operating or if FPWM mode is
required for a light load application, the low side FET and inductor should be closely evaluated under this specific
condition.
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CH1: PGOOD, CH2: Vo, CH3: LDRV, CH4: IL (1A/div)
Output 1V @ 0A, VIN = 10V, L = 10µH, f = 300kHz
Figure 11. SKIP to FPWM 'On The Fly'
If the part is operated in FPWM mode with a light load the user will experience lower efficiency and negative
current during the transition (as discussed). The user may also experience a momentary drop on Vout when the
transition is made from SKIP to FPWM mode. This only occurs for no load or very light load conditions (above
the DCM boundary there is no difference between SKIP FPWM modes).
In some cases, such as low Vout (
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