LM2664M6

Product Folder Sample & Buy Support & Community Tools & Software Technical Documents LM2664 SNVS005E – NOVEMBER 1999 – REVISED DECEMBER 2014 LM2664 Switched Capacitor Voltage Converter 1 Features 3 Description • • • • • The LM2664 CMOS charge-pump voltage converter inverts a positive voltage in the range of 1.8 V to 5.5 V to the corresponding negative voltage of −1.8 V to −5.5 V. The device uses two low-cost capacitors to provide up to 40 mA of output current. 1 Inverts Input Supply Voltage 6-Pin SOT-23 Package 12-Ω Typical Output Impedance 91% Typical Conversion Efficiency at 40 mA 1-µA Typical Shutdown Current 2 Applications • • • • • • Cellular Phones Pagers PDAs Operational Amplifier Power Suppliers Interface Power Suppliers Handheld Instruments The LM2664 operates at 160-kHz oscillator frequency to reduce output resistance and voltage ripple. With an operating current of only 220 µA (operating efficiency greater than 91% with most loads) and 1µA typical shutdown current, the LM2664 provides ideal performance for battery-powered systems. Device Information(1) PART NUMBER LM2664 PACKAGE BODY SIZE (NOM) SOT-23 (6) 2.90 mm x 1.60 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. space space space Voltage Inverter 5 V to −10 V Converter 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LM2664 SNVS005E – NOVEMBER 1999 – REVISED DECEMBER 2014 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 4 4 4 4 5 6 Absolute Maximum Ratings ...................................... Handling Ratings....................................................... Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics ............................................. 7 Parameter Measurement Information .................. 7 8 Detailed Description .............................................. 8 7.1 Test Circuit ................................................................ 7 8.1 Overview ................................................................... 8 8.2 Functional Block Diagram ......................................... 8 8.3 Feature Description................................................... 8 8.4 Device Functional Modes.......................................... 8 9 Application and Implementation .......................... 9 9.1 Application Information.............................................. 9 9.2 Typical Application - Voltage Inverter ....................... 9 10 Power Supply Recommendations ..................... 13 11 Layout................................................................... 13 11.1 Layout Guidelines ................................................. 13 11.2 Layout Example .................................................... 13 12 Device and Documentation Support ................. 14 12.1 12.2 12.3 12.4 Device Support...................................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 14 14 14 14 13 Mechanical, Packaging, and Orderable Information ........................................................... 14 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (May 2013) to Revision E • Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ................................................................................................................................................................................... 1 Changes from Revision C (May 2013) to Revision D • 2 Page Page Changed layout of National Data Sheet to TI format ........................................................................................................... 11 Submit Documentation Feedback Copyright © 1999–2014, Texas Instruments Incorporated Product Folder Links: LM2664 LM2664 www.ti.com SNVS005E – NOVEMBER 1999 – REVISED DECEMBER 2014 5 Pin Configuration and Functions SOT-23 (DBV) 6 Pins Top View 1 6 2 5 3 4 Pin Functions PIN TYPE DESCRIPTION NUMBER NAME 1 GND Ground Power supply ground input. 2 OUT Power Negative voltage output. 3 CAP− Power Connect this pin to the negative terminal of the charge-pump capacitor. 4 SD Input Shutdown control pin, tie this pin to V+ in normal operation, and to GND for shutdown. 5 V+ Power Power supply positive voltage input. 6 CAP+ Power Connect this pin to the positive terminal of the charge-pump capacitor. Submit Documentation Feedback Copyright © 1999–2014, Texas Instruments Incorporated Product Folder Links: LM2664 3 LM2664 SNVS005E – NOVEMBER 1999 – REVISED DECEMBER 2014 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) MIN MAX UNIT 5.8 V Supply voltage (V+ to GND, or GND to OUT) (GND − 0.3) SD (V+ + 0.3) V 50 mA 1 sec. V+ and OUT continuous output current Output short-circuit duration to GND (3) Continuous power dissipation (TA = 25°C) (4) 600 mW TJMax (4) 150 °C Lead temp. (soldering, 10 seconds) 300 °C (1) (2) (3) (4) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. OUT may be shorted to GND for one second without damage. However, shorting OUT to V+ may damage the device and should be avoided. Also, for temperatures above 85°C, OUT must not be shorted to GND or V+, or device may be damaged. The maximum allowable power dissipation is calculated by using PDMax = (TJMax − TA)/RθJA, where TJMax is the maximum junction temperature, TA is the ambient temperature, and RθJA is the junction-to-ambient thermal resistance of the specified package. 6.2 Handling Ratings MIN Tstg Storage temperature range V(ESD) Electrostatic discharge (1) –65 Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) MAX UNIT 150 °C 2000 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN Operating junction temperature NOM –40 MAX 85 UNIT °C 6.4 Thermal Information LM2664 THERMAL METRIC (1) DBV UNIT 6 PINS RθJA (1) 4 Junction-to-ambient thermal resistance 210 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 1999–2014, Texas Instruments Incorporated Product Folder Links: LM2664 LM2664 www.ti.com SNVS005E – NOVEMBER 1999 – REVISED DECEMBER 2014 6.5 Electrical Characteristics MIN and MAX limits apply over the full operating temperature range. Unless otherwise specified: TJ = 25°C, V+ = 5 V, C1 = C2 = 3.3 μF. (1) PARAMETER V+ Supply voltage IQ Supply current ISD Shutdown supply current VSD Shutdown pin input voltage TEST CONDITIONS MIN (2) TYP (3) 1.8 No load 220 MAX (2) V 500 µA 1 Normal operation µA 2 (4) 0.8 (5) Shutdown mode UNIT 5.5 40 V IL Output current RSW Sum of the Rds(on)of the four internal MOSFET switches IL = 40 mA ROUT Output resistance (6) IL = 40 mA fOSC Oscillator frequency See (7) 80 160 kHz fSW Switching frequency See (7) 40 80 kHz PEFF Power efficiency RL (1 k) between GND and OUT 90% 94% 99% 99.96% IL = 40 mA to GND VOEFF (1) (2) (3) (4) (5) (6) (7) Voltage conversion efficiency No load mA 4 8 12 25 Ω Ω 91% In the test circuit, capacitors C1 and C2 are 3.3-µF, 0.3-Ω maximum ESR capacitors. Capacitors with higher ESR will increase output resistance, reduce output voltage and efficiency. Min. and Max. limits are ensured by design, test, or statistical analysis. Typical numbers are not ensured but represent the most likely norm. The minimum input high for the shutdown pin equals 40% of V+. The maximum input low for the shutdown pin equals 20% of V+. Specified output resistance includes internal switch resistance and capacitor ESR. See the details in Application and Implementation for simple negative voltage converter. The output switches operate at one half of the oscillator frequency, ƒOSC = 2ƒSW. Submit Documentation Feedback Copyright © 1999–2014, Texas Instruments Incorporated Product Folder Links: LM2664 5 LM2664 SNVS005E – NOVEMBER 1999 – REVISED DECEMBER 2014 www.ti.com 6.6 Typical Characteristics (Circuit of Figure 9 V+ = 5 V unless otherwise specified) 6 Figure 1. Supply Current vs Supply Voltage Figure 2. Supply Current vs Temperature Figure 3. Output Source Resistance vs Supply Voltage Figure 4. Output Source Resistance vs Temperature Figure 5. Output Voltage Drop vs Load Current Figure 6. Oscillator Frequency vs Supply Voltage Submit Documentation Feedback Copyright © 1999–2014, Texas Instruments Incorporated Product Folder Links: LM2664 LM2664 www.ti.com SNVS005E – NOVEMBER 1999 – REVISED DECEMBER 2014 Typical Characteristics (continued) (Circuit of Figure 9 V+ = 5 V unless otherwise specified) Figure 7. Oscillator Frequency vs Temperature Figure 8. Shutdown Supply Current vs Temperature 7 Parameter Measurement Information 7.1 Test Circuit *C1 and C2 are 3.3 µF, SC series OS-CON capacitors. Figure 9. LM2664 Test Circuit Submit Documentation Feedback Copyright © 1999–2014, Texas Instruments Incorporated Product Folder Links: LM2664 7 LM2664 SNVS005E – NOVEMBER 1999 – REVISED DECEMBER 2014 www.ti.com 8 Detailed Description 8.1 Overview The LM2664 CMOS charge-pump voltage converter inverts a positive voltage in the range of 1.8 V to 5.5 V to the corresponding negative voltage of −1.8 V to −5.5 V. The LM2664 uses two low-cost capacitors to provide up to 40 mA of output current. 8.2 Functional Block Diagram LM2664 V+ SD OUT OSCILLATOR CAP+ Switch Array Switch Drivers CAPGND 8.3 Feature Description The LM2664 contains four large CMOS switches which are switched in a sequence to invert the input supply voltage. Energy transfer and storage are provided by external capacitors. Figure 10 illustrates the voltage conversion scheme. When S1 and S3 are closed, C1 charges to the supply voltage V+. During this time interval, switches S2 and S4 are open. In the second time interval, S1 and S3 are open; at the same time, S2 and S4 are closed, C1 is charging C2. After a number of cycles, the voltage across C2 will be pumped to V+. Since the anode of C2 is connected to ground, the output at the cathode of C2 equals −(V+) when there is no load current. The output voltage drop when a load is added is determined by the parasitic resistance (Rds(on) of the MOSFET switches and the ESR of the capacitors) and the charge transfer loss between capacitors. Details will be discussed in the following application information section. Figure 10. Voltage Inverting Principle 8.4 Device Functional Modes 8.4.1 Shutdown Mode A shutdown (SD) pin is available to disable the device and reduce the quiescent current to 1 µA. Applying a voltage less than 20% of V+ to the SD pin will bring the device into shutdown mode. While in normal operating mode, the pin is connected to V+. 8 Submit Documentation Feedback Copyright © 1999–2014, Texas Instruments Incorporated Product Folder Links: LM2664 LM2664 www.ti.com SNVS005E – NOVEMBER 1999 – REVISED DECEMBER 2014 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The LM2664 CMOS charge-pump voltage converter inverts a positive voltage in the range of 1.8 V to 5.5 V to the corresponding negative voltage of −1.8 V to −5.5 V. The LM2664 uses two low cost capacitors to provide up to 40 mA of output current. The LM2664 operates at 160-kHz oscillator frequency to reduce output resistance and voltage ripple. With an operating current of only 220 µA (operating efficiency greater than 91% with most loads) and 1 µA typical shutdown current, the LM2664 provides ideal performance for battery powered systems. 9.2 Typical Application - Voltage Inverter Figure 11. Voltage Inverter 9.2.1 Design Requirements Example requirements for typical voltage inverter applications: DESIGN PARAMETER EXAMPLE VALUE Input voltage range 1.8 V to 5.5 V Output current 0 mA to 40 mA Boost switching frequency 80 kHz 9.2.2 Detailed Design Requirements The main application of LM2664 is to generate a negative supply voltage. The voltage inverter circuit uses only two external capacitors as shown in Voltage Inverter and 5 V to −10 V Converter. The range of the input supply voltage is 1.8 V to 5.5 V. The output characteristics of this circuit can be approximated by an ideal voltage source in series with a resistance. The voltage source equals −(V+). The output resistance ROUT is a function of the ON resistance of the internal MOSFET switches, the oscillator frequency, the capacitance and equivalent series resistance (ESR) of C1 and C2. Since the switching current charging and discharging C1 is approximately twice as the output current, the effect of the ESR of the pumping capacitor C1 will be multiplied by four in the output resistance. The output capacitor C2 is charging and discharging at a current approximately equal to the output current, therefore, its ESR only counts once in the output resistance. A good approximation of ROUT is: where • RSW is the sum of the ON resistance of the internal MOSFET switches shown in Figure 10. (1) High capacitance, low ESR capacitors will reduce the output resistance. Submit Documentation Feedback Copyright © 1999–2014, Texas Instruments Incorporated Product Folder Links: LM2664 9 LM2664 SNVS005E – NOVEMBER 1999 – REVISED DECEMBER 2014 www.ti.com The peak-to-peak output voltage ripple is determined by the oscillator frequency, the capacitance and ESR of the output capacitor C2: (2) Again, using a low ESR capacitor will result in lower ripple. 9.2.2.1 Paralleling Devices Any number of LM2664s can be paralleled to reduce the output resistance. Each device must have its own pumping capacitor C1, while only one output capacitor COUT is needed as shown in Figure 12. The composite output resistance is: (3) Figure 12. Lowering Output Resistance by Paralleling Devices 9.2.2.2 Cascading Devices Cascading the LM2664 devices is an easy way to produce a greater negative voltage (a two-stage cascade circuit is shown in Figure 13). If n is the integer representing the number of devices cascaded, the unloaded output voltage Vout is (-nVin). The effective output resistance is equal to the weighted sum of each individual device: ROUT = nRout_1 + n/2 ROUT_2 + ... + ROUT_n (4) NOTE The number of n is practically limited since the increasing of n significantly reduces the efficiency, and increases the output resistance and output voltage ripple. 10 Submit Documentation Feedback Copyright © 1999–2014, Texas Instruments Incorporated Product Folder Links: LM2664 LM2664 www.ti.com SNVS005E – NOVEMBER 1999 – REVISED DECEMBER 2014 Figure 13. Increasing Output Voltage by Cascading Devices 9.2.2.3 Combined Doubler and Inverter In Figure 14, the LM2664 is used to provide a positive voltage doubler and a negative voltage converter. Note that the total current drawn from the two outputs should not exceed 50 mA. Figure 14. Combined Voltage Doubler and Inverter 9.2.2.4 Regulating VOUT It is possible to regulate the negative output of the LM2664 by use of a low dropout regulator (such as LP2980). The whole converter is depicted in Figure 15. This converter can give a regulated output from −1.8 V to −5.5 V by choosing the proper resistor ratio: VOUT = Vref (1 + R1/R2) where, Vref = 1.23 V (5) (6) Note that the following conditions must be satisfied simultaneously for worst case design: Vin_min > Vout_min + Vdrop_max (LP2980) + Iout_max × Rout_max (LM2664) Vin_max < Vout_max + Vdrop_min (LP2980) + Iout_min × Rout_min (LM2664) (7) (8) (9) (10) space Submit Documentation Feedback Copyright © 1999–2014, Texas Instruments Incorporated Product Folder Links: LM2664 11 LM2664 SNVS005E – NOVEMBER 1999 – REVISED DECEMBER 2014 www.ti.com Figure 15. Combining LM2664 with LP2980 to Make a Negative Adjustable Regulator 9.2.2.5 Output Capacitor Selection As discussed in Detailed Design Requirements, the output resistance and ripple voltage are dependent on the capacitance and ESR values of the external capacitors. The output voltage drop is the load current times the output resistance, and the power efficiency is (11) Where IQ(V+) is the quiescent power loss of the IC device, and IL2ROUT is the conversion loss associated with the switch on-resistance, the two external capacitors and their ESRs. The selection of capacitors is based on the specifications of the dropout voltage (which equals Iout ROUT), the output voltage ripple, and the converter efficiency. Table 1 lists recommendations to maximize efficiency, reduce the output voltage drop and voltage ripple. Table 1. Low ESR Capacitor Manufacturers MANUFACTURER CAPACITOR TYPE Nichicon Corp. PL & PF series, through-hole aluminum electrolytic AVX Corp. TPS series, surface-mount tantalum Sprague 593D, 594D, 595D series, surface-mount tantalum Sanyo OS-CON series, through-hole aluminum electrolytic Murata Ceramic chip capacitors Taiyo Yuden Ceramic chip capacitors Tokin Ceramic chip capacitors 9.2.3 Application Curve Figure 16. Efficiency vs Load Current 12 Submit Documentation Feedback Copyright © 1999–2014, Texas Instruments Incorporated Product Folder Links: LM2664 LM2664 www.ti.com SNVS005E – NOVEMBER 1999 – REVISED DECEMBER 2014 10 Power Supply Recommendations The LM2664 is designed to operate from as an inverter over an input voltage supply range between 1.8 V and 5.5 V when the LV pin is grounded. This input supply must be well regulated and capable to supply the required input current. If the input supply is located far from the LM2664 additional bulk capacitance may be required in addition to the ceramic bypass capacitors. 11 Layout 11.1 Layout Guidelines The high switching frequency and large switching currents of the LM2664 make the choice of layout important. The following steps should be used as a reference to ensure the device is stable and maintains proper LED current regulation across its intended operating voltage and current range • Place CIN on the top layer (same layer as the LM2664) and as close to the device as possible. Connecting the input capacitor through short, wide traces to both the V+ and GND pins reduces the inductive voltage spikes that occur during switching which can corrupt the V+ line • Place COUT on the top layer (same layer as the LM2664) and as close as possible to the OUT and GND pin. The returns for both CIN and COUT should come together at one point, as close to the GND pin as possible. Connecting COUT through short, wide traces reduce the series inductance on the OUT and GND pins that can corrupt the VOUT and GND lines and cause excessive noise in the device and surrounding circuitry. • Place C1 on the top layer (same layer as the LM2664) and as close to the device as possible. Connect the flying capacitor through short, wide traces to both the CAP+ and CAP– pins. 11.2 Layout Example LM2664 GND CAP+ OUT V+ CAP- SD Figure 17. LM2664 Layout Example Submit Documentation Feedback Copyright © 1999–2014, Texas Instruments Incorporated Product Folder Links: LM2664 13 LM2664 SNVS005E – NOVEMBER 1999 – REVISED DECEMBER 2014 www.ti.com 12 Device and Documentation Support 12.1 Device Support 12.1.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 12.2 Trademarks All trademarks are the property of their respective owners. 12.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.4 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 14 Submit Documentation Feedback Copyright © 1999–2014, Texas Instruments Incorporated Product Folder Links: LM2664 PACKAGE OPTION ADDENDUM www.ti.com 30-Sep-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) LM2664M6 NRND SOT-23 DBV 6 1000 Non-RoHS & Green Call TI Level-1-260C-UNLIM -40 to 85 S03A LM2664M6/NOPB ACTIVE SOT-23 DBV 6 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 S03A LM2664M6X/NOPB ACTIVE SOT-23 DBV 6 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 S03A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of