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LM2685 Dual Output Regulated Switched Capacitor Voltage Converter
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FEATURES
DESCRIPTION
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The LM2685 CMOS charge-pump voltage converter
operates as an input voltage doubler, +5V regulator
and inverter for an input voltage in the range of
+2.85V to +6.5V. Five low cost capacitors are used in
this circuit to provide up to 50mA of output current at
+5V (± 5%), and 15mA at −5V. The LM2685 operates
at a 130 kHz switching frequency to reduce output
resistance and voltage ripple. With an operating
current of only 800µA (operating efficiency greater
than 80% with most loads) and 6µA typical shutdown
current, the LM2685 is ideal for use in battery
powered systems. The device is in a small 14-pin
TSSOP package.
1
2
+5V Regulated Output
Inverts V05(+5V) to VNEG(−5V)
Doubles Input Supply Voltage
TSSOP-14 Package
80% Typical Conversion Efficiency at 25mA
Input Voltage Range of 2.85V to 6.5V
Independent Shutdown Control Pins
APPLICATIONS
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Cellular Phones
Pagers
PDAs
Handheld Instrumentation
3.3V to 5V Voltage Conversion Applications
Typical Application and Connection Diagram
14-Pin TSSOP
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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PIN DESCRIPTIONS
Pin No.
Name
Function
1
VIN
2
GND
Power supply ground.
3
VNEG
Negative output voltage created by inverting V05.
4
VNSW
VNEG output connected through a series switch, NSW.
5
CE
6
SDP
Positive side shutdown input. This pin is low for normal operation and high for positive side shutdown and
VPSW load disconnect. (See Shutdown and Load Disconnect section in the Detailed Device Description
division.)
7
SDN
Negative side shutdown input. This pin is low for normal operation and high for negative side shutdown
and VNSW load disconnect. (See Shutdown and Load Disconnect section in the Detailed Device
Description division.)
8
C2−
The negative terminal of inverting charge-pump capacitor, C2.
9
C2+
The positive terminal of inverting charge-pump capacitor, C2.
10
V05
Regulated +5V output.
11
VPSW
V05 output connected through a series switch, PSW.
12
VDBL
Voltage Doubler Output. (2.85V ≤ VIN ≤ 5.4V. See Voltage Doubler section).
13
C1+
The positive terminal of doubling charge-pump capacitor, C1.
14
−
C1
Power supply input voltage.
Chip enable input. This pin is high for normal operation and low for shutdown. (See Shutdown and Load
Disconnect section in the Detailed Device Description division.)
The negative terminal of doubling charge-pump capacitor, C1.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2
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ABSOLUTE MAXIMUM RATINGS (1) (2)
Supply Voltage (VIN to GND or GND to VNEG)
6.8V
(GND − 0.3V) to (VIN + 0.3V)
SDN, SDP, CE
V05 Continuous Output Current
V05 Short-Circuit Duration to GND
80mA
(3)
Continuous Power Dissipation (TA = 25°C)
TJMAX
Indefinite
(4)
600mW
(4)
150°C
θJA (4)
140°C/W
Operating Ambient Temp. Range
−40°C to 85°C
Operating Junction Temp. Range
−40°C to 125°C
Storage Temp. Range
−65°C to 150°C
Lead Temp. (Soldering, 10 sec.)
ESD Rating
(1)
(2)
(3)
(4)
(5)
300°C
(5)
2kV
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications and test
conditions, see the Electrical Characteristics.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office / Distributors for
availability and specifications.
V05 may be shorted to GND without damage. However, shorting VNEG to V05 may damage the device and must be avoided. Also, for
temperature above 85°C, V05 must not be shorted to GND or device may be damaged.
The maximum allowable power dissipation is calculated by using PDMAX = (TJMAX — TA)/θJA, where TJMAX is the maximum junction
temperature, TA is the ambient temperature and θJA is the junction-to-ambient thermal resistance of the specified package.
The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin.
ELECTRICAL CHARACTERISTICS
Limits with standard typeface apply for TJ = 25°C, and limits in boldface type apply over the full temperature range. Unless
otherwise specified VIN = 3.6V, C1 = C2 = C3 = C5 = 2.2µF. C4 = 4.7µF (1)
Symbol
Parameter
V+
Supply Voltage
IQ
Supply Current
Conditions
V
No Load, VIN = 6.5V
300
600
6
30
VIN = 6.5V
Shutdown Pin Input Voltage for CE,
SDP, SDN
Logic Input High @ 6.5V
Output Current at V05
2.85V < VIN < 6.5V
Output Resistance at VNEG
IL = 15mA
2.4
Logic Input Low @ 6.5V
0.8
50
(2)
mA
Ω
180
kHz
Average Power Efficiency at V05
2.85V ≤ VIN ≤ 6.5V
IL = 25mA to GND
Output Regulation
1mA < IL < 50mA, VIN = 6.5V
(3)
4.848
5.05
5.252
1mA < IL < 50mA, VIN = 6.5V
(3)
4.797
5.05
5.303
RSW
V
130
PEFF
GLOAD
µA
40
Switch Frequency
Line Regulation
85
µA
20
FSW
GLINE
82
2.85V < VIN < 3.6V
0.25
3.6V < VIN < 6.5V
0.05
Load Regulation
1mA < IL < 50mA, VIN = 6.5V
0.3
Series Switch Resistance VNEG to
VNSW
VIN > 2.85V
1.5
%
V
%/V
1.0
%
Ω
V05 to VPSW
(2)
(3)
Units
6.5
1600
Shutdown Supply Current
V05
(1)
Max
800
ISD
IL (+5V)
Typ
No Load
VSD
RO (−5V)
Min
2.85
5.0
In the typical operating circuit, capacitors C1 and C2 are 2.2µF, 0.3Ω maximum ESR capacitors. Capacitors with higher ESR will
increase output resistance, reduce output voltage and efficiency.
Specified output resistance includes internal switch resistance and ESR of capacitors. See the Detailed Device Description section.
The 50 mA maximum current assumes no current is drawn from VDBL pin. See Voltage Doubler section in the Detailed Device
Description.
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TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise specified, TA = 25°C, VIN = 3.6V.
4
Supply Current
vs
Input Voltage
Supply Current
vs
Temperature
Figure 1.
Figure 2.
Efficiency
vs
Load Current
Output Voltage (V05)
vs.
Load Current
Figure 3.
Figure 4.
V05 Voltage
vs.
Input Voltage
Output Resistance (VNEG)
vs.
Temperature
Figure 5.
Figure 6.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified, TA = 25°C, VIN = 3.6V.
Output Resistance (VDBL)
vs.
Input Voltage
Output Resistance (VDBL)
vs.
Temperature
Figure 7.
Figure 8.
Switch Frequency
vs.
Temperature
Line Transient Response (with 5mA Load)
A. INPUT VOLTAGE: VIN = 3.2V to 6.0V, 5V/div
B. OUTPUT VOLTAGE: VPSW: 100mV/div
C.OUTPUT VOLTAGE: VNSW: 100mV/div
Figure 10.
Figure 9.
V05 Load Transient Response
VNSW Load Transient Response
A. LOAD CURRENT: ILOAD = 5mA to 39.6mA, 10mA/div
B. OUTPUT VOLTAGE: V05: 10mV/div
Figure 11.
A. LOAD CURRENT: ILOAD = 4.4mA to −9.4mA, 10mA/div
B. OUTPUT VOLTAGE: VNSW: 50mV/div
Figure 12.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified, TA = 25°C, VIN = 3.6V.
VPSW and VNSW Response to CE
(with 5mA Load)
V05 Response to SDP (with 5mA Load)
A. CE INPUT: 5V/div
B. OUTPUT VOLTAGE: VPSW: 5V/div
C. OUTPUT VOLTAGE: VNSW: 5V/div
Figure 13.
A. SDP INPUT: 5V/div
B. OUTPUT VOLTAGE: 5V/div
Figure 14.
VNSW Response to SDN
(with 5mA Load)
VNSW Response to SDP (with 5mA Load)
A. SDP INPUT: 5V/div
B. OUTPUT VOLTAGE (VNSW): 5V/div
Figure 15.
6
A. SDN INPUT: 5V/div
B. OUTPUT VOLTAGE (VNSW): 5V/div
Figure 16.
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DETAILED DEVICE DESCRIPTION
Figure 17. Functional Block Diagram
The LM2685 CMOS charge pump voltage converter operates as an input voltage doubler, +5V regulator and
inverter for an input voltage in the range of +2.85V to +6.5V. It delivers maximum load currents of 50mA and
15mA for the regulated +5V and the inverted output voltages respectively, with an operating current of only
800µA. It also has a typical shutdown current of 6µA. All these performance qualities make the LM2685 an ideal
device for battery powered systems.
The LM2685 has three main functional blocks: a voltage doubler, a low dropout (LDO) regulator, and a voltage
inverter. Figure 17 shows the LM2685 functional block diagram.
VOLTAGE DOUBLER
The voltage doubler stage doubles the input voltage VIN, within the range of +2.85V to +5.4V. For VIN above
5.4V, the doubler shuts off and the input voltage is passed directly to VDBL via an internal power switch.
The doubler contains four large CMOS switches which are switched in a sequence to double the input supply
voltage. Figure 18 illustrates the voltage conversion scheme. When S2 and S4 are closed, C1 charges to the
supply voltage VIN. During this time interval, switches S1 and S3 are open. In the next time interval, S2 and S4
are opened at the same time, S1 and S3 are closed, the sum of the input voltage VIN and the voltage across C1
gives the 2VIn and the voltage across C2 gives the 2VIN at VDBL output. VDBL supplies the LDO regulator. It is
recommended not to load VDBL when V05 has a load of 50mA. For proper operation, the sum of VDBL and V05
loads must not be more than 50mA.
The Schottky diode D1 is only needed for start-up. The internal oscillator circuit uses the VDBL and GND pins.
The voltage across them must be larger than 1.8V to ensure the operation of the oscillator. During start-up, D1 is
used to charge up the voltage at VDBL pin to start the oscillator; it also protects the device from turning on its own
parasitic diode and potentially latching up. The diode should have enough current carrying capability to change
capacitor C3 at start-up, as well as a low forward voltage to prevent the internal parasitic diode from turning on.
A Schottky diode like 1N5817 can be used for most applications. If the input ramp is less than 10V/ms, a smaller
schottky diode like MBR0520LT1 can be used to reduce the circuit size.
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Figure 18. Voltage Doubler Principle
+5 LDO REGULATOR
VDBL is the input to an LDO regulator that regulates it to a +5 output voltage at V05. VPSW is tied to V05 through a
series switch PSW. The LDO output capacitor (4.7µF Tantalum) may be tied to either V05 or VPSW.
INVERTER
From the V05 output, a −5V output is created at VNEG by means of an inverting charge pump. This negative
output is unregulated, meaning that it's output will droop as the load current at VNEG increases. The inverter
contains four large CMOS switches which are in a sequence to invert the input supply voltage. Figure 19
illustrates the voltage conversion scheme. When S1 and S3 are closed, C1 charges to the supply voltage V05.
During this time interval, switches S2 and S4 are open. In the second time interval, S1 and S3 are open;at the
same time, S2 and S4 are closed, C1 is charging C2. After a number of cycles, the voltage cross C2 will be
pumped to V05. Since the anode of C2 is connected to ground, the output at the cathode of C2 equals −(V05)
when there is no load current. The output voltage drop when a load is added is determined by the parasitic
resistance (Rds(on) of the MOSFET switches and the ESR of the capacitors) and the charge transfer loss
between capacitors.
Figure 19. Voltage Inverter Principle
8
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SHUTDOWN AND LOAD DISCONNECT
In addition to the nominal charge pump and regulator functions, the LM2685 features shutdown and load
disconnect circuitry. CE (chip enable) and SDP (shutdown positive) perform the same task with opposite input
polarities. When CE is low or SDP is high, all circuit blocks are disabled and V05 falls to ground potential. This is
the same result as when the die temperature exceeds 150°C (typical), and the device's internal thermal
shutdown is triggered.
Forcing SDN (shutdown negative) high disables only the inverting charge pump. The doubling charge pump and
the LDO regulator continue to operate, so the V05 and the VPSW remain at 5V.
The LM2685 incorporates two low impedance switches tied to the V05 and VNEG outputs, because some special
applications require load disconnect and this is achievable via the switches. Switch PSW connects V05 to VPSW,
and switch NSW connects VNEG to VNSW. In normal operation, these switches are closed, allowing 5V loads to be
tied to either V05 or VPSW and −5V loads to be tied to either VNEG or VNSW. Driving SDN high opens switch NSW
only, while forcing CE low or SDP high, opens both the PSW and NSW.
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APPLICATION INFORMATION
CAPACITOR SELECTION
The output resistance and ripple voltage are dependent on the capacitance and ESR values of the external
capacitors.
VOLTAGE DOUBLER EXTERNAL CAPACITORS
The selection of capacitors are based on the specifications of the dropout voltage (which equals IOUT ROUT), the
output voltage ripple, and the converter efficiency.
where
•
RSW is the sum of the ON resistance of the internal MOSFET switches as shown in Figure 18
The peak-to-peak output voltage ripple is determined by the oscillator frequency, the capacitance and ESR of the
capacitor C3.
High capacitance (2.2µF to higher), low ESR capacitors can reduce the output resistance and the voltage ripple.
where
•
•
IQ(V+) is the quiescent power loss of the IC device
I2LR is the conversion loss associated with the switch on-resistance, the two external capacitors and their
ESRs
Low ESR capacitors (table to be referenced) are recommended to maximize efficiency, reduce the output voltage
drop and voltage ripple.
+5 LDO REGULATOR EXTERNAL CAPACITORS
The voltage doubler output capacitor, C3, serves as the input capacitor of the +5 LDO regulator. The output
capacitor C4, must meet the requirement for minimum amount of capacitance and appropriate ESR (Equivalent
Serving Resistance) for proper operation. The ESR value must remain within the regions of stability as shown in
Figure 20, Figure 21 and Figure 22 to ensure output's stability. A minimum capacitance of 1µF is required at the
output. This can be increased without limit, but a 4.7µF tantalum capacitor is recommended for loads ranging
upto the maximum specification. With lighter loads of less or equal to 10mA, ceramic capacitor of at least 1µF
and ESR in the milliohms can be used. This has to be connected to VPSW pin instead of the V05 pin.
Any output capacitor used should have a good tolerance over temperature for capacitance and ESR values. The
larger the capacitor, with ESR within the stable region, the better the stability and noise performance.
10
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Figure 20. ESR Curve for COUT = 2.2µF
Figure 21. ESR Curve for COUT = 4.7µF
Figure 22. ESR Curve for COUT =10µF
INVERTER EXTERNAL CAPACITORS
As discussed in the +5 LDO Regulator External Capacitors section, the output resistance and ripple voltage are
dependent on the capacitance and ESR values of the external capacitors. A minimum of 1µF capacitor with good
tolerance over temperature for capacitance and ESR values. The capacitance value can be increased without
limit while still maintain high low ESR value. 2.2µF capacitors are recommended for the two external capacitors,
C2 and C5 of the inverter.
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REVISION HISTORY
Changes from Revision B (April 2013) to Revision C
•
12
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 11
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