LM2698
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SNVS153E – MAY 2001 – REVISED APRIL 2013
LM2698 SIMPLE SWITCHER® 1.35A Boost Regulator
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FEATURES
DESCRIPTION
•
•
•
The LM2698 is a general purpose PWM boost
converter. The 1.9A, 18V, 0.2ohm internal switch
enables the LM2698 to provide efficient power
conversion to outputs ranging from 2.2V to 17V. It
can operate with input voltages as low as 2.2V and
as high as 12V. Current-mode architecture provides
superior line and load regulation and simple
frequency compensation over the device's 2.2V to
12V input voltage range. The LM2698 sets the
standard in power density and is capable of supplying
12V at 400mA from a 5V input. The LM2698 can also
be used in flyback or SEPIC topologies.
1
23
•
•
1.9A, 0.2Ω, Internal Switch (typical)
Operating Voltage as Low as 2.2V
600kHz/1.25MHz Adjustable Frequency
Operation
Switchers Made Simple® Software
8-Lead VSSOP package
APPLICATIONS
•
•
•
•
•
•
•
•
3.3V to 5V, 5V to 12V Conversion
Distributed Power
Set-Top Boxes
DSL Modems
Diagnostic Medical Instrumentation
Boost Converters
Flyback Converters
SEPIC Converters
The LM2698 SIMPLE SWITCHER® features a pin
selectable switching frequency of either 600kHz or
1.25MHz. This promotes flexibility in component
selection and filtering techniques. A shutdown pin is
available to suspend the device and decrease the
quiescent current to 5µA. An external compensation
pin gives the user flexibility in setting frequency
compensation, which makes possible the use of
small, low ESR ceramic capacitors at the output.
Switchers Made Simple® software is available to
ensure a quick, easy and assured design. The
LM2698 is available in a low profile 8-lead VSSOP
(DGK) package.
Typical Application Circuit
L
10PH
D
4.5V-5.5V
5
SW
6
VIN
FSLCT
7
LM2698
3
Battery or Power
Source
FB
SHDN
VC
2
RFB1
30.1k
12V
400mA
GND
1
4
CIN
22PF, 10V
RC
24.9k
RFB2
3.48k
COUT
10PF
CC
4.7 nF
CIN: LMK316F226Z (TAIYO YUDEN)
COUT: EMK325B5106K (TAIYO YUDEN)
L: DO3316-103 (COILCRAFT)
D: 0MQ040N (MOTOROLA)
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SIMPLE SWITCHER is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2001–2013, Texas Instruments Incorporated
LM2698
SNVS153E – MAY 2001 – REVISED APRIL 2013
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Connection Diagram
Top View
1
8
VC
NC
FB
FSLCT
2
7
3
SHDN
4
GND
VIN
6
VSW
5
Figure 1. 8-Lead Plastic VSSOP
Pin Functions
Pin Description
2
Pin
Name
1
VC
Compensation network connection. Connected to the output of the voltage error amplifier.
Function
2
FB
Output voltage feedback input.
3
SHDN
4
GND
Analog and power ground.
5
VSW
Power switch input. Switch connected between SW pin and GND pin.
6
VIN
Analog power input.
7
FSLCT
8
NC
Shutdown control input, active low.
Switching frequency select input. VIN= 1.25MHz. Ground = 600kHz.
Connect to ground.
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Block Diagram
FSLCT
¦
85% Duty
Cycle Limit
Oscillator
Load Current
Measurement
SW
+
PWM
COMP
-
FB
-
RESET
DRIVE
Driver
LOGIC
ERROR
AMP
BG
SET
RESET
OVP
+
UVP
THERMAL
-
SD
OVP
COMP
BG
+
BG
+
Internal
Supply
Thermal
Shutdown
Bandgap Voltage
Reference
VC
Shutdown
Comparator
SHDN
UVP
COMP
VIN
GND
ORDERING INFORMATION (1)
ORDER NUMBER
PACKAGE TYPE
LM2698MM-ADJ
LM2698MM-ADJ/NOPB
LM2698MMX-ADJ
1000
VSSOP
LM2698MMX-ADJ/NOPB
(1)
PACKAGE QUANTITY
1000
3500
3500
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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LM2698
SNVS153E – MAY 2001 – REVISED APRIL 2013
Absolute Maximum Ratings
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(1)
−0.3V ≤ VIN ≤ 12V
VIN
−0.3V ≤ VSW ≤ 18V
SW Voltage
FB Voltage
−0.3V ≤ VFB ≤ 7V
VC Voltage
0.965 < VC < 1.565
SHDN Voltage (2)
−0.3V ≤ VSHDN ≤ 7V
FSLCT (2)
−0.3V ≤ VFSLCT ≤ 12V
Maximum Junction Temperature
Power Dissipation
150°C
(3)
Internally Limited
Lead Temperature
300°C
Vapor Phase (60 sec.)
215°C
Infrared (15 sec.)
220°C
ESD Susceptibility (4)
Human Body Model (5)
2kV
Machine Model
(1)
(2)
(3)
(4)
(5)
200V
Absolute maximum ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions for which the
device is intended to be functional, but device parameter specifications may not be specified. For assured specifications and test
conditions, see the Electrical Characteristics.
Shutdown and voltage frequency select should not exceed VIN.
The maximum allowable power dissipation is a function of the maximum junction temperature, TJ(MAX), the junction-to-ambient thermal
resistance, θJA, and the ambient temperature, TA. See the Electrical Characteristics table for the thermal resistance of various layouts.
The maximum allowable power dissipation at any ambient temperature is calculated using: PD (MAX) = (TJ(MAX) − TA)/θJA. Exceeding
the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown.
The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin. The machine model is a 200pF
capacitor discharged directly into each pin.
ESD susceptibility using the human body model is 500V for VC.
Operating Conditions
Operating Junction Temperature Range (1)
−40°C to +125°C
Storage Temperature
−65°C to +150°C
Supply Voltage
2.2V to 12V
0 ≤ VSW ≤ 17.5V
SW Voltage
(1)
4
All limits are specified at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits
are 100% tested or specified through statistical analysis. All limits at temperature extremes are specified via correlation using standard
Statistical Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level (AOQL).
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Electrical Characteristics
Specifications in standard type face are for TJ = 25°C and those with boldface type apply over the full Operating
Temperature Range ( TJ = −40°C to +125°C)Unless otherwise specified. VIN =2.2V and IL = 0A, unless otherwise specified.
Symbol
IQ
Parameter
Quiescent Current
Min
Typ
Max
(1)
Units
1.3
2.0
mA
5
10
µA
1.2285
1.26
1.2915
V
1.35
1.9
2.4
A
0.013
0.1
%/V
0.5
20
nA
12
V
135
290
µmho
Conditions
(1)
FB = 0V (Not Switching)
VSHDN = 0V
(2)
VFB
Feedback Voltage
ICL
Switch Current Limit
VIN = 2.7V
%VFB/ΔVIN
Feedback Voltage Line
Regulation
2.2V ≤ VIN ≤ 12.0V
IB
FB Pin Bias Current
VIN
Input Voltage Range
gm
Error Amp Transconductance
AV
Error Amp Voltage Gain
DMAX
Maximum Duty Cycle
FSLCT = Ground
DMIN
Minimum Duty Cycle
FSLCT = Ground
FSLCT = VIN
30
(3)
(4)
fS
Switching Frequency
2.2
ΔI = 5µA
FSLCT = Ground
40
78
120
V/V
85
%
15
%
480
600
720
kHz
1
1.25
1.5
MHz
VSHDN = VIN
0.01
0.1
µA
-1
FSLCT = VIN
ISHDN
Shutdown Pin Current
VSHDN = 0V
−0.5
IL
Switch Leakage Current
VSW = 18V
0.01
3
µA
RDS(ON)
Switch RDS(ON)
VIN = 2.7V, ISW = 1A
0.2
0.4
Ω
THSHDN
SHDN Threshold Voltage
Output High
0.6
0.9
V
0.3
0.6
UVP
On Threshold
1.95
2.05
2.2
V
Off Threshold
1.85
1.95
2.1
V
Output Low
θJA
Thermal Resistance
Junction to Ambient
235
Junction to Ambient
225
Junction to Ambient
220
Junction to Ambient
200
Junction to Ambient
195
(5)
(6)
(7)
(8)
(9)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
V
°C/W
All limits are specified at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits
are 100% tested or specified through statistical analysis. All limits at temperature extremes are specified via correlation using standard
Statistical Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level (AOQL).
Typical numbers are at 25°C and represent the most likely norm.
This is the switch current limit at 0% duty cycle. The switch current limit will change as a function of duty cycle. See Typical performance
Characteristics section for ICL vs. VIN
Bias current flows into FB pin.
Junction to ambient thermal resistance (no external heat sink) for the MSO8 package with minimal trace widths (0.010 inches) from the
pins to the circuit. See "Scenario 'A'" in the Power Dissipation section.
Junction to ambient thermal resistance for the MSO8 package with minimal trace widths (0.010 inches) from the pins to the circuit and
approximately 0.0191 sq. in. of copper heat sinking. See "Scenario 'B'" in the Power Dissipation section.
Junction to ambient thermal resistance for the MSO8 package with minimal trace widths (0.010 inches) from the pins to the circuit and
approximately 0.0465 sq. in. of copper heat sinking. See "Scenario 'C'" in the Power Dissipation section.
Junction to ambient thermal resistance for the MSO8 package with minimal trace widths (0.010 inches) from the pins to the circuit and
approximately 0.2523 sq. in. of copper heat sinking. See "Scenario 'D'" in the Power Dissipation section.
Junction to ambient thermal resistance for the MSO8 package with minimal trace widths (0.010 inches) from the pins to the circuit and
approximately 0.0098 sq. in. of copper heat sinking on the top layer and 0.0760 sq. in. of copper heat sinking on the bottom layer, with
three 0.020 in. vias connecting the planes. See "Scenario 'E'" in the Power Dissipation section.
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Typical Performance Characteristics
Efficiency vs Load Current
(VOUT = 8V, fS = 600kHz)
Efficiency vs Load Current
(VOUT = 8V, fS = 1.25MHz)
Figure 2.
Figure 3.
Iq vs VIN (600 kHz, non-switching)
2.0
Iq vs VIN (600 kHz, switching)
4.0
R
3.5
1.8
TA = 85R C
1.7
3.0
TA = 85R C
1.6
Iq (mA)
Iq (mA)
TA = 25R C
TA = 25 C
1.9
TA = -40R C
1.5
TA = -40R C
2.5
1.4
2.0
1.3
1.2
1.5
1.1
1.0
1.0
2
4
8
6
10
12
2
14
4
6
VIN (V)
Figure 4.
10
12
14
Figure 5.
Iq vs. VIN (1.25MHz, non-switching)
2.0
8
VIN (V)
Iq vs VIN (1.25MHz, switching)
7
TA = 25R C
TA = 85R C
1.9
6
1.8
1.7
TA = -40R C
1.6
Iq (mA)
Iq (mA)
TA = 25R C
TA = 85R C
1.5
5
TA = -40R C
4
1.4
1.3
3
1.2
1.1
2
1.0
2
4
6
8
10
12
14
4
6
8
10
12
14
VIN (V)
VIN (V)
Figure 6.
6
2
Figure 7.
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Typical Performance Characteristics (continued)
Iq(SHDN) vs VIN
12
RDS(ON) vs VIN
250
TA = 85R C
11
200
10
RDS(ON) (m:)
Iq (PA)
TA = 85R C
TA = 25R C
9
R
TA = -40 C
8
7
150
TA = 25R C
100
TA = -40R C
6
50
5
4
0
2
4
6
8
VIN (V)
12
10
0
14
4
2
Figure 8.
10
12
14
Figure 9.
Switching Frequency vs VIN (600kHz)
Switching Frequency vs VIN (1.25MHz)
650
1.4
645
TA = -40R C
640
635
630
625
620
TA = 25R C
615
1.36
1.34
TA = 25R C
1.32
TA = 85R C
1.3
1.28
TA = 85R C
610
TA = -40R C
1.38
Switching Frequency (MHz)
Switching Frequency (kHz)
8
6
VIN (V)
1.26
605
2
4
6
8
VIN (V)
12
10
14
2
6
4
8
10
12
14
VIN (V)
Figure 10.
Figure 11.
ICL vs. Ambient Temperature
VIN = 3.3V, VOUT = 8V
ICL vs. VIN
2.0
1.560
1.540
1.9
1.520
ICL (A)
ICL (A)
VOUT = 8V
1.8
1.500
1.480
1.460
1.7
1.6
1.440
VOUT = 12V
1.5
1.420
1.400
-50 -30 -10
1.4
10
30
50
70
90 110
R
Temp ( C)
Figure 12.
2
3
4
5
6
7
VIN (V)
8
9
10
11
Figure 13.
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Operation
Continuous Conduction Mode
L
D
COUT
VIN
RLOAD
PWM
L
X
+
+
L
COUT
VIN
RLOAD
VI
N
COUT
R LOAD
V OU
V OUT
T
-
Cycle
1
(a)
-
Cycle
2
(b)
Figure 14. Simplified Boost Converter Diagram
(a) First Cycle of Operation (b) Second Cycle Of Operation
The LM2698 is a current-mode, PWM boost regulator. A boost regulator steps the input voltage up to a higher
output voltage. In continuous conduction mode (when the inductor current never reaches zero at steady state),
the boost regulator operates in two cycles.
In the first cycle of operation, shown in Figure 14 (a), the transistor is closed and the diode is reverse biased.
Energy is collected in the inductor and the load current is supplied by COUT.
The second cycle is shown in Figure 14 (b). During this cycle, the transistor is open and the diode is forward
biased. The energy stored in the inductor is transferred to the load and output capacitor.
The ratio of these two cycles determines the output voltage. The output voltage is defined as:
VOUT =
VIN
1-D
(1)
where D is the duty cycle of the switch.
8
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Inductor
IL (A)
VIN - VOUT
VIN
L
L
'iL
IL(AVG)
t (s)
D*Ts
Ts
(a)
ID (A)
VIN - VOUT
L
ID(AVG) =
IOUT(AVG)
t (s)
D*Ts
Ts
(b)
Figure 15. (a) Inductor Current (b) Diode Current
The inductor is one of the two energy storage elements in a boost converter. Figure 15 shows how the inductor
current varies during a switching cycle. The current through an inductor is quantified as:
VL(t) = L
diL(t)
dt
(2)
If VL(t) is constant, diL / dt must be constant, thus the current in the inductor changes at a constant rate. This is
the case in DC/DC converters since the voltages at the input and output can be approximated as a constant. The
current through the inductor of the LM2698 boost converter is shown in Figure 15(a). The important quantities in
determining a proper inductance value are IL(AVG) (the average inductor current) and ΔiL (the inductor current
ripple). If ΔiL is larger than IL(AVG), the inductor current will drop to zero for a portion of the cycle and the converter
will operate in discontinuous conduction mode. If ΔiL is smaller than IL(AVG), the inductor current will stay above
zero and the converter will operate in continuous conduction mode (CCM). All the analysis in this datasheet
assumes operation in continuous conduction mode. To operate in CCM:
IL(AVG) > ΔiL
(3)
VIN x D
IOUT(AVG)
> 2xf xL
1-D
S
(4)
VIN x D x (1-D)
L>
2 x fS x IOUT(AVG)
(5)
Choose the minimum IOUT to determine the minimum L for CCM operation. A common choice is to set ΔiL to 30%
of IL(AVG).
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The inductance value will also affect the stability of the converter. Because the LM2698 utilizes current mode
control, the inductor value must be carefully chosen. See the Compensation section for recommended
inductance values.
Choosing an appropriate core size for the inductor involves calculating the average and peak currents expected
through the inductor. In a boost converter,
IL(AVG) =
IOUT(AVG)
1-D
(6)
and
IL(Peak) = IL(AVG) + ΔiL,
where
'iL =
DVIN
2Lfs
(7)
A core size with ratings higher than these values should be chosen. If the core is not properly rated, saturation
will dramatically reduce overall efficiency.
Current Limit
The current limit in the LM2698 is referenced to the peak switch current. The peak currents in the switch of a
boost converter will always be higher than the average current supplied to the load. To determine the maximum
average output current that the LM2698 can supply, use:
IOUT(MAX) = (ICL − ΔiL)*(1−D) = (ICL − ΔiL)*VIN/VOUT
(8)
Where ICL is the switch current limit (see Electrical Charateristics table and Typical Performance Curves). Hence,
as VIN increases, the maximum current that can be supplied to the load increases, as shown in Figure 16.
1.6
1.4
VOUT = 12V
1.2
IOUT (A)
1.0
0.8
0.6
0.4
0.2
0
2
4
6
8
10
12
VIN (V)
Figure 16. Maximum Output Current vs Input Voltage
Diode
The diode in a boost converter such as the LM2698 acts as a switch to the output. During the first cycle, when
the transistor is closed, the diode is reverse biased and current is blocked; the load current is supplied by the
output capacitor. In the second cycle, the transistor is open and the diode is forward biased; the load current is
supplied by the inductor.
Observation of the boost converter circuit shows that the average current through the diode is the average load
current, and the peak current through the diode is the peak current through the inductor. The diode should be
rated to handle more than its peak current. To improve efficiency, a low forward drop Schottky diode is
recommended.
10
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Input Capacitor
Due to the presence of an inductor at the input of a boost converter, the input current waveform is continuous
and triangular. The inductor ensures that the input capacitor sees fairly low ripple currents. However, as the
inductor gets smaller, the input ripple increases. The rms current in the input capacitor is given by:
1
2 3
VinVo - Vin2
)
ICIN(RMS) = 'iL/ 3 =
fs L Vo
)
(9)
The input capacitor should be capable of handling the rms current. Although the input capacitor is not so critical
in boost applications, a 10 µF or higher value, good quality capacitor prevents any impedance interactions with
the input supply.
A 0.1µF or 1µF ceramic bypass capacitor is also recommended on the VIN pin (pin 6) of the IC. This capacitor
must be connected very close to pin 6 to effectively filter high frequency noise. When operating at 1.25 MHz
switching frequency, a minimum bypass capacitance of 0.22 µF is recommended.
Output Capacitor
The output capacitor in a boost converter provides all the output current when the switch is closed and the
inductor is charging. As a result, it sees very large ripple currents. The output capacitor should be capable of
handling the maximum RMS current. The RMS current in the output capacitor is:
>
(1-D) IOUT2
'iL
D
+
3
(1-D)2
2
>
ICOUT(RMS) =
(10)
where,
'iL =
DVIN
2Lfs
(11)
and
D = (VOUT - VIN)/VOUT
(12)
The ESR and ESL of the output capacitor directly control the output ripple. Use capacitors with low ESR and ESL
at the output for high efficiency and low ripple voltage. Surface mount tantalums, surface mount polymer
electrolytic, and polymer tantalum, Sanyo OS-CON, or multi-layer ceramic capacitors are recommended at the
output.
Compensation
This section presents a step-by-step procedure to design the compensation network at pin 1 (Vc) of the LM2698.
These design methods will produce a conservative and stable control loop.
There is a minimum inductance requirement in any current mode converter. This is a function of VOUT, duty cycle,
and switching frequency, among other things. Figure 18 plots the recommended inductance range vs. duty cycle
for VOUT = 12V. The two lines represent the upper and lower bounds of the recommended inductance range. The
simplified compensation procedure that follows assumes that the inductance never drops below the Q = 5 line.
Figure 18 plots the equation:
L=
VOUT x RDSON 1
+ D - 0.5
SQ
Se
(13)
where,
RDSON = 0.15,
Se = 0.072*fS,
and Q = 0.5 and 5
Use Q = 5 to calculate the minimum inductance recommended for a stable design. Choosing an inductor
between the Q = 0.5 and Q = 5 values provides a good tradeoff between size and stability. Note that as VIN
drops less than 5V, RDS(ON) increases, as shown in the Typical Performance Characteristics section (RDS(ON)
vs.VIN curve). The worst case RDS(ON) should be used when choosing the inductance. To view plots for different
Vout, multiply the Y axis by a factor of VOUT/12, or plot Equation 13 for the respective output voltage.
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xxxx
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50
45
25
30
20
Inductance (PH)
35
Q = 0.5
25
20
15
10
xxx
xxx
xxx
VOUT = 12V
VOUT = 12V
40
Inductance (PH)
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15
Q = 0.5
10
5
Q=5
5
1
0
0.1 0.2
0.3
0.4 0.5
0.6
Q=5
1
0.7 0.8
0
0.1 0.2
Duty Cycle (1-VIN/VOUT)
0.3
0.4 0.5
0.6
0.7
0.8
Duty Cycle (1-VIN/VOUT)
(a)
(b)
Figure 17. Minimum Inductance Requirements for
(a) fS = 600kHz
Figure 18. Minimum Inductance Requirements for
(b) fS = 1.25MHz
The goal of the compensation network is to provide the best static and dynamic performance while insuring
stability over line and load variations. The relationship of stability and performance can be best analyzed by
plotting the magnitude and phase of the open loop frequency response in the form of a bode plot. A typical bode
plot of the LM2698 open loop frequency response is shown in Figure 19.
Bandwidth = 6.9kHz, Phase Margin = 78.4
,R
DSON
= 0.15 : , L = 10uH
X
0
O
X
X
f
Z2
O
nf
P
X
f
RH
20
Powerstage
Compensator
T
f
P1
40
f
P2
Magnitude(dB)
60
-20
-40
10e1
10e2
10e3
10e4
Frequency (Hz)
10e5
10e6
Phase ( q)
0
-50
X
X
O
-100
O
-150
-200
10e1
10e2
10e3
10e4
Frequency (Hz)
10e5
10e6
Figure 19. Bode plot of the LM2698 Frequency Response using the Typical Application Circuit
Poles are marked with an 'X', and zeros are marked with a 'O'. The bolded 'O' labeled 'fRHP' is a right-half plane
zero. Right half plane zeros act like normal zeros to the magnitude (+20dB/decade slope influence) and like
poles to the phase (−90° shift). Three curves are shown. The powerstage curve is the frequency response of the
powerstage, which includes the switch, diode, inductor, output capacitor, and load. The compensator curve is the
frequency response of the compensator, which is the error amp combined with the compensation network. T is
the product of the powerstage and the compensator and is the complete open loop frequency response. The
power stage response is fixed by line and load constraints, while the compensator is set by the external
compensation network at pin 1. The compensator can be designed in a few simple steps as follows.
12
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Quick Compensator Design
Calculate:
ZPI(MAX) |
1
(rad/s)
COUTRLOAD(MIN)
(14)
where,
RLOAD(MIN) =
VOUT
IOUT(MAX)
(15)
2
RLOAD(MIN) VIN(MIN)
VOUT
(rad/s)
ZRHP(MIN) =
L
(
(
(16)
1
Set ZP2 = 2S(40)(rad/s) |
(rad/s)
CC1ROUT
(17)
where ROUT = 875kΩ
Choose CC1 = 4.7nF
Zz2 = 10 x ZP1(max)
ADCZP2
1
(rad/s),
ZRHP(MIN) = CC1RC
(18)
Choose
RC =
ZRHP(MIN)
:
10 x ADCCC1ZP1(max)ZP2
(19)
Where,
ADC =
118 * RLOAD(MIN)
RDSON(MIN)
x
(1 - DMAX)
3
(1 - DMAX) RLOAD(MIN)
0.144 * fSL
1+
2LfS
VINRDSON(MIN)
+ 1 + DMAX
(20)
If the output capacitor is of high ESR (0.1Ω or higher), it may be necessary to use CC2. A rule of thumb is that if
1/(2πCOUTESR) (Hz) is lower than fS/2 (Hz), CC2 should be used. Choose CC2 such that:
(RC + ROUT)(COUTESR) / (RCROUT) (F)
(21)
where ROUT = output impedance of the error amp (875 kΩ).
Improving Transient Response Time
The above compensator design provides a loop gain with high phase margin for a large stability margin. The
transient response time of this loop is limited by the lower mid-frequency gain necessary to achieve a high phase
margin. If it is desired to increase the transient response time, CC1 may be decreased. Decreasing CC1 by 2x, 4x,
and 6x will yield increasingly shorter transient response times, however the loop phase margin will become
progressively lower as CC1 is decreased. When optimizing the loop gain for transient response time, it is
recommended to keep the phase margin above 40°.
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Additional Comments on the Open Loop Frequency Response
The procedure used here to pick the compensation network will provide a good starting point. In most cases,
these values will be sufficient for a stable design. It is always recommended to check the design in a real test
setup. This is easy to do with the aid of a dynamic load. Set the high and low load values to your system
requirements and switch between the two at about 1kHz. View the output voltage with an oscilloscope using AC
coupling, and zoom in enough to see the waveform react to the load change. Use the following table to
determine if your design is stable. Remember to use worst case conditions (VIN(MIN), ROUT(MIN), ROUT(MAX)).
Response
Conclusion
What to Change
Underdamped, weak attenuation
Nearing instability
Make CC1 larger
Underdamped, strong attenuation
Stable
Nothing
Critically damped
Stable
Nothing
Overdamped
Stable
Nothing
APPLICATION INFORMATION
L1
10PH
2.5V to 3.3V
D
5
SW
6
FSLCT
VIN
7
LM2698
Battery or Power
Source
3
CIN
22PF
FB
SHDN
VC
RFB1
1M
2
10V
GND
1
4
COUT
10PF
RC
20k
RFB2
140k
CC
4.7nF
Figure 20. 3.3V to 10V Boost Converter
1.25MHz Boost Converter
Figure 20 shows the LM2698 boosting 3.3V to 10V at 300mA. As discussed in the Compensation section, the
RDS(ON) of the internal FET in the LM2698 raises as the input voltage drops below 5V (see Typical Performance
Characteristics). The minimum input voltage for this application is 2.5V, at which point the RDS(ON) is
approximately 200mΩ. Substituting these values in for Equation 13, it is found that either a 10 µH (1.25MHz
operation) or a 22 µH (600kHz operation) is necessary for a stable design. The circuit is operated at 1.25MHz to
allow for a smaller inductance. From the Compensator Design equations, RC is calculated to be 18.6kΩ, and a
20kΩ resistor is used.
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L1
10PH
D0-1608
CSEPIC
1PF
D
(Schottky)
2.2V - 12V
L2
10PH
D0-1608
5
SW
6
7
VIN
FSLCT
LM2698
3
Battery or Power
Source
SHDN
FB
VC
2
RFB1
20k
3.3V
GND
1
4
COUT
10PF
Ceramic
CIN
22PF
Ceramic
RC
10k
RFB2
12.1k
CC
680pF
Figure 21. 3.3V SEPIC Converter
3.3V SEPIC
The LM2698 can be used to implement a SEPIC technology. The advantages of the SEPIC topology are that it
can step up or step down an input voltage, and it has low input current ripple.
The conversion ratio for the SEPIC is :
VOUT D
= D'
VIN
(22)
where
D' = 1−D
(23)
Solving for D yields:
1
D=
1 + VIN / VOUT
(24)
To avoid subharmonic oscillations, it is recommended that inductors L1 and L2 be the same inductance. Currents
conducted by the inductors are:
I1 = IOUT(VOUT/VIN)
Δi1 = VIND/(2*L1*fs)
I2 = IOUT
Δi1 = VIND/(2*L2*fs)
The switch sees a maximum current of I1 + I2 + Δi1 + Δi2. If L1 = L2 = L, the maximum switch current is given by:
IOUT(1 + VOUT/VIN) + VIND/(L*fs)
(25)
The maximum load current is limited by this relationship to the switch current.
The polarity of CSEPIC will change between each cycle, so a ceramic capacitor should be used here. A high
quality, low ESR capacitor will directly improve efficiency because all the load current passes through CSEPIC.
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CIN should be chosen using the same relationship as in the boost converter (see the CIN section). CIN must be
able to provide the necessary RMS current.
L1
6.8PH
12V
CSEPIC
1PF
5
SW
500
6
VIN
FSLCT
6.8V
3
Battery or
Power
Source
SHDN
FB
VC
0.1PF
2
RFB1
30.1k
GND
4
1
CIN
47PF
L2
6.8PH
7
LM2698
D
(Schottky)
COUT
10PF
RC
10k
RFB2
10k
CC
680pF
-5V,
400mA
Figure 22. Level-Shifted SEPIC Converter
Level-Shifted SEPIC
The circuit shown in Figure 22 is similar to the SEPIC shown in Figure 21, except that it is level shifted to provide
a negative output voltage. This is achieved by connecting the ground of the LM2698 to the output. The circuit
analysis for the level-shifted SEPIC is the same as the SEPIC. The voltage at the input of the LM2698 will need
to be clamped if the absolute value of the output voltage plus the input voltage exceeds 12V, the absolute
maximum rating for the VIN pin. The simplest way to do this is with a zener diode, as shown in Figure 22.
Likewise, if the FSLCT pin is pulled high to operate at 1.25 MHz, its voltage must not exceed 12V. To prevent
any high frequency noise from entering the LM2698's internal circuitry, a high frequency bypass capacitor must
be placed as close to pin 6 as possible. A good choice for this capacitor is a 0.1µF ceramic capacitor.
Layout Consideration
The GND pin and the NC pin is recommended to be connected by a short trace as shown below.
Power Dissipation
The output power of the LM2698 is limited by its maximum power dissipation. The maximum power dissipation is
determined by the formula
PD = (Tjmax - TA)/θJA
(26)
where Tjmax is the maximum specified junction temperature (125°C), TA is the ambient temperature, and θJA is
the thermal resistance of the package. θJA is dependant on the layout of the board as shown below.
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Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
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REVISION HISTORY
Changes from Revision D (April 2013) to Revision E
•
18
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 17
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PACKAGE OPTION ADDENDUM
www.ti.com
23-Sep-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
LM2698MM-ADJ
ACTIVE
VSSOP
DGK
8
LM2698MM-ADJ/NOPB
ACTIVE
VSSOP
DGK
8
LM2698MMX-ADJ
ACTIVE
VSSOP
DGK
8
LM2698MMX-ADJ/NOPB
ACTIVE
VSSOP
DGK
8
1000
3500
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
TBD
Call TI
Call TI
-40 to 125
S22B
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
S22B
TBD
Call TI
Call TI
-40 to 125
S22B
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
S22B
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
23-Sep-2013
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
LM2698MM-ADJ/NOPB
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
VSSOP
DGK
8
1000
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LM2698MMX-ADJ/NOPB VSSOP
DGK
8
3500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM2698MM-ADJ/NOPB
VSSOP
DGK
8
1000
210.0
185.0
35.0
LM2698MMX-ADJ/NOPB
VSSOP
DGK
8
3500
367.0
367.0
35.0
Pack Materials-Page 2
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