LM2716MTX/NOPB

LM2716 www.ti.com SNVS240G – NOVEMBER 2003 – REVISED MARCH 2013 LM2716 Dual (Step-Up and Step-Down) PWM DC/DC Converter Check for Samples: LM2716 FEATURES APPLICATIONS • • • • • 1 2 • • • • • • • • Fixed 3.3V Buck Converter with a 1.8A, 0.16Ω, Internal Switch Adjustable Boost Converter with a 3.6A, 0.12Ω, Internal Switch Adjustable Boost Output Voltage up to 20V Operating Input Voltage Range of 4V to 20V Input Undervoltage Protection 300kHz to 600kHz Pin Adjustable Operating Frequency Over Temperature Protection Small 24-Lead TSSOP Package Patented Current Limit Circuitry TFT-LCD Displays Handheld Devices Portable Applications Cellular Phones/Digital Cameras DESCRIPTION The LM2716 is composed of two PWM DC/DC converters. A buck (step-down) converter is used to generate a fixed output voltage of 3.3V. A boost (step-up) converter is used to generate an adjustable output voltage. Both converters feature low RDSON (0.16Ω and 0.12Ω) internal switches for maximum efficiency. Operating frequency can be adjusted anywhere between 300kHz and 600kHz allowing the use of small external components. External soft-start pins for each enables the user to tailor the soft-start times to a specific application. Each converter may also be shut down independently with its own shutdown pin. The LM2716 is available in a low profile 24-lead TSSOP package. Typical Application Circuit CBOOT L1 CSS1 CB1 SW1 SS1 SHDN1 VBUCK_OUT COUT1 D1 Step-Down FB1 CC1 VIN VIN RC1 CIN VC1 RF L2 D2 FSLCT VBOOST_OUT SW2 CSS2 SS2 COUT2 RFB1 Step-Up CBG FB2 VBG CC2 RC2 SHDN2 AGND VC2 RFB2 PGND LM2716 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003–2013, Texas Instruments Incorporated LM2716 SNVS240G – NOVEMBER 2003 – REVISED MARCH 2013 www.ti.com Connection Diagram Figure 1. 24-Lead TSSOP Top View Pin Descriptions 2 Pin Name 1 PGND Function 2 FB1 Buck output voltage feedback input. 3 VC1 Buck compensation network connection. Connected to the output of the voltage error amplifier. 4 VBG Bandgap connection. 5 SS2 Boost soft start pin. 6 VC2 Boost compensation network connection. Connected to the output of the voltage error amplifier. 7 FB2 Boost output voltage feedback input. 8 AGND Analog ground. AGND and PGND pins must be connected together directly at the part. Power ground. AGND and PGND pins must be connected together directly at the part. 9 AGND Analog ground. AGND and PGND pins must be connected together directly at the part. 10 PGND Power ground. AGND and PGND pins must be connected together directly at the part. 11 PGND Power ground. AGND and PGND pins must be connected together directly at the part. 12 PGND Power ground. AGND and PGND pins must be connected together directly at the part. 13 SW2 Boost power switch input. Switch connected between SW2 pins and PGND pins. SW2 pins should be connected directly together at the device. 14 SW2 Boost power switch input. Switch connected between SW2 pins and PGND pins. SW2 pins should be connected directly together at the device. 15 SW2 Boost power switch input. Switch connected between SW2 pins and PGND pins. SW2 pins should be connected directly together at the device. 16 VIN Analog power input. VIN pins must be connected together directly at the DUT. 17 VIN Analog power input. VIN pins must be connected together directly at the DUT. 18 SHDN2 Shutdown pin for Boost converter. Active low. 19 FSLCT Switching frequency select input. Use a resistor to set the frequency anywhere between 300kHz and 600kHz. 20 SS1 21 SHDN1 Buck soft start pin. 22 CB1 Buck converter bootstrap capacitor connection. 23 VIN Analog power input. VIN pins must be connected together directly at the DUT. 24 SW1 Shutdown pin for Buck converter. Active low. Buck power switch input. Switch connected between VIN pins and SW1 pin. Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LM2716 LM2716 www.ti.com SNVS240G – NOVEMBER 2003 – REVISED MARCH 2013 Block Diagram FSLCT CB1 VIN + 6 SS1 95% Duty Cycle Limit + OSC PWM Comp Soft Start DC LIMIT SET + FB1 Buck Load Current Measurement RESET - BUCK DRIVE Buck Driver SW1 OVP Error Amp TSH + SD OVP Comp + - PGND Thermal Shutdown BG SHDN1 Bandgap Buck Converter VBG VC1 Boost Converter FSLCT + 6 OSC SET + PWM Comp FB2 95% Duty Cycle Limit + DC LIMIT RESET - VC2 SW2 Boost Load Current Measurement BOOST DRIVE Boost Driver OVP Error Amp SD PGND OVP Comp + - Soft Start BG Bandgap VBG TSH + Thermal Shutdown VIN SHDN2 SS2 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LM2716 3 LM2716 SNVS240G – NOVEMBER 2003 – REVISED MARCH 2013 www.ti.com Absolute Maximum Ratings (1) (2) VIN −0.3V to 22V SW1 Voltage −0.3V to 22V SW2 Voltage −0.3V to 22V FB1 Voltage −0.3V to 7V FB2 Voltage −0.3V to 7V VC1 Voltage 1.75V ≤ VC1 ≤ 2.25V VC2 Voltage 0.965V ≤ VC2 ≤ 1.565V SHDN1 Voltage −0.3V to 7.5V SHDN2 Voltage −0.3V to 7.5V SS1 Voltage −0.3V to 2.1V SS2 Voltage −0.3V to 0.6V FSLCT Voltage AGND to 5V CB1 Voltage VIN + 7V (VIN = VSW) Maximum Junction Temperature Power Dissipation 150°C (3) Internally Limited Lead Temperature 300°C Vapor Phase (60 sec.) 215°C Infrared (15 sec.) ESD Susceptibility (4) 220°C Human Body Model Machine Model (1) (2) (3) (4) 2kV 200V Absolute maximum ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions for which the device is intended to be functional, but device parameter specifications may not be ensured. For ensured specifications and test conditions, see the Electrical Characteristics. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. The maximum allowable power dissipation is a function of the maximum junction temperature, TJ(MAX), the junction-to-ambient thermal resistance, θJA, and the ambient temperature, TA. See the Electrical Characteristics table for the thermal resistance. The maximum allowable power dissipation at any ambient temperature is calculated using: PD (MAX) = (TJ(MAX) − TA)/θJA. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin. The machine model is a 200pF capacitor discharged directly into each pin. Operating Conditions Operating Junction Temperature Range (1) −40°C to +125°C Storage Temperature −65°C to +150°C Supply Voltage 4V to 20V SW1 Voltage 20V SW2 Voltage 20V (1) 4 All limits specified at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are 100% tested or specified through statistical analysis. All limits at temperature extremes are specified via correlation using standard Statistical Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level (AOQL). Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LM2716 LM2716 www.ti.com SNVS240G – NOVEMBER 2003 – REVISED MARCH 2013 Electrical Characteristics Specifications in standard type face are for TJ = 25°C and those with boldface type apply over the full Operating Temperature Range (TJ = −40°C to +125°C) Unless otherwise specified. VIN = 5V and IL = 0A, unless otherwise specified. Symbol IQ Total Quiescent Current (both switchers) VBG Bandgap Voltage ICL1 (3) Buck Switch Current Limit ICL2 (3) Typ (2) Max (1) Units 2.8 3.5 mA Switching, switch open 4 4.5 mA V SHDN = 0V 9 15 µA 1.26 1.285 V Parameter Conditions Min (1) Not Switching 1.235 95% Duty Cycle (4) 1.8 (4) 3.6 A Boost Switch Current Limit 95% Duty Cycle IFB1 Buck FB Pin Bias Current (5) VFB1 = 3.3V 65 75 µA IFB2 Boost FB Pin Bias Current (5) VFB2 = 1.265V 27 55 nA VIN Input Voltage Range 20 V gm1 Buck Error Amp Transconductance ΔI = 20µA gm2 Boost Error Amp Transconductance ΔI = 5µA AV1 AV2 DMAX Maximum Duty Cycle FSW Switching Frequency 4 A 1200 µmho 175 µmho Buck Error Amp Voltage Gain 100 V/V Boost Error Amp Voltage Gain 135 V/V 90 95 98 % RF = 47.5kΩ 250 300 350 kHz RF = 22.6kΩ 500 600 700 kHz I SHDN1 Buck Shutdown Pin Current 0V < V SHDN1 < 7.5V −5 5 µA I SHDN2 Boost Shutdown Pin Current 0V < V SHDN2 < 7.5V −5 5 µA IL1 Buck Switch Leakage Current VDS = 20V 0.2 5 µA IL2 Boost Switch Leakage Current VDS = 20V 0.2 3 µA RDSON1 Buck Switch RDSON 160 RDSON2 Boost Switch RDSON 120 Th SHDN1 Buck SHDN Threshold Output High Output Low Th SHDN2 Boost SHDN Threshold 1.37 0.8 Output High Output Low mΩ mΩ 2 V 1.35 1.37 0.8 1.35 2 V ISS1 Buck Soft Start Pin Current 6 9.5 12 µA ISS2 Boost Soft Start Pin Current 15 19 22 µA UVP On Threshold 3.35 3.8 4.0 Off Threshold 3.10 3.6 3.9 θJA (1) (2) (3) (4) (5) (6) Thermal Resistance (6) TSSOP, package only 115 V °C/W All limits specified at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are 100% tested or specified through statistical analysis. All limits at temperature extremes are specified via correlation using standard Statistical Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level (AOQL). Typical numbers are at 25°C and represent the most likely norm. Duty cycle affects current limit due to ramp generator. Current limit at 95% duty cycle. Bias current flows into FB pin. Refer to TI's packaging website www.ti.com/packaging for more detailed thermal information and mounting techniques for the TSSOP package. Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LM2716 5 LM2716 SNVS240G – NOVEMBER 2003 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics Switching Frequency vs. Input Voltage (FSW = 300kHz) Switching Frequency vs. RF Resistor 350 340 330 320 FSW (kHz) 310 300 290 280 270 260 250 4 6 8 10 12 14 16 18 20 VIN (V) Figure 2. Figure 3. Switching Frequency vs. Input Voltage (FSW = 600kHz) Buck Efficiency vs. Load Current (FSW = 300kHz) 100 VIN = 5V 90 VIN = 12V 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0 0.5 1 1.5 2 LOAD CURRENT (A) Figure 4. Figure 5. Buck Efficiency vs. Load Current (FSW = 600kHz) Boost Efficiency vs. Load Current (FSW = 300kHz) 100 100 VIN = 5V 90 90 VIN = 12V 70 60 50 40 30 50 40 30 10 10 0 0 1 1.5 2 LOAD CURRENT (A) VOUT = 15V 0 200 400 600 800 LOAD CURRENT (mA) Figure 6. 6 60 20 0.5 VIN = 12V 70 20 0 VIN = 5V 80 EFFICIENCY (%) EFFICIENCY (%) 80 Figure 7. Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LM2716 LM2716 www.ti.com SNVS240G – NOVEMBER 2003 – REVISED MARCH 2013 Typical Performance Characteristics (continued) Boost Efficiency vs. Load Current (FSW = 600kHz) Boost Switch RDSON vs. Input Voltage 100 90 VIN = 5V EFFICIENCY (%) 80 VIN = 12V 70 60 50 40 30 20 10 VOUT = 15V 0 0 200 400 600 800 LOAD CURRENT (mA) Figure 8. Figure 9. Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LM2716 7 LM2716 SNVS240G – NOVEMBER 2003 – REVISED MARCH 2013 www.ti.com Buck Operation PROTECTION (BOTH REGULATORS) The LM2716 has dedicated protection circuitry running during normal operation to protect the IC. The Thermal Shutdown circuitry turns off the power devices when the die temperature reaches excessive levels. The UVP comparator protects the power devices during supply power startup and shutdown to prevent operation at voltages less than the minimum input voltage. The OVP comparator is used to prevent the output voltage from rising at no loads allowing full PWM operation over all load conditions. The LM2716 also features a shutdown mode for each converter decreasing the supply current to 9µA (both in shutdown mode). CONTINUOUS CONDUCTION MODE The LM2716 contains a current-mode, PWM buck regulator. A buck regulator steps the input voltage down to a lower output voltage. In continuous conduction mode (when the inductor current never reaches zero at steady state), the buck regulator operates in two cycles. The power switch is connected between VIN and SW1. In the first cycle of operation the transistor is closed and the diode is reverse biased. Energy is collected in the inductor and the load current is supplied by COUT and the rising current through the inductor. During the second cycle the transistor is open and the diode is forward biased due to the fact that the inductor current cannot instantaneously change direction. The energy stored in the inductor is transferred to the load and output capacitor. The ratio of these two cycles determines the output voltage. The output voltage is defined approximately as: D= VOUT , D' = (1-D) VIN where D is the duty cycle of the switch, D and D′ will be required for design calculations. DESIGN PROCEDURE This section presents guidelines for selecting external components. INPUT CAPACITOR A low ESR aluminum, tantalum, or ceramic capacitor is needed betwen the input pin and power ground. This capacitor prevents large voltage transients from appearing at the input. The capacitor is selected based on the RMS current and voltage requirements. The RMS current is given by: The RMS current reaches its maximum (IOUT/2) when VIN equals 2VOUT. This value should be increased by 50% to account for the ripple current increase due to the boost regulator. For an aluminum or ceramic capacitor, the voltage rating should be at least 25% higher than the maximum input voltage. If a tantalum capacitor is used, the voltage rating required is about twice the maximum input voltage. The tantalum capacitor should be surge current tested by the manufacturer to prevent being shorted by the inrush current. The minimum capacitor value should be 47µF for lower output load current applications and less dynamic (quickly changing) load conditions. For higher output current applications or dynamic load conditions a 68µF to 100µF low ESR capacitor is recommended. It is also recommended to put a small ceramic capacitor (0.1 µF) between the input pin and ground pin to reduce high frequency spikes. INDUCTOR SELECTION The most critical parameters for the inductor are the inductance, peak current and the DC resistance. The inductance is related to the peak-to-peak inductor ripple current, the input and the output voltages: 8 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LM2716 LM2716 www.ti.com SNVS240G – NOVEMBER 2003 – REVISED MARCH 2013 A higher value of ripple current reduces inductance, but increases the conductance loss, core loss, current stress for the inductor and switch devices. It also requires a bigger output capacitor for the same output voltage ripple requirement. A reasonable value is setting the ripple current to be 30% of the DC output current. Since the ripple current increases with the input voltage, the maximum input voltage is always used to determine the inductance. The DC resistance of the inductor is a key parameter for the efficiency. Lower DC resistance is available with a bigger winding area. A good tradeoff between the efficiency and the core size is letting the inductor copper loss equal 2% of the output power. OUTPUT CAPACITOR The selection of COUT is driven by the maximum allowable output voltage ripple. The output ripple in the constant frequency, PWM mode is approximated by: The ESR term usually plays the dominant role in determining the voltage ripple. A low ESR aluminum electrolytic or tantalum capacitor (such as Nichicon PL series, Sanyo OS-CON, Sprague 593D, 594D, AVX TPS, and CDE polymer aluminum) is recommended. An electrolytic capacitor is not recommended for temperatures below −25°C since its ESR rises dramatically at cold temperature. A tantalum capacitor has a much better ESR specification at cold temperature and is preferred for low temperature applications. BOOT CAPACITOR A 3.3 nF or larger ceramic capacitor is recommended for the bootstrap capacitor. SOFT-START CAPACITOR (BOTH REGULATORS) The SS pins are used to tailor the soft-start for a specific application. A current source charges the external softstart capacitor, CSS. The soft-start time can be estimated as: TSS = CSS*0.6V/ISS Soft-start times may be implemented using the SS pin and a capacitor CSS. When programming the softstart time, simply use the equation given in the SOFT-START CAPACITOR section above. This equation uses the typical room temperature value of the soft start current to set the soft start time. COMPENSATION COMPONENTS In the control to output transfer function, the first pole FP1 can be estimated as 1/(2πROUTCOUT); The ESR zero FZ1 of the output capacitor is 1/(2πESRCOUT); Also, there is a high frequency pole FP2 in the range of 45kHz to 150kHz: FP2 = FSW/(πn(1−D)) where D = VOUT/VIN, n = 1+0.348L/(VIN−VOUT) (L is in µHs and VIN and VOUT in volts). The total loop gain G is approximately 500/IOUT where IOUT is in amperes. A Gm amplifier is used inside the LM2716. The output resistor Ro of the Gm amplifier is about 85kΩ. CC1 and RC1 together with Ro give a lag compensation to roll off the gain: FPC1 = 1/(2πCC1(Ro+RC1)), FZC1 = 1/2πCC1RC1. In some applications, the ESR zero FZ1 can not be cancelled by FP2. Then, CC3 is needed to introduce FPC2 to cancel the ESR zero, FP2 = 1/(2πCC3Ro‖RC1). The rule of thumb is to have more than 45° phase margin at the crossover frequency (G=1). SCHOTTKY DIODE The breakdown voltage rating of D1 is preferred to be 25% higher than the maximum input voltage. Since D1 is only on for a short period of time, the average current rating for D1 only requires being higher than 30% of the maximum output current. Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LM2716 9 LM2716 SNVS240G – NOVEMBER 2003 – REVISED MARCH 2013 www.ti.com Boost Operation Figure 10. Simplified Boost Converter Diagram (a) First Cycle of Operation (b) Second Cycle Of Operation CONTINUOUS CONDUCTION MODE The LM2716 contains a current-mode, PWM boost regulator. A boost regulator steps the input voltage up to a higher output voltage. In continuous conduction mode (when the inductor current never reaches zero at steady state), the boost regulator operates in two cycles. In the first cycle of operation, shown in Figure 10 (a), the transistor is closed and the diode is reverse biased. Energy is collected in the inductor and the load current is supplied by COUT. The second cycle is shown in Figure 10 (b). During this cycle, the transistor is open and the diode is forward biased. The energy stored in the inductor is transferred to the load and output capacitor. The ratio of these two cycles determines the output voltage. The output voltage is defined approximately as: VOUT = VIN 1-D , D' = (1-D) = VIN VOUT where D is the duty cycle of the switch, D and D′ will be required for design calculations. SETTING THE OUTPUT VOLTAGE The output voltage is set using the feedback pin and a resistor divider connected to the output as shown in Figure 12. The feedback pin voltage is 1.26V, so the ratio of the feedback resistors sets the output voltage according to the following equation: VOUT - 1.26 : RFB1 = RFB2 x 1.26 10 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LM2716 LM2716 www.ti.com SNVS240G – NOVEMBER 2003 – REVISED MARCH 2013 INTRODUCTION TO COMPENSATION Figure 11. (a) Inductor current. (b) Diode current. The LM2716 has a current mode PWM boost converter. The signal flow of this control scheme has two feedback loops, one that senses switch current and one that senses output voltage. To keep a current programmed control converter stable above duty cycles of 50%, the inductor must meet certain criteria. The inductor, along with input and output voltage, will determine the slope of the current through the inductor (see Figure 11 (a)). If the slope of the inductor current is too great, the circuit will be unstable above duty cycles of 50%. If the duty cycle is approaching near 85% up to the maximum of 95%, it may be necessary to increase the inductance by as much as 2X. See INDUCTOR AND DIODE SELECTION for more detailed inductor sizing. The LM2716 provides a compensation pin (VC2) to customize the voltage loop feedback. It is recommended that a series combination of RC2 and CC2 be used for the compensation network, as shown in Figure 12. For any given application, there exists a unique combination of RC2 and CC2 that will optimize the performance of the LM2716 circuit in terms of its transient response. The series combination of RC2 and CC2 introduces a pole-zero pair according to the following equations: fZC = 1 Hz 2SRC2CC2 fPC = 1 Hz 2S(RC2 + RO)CC2 where RO is the output impedance of the error amplifier, approximately 850kΩ. Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LM2716 11 LM2716 SNVS240G – NOVEMBER 2003 – REVISED MARCH 2013 www.ti.com For most applications, performance can be optimized by choosing values within the range 5kΩ ≤ RC2 ≤ 20kΩ (RC2 can be up to 200kΩ if CC4 is used, see HIGH OUTPUT CAPACITOR ESR COMPENSATION) and 680pF ≤ CC2 ≤ 4.7nF. Refer to the Application Information section for recommended values for specific circuits and conditions. Refer to the COMPENSATION section for other design requirement. COMPENSATION This section will present a general design procedure to help insure a stable and operational circuit. The designs in this datasheet are optimized for particular requirements. If different conversions are required, some of the components may need to be changed to ensure stability. Below is a set of general guidelines in designing a stable circuit for continuous conduction operation (loads greater than approximately 100mA), in most all cases this will provide for stability during discontinuous operation as well. The power components and their effects will be determined first, then the compensation components will be chosen to produce stability. INDUCTOR AND DIODE SELECTION Although the inductor sizes mentioned earlier are fine for most applications, a more exact value can be calculated. To ensure stability at duty cycles above 50%, the inductor must have some minimum value determined by the minimum input voltage and the maximum output voltage. This equation is: 2 L> VINRDSON 0.144 FSW ( D'D ) -1 (in H) ( D'D )+1 where FSW is the switching frequency, D is the duty cycle, and RDSON is the ON resistance of the internal switch taken from the graph "Boost Switch RDSON vs. Input Voltage" in the Typical Performance Characteristics section. This equation is only good for duty cycles greater than 50% (D>0.5), for duty cycles less than 50% the recommended values may be used. The corresponding inductor current ripple as shown in Figure 11 (a) is given by: 'iL = VIND 2LFSW (in Amps) The inductor ripple current is important for a few reasons. One reason is because the peak switch current will be the average inductor current (input current or ILOAD/D') plus ΔiL. As a side note, discontinuous operation occurs when the inductor current falls to zero during a switching cycle, or ΔiL is greater than the average inductor current. Therefore, continuous conduction mode occurs when ΔiL is less than the average inductor current. Care must be taken to make sure that the switch will not reach its current limit during normal operation. The inductor must also be sized accordingly. It should have a saturation current rating higher than the peak inductor current expected. The output voltage ripple is also affected by the total ripple current. The output diode for a boost regulator must be chosen correctly depending on the output voltage and the output current. The typical current waveform for the diode in continuous conduction mode is shown in Figure 11 (b). The diode must be rated for a reverse voltage equal to or greater than the output voltage used. The average current rating must be greater than the maximum load current expected, and the peak current rating must be greater than the peak inductor current. During short circuit testing, or if short circuit conditions are possible in the application, the diode current rating must exceed the switch current limit. Using Schottky diodes with lower forward voltage drop will decrease power dissipation and increase efficiency. DC GAIN AND OPEN-LOOP GAIN Since the control stage of the converter forms a complete feedback loop with the power components, it forms a closed-loop system that must be stabilized to avoid positive feedback and instability. A value for open-loop DC gain will be required, from which you can calculate, or place, poles and zeros to determine the crossover frequency and the phase margin. A high phase margin (greater than 45°) is desired for the best stability and transient response. For the purpose of stabilizing the LM2716, choosing a crossover point well below where the right half plane zero is located will ensure sufficient phase margin. A discussion of the right half plane zero and checking the crossover using the DC gain will follow. 12 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LM2716 LM2716 www.ti.com SNVS240G – NOVEMBER 2003 – REVISED MARCH 2013 OUTPUT CAPACITOR SELECTION The choice of output capacitors is somewhat arbitrary and depends on the design requirements for output voltage ripple. It is recommended that low ESR (Equivalent Series Resistance, denoted RESR) capacitors be used such as ceramic, polymer electrolytic, or low ESR tantalum. Higher ESR capacitors may be used but will require more compensation which will be explained later on in the section. The ESR is also important because it determines the peak to peak output voltage ripple according to the approximate equation: ΔVOUT ≊ 2ΔiLRESR (in Volts) A minimum value of 10µF is recommended and may be increased to a larger value. After choosing the output capacitor you can determine a pole-zero pair introduced into the control loop by the following equations: fP1 = 1 (in Hz) 2S(RESR + RL)COUT fZ1 = 1 (in Hz) 2SRESRCOUT Where RL is the minimum load resistance corresponding to the maximum load current. The zero created by the ESR of the output capacitor is generally very high frequency if the ESR is small. If low ESR capacitors are used it can be neglected. If higher ESR capacitors are used see the HIGH OUTPUT CAPACITOR ESR COMPENSATION section. RIGHT HALF PLANE ZERO A current mode control boost regulator has an inherent right half plane zero (RHP zero). This zero has the effect of a zero in the gain plot, causing an imposed +20dB/decade on the rolloff, but has the effect of a pole in the phase, subtracting another 90° in the phase plot. This can cause undesirable effects if the control loop is influenced by this zero. To ensure the RHP zero does not cause instability issues, the control loop should be designed to have a bandwidth of less than ½ the frequency of the RHP zero. This zero occurs at a frequency of: RHPzero = VOUT(D')2 (in Hz) 2S,LOADL where ILOAD is the maximum load current and D' corresponds to the minimum input voltage. SELECTING THE COMPENSATION COMPONENTS The first step in selecting the compensation components RC2 and CC2 is to set a dominant low frequency pole in the control loop. Simply choose values for RC2 and CC2 within the ranges given in the INTRODUCTION TO COMPENSATION section to set this pole in the area of 10Hz to 500Hz. The frequency of the pole created is determined by the equation: fPC = 1 (in Hz) 2S(RC2 + RO)CC2 where RO is the output impedance of the error amplifier, approximately 850kΩ. Since RC2 is generally much less than RO, it does not have much effect on the above equation and can be neglected until a value is chosen to set the zero fZC. fZC is created to cancel out the pole created by the output capacitor, fP1. The output capacitor pole will shift with different load currents as shown by the equation, so setting the zero is not exact. Determine the range of fP1 over the expected loads and then set the zero fZC to a point approximately in the middle. The frequency of this zero is determined by: fZC = 1 (in Hz) 2SCC2RC2 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LM2716 13 LM2716 SNVS240G – NOVEMBER 2003 – REVISED MARCH 2013 www.ti.com Now RC2 can be chosen with the selected value for CC2. Check to make sure that the pole fPC is still in the 10Hz to 500Hz range, change each value slightly if needed to ensure both component values are in the recommended range. After checking the design at the end of this section, these values can be changed a little more to optimize performance if desired. This is best done in the lab on a bench, checking the load step response with different values until the ringing and overshoot on the output voltage at the edge of the load steps is minimal. This should produce a stable, high performance circuit. For improved transient response, higher values of RC2 should be chosen. This will improve the overall bandwidth which makes the regulator respond more quickly to transients. If more detail is required, or the most optimal performance is desired, refer to a more in depth discussion of compensating current mode DC/DC switching regulators. HIGH OUTPUT CAPACITOR ESR COMPENSATION When using an output capacitor with a high ESR value, or just to improve the overall phase margin of the control loop, another pole may be introduced to cancel the zero created by the ESR. This is accomplished by adding another capacitor, CC4, directly from the compensation pin VC2 to ground, in parallel with the series combination of RC2 and CC2. The pole should be placed at the same frequency as fZ1, the ESR zero. The equation for this pole follows: fPC4 = 1 (in Hz) 2SCC4(RC2||RO) To ensure this equation is valid, and that CC4 can be used without negatively impacting the effects of RC2 and CC2, fPC4 must be greater than 10fZC. CHECKING THE DESIGN The final step is to check the design. This is to ensure a bandwidth of ½ or less of the frequency of the RHP zero. This is done by calculating the open-loop DC gain, ADC. After this value is known, you can calculate the crossover visually by placing a −20dB/decade slope at each pole, and a +20dB/decade slope for each zero. The point at which the gain plot crosses unity gain, or 0dB, is the crossover frequency. If the crossover frequency is less than ½ the RHP zero, the phase margin should be high enough for stability. The phase margin can also be improved by adding CC4 as discussed earlier in the section. The equation for ADC is given below with additional equations required for the calculation: gmROD' RFB2 {[(ZcLeff)// RL]//RL} (in dB) ADC(DB) = 20log10 RFB1 + RFB2 RDSON ( Zc # 2FSW nD' Leff = L (D')2 n = 1+ ) (in rad/s) 2mc (no unit) m1 mc ≊ 0.072FSW (in V/s) m1 # VINRDSON L (in V/s) where RL is the minimum load resistance, VIN is the minimum input voltage, gm is the error amplifier transconductance found in the Electrical Characteristics table, and RDSON is the value chosen from the graph "RDSON2 vs. VIN " in the Typical Performance Characteristics section. LAYOUT CONSIDERATIONS The LM2716 uses two separate ground connections, PGND for the drivers and boost NMOS power device and AGND for the sensitive analog control circuitry. The AGND and PGND pins should be tied directly together at the package. The feedback and compensation networks should be connected directly to a dedicated analog ground plane and this ground plane must connect to the AGND pin. If no analog ground plane is available then the ground connections of the feedback and compensation networks must tie directly to the AGND pin. Connecting these networks to the PGND can inject noise into the system and effect performance. 14 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LM2716 LM2716 www.ti.com SNVS240G – NOVEMBER 2003 – REVISED MARCH 2013 The input bypass capacitor CIN, as shown in Figure 12, must be placed close to the IC. This will reduce copper trace resistance which effects input voltage ripple of the IC. For additional input voltage filtering, a 100nF bypass capacitor can be placed in parallel with CIN, close to the VIN pin, to shunt any high frequency noise to ground. The output capacitors, COUT1 and COUT2, should also be placed close to the IC. Any copper trace connections for the COUTX capacitors can increase the series resistance, which directly effects output voltage ripple. The feedback network, resistors RFB1 and RFB2, should be kept close to the FB pin, and away from the inductor, to minimize copper trace connections that can inject noise into the system. Trace connections made to the inductors and schottky diodes should be minimized to reduce power dissipation and increase overall efficiency. See Figure 12, Figure 13, and Figure 14 for a good example of proper layout. For more detail on switching power supply layout considerations see Application Note AN-1149 (SNVA021): Layout Guidelines for Switching Power Supplies. APPLICATION INFORMATION Some Recommended Inductors (others may be used) Manufacturer Inductor Contact Information Coilcraft DO3316 and DO5022 series www.coilcraft.com Coiltronics DRQ73 and CD1 series www.cooperet.com Pulse P0751 and P0762 series www.pulseeng.com Sumida CDRH8D28 and CDRH8D43 series www.sumida.com Some Recommended Input and Output Capacitors (others may be used) Manufacturer Capacitor Contact Information Vishay Sprague 293D, 592D, and 595D series tantalum www.vishay.com Taiyo Yuden High capacitance MLCC ceramic www.t-yuden.com Cornell Dubilier ESRD series Polymer Aluminum Electrolytic SPV and AFK series V-chip series www.cde.com Panasonic High capacitance MLCC ceramic EEJ-L series tantalum www.panasonic.com CINB U1 CC3 CC1 500 pF PGND 6.76k 2.2 nF RC1 CSS2 1 PF CC2 2.2 nF AGND CC4 VIN VC1 CB1 SHDN1 D1 MBRM220 AGND AGND PGND SW2 PGND SW2 LM2716 0.1 PF 68 PF CSS1 22.4k RF VIN SW2 3.3V OUT1 COUT1 22 nF SHDN2 VIN PGND COUT1A CB1 to PGND FSLCT FB2 100 pF CBOOT 4.7 nF 100 pF SS1 SS2 VC2 RC2 SW1 FB1 VBG 24k L1 15 PH 0.47 PF L2 33 PH CINA 0.1 PF D2 MBRM320 CIN 4.5V to 12.5V IN 68 PF 15V OUT2 COUT2 68 PF RFB1 82.5k RFB2 PGND 7.5k Figure 12. 15V, 3.3V Output Application Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LM2716 15 LM2716 SNVS240G – NOVEMBER 2003 – REVISED MARCH 2013 www.ti.com Figure 13. PCB Layout, Top Figure 14. PCB Layout, Bottom 16 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LM2716 LM2716 www.ti.com SNVS240G – NOVEMBER 2003 – REVISED MARCH 2013 REVISION HISTORY Changes from Revision F (March 2013) to Revision G • Page Changed layout of National Data Sheet to TI format .......................................................................................................... 16 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LM2716 17 PACKAGE OPTION ADDENDUM www.ti.com 29-Aug-2015 PACKAGING INFORMATION Orderable Device Status (1) LM2716MTX/NOPB ACTIVE Package Type Package Pins Package Drawing Qty TSSOP PW 24 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) TBD Call TI Call TI Op Temp (°C) Device Marking (4/5) -40 to 125 LM2716MT (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. 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