LM2747
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SNVS370B – MARCH 2006 – REVISED MARCH 2013
LM2747 Synchronous Buck Controller with Pre-Bias Startup, and Optional Clock
Synchronization
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FEATURES
DESCRIPTION
•
The LM2747 is a high-speed synchronous buck
regulator controller with a feedback voltage accuracy
of ±1%. It can provide simple down conversion to
output voltages as low as 0.6V. Though the control
section of the IC is rated for 3 to 6V, the driver
section is designed to accept input supply rails as
high as 14V. The use of adaptive non-overlapping
MOSFET gate drivers helps avoid potential shootthrough problems while maintaining high efficiency.
The IC is designed for the more cost-effective option
of driving only N-channel MOSFETs in both the highside and low-side positions. It senses the low-side
switch voltage drop for providing a simple, adjustable
current limit.
1
2
•
•
•
•
•
•
•
•
•
•
•
•
±1% Feedback Voltage Accuracy Over
Temperature
Switching Frequency from 50 kHz to 1 MHz
Switching Frequency Synchronize Range 250
kHz to 1 MHz
Startup with a Pre-Biased Output Load
Power Stage Input Voltage from 1V to 14V
Control Stage Input Voltage from 3V to 6V
Output Voltage Adjustable Down to 0.6V
Power Good Flag and Shutdown
Output Overvoltage and Undervoltage
Detection
Low-Side Adjustable Current Sensing
Adjustable Soft-Start
Tracking and Sequencing with Shutdown and
Soft Start Pins
14-Pin TSSOP Package
APPLICATIONS
•
•
•
•
•
Down Conversion from 3.3V
Cable Modem, DSL and ADSL
Laser Jet and Ink Jet Printers
Low Voltage Power Modules
DSP, ASIC, Core and I/O
The LM2747 features a fixed-frequency voltage-mode
PWM control architecture which is adjustable from 50
kHz to 1 MHz with one external resistor. In addition,
the LM2747 also allows the switching frequency to be
synchronized to an external clock signal over the
range of 250 kHz to 1 MHz. This wide range of
switching frequency gives the power supply designer
the flexibility to make better tradeoffs between
component size, cost and efficiency.
Features include the ability to startup with a prebiased load on the output, soft-start, input
undervoltage lockout (UVLO) and Power Good
(based on both undervoltage and overvoltage
detection). In addition, the shutdown pin of the IC can
be used for providing startup delay, and the soft-start
pin can be used for implementing precise tracking, for
the purpose of sequencing with respect to an external
rail.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2013, Texas Instruments Incorporated
LM2747
SNVS370B – MARCH 2006 – REVISED MARCH 2013
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Typical Application
VCC = 3.3V
RCC
VIN = 3.3V
D1
CBOOT
RPULL-UP
VCC
BOOT
FREQ/SYNC
CClk
RFADJ
CSS
RCS
L1
VOUT = 1.2V@16A
ISEN
PWGD
Clk
CIN1,2
HG
LM2747
SD
CCC
+
Q1
Q2
LG
SS/TRACK
PGND
SGND
PGND
EAO
RFB2
FB
RC2
CC3
+
CO1,2
RFB1
CC1
CC2
RC1
Figure 1. Typical Application Circuit
Connection Diagram
1
2
3
4
5
6
7
HG
BOOT
LG
PGND
LM2747
SGND
VCC
PWGD
ISEN
PGND
SD
FREQ/SYNC
FB
SS/TRACK
EAO
14
13
12
11
10
9
8
Figure 2. 14-Lead Plastic TSSOP
θJA = 155°C/W
See PW Package
PIN DESCRIPTION
BOOT (Pin 1) -
Bootstrap pin. This is the supply rail for the high-side gate driver. When the high-side MOSFET turns on, the
voltage on this pin should be at least one gate threshold above the regulator input voltage VIN to properly turn on
the MOSFET. See MOSFET GATE DRIVERS in the APPLICATION INFORMATION section for more details on
how to select MOSFETs.
LG (Pin 2) -
Low-gate drive pin. This is the gate drive for the low-side N-channel MOSFET. This signal is interlocked with the
high-side gate drive HG (Pin 14), so as to avoid shoot-through.
PGND (Pins 3, 13) -
Power ground. This is also the ground for the low-side MOSFET driver. Both the pins must be connected together
on the PCB and form a ground plane, which is usually also the system ground.
SGND (Pin 4) -
Signal ground. It should be connected appropriately to the ground plane with due regard to good layout practices in
switching power regulator circuits.
VCC (Pin 5) -
Supply rail for the control sections of the IC.
PWGD (Pin 6) -
Power Good pin. This is an open drain output, which is typically meant to be connected to VCC or any other low
voltage source through a pull-up resistor. Choose the pull-up resistor so that the current going into this pin is kept
below 1 mA. A recommended value for the pull-up resistor is 100 kΩ for most applications. The voltage on this pin
is thus pulled low under output undervoltage or overvoltage fault conditions and also under input UVLO.
ISEN (Pin 7) -
Current limit threshold setting pin. This sources a fixed 40 µA current. A resistor of appropriate value should be
connected between this pin and the drain of the low-side MOSFET (switch node). The minimum value for this
resistor is 1 kΩ.
2
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PIN DESCRIPTION (continued)
EAO (Pin 8) -
Output of the error amplifier. The voltage level on this pin is compared with an internally generated ramp signal to
determine the duty cycle. This pin is necessary for compensating the control loop.
SS/TRACK (Pin 9) -
Soft-start and tracking pin. This pin is internally connected to the non-inverting input of the error amplifier during
soft-start, and in fact any time the SS/TRACK pin voltage happens to be below the internal reference voltage. For
the basic soft-start function, a capacitor of minimum value 1 nF is connected from this pin to ground. To track the
rising ramp of another power supply’s output, connect a resistor divider from the output of that supply to this pin as
described in APPLICATION INFORMATION.
FB (Pin 10) -
Feedback pin. This is the inverting input of the error amplifier, which is used for sensing the output voltage and
compensating the control loop.
FREQ/SYNC (Pin 11) Frequency adjust pin. The switching frequency is set by connecting a resistor of suitable value between this pin and
ground. Some typical values (rounded up to the nearest standard values) are 150 kΩ for 200 kHz, 100 kΩ for 300
kHz, 51.1 kΩ for 500 kHz, 18.7 kΩ for 1 MHz. This pin is also used to synchronize to an external clock within the
range of 250kHz to 1MHz.
SD (Pin 12) -
IC shutdown pin. Pull this pin to VCC to ensure the IC is enabled. Connect to ground to disable the IC. Under
shutdown, both high-side and low-side drives are off. This pin also features a precision threshold for power supply
sequencing purposes, as well as a low threshold to ensure minimal quiescent current.
HG (Pin 14) -
High-gate drive pin. This is the gate drive for the high-side N-channel MOSFET. This signal is interlocked with LG
(Pin 2) to avoid shoot-through.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS (1) (2)
VCC
-0.3 to 7V
BOOT Voltage
-0.3 to 18V
ISEN
-0.3 to 14V
FREQ/SYNC Voltage
-0.5 to VCC + 0.3V
All other pins
-0.3 to VCC + 0.3V
Junction Temperature
150°C
Storage Temperature
−65°C to 150°C
Soldering Information
Lead Temperature (soldering, 10sec)
260°C
Infrared or Convection (20sec)
235°C
ESD Rating (3)
(1)
(2)
(3)
2kV
Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating ratings indicate conditions for
which the device operates correctly. Operating Ratings do not imply ensured performance limits.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
ESD using the human body model which is a 100pF capacitor discharged through a 1.5 kΩ resistor into each pin.
OPERATING RATINGS
Supply Voltage Range, VCC (1)
3V to 6V
BOOT Voltage Range
1V to 17V
−40°C to +125°C
Junction Temperature Range (TJ)
Thermal Resistance (θJA)
(1)
155°C/W
The power MOSFETs can run on a separate 1V to 14V rail (Input voltage, VIN). Practical lower limit of VIN depends on selection of the
external MOSFET. See the MOSFET GATE DRIVERS section under APPLICATION INFORMATION for further details.
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ELECTRICAL CHARACTERISTICS
VCC = 3.3V unless otherwise indicated. Typicals and limits appearing in plain type apply for TA= TJ= 25°C. Limits appearing in
boldface type apply over full Operating Temperature Range. Datasheet min/max specification limits are specified by design,
test, or statistical analysis.
Symbol
Parameter
Conditions
VFB
FB Pin Voltage
VCC = 3V to 6V
VON
UVLO Thresholds
VCC Rising
VCC Falling
IQ_VCC
Operating VCC Current
Min
Typ
Max
Units
0.594
0.6
0.606
V
2.79
2.42
VCC = 3.3V, VSD = 3.3V
fSW = 600 kHz
1.1
1.7
2.3
VCC = 5V, VSD = 3.3V
fSW = 600 kHz
1.3
2
2.6
3
mA
Shutdown VCC Current
VCC = 3.3V, VSD = 0V
1
tPWGD1
PWGD Pin Response Time
VFB Rising
10
tPWGD2
PWGD Pin Response Time
VFB Falling
ISS-ON
SS Pin Source Current
VSS = 0V
ISS-OC
SS Pin Sink Current During Over
Current
VSS = 2.0V
ISEN-TH
ISEN Pin Source Current Trip Point
IFB
10
µs
14
90
Sourcing
40
µA
µs
10
7
25
FB Pin Current
V
µA
µA
55
µA
20
nA
9
MHz
ERROR AMPLIFIER
GBW
Error Amplifier Unity Gain Bandwidth
G
Error Amplifier DC Gain
118
SR
dB
Error Amplifier Slew Rate
2
V/µs
IEAO
EAO Pin Current Sourcing and
Sinking Capability
14
16
mA
VEAO
Error Amplifier Output Voltage
Minimum
1
V
Maximum
2.2
V
GATE DRIVE
IQ-BOOT
BOOT Pin Quiescent Current
VBOOT = 12V, VSD = 0
18
RHG_UP
High-Side MOSFET Driver Pull-Up
ON resistance
90
µA
VBOOT = 5V @ 350 mA Sourcing
2.7
Ω
RHG_DN
High-Side MOSFET Driver Pull-Down
350 mA Sinking
ON resistance
0.8
Ω
RLG_UP
Low-Side MOSFET Driver Pull-Up
ON resistance
VBOOT = 5V @ 350 mA Sourcing
2.7
Ω
RLG_DN
Low-Side MOSFET Driver Pull-Down
ON resistance
350 mA Sinking
0.8
Ω
OSCILLATOR
PWM Frequency
fSW
RFADJ = 750 kΩ
50
RFADJ = 100 kΩ
300
RFADJ = 42.2 kΩ
475
RFADJ = 18.7 kΩ
External Synchronizing Signal
Frequency
Voltage Swing = 0V to VCC
SYNCL
Synchronization Signal Low
Threshold
fSW = 250 kHz to 1 MHz
SYNCH
Synchronization Signal High
Threshold
fSW = 250 kHz to 1 MHz
DMAX
4
Max High-Side Duty Cycle
fSW = 300 kHz
fSW = 600 kHz
fSW = 1 MHz
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600
725
kHz
1000
250
1000
1
2
V
V
86
78
67
%
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ELECTRICAL CHARACTERISTICS (continued)
VCC = 3.3V unless otherwise indicated. Typicals and limits appearing in plain type apply for TA= TJ= 25°C. Limits appearing in
boldface type apply over full Operating Temperature Range. Datasheet min/max specification limits are specified by design,
test, or statistical analysis.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
LOGIC INPUTS AND OUTPUTS
VSTBY-IH
Standby High Trip Point
VFB = 0.575V, VBOOT = 3.3V
VSD Rising
VSTBY-IL
Standby Low Trip Point
VFB = 0.575V, VBOOT = 3.3V
VSD Falling
VSD-IH
SD Pin Logic High Trip Point
VSD Rising
VSD-IL
1.1
0.232
V
V
1.3
V
SD Pin Logic Low Trip Point
VSD Falling
0.8
VPWGD-TH-LO
PWGD Pin Trip Points
VFB Falling
0.408
0.434
0.457
V
V
VPWGD-TH-HI
PWGD Pin Trip Points
VFB Rising
0.677
0.710
0.742
V
VPWGD-HYS
PWGD Hysteresis
VFB Falling
VFB Rising
60
90
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TYPICAL PERFORMANCE CHARACTERISTICS
6
Efficiency (VOUT = 1.2V)
VCC = 3.3V, fSW = 1 MHz
Internal Reference Voltage vs Temperature
Figure 3.
Figure 4.
Frequency vs Temperature
Output Voltage vs Output Current
Figure 5.
Figure 6.
Switch Waveforms
VCC = 3.3V, VIN = 5V, VOUT = 1.2V
IOUT = 3A, CSS = 12 nF, fSW = 1 MHz
Start-Up (Full-Load)
VCC = 3.3V, VIN = 5V, VOUT = 1.2V
IOUT = 3A, CSS = 12 nF, fSW = 1 MHz
Figure 7.
Figure 8.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Start-Up (No-Load)
VCC = 3.3V, VIN = 5V, VOUT = 1.2V
CSS = 12 nF, fSW = 1 MHz
Shutdown (Full-Load)
VCC = 3.3V, VIN = 5V, VOUT = 1.2V
IOUT = 3A, CSS = 12 nF, fSW = 1 MHz
Figure 9.
Figure 10.
Load Transient Response
VCC = 3.3V, VIN = 14V, VOUT = 1.2V
fSW = 1 MHz
Line Transient Response (VIN = 3V to 9V)
VCC = 3.3V, VOUT = 1.2V
IOUT = 2A, fSW = 1 MHz
Figure 11.
Figure 12.
Frequency vs. Frequency Adjust Resistor
Maximum Duty Cycle vs Frequency
VCC = 3.3V
Figure 13.
Figure 14.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
8
Maximum Duty Cycle vs VCC
fSW = 600 kHz
Maximum Duty Cycle vs VCC
fSW = 1 MHz
Figure 15.
Figure 16.
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BLOCK DIAGRAM
FREQ/SYNC
VCC
SD
PGND
PGND
SGND
UVLO
PLL
CLOCK &
RAMP
SHUT DOWN
LOGIC
BOOT
10 Ps
DELAY
HG
SSDONE
PWGD
SYNCHRONOUS
DRIVER LOGIC
OV
UV
LG
0.71V
0.434V
10 PA
Zero Detector
SS/TRACK
1VPP
PWM LOGIC
PWM
Soft-Start
Comparator
+ Logic
REF
40 PA
-
+
90 PA
ISEN
ILIM
EA
-
+
VREF=0.6V
FB
EAO
Figure 17. Block Diagram
APPLICATION INFORMATION
The LM2747 is a voltage-mode, high-speed synchronous buck regulator with a PWM control scheme. It is
designed for use in set-top boxes, thin clients, DSL/Cable modems, and other applications that require high
efficiency buck converters. It has output shutdown (SD), input undervoltage lock-out (UVLO) mode and power
good (PWGD) flag (based on overvoltage and undervoltage detection). The overvoltage and undervoltage
signals are OR-gated to drive the power good signal and provide a logic signal to the system if the output voltage
goes out of regulation. Current limit is achieved by sensing the voltage VDS across the low side MOSFET. The
LM2747 is also able to start-up with the output pre-biased with a load and allows for the switching frequency to
be synchronized with an external clock source.
START UP/SOFT-START
When VCC exceeds 2.79V and the shutdown pin (SD) sees a logic high, the soft-start period begins. Then an
internal, fixed 10 µA source begins charging the soft-start capacitor. During soft-start the voltage on the soft-start
capacitor CSS is connected internally to the non-inverting input of the error amplifier. The soft-start period lasts
until the voltage on the soft-start capacitor exceeds the LM2747 reference voltage of 0.6V. At this point the
reference voltage takes over at the non-inverting error amplifier input. The capacitance of CSS determines the
length of the soft-start period, and can be approximated by:
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CSS =
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tSS
60
Where
•
CSS is in µF and tSS is in ms.
(1)
During soft start the Power Good flag is forced low and it is released when the FB pin voltage reaches 70% of
0.6V. At this point the chip enters normal operation mode, and the output overvoltage and undervoltage
monitoring starts.
SETTING THE OUTPUT VOLTAGE
The LM2747 regulates the output voltage by controlling the duty cycle of the high side and low side MOSFETs
(see Typical Application Circuit).The equation governing output voltage is:
RFB1 + RFB2
VOUT =
RFB1
VFB
(VFB = 0.6V)
(2)
SETTING THE SWITCHING FREQUENCY
During fixed-frequency mode of operation the PWM frequency is adjustable between 50 kHz and 1 MHz and is
set by an external resistor, RFADJ, between the FREQ/SYNC pin and ground. The resistance needed for a
desired frequency is approximated by the curve FREQUENCY vs. FREQUENCY ADJUST RESISTOR in the
TYPICAL PERFORMANCE CHARACTERISTICS section.
When it is desired to synchronize the switching frequency with an external clock source, the LM2747 has the
unique ability to synchronize from this external source within the range of 250 kHz to 1 MHz. The external clock
signal should be AC coupled to the FREQ/SYNC pin as shown below in Figure 18, where the RFADJ is chosen so
that the fixed frequency is approximately within ±30% of the external synchronizing clock frequency. An internal
protection diode clamps the low level of the synchronizing signal to approximately -0.5V. The internal clock
synchrinizes to the rising edge of the external clock.
CCLK
External Clock
Signal
To FREQ/SYNC Pin
RFADJ
Figure 18. AC Coupled Clock
It is recommended to choose an AC coupling capacitance in the range of 50 pF to 100 pF. Exceeding the
recommended capacitance may inject excessive energy through the internal clamping diode structure present on
the FREQ/SYNC pin.
The typical trip level of the synchronization pin is 1.5V. To ensure proper synchronization and to avoid damaging
the IC, the peak-to-peak value (amplitude) should be between 2.5V and VCC. The minimum width of this pulse
must be greater than 100 ns, and it's maximum width must be 100ns less than the period of the switching cycle.
The external clock synchronization process begins once the LM2747 is enabled and an external clock signal is
detected. During the external clock synchronization process the internal clock initially switches at approximately
1.5 MHz and decreases until it has matched the external clock’s frequency. The lock-in period is approximately
30 µs if the external clock is switching at 1 MHz, and about 100 µs if the external clock is at 200 kHz. When
there is no clock signal present, the LM2747 enters into fixed-frequency mode and begins switching at the
frequency set by the RFADJ resistor. If the external clock signal is removed after frequency synchronization, the
LM2747 will enter fixed-frequency mode within two clock cycles. If the external clock is removed within the 30 µs
lock-in period, the LM2747 will re-enter fixed-frequency mode within two internal clock cycles after the lock-in
period.
10
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OUTPUT PRE-BIAS STARTUP
If there is a pre-biased load on the output of the LM2747 during startup, the IC will disable switching of the lowside MOSFET and monitor the SW node voltage during the off-time of the high-side MOSFET. There is no load
current sensing while in pre-bias mode because the low-side MOSFET never turns on. The IC will remain in this
pre-bias mode until it sees the SW node stays below 0V during the entire high-side MOSFET's off-time. Once it
is determined that the SW node remained below 0V during the high-side off-time, the low-side MOSFET begins
switching during the next switching cycle. Figure 19 shows the SW node, HG, and LG signals during pre-bias
startup. The pre-biased output voltage should not exceed VCC + VGS of the external High-Side MOSFET to
ensure that the High-Side MOSFET will be able to switch during startup.
Figure 19. Output Pre-Bias Mode Waveforms
TRACKING A VOLTAGE LEVEL
The LM2747 can track the output of a master power supply during soft-start by connecting a resistor divider to
the SS/TRACK pin. In this way, the output voltage slew rate of the LM2747 will be controlled by the master
supply for loads that require precise sequencing. When the tracking function is used no soft-start capacitor
should be connected to the SS/TRACK pin. However in all other cases, a CSS value of at least 1 nF between the
soft-start pin and ground should be used.
Master Power
Supply
VOUT1 = 5V
RT2
1 k:
VOUT2 = 1.8V
SS/TRACK
VSS = 0.65V
RT1
150:
LM2747
FB
RFB2
10 k:
VFB
RFB1
5 k:
Figure 20. Tracking Circuit
One way to use the tracking feature is to design the tracking resistor divider so that the master supply’s output
voltage (VOUT1) and the LM2747’s output voltage (represented symbolically in Figure 20 as VOUT2, i.e. without
explicitly showing the power components) both rise together and reach their target values at the same time. For
this case, the equation governing the values of the tracking divider resistors RT1 and RT2 is:
0.65 = VOUT1
RT1
RT1 + RT2
(3)
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The current through RT1 should be about 4 mA for precise tracking. The final voltage of the SS/TRACK pin
should be set higher than the feedback voltage of 0.6V (say about 0.65V as in the above equation). If the master
supply voltage was 5V and the LM2747 output voltage was 1.8V, for example, then the value of RT1 needed to
give the two supplies identical soft-start times would be 150Ω. A timing diagram for the equal soft-start time case
is shown in Figure 21.
5V
VOUT1
1.8V
VOUT2
Figure 21. Tracking with Equal Soft-Start Time
TRACKING A VOLTAGE SLEW RATE
The tracking feature can alternatively be used not to make both rails reach regulation at the same time but rather
to have similar rise rates (in terms of output dV/dt). This method ensures that the output voltage of the LM2747
always reaches regulation before the output voltage of the master supply. In this case, the tracking resistors can
be determined based on the following equation:
0.65 = VOUT2
RT1
RT1 + RT2
(4)
For the example case of VOUT1 = 5V and VOUT2 = 1.8V, with RT1 set to 150Ω as before, RT2 is calculated from the
above equation to be 265Ω. A timing diagram for the case of equal slew rates is shown in Figure 22.
5V
1.8V
VOUT1
1.8V
VOUT2
Figure 22. Tracking with Equal Slew Rates
SEQUENCING
The start up/soft-start of the LM2747 can be delayed for the purpose of sequencing by connecting a resistor
divider from the output of a master power supply to the SD pin, as shown in Figure 23.
12
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Master Power
Supply
VOUT1
VOUT2
RS2
SD
LM2747
RS1
FB
RFB2
VFB
RFB1
Figure 23. Sequencing Circuit
A desired delay time tDELAY between the startup of the master supply output voltage and the LM2747 output
voltage can be set based on the SD pin low-to-high threshold VSD-IH and the slew rate of the voltage at the SD
pin, SRSD:
tDELAY = VSD-IH / SRSD
(5)
Note again, that in Figure 23, the LM2747’s output voltage has been represented symbolically as VOUT2, i.e.
without explicitly showing the power components.
VSD-IH is typically 1.08V and SRSD is the slew rate of the SD pin voltage. The values of the sequencing divider
resistors RS1 and RS2 set the SRSD based on the master supply output voltage slew rate, SROUT1, using the
following equation:
SRSD = SROUT1
RS1
RS1 + RS2
(6)
For example, if the master supply output voltage slew rate was 1V/ms and the desired delay time between the
startup of the master supply and LM2747 output voltage was 5 ms, then the desired SD pin slew rate would be
(1.08V/5 ms) = 0.216V/ms. Due to the internal impedance of the SD pin, the maximum recommended value for
RS2 is 1 kΩ. To achieve the desired slew rate, RS1 would then be 274Ω. A timing diagram for this example is
shown in Figure 24.
5V
VSD-IH
1.08V
VOUT1
1.8V
VOUT2
t = 5 ms
Figure 24. Delay for Sequencing
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SD PIN IMPEDANCE
When connecting a resistor divider to the SD pin of the LM2747 some care has to be taken. Once the SD voltage
goes above VSD-IH, a 17 µA pull-up current is activated as shown in Figure 25. This current is used to create the
internal hysteresis (≊170 mV); however, high external impedances will affect the SD pin logic thresholds as well.
The external impedance used for the sequencing divider network should preferably be a small fraction of the
impedance of the SD pin for good performance (around 1 kΩ).
17 PA
8 PA
Bias Enable
SD
10k
Soft-Start Enable
1.25V
+
-
Figure 25. SD Pin Logic
MOSFET GATE DRIVERS
The LM2747 has two gate drivers designed for driving N-channel MOSFETs in a synchronous mode. Note that
unlike most other synchronous controllers, the bootstrap capacitor of the LM2747 provides power not only to the
driver of the upper MOSFET, but the lower MOSFET driver too (both drivers are ground referenced, i.e. no
floating driver).
Two things must be kept in mind here. First, the BOOT pin has an absolute maximum rating of 18V. This must
never be exceeded, even momentarily. Since the bootstrap capacitor is connected to the SW node, the peak
voltage impressed on the BOOT pin is the sum of the input voltage (VIN) plus the voltage across the bootstrap
capacitor (ignoring any forward drop across the bootstrap diode). The bootstrap capacitor is charged up by a
given rail (called VBOOT_DC here) whenever the upper MOSFET turns off. This rail can be the same as VCC or it
can be any external ground-referenced DC rail. But care has to be exercised when choosing this bootstrap DC
rail that the BOOT pin is not damaged. For example, if the desired maximum VIN is 14V, and VBOOT_DC is chosen
to be the same as VCC, then clearly if the VCC rail is 6V, the peak voltage on the BOOT pin is 14V + 6V = 20V.
This is unacceptable, as it is in excess of the rating of the BOOT pin. A VCC of 3V would be acceptable in this
case. Or the VIN range must be reduced accordingly. There is also the option of deriving the bootstrap DC rail
from another 3V external rail, independent of VCC.
The second thing to be kept in mind here is that the output of the low-side driver swings between the bootstrap
DC rail level of VBOOT_DC and Ground, whereas the output of the high-side driver swings between VIN+ VBOOT_DC
and Ground. To keep the high-side MOSFET fully on when desired, the Gate pin voltage of the MOSFET must
be higher than its instantaneous Source pin voltage by an amount equal to the 'Miller plateau'. It can be shown
that this plateau is equal to the threshold voltage of the chosen MOSFET plus a small amount equal to Io/g. Here
Io is the maximum load current of the application, and g is the transconductance of this MOSFET (typically about
100 for logic-level devices). That means we must choose VBOOT_DC to at least exceed the Miller plateau level.
This may therefore affect the choice of the threshold voltage of the external MOSFETs, and that in turn may
depend on the chosen VBOOT_DC rail.
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So far, in the discussion above, the forward drop across the bootstrap diode has been ignored. But since that
does affect the output of the driver somewhat, it is a good idea to include this drop in the following examples.
Looking at the Typical Application schematic, this means that the difference voltage VCC - VD1, which is the
voltage the bootstrap capacitor charges up to, must always be greater than the maximum tolerance limit of the
threshold voltage of the upper MOSFET. Here VD1 is the forward voltage drop across the bootstrap diode D1.
This may place restrictions on the minimum input voltage and/or type of MOSFET used.
A basic bootstrap circuit can be built using one Schottky diode and a small capacitor, as shown in Figure 26. The
capacitor CBOOT serves to maintain enough voltage between the top MOSFET gate and source to control the
device even when the top MOSFET is on and its source has risen up to the input voltage level. The charge pump
circuitry is fed from VCC, which can operate over a range from 3.0V to 6.0V. Using this basic method the voltage
applied to the gates of both high-side and low-side MOSFETs is VCC - VD. This method works well when VCC is
5V±10%, because the gate drives will get at least 4.0V of drive voltage during the worst case of VCC-MIN = 4.5V
and VD-MAX = 0.5V. Logic level MOSFETs generally specify their on-resistance at VGS = 4.5V. When VCC =
3.3V±10%, the gate drive at worst case could go as low as 2.5V. Logic level MOSFETs are not ensured to turn
on, or may have much higher on-resistance at 2.5V. Sub-logic level MOSFETs, usually specified at VGS = 2.5V,
will work, but are more expensive, and tend to have higher on-resistance. The circuit in Figure 26 works well for
input voltages ranging from 1V up to 14V and VCC = 5V±10%, because the drive voltage depends only on VCC.
LM2747
BOOT
D1
VCC
CBOOT
VIN
HG
+
VO
+
LG
Figure 26. Basic Charge Pump (Bootstrap)
Note that the LM2747 can be paired with a low cost linear regulator like the LM78L05 to run from a single input
rail between 6.0 and 14V. The 5V output of the linear regulator powers both the VCC and the bootstrap circuit,
providing efficient drive for logic level MOSFETs. An example of this circuit is shown in Figure 27.
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LM2747
VCC
5V
LM78L05
D1
BOOT
CBOOT
VIN
+
HG
VO
LG
+
Figure 27. LM78L05 Feeding Basic Charge Pump
Figure 28 shows a second possibility for bootstrapping the MOSFET drives using a doubler. This circuit provides
an equal voltage drive of VCC - 3VD + VIN to both the high-side and low-side MOSFET drives. This method should
only be used in circuits that use 3.3V for both VCC and VIN. Even with VIN = VCC = 3.0V (10% lower tolerance on
3.3V) and VD = 0.5V both high-side and low-side gates will have at least 4.5V of drive. The power dissipation of
the gate drive circuitry is directly proportional to gate drive voltage, hence the thermal limits of the LM2747 IC will
quickly be reached if this circuit is used with VCC or VIN voltages over 5V.
LM2747
BOOT
D3
D2
D1
VCC
VIN
HG
+
VO
LG
+
Figure 28. Charge Pump with Added Gate Drive
All the gate drive circuits shown in the above figures typically use 100 nF ceramic capacitors in the bootstrap
locations.
POWER GOOD SIGNAL
The open drain output on the Power Good pin needs a pull-up resistor to a low voltage source. The pull-up
resistor should be chosen so that the current going into the Power Good pin is less than 1 mA. A 100 kΩ resistor
is recommended for most applications.
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The Power Good signal is an OR-gated flag which takes into account both output overvoltage and undervoltage
conditions. If the feedback pin (FB) voltage is 18% above its nominal value (118% x VFB = 0.708V) or falls 28%
below that value (72% x VFB = 0.42V) the Power Good flag goes low. The Power Good flag can be used to signal
other circuits that the output voltage has fallen out of regulation, however the switching of the LM2747 continues
regardless of the state of the Power Good signal. The Power Good flag will return to logic high whenever the
feedback pin voltage is between 72% and 118% of 0.6V.
UVLO
The 2.79V turn-on threshold on VCC has a built in hysteresis of about 300 mV. If VCC drops below 2.42V, the chip
definitely enters UVLO mode. UVLO consists of turning off the top and bottom MOSFETS and remaining in that
condition until VCC rises above 2.79V. As with normal shutdown initiated by the SD pin, the soft-start capacitor is
discharged through an internal MOSFET, ensuring that the next start-up will be controlled by the soft-start
circuitry.
CURRENT LIMIT
Current limit is realized by sensing the voltage across the low-side MOSFET while it is on. The RDSON of the
MOSFET is a known value; hence the current through the MOSFET can be determined as:
VDS = IOUT x RDSON
(7)
The current through the low-side MOSFET while it is on is also the falling portion of the inductor current. The
current limit threshold is determined by an external resistor, RCS, connected between the switching node and the
ISEN pin. A constant current (ISEN-TH) of 40 µA typical is forced through RCS, causing a fixed voltage drop. This
fixed voltage is compared against VDS and if the latter is higher, the current limit of the chip has been reached.
To obtain a more accurate value for RCS you must consider the operating values of RDSON and ISEN-TH at their
operating temperatures in your application and the effect of slight parameter differences from part to part. RCS
can be found by using the following equation using the RDSON value of the low side MOSFET at it's expected hot
temperature and the absolute minimum value expected over the full temperature range for the for the ISEN-TH
which is 25 µA:
RCS = RDSON-HOT x ILIM / ISEN-TH
(8)
For example, a conservative 15A current limit in a 10A design with a RDSON-HOT of 10 mΩ would require a 6 kΩ
resistor. The minimum value for RCS in any application is 1 kΩ. Because current sensing is done across the lowside MOSFET, no minimum high-side on-time is necessary. The LM2747 enters current limit mode if the inductor
current exceeds the current limit threshold at the point where the high-side MOSFET turns off and the low-side
MOSFET turns on. (The point of peak inductor current, see Figure 29). Note that in normal operation mode the
high-side MOSFET always turns on at the beginning of a clock cycle. In current limit mode, by contrast, the highside MOSFET on-pulse is skipped. This causes inductor current to fall. Unlike a normal operation switching
cycle, however, in a current limit mode switching cycle the high-side MOSFET will turn on as soon as inductor
current has fallen to the current limit threshold. The LM2747 will continue to skip high-side MOSFET pulses until
the inductor current peak is below the current limit threshold, at which point the system resumes normal
operation.
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Normal Operation
Current Limit
ILIM
IL
D
Figure 29. Current Limit Threshold
Unlike a high-side MOSFET current sensing scheme, which limits the peaks of inductor current, low-side current
sensing is only allowed to limit the current during the converter off-time, when inductor current is falling.
Therefore in a typical current limit plot the valleys are normally well defined, but the peaks are variable, according
to the duty cycle. The PWM error amplifier and comparator control the off-pulse of the high-side MOSFET, even
during current limit mode, meaning that peak inductor current can exceed the current limit threshold. Assuming
that the output inductor does not saturate, the maximum peak inductor current during current limit mode can be
calculated with the following equation:
IPK-CL = ILIM + (TSW - 200 ns)
VIN - VO
L
Where
•
TSW is the inverse of switching frequency fSW.
(9)
The 200 ns term represents the minimum off-time of the duty cycle, which ensures enough time for correct
operation of the current sensing circuitry.
In order to minimize the time period in which peak inductor current exceeds the current limit threshold, the IC
also discharges the soft-start capacitor through a fixed 90 µA sink. The output of the LM2747 internal error
amplifier is limited by the voltage on the soft-start capacitor. Hence, discharging the soft-start capacitor reduces
the maximum duty cycle D of the controller. During severe current limit this reduction in duty cycle will reduce the
output voltage if the current limit conditions last for an extended time. Output inductor current will be reduced in
turn to a flat level equal to the current limit threshold. The third benefit of the soft-start capacitor discharge is a
smooth, controlled ramp of output voltage when the current limit condition is cleared.
SHUTDOWN
If the shutdown pin is pulled low, (below 0.8V) the LM2747 enters shutdown mode, and discharges the soft-start
capacitor through a MOSFET switch. The high and low-side MOSFETs are turned off. The LM2747 remains in
this state as long as VSD sees a logic low (see the ELECTRICAL CHARACTERISTICS table). To assure proper
IC start-up the shutdown pin should not be left floating. For normal operation this pin should be connected
directly to VCC or to another voltage between 1.3V to VCC (see the ELECTRICAL CHARACTERISTICS table).
DESIGN CONSIDERATIONS
The following is a design procedure for all the components needed to create the Typical Application Circuit
shown on the front page. This design converts 3.3V (VIN) to 1.2V (VOUT) at a maximum load of 4A with an
efficiency of 89% and a switching frequency of 300 kHz. The same procedures can be followed to create many
other designs with varying input voltages, output voltages, and load currents.
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Input Capacitor
The input capacitors in a Buck converter are subjected to high stress due to the input current trapezoidal
waveform. Input capacitors are selected for their ripple current capability and their ability to withstand the heat
generated since that ripple current passes through their ESR. Input rms ripple current is approximately:
IRMS_RIP = IOUT x
D(1 - D)
Where
•
duty cycle D = VOUT/VIN.
(10)
The power dissipated by each input capacitor is:
(IRMS_RIP)2 x ESR
PCAP =
n2
where
•
n is the number of paralleled capacitors, and ESR is the equivalent series resistance of each capacitor.
(11)
The equation above indicates that power loss in each capacitor decreases rapidly as the number of input
capacitors increases. The worst-case ripple for a Buck converter occurs during full load and when the duty cycle
(D) is 0.5. For this 3.3V to 1.2V design the duty cycle is 0.364. For a 4A maximum load the ripple current is
1.92A.
Output Inductor
The output inductor forms the first half of the power stage in a Buck converter. It is responsible for smoothing the
square wave created by the switching action and for controlling the output current ripple (ΔIOUT). The inductance
is chosen by selecting between tradeoffs in efficiency and response time. The smaller the output inductor, the
more quickly the converter can respond to transients in the load current. However, as shown in the efficiency
calculations, a smaller inductor requires a higher switching frequency to maintain the same level of output current
ripple. An increase in frequency can mean increasing loss in the MOSFETs due to the charging and discharging
of the gates. Generally the switching frequency is chosen so that conduction loss outweighs switching loss. The
equation for output inductor selection is:
VIN - VOUT
L=
L=
xD
'IOUT x fSW
(12)
3.3V - 1.2V
1.2V
x
3.3V
0.4 x 4A x 300 kHz
(13)
(14)
L = 1.6 µH
Here we have plugged in the values for output current ripple, input voltage, output voltage, switching frequency,
and assumed a 40% peak-to-peak output current ripple. This yields an inductance of 1.6 µH. The output inductor
must be rated to handle the peak current (also equal to the peak switch current), which is (IOUT + (0.5 x ΔIOUT)) =
4.8A, for a 4A design.
The Coilcraft DO3316P-222P is 2.2 µH, is rated to 7.4A peak, and has a direct current resistance (DCR) of 12
mΩ. After selecting the Coilcraft DO3316P-222P for the output inductor, actual inductor current ripple should be
re-calculated with the selected inductance value, as this information is needed to select the output capacitor. Rearranging the equation used to select inductance yields the following:
VIN(MAX) - VO
'IOUT =
fSW x LACTUAL
xD
(15)
VIN(MAX) is assumed to be 10% above the steady state input voltage, or 3.6V at VIN = 3.3V. The re-calculated
current ripple will then be 1.2A. This gives a peak inductor/switch current will be 4.6A.
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Output Capacitor
The output capacitor forms the second half of the power stage of a Buck switching converter. It is used to control
the output voltage ripple (ΔVOUT) and to supply load current during fast load transients.
In this example the output current is 4A and the expected type of capacitor is an aluminum electrolytic, as with
the input capacitors. Other possibilities include ceramic, tantalum, and solid electrolyte capacitors, however the
ceramic type often do not have the large capacitance needed to supply current for load transients, and tantalums
tend to be more expensive than aluminum electrolytic. Aluminum capacitors tend to have very high capacitance
and fairly low ESR, meaning that the ESR zero, which affects system stability, will be much lower than the
switching frequency. The large capacitance means that at the switching frequency, the ESR is dominant, hence
the type and number of output capacitors is selected on the basis of ESR. One simple formula to find the
maximum ESR based on the desired output voltage ripple, ΔVOUT and the designed output current ripple, ΔIOUT,
is:
ESRMAX =
'VOUT
'IOUT
(16)
In this example, in order to maintain a 2% peak-to-peak output voltage ripple and a 40% peak-to-peak inductor
current ripple, the required maximum ESR is 20 mΩ. The Sanyo 4SP560M electrolytic capacitor will give an
equivalent ESR of 14 mΩ. The capacitance of 560 µF is enough to supply energy even to meet severe load
transient demands.
MOSFETs
Selection of the power MOSFETs is governed by a trade-off between cost, size, and efficiency. One method is to
determine the maximum cost that can be endured, and then select the most efficient device that fits that price.
Breaking down the losses in the high-side and low-side MOSFETs and then creating spreadsheets is one way to
determine relative efficiencies between different MOSFETs. Good correlation between the prediction and the
bench result is not ensured, however. Single-channel buck regulators that use a controller IC and discrete
MOSFETs tend to be most efficient for output currents of 2 to 10A.
Losses in the high-side MOSFET can be broken down into conduction loss, gate charging loss, and switching
loss. Conduction, or I2R loss, is approximately:
PC = D (IO2 x RDSON-HI x 1.3) (High-Side MOSFET)
PC = (1 - D) x (IO2 x RDSON-LO x 1.3) (Low-Side MOSFET)
(17)
(18)
In the above equations the factor 1.3 accounts for the increase in MOSFET RDSON due to heating. Alternatively,
the 1.3 can be ignored and the RDSON of the MOSFET estimated using the RDSON Vs. Temperature curves in the
MOSFET datasheets.
Gate charging loss results from the current driving the gate capacitance of the power MOSFETs, and is
approximated as:
PGC = n x (VDD) x QG x fSW
where
•
•
•
‘n’ is the number of MOSFETs (if multiple devices have been placed in parallel)
VDD is the driving voltage (see MOSFET GATE DRIVERS section)
QGS is the gate charge of the MOSFET.
(19)
If different types of MOSFETs are used, the ‘n’ term can be ignored and their gate charges simply summed to
form a cumulative QG. Gate charge loss differs from conduction and switching losses in that the actual
dissipation occurs in the LM2747, and not in the MOSFET itself.
Switching loss occurs during the brief transition period as the high-side MOSFET turns on and off, during which
both current and voltage are present in the channel of the MOSFET. It can be approximated as:
PSW = 0.5 x VIN x IO x (tr + tf) x fSW
where
•
tr and tf are the rise and fall times of the MOSFET.
(20)
Switching loss occurs in the high-side MOSFET only.
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For this example, the maximum drain-to-source voltage applied to either MOSFET is 3.6V. The maximum drive
voltage at the gate of the high-side MOSFET is 3.1V, and the maximum drive voltage for the low-side MOSFET
is 3.3V. Due to the low drive voltages in this example, a MOSFET that turns on fully with 3.1V of gate drive is
needed. For designs of 5A and under, dual MOSFETs in SO-8 provide a good trade-off between size, cost, and
efficiency.
Support Components
CIN2
A small (0.1 to 1 µF) ceramic capacitor should be placed as close as possible to the drain of the high-side
MOSFET and source of the low-side MOSFET (dual MOSFETs make this easy). This capacitor should be
X5R type dielectric or better.
RCC, CCC These are standard filter components designed to ensure smooth DC voltage for the chip supply. RCC
should be 1 to 10Ω. CCC should 1 µF, X5R type or better.
CBOOT Bootstrap capacitor, typically 100 nF.
RPULL-UP This is a standard pull-up resistor for the open-drain power good signal (PWGD). The recommended
value is 100 kΩ connected to VCC. If this feature is not necessary, the resistor can be omitted.
D1
A small Schottky diode should be used for the bootstrap. It allows for a minimum drop for both high and
low-side drivers. The MBR0520 or BAT54 work well in most designs.
RCS
Resistor used to set the current limit. Since the design calls for a peak current magnitude (IOUT + (0.5 x
ΔIOUT)) of 4.8A, a safe setting would be 6A. (This is below the saturation current of the output inductor,
which is 7A.) Following the equation from the CURRENT LIMIT section, a 1.3 kΩ resistor should be used.
RFADJ This resistor is used to set the switching frequency of the chip. The resistor value is approximated from
the Frequency vs Frequency Adjust Resistor curve in the TYPICAL PERFORMANCE
CHARACTERISTICS section. For 300 kHz operation, a 100 kΩ resistor should be used.
CSS
The soft-start capacitor depends on the user requirements and is calculated based on the equation given
in the section titled START UP/SOFT-START. Therefore, for a 7 ms delay, a 12 nF capacitor is suitable.
Control Loop Compensation
The LM2747 uses voltage-mode (‘VM’) PWM control to correct changes in output voltage due to line and load
transients. VM requires careful small signal compensation of the control loop for achieving high bandwidth and
good phase margin.
The control loop is comprised of two parts. The first is the power stage, which consists of the duty cycle
modulator, output inductor, output capacitor, and load. The second part is the error amplifier, which for the
LM2747 is a 9 MHz op-amp used in the classic inverting configuration. Figure 30 shows the regulator and control
loop components.
L
RL
+ C
O
VIN
RO
+
RC
+
VRAMP
RC2
CC2
RC1
RFB2
CC3
CC1
+
RFB1
+
-
VREF
Figure 30. Power Stage and Error Amp
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One popular method for selecting the compensation components is to create Bode plots of gain and phase for
the power stage and error amplifier. Combined, they make the overall bandwidth and phase margin of the
regulator easy to see. Software tools such as Excel, MathCAD, and Matlab are useful for showing how changes
in compensation or the power stage affect system gain and phase.
The power stage modulator provides a DC gain ADC that is equal to the input voltage divided by the peak-to-peak
value of the PWM ramp. This ramp is 1.0Vpk-pk for the LM2747. The inductor and output capacitor create a
double pole at frequency fDP, and the capacitor ESR and capacitance create a single zero at frequency fESR. For
this example, with VIN = 3.3V, these quantities are:
VIN
ADC =
VRAMP
1
2S
fDP =
fESR =
3.3
= 10.4 dB
1.0
=
RO + RL
LCO(RO + ESR)
1
2SCOESR
(21)
= 4.5 kHz
(22)
= 20.3 kHz
(23)
In the equation for fDP, the variable RL is the power stage resistance, and represents the inductor DCR plus the
on resistance of the top power MOSFET. RO is the output voltage divided by output current. The power stage
transfer function GPS is given by the following equation, and Figure 31 shows Bode plots of the phase and gain in
this example.
GPS =
•
•
•
VIN x RO
VRAMP
x
sCORC + 1
as2 + bs + c
a = LCO(RO + RC)
b = L + CO(RORL + RORC + RCRL)
c = RO + RL
(24)
20
GAIN (dB)
4
-12
-28
-44
-60
100
1k
10k
100k
1M
FREQUENCY (Hz)
0
PHASE (o)
-30
-60
-90
-120
-150
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 31. Power Stage Gain and Phase
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The double pole at 4.5 kHz causes the phase to drop to approximately -130° at around 10 kHz. The ESR zero, at
20.3 kHz, provides a +90° boost that prevents the phase from dropping to -180º. If this loop were left
uncompensated, the bandwidth would be approximately 10 kHz and the phase margin 53°. In theory, the loop
would be stable, but would suffer from poor DC regulation (due to the low DC gain) and would be slow to
respond to load transients (due to the low bandwidth.) In practice, the loop could easily become unstable due to
tolerances in the output inductor, capacitor, or changes in output current, or input voltage. Therefore, the loop is
compensated using the error amplifier and a few passive components.
For this example, a Type III, or three-pole-two-zero approach gives optimal bandwidth and phase.
In most voltage mode compensation schemes, including Type III, a single pole is placed at the origin to boost DC
gain as high as possible. Two zeroes fZ1 and fZ2 are placed at the double pole frequency to cancel the double
pole phase lag. Then, a pole, fP1 is placed at the frequency of the ESR zero. A final pole fP2 is placed at one-half
of the switching frequency. The gain of the error amplifier transfer function is selected to give the best bandwidth
possible without violating the Nyquist stability criteria. In practice, a good crossover point is one-fifth of the
switching frequency, or 60 kHz for this example. The generic equation for the error amplifier transfer function is:
s
+1
2SfZ1
GEA = AEA x
s
s
+1
2SfP1
s
+1
2SfZ2
s
+1
2SfP2
(25)
In this equation the variable AEA is a ratio of the values of the capacitance and resistance of the compensation
components, arranged as shown in Figure 30. AEA is selected to provide the desired bandwidth. A starting value
of 80,000 for AEA should give a conservative bandwidth. Increasing the value will increase the bandwidth, but will
also decrease phase margin. Designs with 45-60° are usually best because they represent a good trade-off
between bandwidth and phase margin. In general, phase margin is lowest and gain highest (worst-case) for
maximum input voltage and minimum output current. One method to select AEA is to use an iterative process
beginning with these worst-case conditions.
1. Increase AEA
2. Check overall bandwidth and phase margin
3. Change VIN to minimum and recheck overall bandwidth and phase margin
4. Change IO to maximum and recheck overall bandwidth and phase margin
The process ends when the both bandwidth and the phase margin are sufficiently high. For this example input
voltage can vary from 3.0 to 3.6V and output current can vary from 0 to 4A, and after a few iterations a moderate
gain factor of 101dB is used.
The error amplifier of the LM2747 has a unity-gain bandwidth of 9 MHz. In order to model the effect of this
limitation, the open-loop gain can be calculated as:
OPG =
2S x 9 MHz
s
(26)
The new error amplifier transfer function that takes into account unity-gain bandwidth is:
GEA x OPG
HEA =
1 + GEA + OPG
(27)
The gain and phase of the error amplifier are shown in Figure 32.
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60
GAIN (dB)
48
36
24
12
0
100
1k
10k
100k
1M
FREQUENCY (Hz)
50
PHASE (o)
20
-10
-40
-70
-100
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 32. Error Amp. Gain and Phase
In VM regulators, the top feedback resistor RFB2 forms a part of the compensation. Setting RFB2 to 10 kΩ±1%,
usually gives values for the other compensation resistors and capacitors that fall within a reasonable range.
(Capacitances > 1 pF, resistances
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