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LM3017
SNOSC66D – MARCH 2012 – REVISED SEPTEMBER 2016
LM3017 High Efficiency Low-Side Controller With True Shutdown
1 Features
3 Description
•
The LM3017 device is a versatile low-side NFET
controller incorporating true shutdown and input side
current limiting. The LM3017 is designed for simple
implementation
of
boost
conversions
in
Thunderbolt™ Technology. The LM3017 can also be
configured for flyback or SEPIC designs. The input
voltage range of 5 V to 18 V accommodates a two- or
three-cell lithium ion battery or a 12-V rail. The enable
pin accepts a single input to drive three different
modes of operation: boost, pass-through, or
shutdown mode. The LM3017 draws very low current
in shutdown mode, typically 40 nA from the input
supply.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Fully Compliant to Thunderbolt™ Technology
Specifications
True Shutdown for Short-Circuit Protection
Input Side Current Limit
Single Enable Pin With Three Modes of
Operation: Boost, Pass-Through, or Shutdown
Built-in Charge Pump for High-Side NFET
Disconnect Switch
1-A Push-Pull Driver for Low-Side NFET
Peak Current Mode Control
Simple Slope Compensation
Protection Features: Thermal Shutdown, Cycleby-Cycle Current Limit, Short-Circuit Protection,
Output Overvoltage Protection, and Latch-Off
Internal Soft Start
Input Voltage Range: 5 V to 18 V
600-kHz Fixed Frequency Operation
±1% Reference Voltage Accuracy Over
Temperature
Low Shutdown Current (< 1 µA), 40 nA Typical
2.4 mm × 2.7 mm × 0.8 mm, 10-Pin WQFN
Package
The LM3017 provides an adjustable output to drive
the Power Load Switch or MUX for the host
Thunderbolt™ port. The ability to drive an external
high-side NMOS provides for true isolation of the load
from the input. Current limiting on the input ensures
that inrush and short-circuit currents are always under
control. The LM3017 incorporates built-in thermal
shutdown, cycle-by-cycle current limit, short-circuit
protection, output overvoltage protection, and soft
start. It is available in a 10-pin WQFN package.
Device Information(1)
PART NUMBER
LM3017
2 Applications
•
•
•
•
•
Thunderbolt™ Technology Host Ports
Notebook and Desktop Computers, Tablets, and
Other Portable Consumer Electronics
Hard Disc Drives, Solid-State Drives
Offline Power Supplies
Set-Top Boxes
PACKAGE
WQFN (10)
BODY SIZE (NOM)
2.40 mm × 2.70 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Circuit
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM3017
SNOSC66D – MARCH 2012 – REVISED SEPTEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 9
7.1
7.2
7.3
7.4
Overview ................................................................... 9
Functional Block Diagram ......................................... 9
Feature Description................................................. 10
Device Functional Modes........................................ 12
8
Application and Implementation ........................ 14
8.1 Application Information............................................ 14
8.2 Typical Application .................................................. 14
9 Power Supply Recommendations...................... 28
10 Layout................................................................... 28
10.1 Layout Guidelines ................................................. 28
10.2 Layout Examples................................................... 30
10.3 Thermal Considerations ........................................ 30
11 Device and Documentation Support ................. 31
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
31
31
31
31
31
31
12 Mechanical, Packaging, and Orderable
Information ........................................................... 31
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (March 2013) to Revision D
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
•
Changed RθJA value in the Thermal Information table From: 36 To: 79.2.............................................................................. 4
Changes from Revision B (November 2012) to Revision C
•
2
Page
Added Updated to Rev C as Rev A and B were SVA Confidentials ...................................................................................... 1
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5 Pin Configuration and Functions
NKL Package
10-Pin WQFN
Top View
30180903
Pin Functions
PIN
NO.
NAME
TYPE (1)
DESCRIPTION
1
VCC
O
Driver supply voltage pin: output of internal regulator powering low side NMOS driver. A minimum of
0.47 µF must be connected from this pin to PGND for proper operation.
2
DR
O
Low-side NMOS gate driver output: output gate drive to low side NMOS gate.
3
PGND
G
Power ground: ground for power section. External power circuit reference. Must be connected to
AGND at a single point.
4
VG
O
High side NMOS gate driver output: output gate drive to high side NMOS gate.
5
EN/MODE
A
Multi-function input pin: this input provides for chip enable, and mode selection. See Device
Functional Modes for details.
6
FB
A
Feed-back input pin: negative input to error amplifier. Connect to feedback resistor tap to regulate
output.
7
COMP
A
Compensation pin: a resistor and capacitor combination connected to this pin provides frequency
compensation for the regulator control loop.
8
AGND
G
Analog ground: ground for analog control circuitry. Reference point for all stated voltages.
9
ISEN
A
Current sense input: current sense input, with respect to VIN, for all current limit functions.
10
VIN
P
Power supply input pin: input supply to regulator. See Application and Implementation for
recommendations on bypass capacitors on this pin.
(1)
A = Analog, G = Ground, O = Output, P = Power
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SNOSC66D – MARCH 2012 – REVISED SEPTEMBER 2016
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN
MAX
UNIT
VIN to PGND, AGND
–0.3
20
V
FB, COMP, VCC,DR to PGND, AGND
–0.2
6
V
EN/MODE
–0.2
5.5
V
VG
–0.3
VIN + 6
V
VIN – 0.3
VIN
V
1
A
ISEN to PGND, AGND
Peak low side driver output current
Power dissipation
Internally limited
Junction temperature, TJ
Storage temperature, Tstg
(1)
(2)
–65
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
6.2 ESD Ratings
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
VALUE
UNIT
±1500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VIN
Supply voltage
5.4
18
UNIT
V
TJ
Junction temperature
–40
125
°C
6.4 Thermal Information
LM3017
THERMAL METRIC (1)
NKL (WQFN)
UNIT
10 PINS
RθJA
Junction-to-ambient thermal resistance
79.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
29.8
°C/W
RθJB
Junction-to-board thermal resistance
21.4
°C/W
ψJT
Junction-to-top characterization parameter
0.6
°C/W
ψJB
Junction-to-board characterization parameter
20.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
Minimum and maximum limits are specified through test, design, or statistical correlation, and apply over the junction
temperature range at TJ = –40°C to 125°C. Typical values are provided for reference purposes only, and represent the most
likely parametric norm at TJ = 25°C. VIN = 12 V (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN (1)
TYP (2)
MAX (1)
1.256
1.27
1.282
VFB
Feedback voltage
Vcomp = 1.4 V
ΔVLINE
Feedback voltage line regulation
5 V ≤ VIN ≤ 18 V
Input undervoltage lockout voltage
Rising
Input undervoltage lockout hysteresis
Falling, below VUVLO
Nominal switching frequency
EN/MODE = 1.6 V
Low-side NMOS driver resistance,
top driver FET
VIN = 5 V, IDR = 0.2 A
3.4
Low-side NMOS driver resistance,
bottom driver FET
VIN = 5 V, IDR = 0.2 A
1
VUVLO
FSW
RDS(ON)
UNIT
V
0.33%
4.6
4.82
4.9
280
550
600
V
mV
635
kHz
Ω
VIN < 6 V
VIN
VIN ≥ 6 V
5.6
VCC
Driver voltage supply
Dmax
Maximum duty cycle
Tmin(on)
Minimum on-time
IQ-boost
Supply current in boost mode,
no switching
EN/MODE = 1.6 V, FB = 1.4 V
IQ-SD
Supply current in shutdown mode
EN/MODE pin = 0.4 V
IQ-pass
Supply current in pass-through mode
EN/MODE = 2.6 V, FB = 1.4 V
Ven-pass
Pass-through mode threshold (3)
Rising
2.19
Vmode-hyst
Mode change hysteresis, falling (3)
Falling
65
V
86%
125
(3)
ns
5.2
9
mA
0.025
1
µA
1.4
2.3
mA
2.4
2.56
V
107
165
V
V
Ven-shutdown
Shutdown mode threshold
Falling
0.2
0.4
0.59
Ven-boost
Boost mode enable window (3)
Rising
0.65
1.22
1.6
Ien
EN/MODE pin bias current (4)
EN/MODE = 1.6 V
VSENSE
Cycle-by-cycle current limit threshold
during boost mode
EN/MODE = 1.6 V, FB = 50 V
142
170
182
mV
ΔVSC
Short-circuit current limit threshold
during boost mode
EN/MODE = 1.6 V, FB = 0 V
18
30
42
mV
VSL
Internal ramp compensation voltage
VLIM1
Input current limit threshold voltage in
pass-through mode during TLIM1 (3)
EN/MODE = 2.6 V
70
85
95
mV
ΔVLIM2
Input current limit threshold voltage in
pass-through mode during TLIM2 (3)
EN/MODE = 2.6 V
14.5
18
21
mV
±1
90
(3)
TLIM1
Curent limit time at TLIM1
TLIM2
Current limit time at TLIM2 (3)
TSC
Current limit time at TSC (3)
µs
3.6
ms
900
µs
Rising threshold measured at FB pin with
respect to FB pin, VCOMP = 1.45 V
40
Lower-output overvoltage protection
threshold
Falling threshold measured at FB pin with
respect to FB pin, VCOMP = 1.45 V
26
VGS-on
On-state drive voltage at VG pin (5)
VIN = 5 V, ISEN = 5 V, IG = 0 A
VGS-off
Off-state drive voltage at VG pin (6)
Vin = 5 V, ISEN = VIN – 200 mV, IG = 0 A
IG
Maximum drive current at VG pin
VIN = 5 V, ISEN = 5 V, VG = VIN
Gm
Error amplifier transconductance
VCOM = 1.4 V, ICOMP = ±50 µA
(1)
(2)
(3)
(4)
(5)
(6)
mV
900
Upper-output overvoltage protection
threshold
VOVP
V
µA
mV
3.8
4.9
V
5
mV
20
340
522
µA
900
µA/V
All limits are specified at room temperature and at temperature extremes. All room temperatures are 100% production tested. All limits at
temperature extremes are specified through correlation using Statistical Quality Control (SQD) methods. All limits are used to calculate
Average Outgoing Quaity Level (AOQL).
Typical numbers are at 25°C and represent the most likely parametric norm.
See Device Functional Modes and Overvoltage Protection.
The bias current flowing through this pin is compensated and can flow either into or out-of this pin.
This is the gate-to-source voltage drive of Q2, when the controller turns on this FET.
This voltage is measured from the VG pin to AGND, when the controller fully turns off Q2.
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Electrical Characteristics (continued)
Minimum and maximum limits are specified through test, design, or statistical correlation, and apply over the junction
temperature range at TJ = –40°C to 125°C. Typical values are provided for reference purposes only, and represent the most
likely parametric norm at TJ = 25°C. VIN = 12 V (unless otherwise noted).
PARAMETER
TEST CONDITIONS
TYP (2)
MAX (1)
190
313
450
UNIT
AVOL
Error amplifier open-loop voltage gain
RO
Error amplifier open-loop output
resistance (7)
IEAO
Error amplifier output current swings
VEAO
Error amplifier output voltage limits
Tr
Drive pin rise time
Cload = 3 nF, VDR = 0 V to 3 V
25
ns
Tf
Drive pin fall time
Cload = 3 nF, VDR = 3 V to 0 V
25
ns
TSD
Thermal shutdown threshold
165
°C
TSD-hyst
Thermal shutdown threshold hysteresis
10
°C
(7)
6
VCOM = 1.2 V to 1.8 V, ICOMP = 0 A
MIN (1)
600
kΩ
Sourcing: VCOMP = 1.4 V, VFB = 1.1 V
27
66
115
Sinking: VCOMP = 1.4 V, VFB = 1.4 V
49
68
125
Upper: VFB = 0 V, COMP pin floating
Lower: VFB = 1.4 V
2.3
0.82
V/V
µA
V
This parameter is calculated from the error amplified Gm and AVOL, and is not tested.
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6.6 Typical Characteristics
VIN = 12 V, TJ = 25°C, and see Figure 16 (unless otherwise noted).
650
1.6
8V
12V
SUPPLY CURRENT (mA)
640
FREQUENCY (kHz)
630
620
610
600
590
580
570
-40°C
27°C
90°C
1.4
1.2
1.0
560
550
0.8
-60 -40 -20 0 20 40 60
TEMPERATURE (°C)
80 100
Figure 1. Switching Frequency vs Temperature
3.4
3.2
18
135
130
125
120
115
110
3.0
4
6
8
10 12 14
INPUT VOLTAGE (V)
16
18
-60 -40 -20 0 20 40 60
TEMPERATURE (°C)
TLIM1
TLIM2
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
-60 -40 -20 0 20 40 60
TEMPERATURE (°C)
80 100
Figure 5. Current Limit Timing vs Temperature
80 100
Figure 4. Minimum ON-Time vs Temperature
PASS FET GATE-SOURCE VOLTAGE (V)
Figure 3. Supply Current in Boost Mode (IQ-boost)
CURRENT LIMIT TIMING (ms)
16
140
3.6
4.5
8
10 12 14
INPUT VOLTAGE (v)
145
-40°C
27°C
90°C
3.8
5.0
6
Figure 2. Supply Current in Pass-Through Mode (IG-pass)
MINIMUM ON-TIME (ns)
SUPPLY CURRENT (mA)
4.0
4
6.5
-40°C
27°C
90°C
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
4
5
6
7 8 9 10 11 12 13 14
INPUT VOLTAGE (V)
Figure 6. Pass FET Drive Voltage vs Input Voltage (VGS-on)
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Typical Characteristics (continued)
VIN = 12 V, TJ = 25°C, and see Figure 16 (unless otherwise noted).
PASS FET GATE DRIVE CURRENT ( A)
35
6.2
VIN = 12V
-40°C
27°C
90°C
6.0
30
5.8
VCC (V)
25
20
5.6
5.4
5.2
15
5.0
10
4.8
-60 -40 -20 0 20 40 60
TEMPERATURE (°C)
80 100
2
Figure 7. Pass FET Drive Current vs Temperature
0.20
96
0.15
94
0.10
ûVOUT(%)
98
EFFICIENCY (%)
0.25
90
8Vin
10Vin
12Vin
0.05
0.00
-0.10
86
-0.15
84
8Vin
10Vin
12Vin
82
80
-0.20
-0.25
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
OUTPUT CURRENT (A)
= 15 V
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
OUTPUT CURRENT (A)
Figure 9. Efficiency
Figure 10. Load Regulation
0.25
0.1A output current
0.5A output current
1A output current
0.20
0.15
VO
5V/Div
0.10
ûVOUT(%)
5 6 7 8 9 10 11 12
INPUT VOLTAGE (V)
-0.05
88
VOUT
4
Figure 8. VCC Voltage vs Input Voltage
100
92
3
EN
500 mV/Div
0.05
0.00
-0.05
-0.10
IO
200 mA/Div
-0.15
-0.20
-0.25
8
9
10
11
INPUT VOLTAGE (V)
12
TIME (5 ms/DIV)
VIN = 8 V
Figure 12. Start-Up Waveforms
Figure 11. Line Regulation
8
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7 Detailed Description
7.1 Overview
The LM3017 uses a fixed frequency, Pulse Width Modulated (PWM), current mode control architecture. A highside current sense amplifier provides inductor current information by sensing the voltage drop across RSEN. The
voltage across this resistor is fed into the ISEN pin. This voltage is then level shifted and fed into the positive input
of the PWM comparator. As with all architectures of this type, a compensation ramp is required to ensure stability
of the current control loop under all operating conditions. A nominal value of the ramp is provided internally while
additional ramp can be added through the ISEN pin. The output voltage is sensed through an external feedback
resistor divider network and fed into the error amplifier (EA) negative input (feedback pin, FB). The output of the
error amplifier (COMP pin) is added to the slope compensation ramp and fed into the negative input of the PWM
comparator.
At the start of any switching cycle, the oscillator sets a high signal on the DR pin (gate of the external MOSFET)
and the external MOSFET turns on. When the voltage on the positive input of the PWM comparator exceeds the
negative input, the Drive Logic is reset and the external MOSFET turns off.
Under extremely light load or no-load conditions, the energy delivered to the output capacitor when the external
MOSFET is on during the minimum on time is more than what is delivered to the load. An overvoltage
comparator inside the LM3017 prevents the output voltage from rising under these conditions by sensing the
feedback (FB pin) voltage and resetting the RS latch. The latch remains in a reset state until the output decays to
the nominal value. Thus the operating frequency decreases at light loads, resulting in excellent efficiency.
7.2 Functional Block Diagram
VG
ISEN
VIN
Ramp Adjust
-
+
200 mV
+
Pass
Control
Current
Sense
Amp.
-
A
Internal
Reg
Short-circuit
Comparator
+
Limit
References
Charge
Pump
VCC
Limit
-
Level
Shifter
1.27V
Reference
Soft
Start
+
-
Drive
Logic
+
PWM
-
DR
+
E.A.
-
EN/MODE
Logic
Internal Slope
Compensation
OSC
OVP
FB
EN/MODE
COMP
AGND
PGND
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7.3 Feature Description
7.3.1 True Shutdown
The LM3017 incorporates circuitry to control a high side NMOS transistor in series with the inductor. This feature
is used to disconnect the load from the input supply and protect the system from shorts on the output. Using an
NMOS, rather than a PMOS transistor, saves the use of a diode from the inductor to ground. When the NMOS is
turned off, the inductor brings the source belowground, keeping it on until the current is safely brought to zero. A
built-in charge pump supplies typically VIN+ 5 V to drive the gate of this NMOS.
7.3.2 Operation of the EN/MODE Pin
The EN/MODE pin is used to control the modes of the regulator by driving the high side gate (VG pin) to enable
or disable the output through the pass MOSFET. Furthermore, it defines the current limit for each operation
mode (see Device Functional Modes). Table 1 shows the modes versus the voltage on the EN/MODE pin.
Table 1. EN/MODE Voltage
EN/MODE PIN VOLTAGE
MODE
≤ 0.4 V
Shutdown
1.6 V to 2.2 V
Boost
≥ 2.6 V
Pass-through
Figure 13 shows the output voltage behavior in the various operation modes.
7.3.3 EN/MODE Control
As stated previously, the EN/MODE pin controls the state of the LM3017. As with any digital input, the voltage on
this pin must not be allowed to slowly cross the various thresholds. Although hysteresis is used on this input,
slowly varying signal may cause unpredictable behavior. Also, the EN/MODE pin must not be allowed to float.
One way to control the LM3017, from digital logic, is to use the circuit shown in Figure 14. The resistor values
are adjusted based on the above table and the logic supply used. The MOSFET can be any small signal device,
such as the 2N7002.
10
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EN/MODE
> 2.6V
1.6V < EN/MODE 450 µs the pass FET is latched off. In this way, the current is limited to VSC / Rsen until the short is removed
or the time of TSC = 450 µs is completed. Pulling the EN/MODE pin low (< 0.4 V, typical) is required to reset this
short-circuit latch-off mode. The delay of TSC = 450 µs helps to prevent nuisance latch-off during a momentary
short on the output.
7.4 Device Functional Modes
7.4.1 Shutdown Mode
Pulling the EN/MODE pin to less than 0.4 V (typical), during any mode of operation, places the part in full
shutdown mode. The boost regulator and the pass FET is off and the load is disconnected from the input supply.
In this mode, the regulator draws a maximum of 1 µA from the input supply.
7.4.2 Boost Mode
The boost regulator can be turned on by bringing the EN/MODE pin to greater than 1.6 V, but less than 2.2 V.
This is the run mode for the boost regulator. Note that the LM3017 always starts in pass-through and transitions
to boost mode.
7.4.3 Standby Mode
Setting the EN/MODE pin to greater than 2.6 V (typical), places the part in pass-through mode. The boost
regulator is off and the pass MOSFET is on. During this mode, the load is connected to the input supply through
the inductor and power diode, and is fully protected from output short circuits.
7.4.4 Start-Up Boost Mode
During start-up in boost mode, peak inductor current may be higher compared to normal operation. To allow for
this, current limit levels and timing are different during start-up. The current limit is defined by VLIM2 = 100 mV
(typical) in Electrical Characteristics, for the first TLIM2 = 3.6 ms (typical). The current is limited to VLIM2 / RSEN, for
this period. Once the TLIM2 = 3.6 ms (typical) timer has finished, the current limit is increased to VSC = 200 mV
(typical). For the first TLIM2 = 3.6 ms (typical) of the start-up, the latch-off feature is not enabled; however, the
current is always limited to VLIM2 / RSEN. This allows the part to start up normally. If the current limit is still tripped
at the end of TLIM2 = 3.6 ms (typical) , the TSC = 900 µs (typical) timer is started. Once the TSC = 900 µs (typical)
time has expired, the pass FET (Q2) is latched off. This gives a total current-limited time of TSC + TLIM2 = 4.05 ms
(typical), in cases where the LM3017 is started into a short circuit at the output.
7.4.5 Pass-Through Mode
In pass-through mode the power path is protected from shorts and overloads by the current limit defined as
VLIM1 = 85 mV (typical) in Electrical Characteristics. When this current limit is tripped, the current is limited to
VLIM1 / RSEN by controlling the pass FET. If the short persists for TLIM1 > 900 µs (typical) the pass FET (Q2) is
latched off. In this way, the current is limited to VLIM1 / RSEN until the short is removed or the time of
TLIM1 = 900 µs (typical) is completed. Pulling the EN/MODE pin low (0.4 V, typical) is required to reset this latchoff mode.
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Device Functional Modes (continued)
7.4.6 Start-Up Pass-Through Mode
During start-up in pass mode, the current limit is defined by VLIM2 = 100 mV (typical) in Electrical Characteristics,
for the first TLIM2 = 3.6 ms (typical). The current is limited to VLIM2 / RSEN, for this period. Once the TLIM2 = 3.6 ms
(typical) timer has finished, the current limit is reduced to VLIM1 = 85 mV (typical). For the first TLIM2 = 3.6 ms
(typical) of the start-up, the latch-off feature is not enabled; however, the current is always limited to VLIM2 / RSEN.
This higher limit allows the part to start up normally. If the current limit is still tripped at the end of TLIM2 = 3.6 ms
(typical), the TLIM1 = 900 µs (typical) timer is started. Once the TLIM1= 900 µs time has expired, the pass FET(Q2)
is latched off. This gives a total current-limited time of TLIM1+ TLIM2 = 4.5 ms (typical), in cases where the LM3017
is started into a short circuit at the output.
Figure 15. Current Limit and Short-Circuit Protection
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LM3017 may be operated in either continuous or discontinuous conduction mode. The following descriptions
assume continuous conduction operation (CCM). This mode of operation has higher efficiency and lower EMI
characteristics than the discontinuous mode.
8.2 Typical Application
VIN = 8V to 12V
L1
RSEN
D1
Q2
VOUT = 15V@1A
RS
EN/MODE
U1
ISEN
RFBT
VG
EN/MODE
CIN1
VIN
CO1
Q1
DR
CO2
CO3
VCC LM3017
COMP
CBYP
CVCC
CCOMP2
RCOMP
PGND
FB
AGND
RFBB
CCOMP
GND
GND
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Figure 16. 1-A High Efficiency Step-Up (Boost) Converter
8.2.1 Design Requirements
To properly size the components for the application, the designer requires the following parameters: Input
voltage range, output voltage, output current, and switching frequency. These four main parameters affect the
choices of component available to achieve a proper system behavior.
Table 2 lists the design parameters for this application example.
Table 2. Design Parameters
PARAMETER
VALUE
Input voltage, VIN
8 V to 12 V
Output voltage, VOUT
15 V
Output current, IOUT
1A
Switching frequency, fS
600 kHz
8.2.2 Detailed Design Procedure
The most common topology for the LM3017 is the boost or step-up topology. The boost converter converts a low
input voltage into a higher output voltage. The basic configuration for a boost regulator is shown in Figure 17. In
continuous conduction mode (when the inductor current never reaches zero at steady state), the boost regulator
operates in two cycles. In the first cycle of operation, MOSFET Q is turned on and energy is stored in the
inductor. During this cycle, diode D1 is reverse biased and load current is supplied by the output capacitor,
COUT.
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In the second cycle, MOSFET Q is off and the diode is forward biased. The energy stored in the inductor is
transferred to the load and output capacitor. The ratio of these two cycles determines the output voltage. The
output voltage is defined with Equation 1.
V
V
VOUT = IN ; D = 1 - IN
1- D
VOUT
(1)
Including the voltage drop of the diode in Equation 2.
V
- VIN + VD1
V
VOUT +VD1 = IN ; D = OUT
1- D
VOUT + VD1
where
•
•
D is the duty cycle of the switch
VD1 is the forward voltage drop of the diode
(2)
The following sections describe selection of components for a boost converter.
L
VIN
D1
+
+
Q
PWM
(a)
L
VOUT
COUT
VOUT
+
+
COUT
-
VIN
+
RLOAD
-
(b)
L
+
-
VIN
D1
VOUT
+
COUT
+
RLOAD
-
Figure 17. 4 Simplified Boost Converter Diagram
(a) First Cycle of Operation, (b) Second Cycle of Operation
8.2.2.1 Programming the Output Voltage
The output voltage can be programmed using a resistor divider between the output and the feedback pins, as
shown in Figure 20. The resistors are selected such that the voltage at the feedback pin is equal to VFB (see
Electrical Characteristics). RFBT and RFBB can be selected using Equation 3.
æ R
VOUT = VFB ´ ç 1 + FBT
ç R
FBB
è
ö
÷
÷
ø
(3)
25
MAXIMUM OUTPUT VOLTAGE (V)
MAXIMUM OUTPUT VOLTAGE (V)
140
120
100
80
60
40
20
20
15
10
5
5 6
7
8
9 10 11 12 13 14 15 16 17 18
5 6
INPUT VOLTAGE (V)
7
8
9 10 11 12 13 14 15 16 17 18
INPUT VOLTAGE (V)
Figure 18. Maximum Output Voltage
Figure 19. Minimum Output Voltage
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Figure 18 shows maximum regulated output voltage based on maximum duty cycle value of 85% and by
assuming a voltage drop on the output diode of 0.5 V and 90% efficiency. Figure 19 shows the minimum
regulated output voltage, the calculation is based on minimum on time of 126 ns (typical) that generates a
minimum duty cycle equal to Equation 4.
DMIN = tON(min) × fS = 0.076
where
•
fS is the switching frequency and it's equal to 600 kHz and by assuming 90% efficiency
(4)
8.2.2.2 Power Inductor Selection
The inductor is one of the two energy storage elements in a boost converter.
Choose the minimum IOUT to determine the minimum inductance L. A common choice is to set (2 x ΔiL) from 30%
to 50% of IL. Choosing an appropriate core size for the inductor involves calculating the average and peak
currents expected through the inductor. In a boost converter the inductor current IL, the peak of the inductor
current and the inductor current ripple ΔiL are equal to Equation 5.
I
IL = OUT
1- D
ILpeak = IL (max) + DiL (max)
D ´ VIN
DiL =
2 ´ L ´ fS
(5)
The inductance used is a tradeoff between size and cost. Larger inductance means lower input ripple current;
however, because the inductor is connected to the output during the off-time only, there is a limit to the reduction
in output voltage ripple. Lower inductance results in smaller, less expensive magnetics.
All the analysis in this data sheet assumes operation in continuous conduction mode. To operate in continuous
conduction mode, the conditions in Equation 6 must be met.
IL = DiL
IOUT
D ´ VIN
=
1 - D 2 ´ fS ´ L
L³
(1 - D )´ D ´ VIN
2 ´ fS ´ IOUT
(6)
A core size with ratings higher than these values must be chosen. If the core is not properly rated, saturation
dramatically reduces overall efficiency or damage the power stage. Choose an inductor with a saturation current
value higher than ILpeak. The LM3017 senses the peak current through the switch. The peak current through the
switch is the same as the peak current calculated in the previous equation.
Losses due to DCR of the inductance can be easily calculated with Equation 7.
2
éæ I
Di2 ù
ö
PL = DCR ´ êç OUT ÷ + L ú
12 ú
êè 1 - D ø
ë
û
(7)
No core losses are considered.
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8.2.2.3 Setting the Output Current
The maximum amount of current that can be delivered at the output can be controlled by the sense resistor,
RSEN. Current limit occurs when the voltage that is generated across the sense resistor equals the current sense
threshold voltage, VSENSE. Limits for VSENSE are specified in Electrical Characteristics. This is expressed with
Equation 8.
Isw(peak) × RSEN = VSENSE
(8)
The peak current through the switch is equal to the peak inductor current in Equation 9.
Isw(peak) = IL(max) + ΔiL
(9)
Therefore for a boost converter in Equation 10.
I
D ´ VIN
= OUT +
ISW
peak
1 - D 2 ´ fS ´ L
(10)
Combining the two equations yields an expression for RSEN and includes a 20% margin on the peak of the
switching current with Equation 11.
VSENSE
RSEN =
æI
D ´ VIN ö
1.2 ´ ç OUT +
÷
è 1 - D 2 ´ fS ´ L ø
(11)
Evaluate RSEN at the maximum and minimum VIN values and choose the smallest RSEN calculated.
VIN
RSEN
L1
Q2
D1
VOUT
+
ISEN
VG
DR
Q1
COUT
RFBT
LM3017
FB
RFBB
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Figure 20. Adjusting the Output Voltage
8.2.2.4 Additional Slope Compensation
It is good design practice to only add as much slope compensation as required to avoid instability. Additional
slope compensation (see Figure 24) minimizes the influence of the sensed current in the control loop. With very
large slope compensation the control loop characteristics are similar to a voltage mode regulator which compares
the error voltage to a saw tooth waveform rather than the inductor current. It is possible to calculate the minimum
value of RS to meet Equation 12.
MC > M2/2
(12)
Hence Equation 13,
RS ³
ù
1 é RSEN ´ (VOUT - VIN (min) )
´ê
- VSL ú
K ëê
2 ´ L ´ fS
ûú
where
•
K = 40 µA
(13)
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If the result of the previous equation is negative, it means that no additional slope compensation is required. TI
recommends a 100-Ω resistor.
8.2.2.5 Current Limit With Additional Slope Compensation
If an external slope compensation resistor is used, then the internal control signal is modified and this has an
effect on the current limit.
If RS is used, then this adds to the existing slope compensation. The command voltage, VCS, is then given by
Equation 14.
VCS = VSL + ΔVSL
where
•
•
•
VSENSE is a defined parameter in Electrical Characteristics
VSL is the amplitude of the internal compensation ramp
ΔVSL = RS x K is the additional slope compensation generated
(14)
This changes the equation for RSEN to Equation 15.
V
- D ´ VCS
RSEN = SENSE
æ IOUT
D ´ VIN ö
+
ç
÷
è 1 - D 2 ´ fS ´ L ø
(15)
Because ΔVSL = RS × K as defined earlier, RS can be used to provide an additional method for setting the current
limit. In some designs RS can also be used to help filter noise to keep the ISEN pin quiet. Dissipation due to RSEN
resistor is equal to Equation 16.
2
2 ù
éæ I
DiLpp
ö
ú
PSEN = RSEN ´ êç OUT ÷ +
12 ú
êè 1 - D ø
ë
û
(16)
8.2.2.6 Power Diode Selection
Observation of the boost converter circuit shows that the average current through the diode is the average output
current, and the peak current through the diode is the peak current through the inductor. The peak diode current
can be calculated using Equation 17.
ID(Peak) = [IOUT / (1 − D)] + ΔiL
(17)
The peak reverse voltage for a boost converter is equal to the regulator output voltage. The diode must be
capable of handling this peak reverse voltage as well as the output rms current. To improve efficiency, TI
recommends a low forward drop Schottky diode due to low forward drop and near-zero reverse recovery time.
The overall efficiency becomes more dependent on the selection of D at low duty cycles, where the boost diode
carries the load current for an increasing percentage of the time. This power dissipation can be calculated by
checking the typical diode forward voltage VD, from the I-V curve on the diode's datasheet and the multiplying it
by IO. Diode data sheets also provides a typical junction-to-ambient thermal resistance, RθJA, which can be used
to estimate the operating die temperature of the Schottky. Multiplying the power dissipation (PD = IO × VD) by
RθJA gives the temperature rise. The diode case size can then be selected to maintain the Schottky diode
temperature below the operational maximum.
8.2.2.7 Low-Side MOSFET Selection (Switching MOSFET)
The drive pin, DR, of the LM3017 must be connected to the gate of an external MOSFET. In a boost topology,
the drain of the external N-Channel MOSFET is connected to the inductor and the source is connected to the
ground. The drive pin voltage, VDR, depends on the input voltage (see Typical Characteristics).
The selected MOSFET directly affects the efficiency. The critical parameters for selection of a MOSFET are:
1. Minimum threshold voltage, VTH(MIN)
2. On-resistance, RDS(ON)
3. Total gate charge, Qg
4. Reverse transfer capacitance, CRSS
5. Maximum drain to source voltage, VDS(MAX)
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The off-state voltage of the MOSFET is approximately equal to the output voltage. VDS(MAX) of the MOSFET must
be greater than the output voltage plus the voltage drop across the output diode (20% margin recommended).
The power losses in the MOSFET can be categorized into conduction losses, gate charging losses and switching
losses. RDS(ON) is required to estimate the conduction losses. The conduction loss, PCOND, is the I2R loss across
the MOSFET. The maximum conduction loss is given by Equation 18 and Equation 19.
2
æ I
ö
PCOND = ç OUT ÷ ´ DMAX ´ RDS(on)
è 1 - DMAX ø
where
•
DMAX is the maximum duty cycle
DMAX = 1 -
(18)
VIN (min)
VOUT
(19)
To consider the increase in MOSFET on resistance due to heating, a factor of 1.3 is introduced, hence
Equation 20.
PCOND_real = PCOND(max) × 1.3
(20)
Gate charging loss, PG, results from the current required to charge and discharge the gate capacitance of the
power MOSFET and is approximated with Equation 21.
PG = VCC × QG fS
(21)
QG is the total gate charge of the MOSFET. Gate charge loss differs from conduction and switching losses
because the actual dissipation occurs in the LM3017 and not in the MOSFET itself. This loss, PVCC, is estimated
with Equation 22.
PVCC = (VIN – VCC) × QG × fS
(22)
The switching losses are very difficult to calculate due to changing parasitics of a given MOSFET in operation.
Often, the individual MOSFET datasheet does not give enough information to yield a useful result. The following
formulas give a rough idea how the switching losses are calculated with Equation 23.
I ´ VOUT
´ fS ´ (tLH + tHL )
PSW = L
2
where
•
tLH and tHL are rise and fall times of the MOSFET
(23)
8.2.2.8 Pass MOSFET Selection (High-Side MOSFET)
The VG pin drives the gate of the high side MOSFET (Pass FET Q2). This requires special considerations. When
the output is shorted, this FET must sustain the full input voltage and the short-circuit current simultaneously.
This is due to the fact that the controller regulates the short-circuit current in a quasi-linear manner, through Q2.
This power pulse only lasts for TLIM2 or TSC, depending on the operational mode. Therefore, the designer must
carefully examine the SOA curve for the desired FET before committing to the design. Equation 24 and
Equation 25 give the maximum energy pulses that Q2 is required to survive.
æV
ö
E1 ³ (Vin + 2 )´ ç LIM2 ÷ ´ TLIM2
è Rsen ø
(24)
æV ö
E2 ³ (Vin + 2 )´ ç SC ÷ ´ TSC
è Rsen ø
(25)
These two energy points must fall within the SOA of the selected FET. In addition, Q2 must have a low threshold
voltage and low RDS(on) for high efficiency. Power dissipation during boost mode is given by Equation 26.
2
2 ù
éæ I
DiLpp
ö
ú
PQ2 = RDS(on) ´ êç OUT ÷ +
12 ú
êè 1 - D ø
ë
û
(26)
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8.2.2.9 Input Capacitor Selection
Due to the presence of an inductor at the input of a boost converter, the input current waveform is continuous
and triangular. The inductor ensures that the input capacitor sees fairly low ripple currents. However, as the input
capacitor gets smaller, the input ripple goes up. The rms current in the input capacitor is given by Equation 27.
ICIN (rms) =
DiL
3
=
(VOUT - VIN )´ VIN
12 ´ VOUT ´ fS
(27)
The input capacitor must be capable of handling this rms current. Although the input capacitor is not as critical in
a boost application, low values can cause impedance interactions. Therefore, a good quality capacitor must be
chosen in the range of 10 µF to 20 µF. Furthermore, TI recommends a low-ESR, 0.1-µF ceramic bypass
capacitor to avoid transients and ringing due to parasitics. Bypass capacitors must be placed as close as
possible to the VIN pin and grounded close to the GND pin on the IC to minimize additional ESR and ESL.
Equation 28 can be used to define the input voltage ripple.
æ
ö
1
DVipp = DiLPP ´ ESR2 + ç
÷
´
´
8
f
C
S
i ø
è
2
where
•
•
ΔiLpp = 2 × ΔiL is the peak-to-peak inductor current ripple
ΔVipp is the peak-to-peak input voltage ripple
(28)
Many times it is necessary to use an electrolytic capacitor on the input in parallel with the ceramics. The ESR of
this capacitor can help to damp any ringing on the input supply caused by long power leads.
8.2.2.10 Output Capacitor Selection
The output capacitor in a boost converter provides all the output current when the inductor is charging and it
determines the steady state output voltage ripple ΔVOpp. As a result it sees very large ripple currents. The output
capacitor must be selected based on its capacitance CO, its equivalent series resistance ESR and its RMS
current rating. The rms current in the output capacitor is calculated with Equation 29.
é
DiL2 úù
D
2
IC OUT (rms) = (1 - D) ´ êIOUT
´
+
ê
(1 - D )2 3 úû
ë
where
•
•
ΔiL is the inductor ripple current
D is the duty cycle
(29)
The magnitude of the output voltage ripple during the on-time is equal to the ripple voltage during the off-time
and it is composed of two parts. For simplicity, the analysis is performed for off-time only.
The first part of the ripple voltage is the surge created as the output diode D turns on. At this point inductor or
diode current is at the peak value, and the ripple voltage increase can be calculated with Equation 30.
ΔVO1 = IPK × ESR
where
•
IPK = IOUT / (1 − D)
(30)
The second portion of the ripple voltage is the increase due to the charging of CO through the output diode. This
portion can be approximated with Equation 31.
ΔVO2 = (IO / CO) × (D / fS)
(31)
Equation 32 can be used to define the output voltage ripple.
´D
æI
ö I
DVOpp = ESR ´ ç OUT + DiL ÷ + OUT
1
D
C
´
è
ø
o fS
20
(32)
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The ESR of the output capacitor(s) has a strong influence on the slope and direction of the output voltage ripple.
Capacitors with high ESR such as tantalum and aluminum electrolytic create an output voltage ripple that is
dominated by ΔVO1 with a shape shown in Figure 21. Ceramic capacitors, in contrast, have a very low ESR and
lower capacitance, and the shape of the output voltage ripple is dominated by ΔVO2 with a shape shown in
Figure 22.
PsOpp
VOUT
VOUT
PsOpp
ID
ID
Figure 21. ΔVOpp Using High ESR Capacitors
Figure 22. ΔVOpp Using Low ESR Capacitors
Ceramic capacitors are recommended with a typical value from 10 µF to 100 µF. The minimum quality dielectric
that is suitable for switching power supply output capacitors is X5R, while X7R (or better) is preferred. Careful
attention must be paid to the DC voltage rating and case size, as ceramic capacitors can lose 60% or more of
their rated capacitance at the maximum DC voltage. This is the reason that ceramic capacitors often derate to
50% of their capacitance at their working voltage.
8.2.2.11 VCC Decoupling Capacitor
The internal bias of the LM3017 comes from either the internal bias voltage generator as shown in the block
diagram or directly from the voltage at the VIN pin. At input voltages lower than 6 V, the internal IC bias is the
input voltage and at voltages above 6 V the internal bias voltage generator of the LM3017 provides the bias. A
good quality ceramic bypass capacitor must be connected from the VCC pin to the PGND pin for proper
operation. This capacitor supplies the transient current required by the internal MOSFET driver, as well as
filtering the internal supply voltage for the controller. TI recommends a value of between 0.47 µF and 4.7 µF.
8.2.2.12 Slope Compensation Ramp
The LM3017 uses a current mode control scheme. The main advantages of current mode control are inherent
cycle-by-cycle current limit for the switch, simpler control loop characteristics and excellent line and load transient
response. However, there is a natural instability due to subharmornic oscillations that occurs for duty cycles, D,
greater than 50% if slope compensation is not addressed in Equation 33.
MC > M2 / 2
(33)
For best input noise immunity, use Equation 34.
MC = M2
(34)
For best sub-harmonic suppression, use Equation 35.
MC = M2 / 2
where
•
•
•
•
•
•
•
MC is the slope of the compensation ramp
M1 is the slope of the inductor current during the ON time
M2 is the slope of the inductor current during the OFF time
RSEN is the sensing resistor value
VOUT represents the output voltage
VIN represents the input voltage
A is equal to 0.86 and it is the internal sensing amplification of the LM3017
(35)
In the case of the boost topology, use Equation 36 and Equation 37.
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M1 = [VIN / L] × RSEN × A
M2 = [(VOUT – VIN) / L] × RSEN × A
(36)
(37)
The compensation ramp is added internally in the LM3017. The slope of this compensation ramp is selected to
satisfy most applications, and its value depends on the switching frequency. This slope can be calculated using
Equation 38.
MC = VSL × fS
(38)
In the above equation, VSL is the amplitude of the internal compensation ramp and fS is the controller's switching
frequency. Limits for VSL are specified in Electrical Characteristics.
To provide the user additional flexibility, a patented scheme is implemented inside the IC to increase the slope of
the compensation ramp externally, if the requirement arises. Adding a single external resistor, RS (as shown in
Figure 24) increases the amplitude of the compensation ramp as shown in Figure 23 where Equation 39.
Control Signal
Compensation Ramp
with RSL
Control Signal
Compensation Ramp
without RSL
'VSL
-MC
VSL
Figure 23. Additional Slope Compensation Added Using External Resistor RS
ΔVSL = K × Rs
where
•
K = 40 µA typically and changes slightly as the switching frequency changes
(39)
A more general equation for the slope compensation ramp, MC, is shown in Equation 40 to include ΔVSL caused
by the resistor, Rs.
MC = (VSL + ΔVSL) × fs
(40)
VIN
L1
Q2
RSEN
CS
RS
ISEN
VG
DR
LM3017
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Figure 24. Increasing the Slope of the Compensation Ramp
An additional capacitor, CS, could be added if the sensing signal generated by RSEN is very noisy (parasitic circuit
capacitance, inductance, and gate drive current create a spike in the current sense voltage at the point where Q1
turns on). The time constant RSEN x CS must be long enough to reduce the parasitics spike without significantly
affecting the shape of the actual current sense voltage (a typical range is from 100 pF to 2.2 nF).
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8.2.2.13 Control Loop Compensation
The LM3017 uses peak current-mode PWM control to correct changes in output voltage due to line and load
transients. Peak current-mode provides inherent cycle-by-cycle current limiting, improved line transient response,
and easier control loop compensation. The control loop is comprised of two parts. The first is the power stage,
which consists of the pulse width modulator, output filter, and the load. The second part is the error amplifier.
Figure 25 shows the regulator control loop components.
L
RSEN
+
D
VIN
CO
RO
+
ESR
RFBT
-
+
A
+
-
Current
Sense
Amp.
+
CCOMP
CCOMP2
RFBB
+ V
REF
-
RCOMP
Figure 25. Power Stage and Error Amp
The power stage in a CCM peak current mode boost converter consists of the DC gain, GVC0, a single low
frequency pole, fP, the ESR zero, fZ, a right-half plane zero, fR, and a double pole resulting from the sampling of
the peak current. The power stage transfer function (also called the Control-to-Output transfer function) can be
written with Equation 41.
æ
s öæ
s ö
ç1 ÷ ç1 +
÷
w
w
R øè
Z ø
GVC (s) = GVC0 ´ è
æ
s öæ
s
s2
+ 2
ç1 +
÷ çç 1 +
wP ø è
wn wn
è
ö
÷
÷
ø
(41)
The DC gain is defined with Equation 42.
RO (1 - D)
GVC0 =
2 ´ A ´ RSEN
where
•
RO = VOUT / IOUT
(42)
In the equation for GVC0, DC gain is highest when input voltage and output current are at the maximum. The
system ESR zero is defined with Equation 43.
wZ
1
=
fZ =
2p 2p ´ CO ´ ESR
(43)
The low frequency pole is Equation 44.
w
2
fP = P =
2p 2p ´ CO ´ (ESR + RO )
(44)
The right-half plane zero is Equation 45.
2
RO ´ (1 - D )
w
fR = R =
2p
2p ´ L
(45)
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The sampling double pole quality factor is Equation 46.
1
Qn =
é
ù
æ M ö
p ´ ê(1 - D )´ ç 1 + C ÷ - 0.5 ú
M1 ø
è
ëê
ûú
(46)
The sampling double corner frequency is Equation 47.
ωn = π × fS
(47)
The natural inductor current slope is Equation 48.
M1 = RSEN × VIN / L
(48)
The external ramp slope is Equation 49.
MC = (VSL + ΔVSL) × fS
(49)
A step-up converter produces an undesirable right-half plane zero in the regulation feedback loop. This requires
compensating the regulator such that the crossover frequency occurs well below the frequency of the right-half
plane zero
8.2.2.13.1 Compensation Network Components Calculations
As shown in Figure 25, the LM3017 uses a compensation network base on a transconductance amplifier. The
closed-loop transfer function is defined with Equation 50 through Equation 54.
T(s) = GVA(s) × GVC(s)
where
•
GVA(s) is the transfer function implemented by the compensation network
(50)
æ
s ö
wP1 ç 1 +
÷
wZ1 ø
è
GVA (s) =
æ
s ö
s ç1 +
÷
wP2 ø
è
(51)
1
=
CCOMP ´ RCOMP
(52)
RFBB
Gm ´
RFBB + RFBT
=
CCOMP + CCOMP2
(53)
CCOMP + CCOMP2
=
CCOMP ´ CCOMP2 ´ RCOMP
(54)
wZ1
wP1
wP2
To stabilize the regulator, ensure that the regulator crossover frequency is less than or equal to one-fifth of the
right-half plane zero with Equation 55.
f
fC £ R
5
(55)
To determine the crossover frequency it is important to note that, at that frequency, the compensation impedance
(ZCOMP) is dominated by a resistor, and the output impedance (ZOUT) is dominated by the impedance of an output
capacitor. Therefore, when solving for the crossover frequency, the equation (by definition of the crossover
frequency) of the loop gain is simplified to Equation 56.
V
V
1
1
| T |= FB ´ IN ´ Gm ´
´ RCOMP ´
=1
VOUT VOUT
2p ´ fC ´ CO
A ´ RSEN
where
•
•
•
•
24
|T| is the loop gain magnitude
VFB is feedback voltage, 1.275 V
VOUT is the output voltage
VIN is the input voltage
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•
•
•
•
•
Gm is the error amplifier transconductance
ZCOMP is the impedance of the compensation network from the COMP pin to ground
RSEN is the current sensing resistor
A is equal to 0.86 and it is the internal sensing amplification of the LM3017
CO is the output capacitor value
(56)
Solve for RCOMP with Equation 57.
RCOMP =
2
2p ´ fC ´ CO ´ VOUT
´ A ´ RSEN
VFB ´ VIN ´ Gm
(57)
Once the compensation resistor is known, set the zero formed by the compensation capacitor and resistor to
one-fourth of the crossover frequency in Equation 58.
2
CCOMP =
p ´ fC ´ RCOMP
where
•
CCOMP is the compensation capacitor
(58)
The high-frequency capacitor CCOMP2, is chosen to cancel the zero introduced by output capacitance ESR with
Equation 59.
ESR ´ CO
CCOMP2 =
RCOMP
(59)
For optimal transient performance, RCOMP and CCOMP might require adjustment by observing the load transient
response.
For detailed explanation on how to select the right compensation components for a boost topology, see AN-1286
Compensation for the LM3478 Boost Controller (SNVA067), and AN-1994 Modeling and Design of Current Mode
Control Boost Converters (SNVA408).
8.2.2.13.2 Compensation Design Example
Table 3 lists the design parameters for this application example to calculate the compensation network.
Table 3. Design Parameters
PARAMETER
VALUE
Input voltage, VIN
8 V to 12 V
Output voltage, VOUT
15 V
Output current, IOUT
1A
Switching frequency, fS
600 kHz
Duty cycle, D
(considering losses)
0.223 with VIN = 12 V
Right-half plane zero, fR
0.482 with VIN = 8 V
136.187 kHz when VIN = 8 V
206.421 kHz when VIN = 12 V
Inductor, L
4.7 µH
Output capacitance, CO
(considering derating due to
applied voltage)
33 µF
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space
VIN = 8 V, VOUT = 15 V, IOUT = 1 A
Figure 26. Control-to-Output Transfer Function
GVC(s) Bode Plot
Choose the crossover frequency with Equation 60.
fC = 20 kHz = fS / 20 fR / 5
(60)
Table 4. Calculated Compensation Network Components
PARAMETER
CALCULATED VALUE
ACTUAL VALUE
RCOMP
3.42 kΩ
3.4 kΩ
CCOMP
9.306 nF
10 nF
CCOMP2
96.48 pF
100 pF
space
VIN = 8 V, VOUT = 15 V, IOUT = 1 A
VIN = 8 V, VOUT = 15 V, IOUT = 1 A
Figure 27. GVC(s) and Compensation Network
GVA(s) Bode Plots
Figure 28. Closed-Loop Bode Plot T(s)
Table 5. Bill of Materials (BOM) for LM3017
DESIGNATION
DESCRIPTION
SIZE
MANUFACTURER PART #
VENDOR
CIN1
Cap 22 µF, 25 V X5R
1206
GRM31CR61E226KE15L
Murata
CO1,CO2, CO3
Cap 22 µF, 25 V X5R
1206
GRM31CR61E226KE15L
Murata
CCOMP
Cap 0.022 µF
0603
C0603C103J1RACTU
Kemet
CCOMP2
Cap 1000 pF
0603
C1608C0G1H101J
TDK
CBYP
Cap 0.1 µF, 25 V X7R
0603
06033C104KAT2A
AVX
CVCC
Cap 0.47 µF, 16 V X7R
0805
C2012X7R1C474K
TDK
RCOMP
RES, 3.4 kΩ, 1%, 0.1W
0603
CRCW06033K40FKEA
Vishay
26
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Table 5. Bill of Materials (BOM) for LM3017 (continued)
DESIGNATION
DESCRIPTION
SIZE
MANUFACTURER PART #
VENDOR
RFBT
RES, 21.5 kΩ, 1%, 0.1W
0603
CRCW060321K5FKEA
Vishay
RFBB
RES, 2 kΩ, 1%, 0.1W
0603
CRCW06032K00FKEA
Vishay
RS
RES, 100 Ω, 1%, 0.1W
0603
CRCW0603100RFKEA
Vishay
RSEN
RES, 0.03 Ω, 1%, 1W
1206
WSLP1206R0300FEA
Vishay
Q1
NexFET™ N-CH, 25 V, 60 A, RDS(on)= 4.4 mΩ
8-SON
CSD16323Q3
TI
Q2
NexFET™ N-CH, 25 V, 60 A, RDS(on)= 4.3 mΩ
8-SON
CSD16340Q3
TI
D1
Diode Schottky, 30 V, 2 A
SMB
20BQ030TRPBF
Vishay
L1
Shielded Inductor, 4.7 µH, 2.3 A
4 mm L × 4 mm W × 1.85 mm H
MPI4040R3-4R7-R
Cooper
U1
LM3017
—
—
TI
8.2.3 Application Curve
Figure 29. Switch Node and Output Voltage Ripple
With 5.5 VIN and 15 V at 1-A Output
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9 Power Supply Recommendations
The LM3017 is designed to operate from an input voltage supply range from 5 V to 18 V. This input supply must
be able to withstand the maximum input current and maintain a voltage above 5 V. In cases where input supply
is placed farther away (more than a few inches) from LM3017, additional bulk capacitance may be required in
addition to the ceramic bypass capacitors.
10 Layout
10.1 Layout Guidelines
Good board layout is critical for switching controllers such as the LM3017. First the ground plane area must be
sufficient for thermal dissipation purposes and second, appropriate guidelines must be followed to reduce the
effects of switching noise. Switch mode converters are very fast switching devices. In such devices, the rapid
increase of input current combined with the parasitic trace inductance generates unwanted voltage noise spikes.
The magnitude of this noise tends to increase as the output current increases. This parasitic spike noise may
create electromagnetic interference (EMI), and can also cause problems in device performance. Therefore, take
care in layout to minimize the effect of this switching noise.
10.1.1 Filter Capacitors
Ceramic filter capacitors are most effective when the inductance of the current loops that they filter is minimized.
Place CBYP as close as possible to the VIN and GND pins of the LM3017. Place CVCC next to the VCC and GND
pins of the LM3017 (see Figure 16 for designators).
10.1.2 Sense Lines
The current sensing circuit in current mode devices can be easily effected by switching noise. This noise can
cause duty cycle jitter which leads to increased spectral noise. RSEN must be connected to the ISEN pin with a
separate trace made as short as possible, TI also recommends to route the trace that connects the VIN pin to
the input voltage as close as possible to RSEN. Route this trace away from the inductor and the switch node
(where D1, Q1, and L1 connect). For the voltage loop, keep RFBB/T close to the LM3017 and run a trace as close
as possible to the positive side of CO. As with the ISEN line, the FB line must be routed away from the inductor
and the switch node. These measures minimize the length of high impedance lines and reduce noise pickup.
10.1.3 Compact Layout
The most important layout rule is to keep the AC current loops as small as possible. Figure 30 shows the current
flow of a boost converter. The top schematic shows a dotted line which represents the current flow during onstate and the middle schematic shows the current flow during off-state. The bottom schematic shows the currents
referred to as AC currents. They are the most critical ones because current is changing in very short time
periods. The dotted line traces of the bottom schematic are the ones to make as short as possible. In a boost
regulator the primary switching loop consists of the output capacitor, diode and MOSFET. Minimizing the area of
this loop reduces the stray inductances and minimizes noise and possible erratic operation (see Layout
Examples). The output capacitor(s) must be placed as close as possible to the diode cathode and MOSFET
GND.
28
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Layout Guidelines (continued)
Figure 30. Current Flow in a Boost Application
10.1.4 Ground Plane and Vias
A ground plane in the printed-circuit board is recommended as a means to connect the quiet end (input voltage
ground side) of the input filter capacitor to the output filter capacitors and the PGND pin of the controller. Connect
all the low power ground connections directly to the regulator AGND. Connect the AGND and PGND pins
together through a copper area covering the entire underside of the device. Place several vias in this underside
copper area to ground plane. If a via is required to connect the sensing resistor to the ISEN pin, then place that
via in the inner side of the sensing resistor such that no current flow occurs. Place several vias from the ground
side of the output capacitor(s) to ground place, that minimizes the path for AC current. The PGND and AGND
pins have to be connected to the same ground very close to the IC. To avoid ground loop currents attach all the
grounds of the system only at one point.
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10.2 Layout Examples
Figure 31. Layout Example (a) Top Layer, (b) Bottom Layer
10.3 Thermal Considerations
The majority of power dissipation and heat generation comes from FETs and diode. Selecting MOSFETs with
exposed pads aids the power dissipation of these devices. Careful attention to RDS(on) at high temperature
must be observed. Diode data sheets provide a typical junction-to-ambient thermal resistance RθJA, which can be
used to estimate the operating die temperature of the Schottky. Multiplying the power dissipation by RθJA gives
the temperature rise. The diode case size can then be selected to maintain the Schottky diode temperature
below the operational maximum. Larger case sizes generally have lower RθJA and lower forward voltage drop.
30
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• AN-1286 Compensation for the LM3478 Boost Controller (SNVA067)
• AN-1994 Modeling and Design of Current Mode Control Boost Converters (SNVA408)
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
Thunderbolt is a trademark of Intel Corporation.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LM3017LE/NOPB
ACTIVE
WQFN
NKL
10
1000
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 125
SK6B
LM3017LEX/NOPB
ACTIVE
WQFN
NKL
10
4500
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 125
SK6B
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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