LM3100EVAL

User's Guide SNVA146C – January 2006 – Revised April 2013 AN-1443 LM3100 Demonstration Board Reference Design 1 Introduction The LM3100 synchronous rectifier buck regulator IC features all functions needed to implement a cost effective, efficient, buck regulator capable of supplying 1.5A to the load. With minimum external component count, very small overall board space is required for a typical application. The LM3100 works well with ceramic output capacitors and contains dual, 40 V N-Channel synchronous switches. The part is available in a thermally enhanced HTSSOP-20 package. The Constant ON-Time (COT) regulation scheme requires no loop compensation, results in fast load transient response, and simplifies circuit implementation. The controller does not rely on output capacitor ESR for stability, while maintaining the simplicity of COT control. The operating frequency remains nearly constant with line and load variations due to the inverse relationship between the input voltage and the ON-Time. Protection features include VCC under-voltage lockout, thermal shutdown and gate drive under-voltage lockout. This demonstration board provides a 3.3 V output with 1.5A load capability from a wide input voltage range of 8 V to 36 V. The design is optimized for overall conversion efficiency and set to run at 250 kHz. This application note contains the demo board schematic, PCB layout, Bill of Materials and circuit design descriptions. Performance and typical operating waveforms are also provided for reference. 2 Demonstration Board Schematic Figure 1. LM3100 Demonstration Board Schematic All trademarks are the property of their respective owners. SNVA146C – January 2006 – Revised April 2013 Submit Documentation Feedback AN-1443 LM3100 Demonstration Board Reference Design Copyright © 2006–2013, Texas Instruments Incorporated 1 Demonstration Board Schematic www.ti.com Figure 2. LM3100 Demonstration Board PCB Top Overlay Figure 3. LM3100 Demonstration Board Top View Figure 4. LM3100 Demonstration Board Bottom View 2 AN-1443 LM3100 Demonstration Board Reference Design SNVA146C – January 2006 – Revised April 2013 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Demonstration Board Quick Setup Procedures www.ti.com 3 Demonstration Board Quick Setup Procedures Step 4 Description Connect power supply to VIN terminals VIN range 8 V to 36 V 2 Connect load to the VOUT terminals IOUT range 0A to 1.5A 3 SD (JP1) should be left open for normal operation Short this jumper to shutdown 4 Set VIN = 18 V, with no load applied, check VOUT with voltmeter Nominal 3.3 V 5 Apply 1.5A load and check VOUT again Nominal 3.3 V 6 Short output terminals and check short circuit current with an ammeter Nominal 2.2A 7 Short SD jumper to check for shutdown function Demonstration Board Performance Characteristic Description Symbol Min Typ Max Unit Input Voltage VIN 8 18 36 V Output Voltage VOUT 3.2 3.3 3.4 V Output Current IOUT 0 - 1.5 A Output Voltage Ripple VOUT(Ripple) - - 50 mVP-P Output Voltage Regulation ΔVOUT Efficiency Output Short Current Limit 5 Notes 1 Condition All VIN and IOUT conditions -1.5 +1.5 % VIN = 8 V 88 93 % VIN = 36 V (IOUT = 0.1A to 1.5A) 73 82 ILIM-SC 2.2 A Design Procedure The LM3100 employs a Constant ON-Time (COT) regulation scheme that requires no loop compensation. That makes designing with this device much easier compared with other devices available on the market. The LM3100 integrates all key components in a single package including both the high-side and low-side power MOSFETs. For a typical application a minimum number of passive external components are required. Below is a design example for this demonstration board with the schematic shown on the front page. Design Parameters: VIN = 8 V to 36 V, Typical 18 V VOUT = 3.3 V IOUT = 1.5A Step 1. Calculate the feedback divider The ratio of the feedback divider can be calculated from Equation 1: R3 R4 = VOUT 0.8 -1 (1) As a general practice, R3 and R4 should be chosen from standard 1% resistor values in the range of 1.0 kΩ - 10 kΩ which satisfy the above ratio. Select R4 = 2.21kΩ and VOUT = 3.3 V, R3 = § VOUT - 1· 2.21 k: = 6.91 k: © 0.8 ¹ SNVA146C – January 2006 – Revised April 2013 Submit Documentation Feedback (2) AN-1443 LM3100 Demonstration Board Reference Design Copyright © 2006–2013, Texas Instruments Incorporated 3 Design Procedure www.ti.com Step 2. Calculate the ON-Time Setting Resistor The minimum value for the ON-Time setting resistor, R1 can be calculated from Equation 3: R1 t 200 ns x VIN(MAX) 1.3 x 10-10 (3) where 200ns is the recommended minimum ON-Time for reliable operation. Alternatively, Equation 4 can be used to calculate the value of the ON-Time setting resistor if a specific switching frequency is desired, as long as the limitation in Equation 3 is met. FSW = VOUT 1.3 x 10-10 x R1 (4) where FSW is the switching frequency of the converter. In order to help you determine the appropriate ON-Time setting resistor, a selector chart is shown in Figure 5. 4000 R1 = 100 k: 3000 TON (ns) R1 = 50 k: 2000 R1 = 25 k: 1000 0 0 5 10 15 20 25 30 35 40 VIN (V) Figure 5. TON vs VIN For the demonstration board design, R1 = 100 kΩ is selected and its equivalent to an ON-Time of 755 ns at VIN = 18 V and FSW is about 250kHz. Step 3. Determine the Inductance of the Power Inductor The main parameter affected by the inductor is the output current ripple amplitude (IOR). The maximum allowable IOR must be determined at both the minimum and maximum nominal load currents. At minimum load current, the lower peak must not reach 0A. At maximum load current, the upper peak must not exceed the current limit threshold (1.9A). The allowable ripple current is calculated from the following Equation 5: IOR(MAX) = 2 x IOUT (5) and Equation 6: IOR(MAX) = 2 x (1.9 - IOUT(max)) 4 (6) AN-1443 LM3100 Demonstration Board Reference Design SNVA146C – January 2006 – Revised April 2013 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Design Procedure www.ti.com The lesser of the two ripple amplitudes calculated above is then used to calculate the required inductance shown in Equation 7: L1 = VOUT x (VIN - VOUT) IOR x FSW x VIN (7) Substitute previous results into the equation with recommended IOR = 0.7A, L1 = 3.3 x (18 ± 3.3) 0.7 x 250 x 103 x 18 (8) From the above calculations, the inductance required is 15 µH. An inductor selector chart is provided in Figure 6. 25.0 R1 = 100 k: INDUCTANCE (PH) 20.0 15.0 R1 = 50 k: 10.0 5.0 R1 = 25 k: 0.0 0 10 20 30 40 VIN (V) Figure 6. Inductor Selector for VOUT = 3.3 V Step 4. Determine Values of Other Components C8: The capacitor on the VCC output provides not only noise filtering and stability, but also prevents false triggering of the VCC UVLO at the buck switch on/off transitions. For this reason, C8 should be no smaller than 0.68 µF for stability, and should be a good quality, low ESR, ceramic capacitor. In the demonstration board, a 0.68 µF capacitor was used. C10 and C11: The Output capacitor should generally be no smaller than 10 µF. Experimentation is usually necessary to determine the minimum value for CO, as the nature of the load may require a larger value. A load which creates significant transients requires a larger value for CO than a fixed load. In the demonstration board, two 22 µF capacitors are connected in parallel to provide low ripple output. C1 and C2: The Input capacitor’s purpose is to supply most of the switch current during the ON-Time, and limit the voltage ripple at VIN, on the assumption that the voltage source feeding VIN has an output impedance greater than zero. If the source’s dynamic impedance is high (effectively a current source), it supplies the average input current, but not the ripple current. At maximum load current, when the buck switch turns on, the current into VIN suddenly increases to the lower peak of the inductor’s ripple current, ramps up to the peak value, then drop to zero at turn-off. The average current during the ON-Time is the load current. For a worst case calculation, assume the input capacitor must supply this average load current during the maximum ON-Time. The total input capacitance required is calculated from: CIN = IO x tON 'V (9) where IOUT is the load current, tON is the maximum ON-Time, and ΔV is the allowable ripple voltage at VIN. The demonstration board uses two 10 µF capacitors in parallel. C3: C3’s purpose is to help avoid transients and ringing due to long lead inductance at VIN. A low ESR, 0.1 µF ceramic chip capacitor is recommended, located close to the LM3100. SNVA146C – January 2006 – Revised April 2013 Submit Documentation Feedback AN-1443 LM3100 Demonstration Board Reference Design Copyright © 2006–2013, Texas Instruments Incorporated 5 PCB Layout Guide www.ti.com C4: The recommended value for the Booststrap capacitor is 0.033µF. A high quality ceramic capacitor with low ESR is recommended as C4 supplies a surge current to charge the buck switch gate at turn-on. A low ESR also helps ensure a complete recharge during each off-time. C5: The capacitor at the SS pin determines the soft-start rise time, that is, the time for the reference voltage at the regulation comparator, and the output voltage, to reach their final value. The capacitor value is determined by Equation 10: C5 = tSS x 8 PA 0.8V (10) For this case, a soft-start capacitor of 10 nF is used and the corresponding soft-start time is about 1 ms. C9: If the regulated output voltage is higher than 1.6 V, this feedback cap is needed for Discontinuous Conduction Mode to improve the output ripple performance, the recommended value for CFB is 10 nF. 6 PCB Layout Guide The LM3100 regulation, over-voltage, and current limit comparators are very fast, and responds to short duration noise pulses. Therefore, layout considerations are critical for optimum performance. The layout must be as neat and compact as possible, and all of the components must be as close as possible to their associated pins. The loop formed by input capacitors, C1 and C2, the high and low-side switches internal to the IC, and the PGND pin should be as small as possible. The PGND connection to C1 and C2 should be as short and direct as possible. There should be several vias connecting the C1 and C2 ground terminal to the ground plane placed as close to the capacitor as possible. The boost capacitor should be connected as close to the SW and BST pins as possible. The feedback divider resistors and the feedback capacitor, C9 should be located close to the FB pin. A long trace run from the top of the divider to the output is generally acceptable since this is a low impedance node. Ground the bottom of the divider directly to the PGND pins. The output capacitor, C10 and C11, should be connected close to the load and tied directly into the ground plane. The inductor, L1 should connect close to the SW pin with as short a trace as possible to help reduce the potential for EMI (electro-magnetic interference) generation. If it is expected that the internal dissipation of the LM3100 will produce excessive junction temperatures during normal operation, good use of the PC board’s ground plane can help considerably to dissipate heat. The exposed pad on the bottom of the IC package can be soldered to a ground plane and that plane should extend out from beneath the IC to help dissipate heat. The exposed pad is internally connected to the IC substrate. Additionally the use of wide PC board traces, where possible, can help conduct heat away from the IC. Using numerous vias to connect the die attach pad to an internal ground plane is a good practice. Judicious positioning of the PC board within the end product, along with the use of any available air flow (forced or natural convection) can help reduce the junction temperature. 6 AN-1443 LM3100 Demonstration Board Reference Design SNVA146C – January 2006 – Revised April 2013 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated PCB Layout Guide www.ti.com Table 1. Bill of Materials (BOM) Designation Description Size Manufacture Part No Vendor C1, C2 Cap MLCC 10 µF 50 V Y5V C3 Cap MLCC 0.1 µF 50 V X7R 1210 ECJ4YF1H106Z Panasonic 0805 ECJ2FB1H104M Panasonic GRM21BR71H104KA01B Murata C4 Cap MLCC 33 nF 50 V X7R 0805 C5, C6, C9 Cap MLCC 10 nF 50 V X7R 0805 C12 Cap MLCC 47 nF 50 V X7R 0805 VJ0805Y104KXAA Vishay ECJ2VB1H333K Panasonic VJ0805Y333KXAA Vishay ECJ2VB1H103K Panasonic VJ0805Y103KXAA Vishay ECJ2FB1H473K Panasonic VJ0805Y473KXAA Vishay C8 Cap MLCC 680 nF 16 V X7R 0805 GRM219R71C684KA01B Murata C10, C11 Cap MLCC 22 µF 10 V X5R 1210 ECJ4YB1A226M Panasonic R1 Resistor Chip 100 kΩ F 0805 CRCW08051003F Vishay R2 Resistor Chip 200 kΩ F 0805 CRCW08052003F Vishay R3 Resistor Chip 6.81 kΩ F 0805 CRCW08056811F Vishay R4 Resistor Chip 2.21 kΩ F 0805 CRCW08052211F Vishay L1 Inductor 15 µH 2.6A 10.5x10.3x3.1 CDRH103RNP-150NC-B Sumida U1 IC LM3100 HTSSOP-20 LM3100 Texas Instruments PCB LM3100 Demoboard SNVA146C – January 2006 – Revised April 2013 Submit Documentation Feedback Texas Instruments AN-1443 LM3100 Demonstration Board Reference Design Copyright © 2006–2013, Texas Instruments Incorporated 7 Typical Performance and Waveforms 7 www.ti.com Typical Performance and Waveforms All curves and waveforms taken at VIN = 18 V with the demonstration board and TA = 25°C, unless otherwise specified. Efficiency vs Load Current (VOUT = 3.3 V) VOUT Regulation vs Load Current (VOUT = 3.3 V) 100 VIN = 8V EFFICIENCY (%) 90 80 VIN = 18V VIN = 36V 70 60 50 40 0 0.3 0.6 0.9 1.2 1.5 LOAD CURRENT (A) Continuous Mode Operation (VOUT = 3.3 V, 1.5A Loaded) 8 AN-1443 LM3100 Demonstration Board Reference Design Discontinuous Mode Operation (VOUT = 3.3 V, 0.15A Loaded) SNVA146C – January 2006 – Revised April 2013 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Typical Performance and Waveforms www.ti.com DCM to CCM Transition (VOUT = 3.3 V, 0.15A - 1.5A Load) Load Transient (VOUT = 3.3 V, 0.15A - 1.5A Load, Current slew-rate: 2.5A/µs) Power Up (VOUT = 3.3 V, 1.5A Loaded) Enable Transient (VOUT = 3.3 V, 1.5A Loaded) Shutdown Transient (VOUT = 3.3 V, 1.5A Loaded) SNVA146C – January 2006 – Revised April 2013 Submit Documentation Feedback AN-1443 LM3100 Demonstration Board Reference Design Copyright © 2006–2013, Texas Instruments Incorporated 9 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS16949. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2013, Texas Instruments Incorporated