User's Guide
SNVA118B – September 2005 – Revised April 2013
AN-1390 LM3203 Evaluation Board
1
Introduction
The LM3203 evaluation board is a working demonstration of a buck converter. This document contains
information about the board. For further information on buck converter topology and component selection,
see the device-specific data sheet.
2
General Description
The LM3203 converts high input voltages to lower output voltages with high efficiency. It does this through
a inductor based switching topology, applying the input voltage to the inductor for a certain portion of the
cycle. The duty cycle in pulse width modulation (PWM) mode will be VOUT / VIN, which can be seen on the
SW pin.
There are three modes of operation. These are fixed frequency PWM, forced bypass, and shutdown
mode. Setting the BYP pin low (1.2 V) places the device in forced bypass mode. Setting the EN pin low (1.2 V) enables normal operation.
At the PWM mode, the output voltage is setting by the voltage of the VCON pin, as in Equation 1:
VOUT = (( R1 + R2 ) / R2 ) × VCON
3
(1)
Operating Conditions
The board will operate under the following conditions:
2.7 V ≤ VIN ≤ 5.5 V
0.267 V ≤ VCON ≤ 1.2 V
0.8 V ≤ VOUT ≤ 3.6 V
0 mA ≤ IOUT ≤ 500 mA
4
Schematic
VIN
C5
0.1 PF
C1
10 PF
PVIN VDD
EN
BYP
L1
3.3 PH
BYPOUT
VOUT
SW
C3
10pF
LM3203
R1
267 k:
FB
VCON
0.267V to 1.20V
VCON
PGND
SGND
C2
4.7 PF
R2
133 k:
Figure 1. Typical Operating Circuit
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SNVA118B – September 2005 – Revised April 2013
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AN-1390 LM3203 Evaluation Board
1
Board Layout
5
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Board Layout
3.3uH
4.7uF
10uF
R6
U1
C5
LM3203
0.1uF
R8
Vcon
C
BYP
EN
B
E
D
Figure 2. Top Layer
2
AN-1390 LM3203 Evaluation Board
SNVA118B – September 2005 – Revised April 2013
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Board Layout
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xxxxxxxxx-001 rev A
LM3203
C4
R2
0:
133 k:
R0
R7
10 pF
C3
C6 R3
267 k:
R1
R5
R4
0:
Figure 3. Bottom Layer
SNVA118B – September 2005 – Revised April 2013
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AN-1390 LM3203 Evaluation Board
3
Board Schematic
6
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Board Schematic
R6
R7
0:
VIN
C5
0.1 PF
VDD
BYPOUT
PVIN
C1
10 PF
EN
E
R8
L1
3.3 PH
LM3203
R5
R3
0:
C
C2
4.7 PF
VCON
R4
C6
SGND
R2
133 k:
VOUT
SW
BYP
B
FB
PGND
C4
GND
R1
267 k:
C3
10 pF
R0
0:
D
Figure 4. Complete Evaluation Board Schematic
7
PCB Guidelines
For your application circuit, proper layout for the buck regulator should be implemented by following a few
simple guidelines. (Also, see the Board Layout Considerations section in the device-specific data sheet.)
• Place C1 right next to the device between PVIN and PGND pin.
• Place C5 right next to the device between VDD and SGND pin.
• Make the traces drawn with heavy lines, which are Power lines, as short and as wide as possible.
• Making the traces drawn with heavy lines on the same layer should be good. However, place as many
vias as possible if traces are on multiple layers.
• Leave R7 unconnected, and short R6 and R5 when BYPASS mode is NOT required.
4
AN-1390 LM3203 Evaluation Board
SNVA118B – September 2005 – Revised April 2013
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Bill of Materials (BOM)
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8
Bill of Materials (BOM)
Table 1. Bill of Materials
Designator
Footprint
Manufacture
Manufacture No
Description
C1 (input C)
1206 (3216)
TDK
C3216JB1A106K
10 µF, 10 V, 20%
C2 (output C)
1206 (3216)
TDK
C2012JB0J475K
4.7 µF, 6.3 V, 20%
C3
0603 (1608)
10 pF
C4
0603 (1608)
optional
C5 (input C)
0402 (1005)
0.1 µF, 10 V, 20%
C6
0603 (1608)
L1 (inductor)
optional
Coilcraft
DO3314-332
3.3 µH inductor, 1.4A Isat, 0.26 Ωmax.
R0
0603 (1608)
0Ω
R1
0603 (1608)
267 kΩ
R2
0603 (1608)
133 kΩ
R3
0603 (1608)
0Ω
R4
0603 (1608)
optional
R5
0603 (1608)
optional
R6
0603 (1608)
optional
R7
0603 (1608)
0Ω
R8
0603 (1608)
optional
COMMON TO ALL
VIN banana jack - red
Johnson Components
108-0902-001
conn jack banana insul nylon red
VOUT banana jack - yellow
Johnson Components
108-0907-001
conn jack banana insul nylon yellow
GND banana jack - black
Johnson Components
108-0903-001
conn jack banana insul nylon black
9
Connection Diagrams
SGND
A2
SGND
A2
A3 BYPOUT
VDD A1
VCON B1
FB C1
B3 PVIN
PVIN B3
C3 SW
SW C3
D3 PGND
BYP D1
A1 VDD
BYPOUT A3
B1 VCON
C1 FB
D1 BYP
PGND D3
D2
EN
D2
EN
Figure 5. Top View
Figure 6. Bottom View
Figure 7. 10–Bump Thin DSBGA Package, Large Bump
SNVA118B – September 2005 – Revised April 2013
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AN-1390 LM3203 Evaluation Board
5
Connection Diagrams
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Table 2. Pin Descriptions
6
Pin No
Name
A1
VDD
Analog Supply Input. A 0.1 µF ceramic capacitor is recommended to be placed as close to this pin as
possible.
Description
Voltage Control Analog input. VCON controls VOUT in PWM mode. Do not leave floating.
B1
VCON
C1
FB
D1
BYP
D2
EN
D3
PGND
C3
SW
Switching Node connection to the internal PFET switch and NFET synchronous rectifier. Connect to an
inductor with a saturation current rating that exceeds the maximum Switch Peak Current Limit specification of
the LM3203.
B3
PVIN
Power Supply Voltage Input to the internal PFET switch and Bypass FET.
A3
BYPOUT
A2
SGND
Feedback Analog Input. Connect to the external resistor divider.
Bypass. Use this digital input to command operation in Bypass mode. Set the BYP pin high (> 1.2 V ) for
Bypass mode. Set BYP low (< 0.4 V ) for PWM operation.
Enable Input. Set this digital input high (> 1.2 V) after Vin > 2.7 V for normal operation. For shutdown, set low
(< 0.4 V).
Power Ground
Bypass FET Drain. Connect to the output capacitor. Connect this pin to VDD when Bypass mode is NOT
required. Do not leave floating.
Analog and Control Ground
AN-1390 LM3203 Evaluation Board
SNVA118B – September 2005 – Revised April 2013
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Copyright © 2005–2013, Texas Instruments Incorporated
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