LM3203
www.ti.com
SNVS355D – MAY 2005 – REVISED APRIL 2013
LM3203 Step-Down DC-DC Converter with Bypass Mode for CDMA / WCDMA RF Power
Amplifiers
Check for Samples: LM3203
FEATURES
DESCRIPTION
•
•
The LM3203 is a DC-DC converter optimized for
powering RF power amplifiers (PAs) from a single
Lithium-Ion cell. However, they may be used in many
other applications. It steps down an input voltage of
2.7V to 5.5V to an adjustable output voltage of 0.8V
to 3.6V. The output voltage is set using a VCON
analog input and external resistor dividers for
optimizing efficiency of the RF PA at various power
levels.
1
2
•
•
•
•
•
•
•
•
•
2MHz (Typ.) PWM Switching Frequency
Operates from a Single Li-Ion Cell (2.7V to
5.5V)
Adjustable Output Voltage (0.8V to 3.6V)
500mA Maximum Load Capability (PWM and
Bypass Mode)
PWM / Forced Bypass Mode
Low RDSON Bypass FET: 85mΩ (Typ.)
High Efficiency (96% typ. at 3.6VIN, 3.2VOUT at
150mA)
Fast Turn-On Time When Enabled (50µs typ.),
3GPP Compliant
10-Pin DSBGA Package
Current Overload Protection
Thermal Overload Protection
The LM3203 offers 3 modes for mobile phones and
similar RF PA applications. Fixed-frequency PWM
mode minimizes RF interference. Bypass mode turns
on an internal bypass switch to power the PA directly
from the battery. Shutdown mode turns the device off
and reduces battery consumption to 0.1µA (typ.).
The LM3203 is available in a 10-pin lead free DSBGA
package. A high switching frequency (2MHz) allows
use of tiny surface-mount components.
APPLICATIONS
•
•
•
•
Cellular Phones
Hand-Held Radios
RF PC Cards
Battery Powered RF Devices
TYPICAL APPLICATION
VIN
2.7V to 5.5V
C1
10 PF
C5
0.1 PF
VDD
PVIN
BYPOUT
VOUT
0.8V to 3.6V
L1
3.3 PH
SW
C3
10 pF
LM3203
R1
267k
EN
VCON
0.267V to 1.20V
C2
4.7 PF
FB
BYP
R2
133k
VCON
SGND
PGND
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2013, Texas Instruments Incorporated
LM3203
SNVS355D – MAY 2005 – REVISED APRIL 2013
www.ti.com
CONNECTION DIAGRAMS
SGND
A2
SGND
A2
A3 BYPOUT
VDD A1
VCON B1
FB C1
BYPOUT A3
B3 PVIN
PVIN B3
C3 SW
SW C3
D3 PGND
BYP D1
A1 VDD
B1 VCON
C1 FB
D1 BYP
PGND D3
D2
EN
D2
EN
Figure 1. Top View
Figure 2. Bottom View
10–Bump Thin DSBGA Package, Large Bump.
See NS Package Number YPA0010NHA.
PIN DESCRIPTION
Pin #
Name
A1
VDD
Analog Supply Input. A 0.1 µF ceramic capacitor is recommended to be placed as close to this pin as
possible. (Figure 31)
Description
B1
VCON
Voltage Control Analog input. VCON controls VOUT in PWM mode. (Refer to Setting the Output Voltage) Do not
leave floating.
C1
FB
D1
BYP
Feedback Analog Input. Connect to the external resistor divider. (Figure 31)
D2
EN
D3
PGND
C3
SW
Switching Node connection to the internal PFET switch and NFET synchronous rectifier.
Connect to an inductor with a saturation current rating that exceeds the maximum Switch Peak Current Limit
specification of the LM3203.
B3
PVIN
Power Supply Voltage Input to the internal PFET switch and Bypass FET. (Figure 31)
A3
BYPOUT
A2
SGND
Bypass. Use this digital input to command operation in Bypass mode. Set BYP low for PWM operation.
Enable Input. Set this digital input high after Vin >2.7V for normal operation. For shutdown, set low.
Power Ground
Bypass FET Drain. Connect to the output capacitor. (Figure 31) Connect this pin to VDD when Bypass mode is
NOT required. Do not leave floating.
Analog and Control Ground
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM3203
LM3203
www.ti.com
SNVS355D – MAY 2005 – REVISED APRIL 2013
ABSOLUTE MAXIMUM RATINGS (1) (2) (3)
−0.2V to +6.0V
VDD, PVIN to SGND
−0.2V to +0.2V
PGND to SGND
(SGND −0.2V) to (VDD +0.2V) w/6.0V max
EN, FB, BYP, VCON
(PGND −0.2V) to (PVIN +0.2V) w/6.0V max
SW, BYPOUT
−0.2V to +0.2V
PVIN to VDD
Continuous Power Dissipation (4)
Internally Limited
Junction Temperature (TJ-MAX)
+150°C
−65°C to +150°C
Storage Temperature Range
Maximum Lead Temperature (Soldering, 10 sec)
ESD Rating (5)
(1)
(2)
(3)
(4)
(5)
+260°C
Human Body Model
2.0 kV
Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under
which operation of the device is ensured. Operating Ratings do not imply specified performance limits. For specified performance limits
and associated test conditions, see the Electrical Characteristics table.
All voltages are with respect to the potential at the GND pins.
If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 150°C (typ.) and
disengages at TJ = 130°C (typ.).
The Human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin. (MIL-STD-883 3015.7) . TI
recommends that all integrated circuits be handled with appropriate precautions.
OPERATING RATINGS (1) (2)
Input Voltage Range
Recommended Load Current
2.7V to 5.5V
PWM Mode
0mA to 500mA
Bypass Mode
0mA to 500mA
−30°C to +125°C
Junction Temperature (TJ) Range
Ambient Temperature (TA) Range (3)
(1)
(2)
(3)
−30°C to +85°C
Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under
which operation of the device is ensured. Operating Ratings do not imply specified performance limits. For specified performance limits
and associated test conditions, see the Electrical Characteristics table.
All voltages are with respect to the potential at the GND pins.
In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be de-rated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP =
125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the
part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX).
THERMAL PROPERTIES
Junction-to-Ambient Thermal
100°C/W
Resistance (θJA), YPA10 Package (1)
(1)
Junction-to-ambient thermal resistance (θJA) is taken from thermal measurements, performed under the conditions and guidelines set
forth in the JEDEC standard JESD51-2. A 1" x 1", 4 layer, 1.5oz. Cu board was used for the measurements.
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM3203
3
LM3203
SNVS355D – MAY 2005 – REVISED APRIL 2013
www.ti.com
ELECTRICAL CHARACTERISTICS (1) (2)
Limits in standard typeface are for TA = TJ = 25°C. Limits in boldface type apply over the full operating ambient temperature
range (−30°C ≤ TA = TJ ≤ +85°C). Unless otherwise noted, specifications apply to the LM3203 with: PVIN = VDD = EN = 3.6V,
BYP = 0V, VCON = 0.267V.
Symbol
Parameter
Conditions
Min
Max
Units
5.5
V
0.267
0.284
V
1.200
1.224
V
100
150
mV
EN = SW = BYPOUT = VCON = FB = 0V
0.1
3
µA
VCON = 0.267V, FB = 2V, BYPOUT = 0V, No
Switching
675
780
µA
VIN
Input Voltage Range (3)
PVIN = VDD = VIN
VFB,
MIN
Feedback Voltage at
Minimum Setting
VCON = 0.267V, VIN = 3.6V
0.250
VFB,
MAX
Feedback Voltage at
Maximum Setting
VCON = 1.20V, VIN = 4.2V
1.176
OVP
Over-Voltage Protection
Threshold
See (4)
ISHDN
Shutdown Supply
Current (5)
IQ_PWM
DC Bias Current into
VDD
IQ_BYP
Typ
2.7
BYP = 3.6V, VCON = 0.5V, No Load
680
780
µA
RDSON (P)
Pin-Pin Resistance for
P-FET
ISW = 500mA
320
450
mΩ
RDSON (N)
Pin-Pin Resistance for
N-FET
ISW = − 200mA
310
450
mΩ
RDSON
Pin-Pin Resistance for
Bypass FET
IBYPOUT = 500mA
85
120
mΩ
700
820
940
mA
800
1000
1200
mA
2
2.2
MHz
(BYP)
(6)
ILIM-PFET
Switch Current Limit
See
ILIM-BYP
Bypass FET Current
Limit
See (7)
FOSC
Internal Oscillator
Frequency
1.7
VIH
Logic High Input
Threshold for EN, BYP
1.20
VIL
Logic Low Input
Threshold for EN, BYP
IPIN
Pin Pull Down Current
for EN, BYP
Gain
VCON to VOUT Gain
ZCON
VCON Input Resistance
(1)
(2)
(3)
(4)
(5)
(6)
(7)
4
EN, BYP = 3.6V
VCON = 1.2V
V
5
0.4
V
10
µA
1
V/V
1
MΩ
All voltages are with respect to the potential at the GND pins.
Min and Max limits are specified by design, test, or statistical analysis. Typical numbers are not ensured, but do represent the most
likely norm.
The LM3203 is designed for mobile phone applications where turn-on after power-up is controlled by the system controller and where
requirements for a small package size overrule increased die size for internal Under Voltage Lock-Out (UVLO) circuitry. Thus, it should
be kept in shutdown by holding the EN pin low until the input voltage exceeds 2.7V.
Over-Voltage protection (OVP) threshold is the voltage above the nominal VOUT where the OVP comparator turns off the PFET switch
while in PWM mode. The OVP threshold will be the value of the threshold at the FB voltage times the resistor divider ratio. In the
Figure 31, 100mV (typ.) × ((267K + 133K) ÷ 133K).
Shutdown current includes leakage current of PFET and Bypass FET.
Electrical Characteristics table reflects open loop data (FB=0V and current drawn from SW pin ramped up until cycle by cycle current
limit is activated). Refer to Typical Performance Characteristics (Open/Closed Loop Current Limit vs Temperature (PWM Mode) curve)
for closed loop data and its variation with regards to supply voltage and temperature. Closed loop current limit is the peak inductor
current measured in the application circuit by increasing output current until output voltage drops by 10%.
Bypass FET current limit is defined as the load current at which the FB voltage is 1V lower than VIN.
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM3203
LM3203
www.ti.com
SNVS355D – MAY 2005 – REVISED APRIL 2013
SYSTEM CHARACTERISTICS
The following spec table entries are specified by design over ambient temperature range if the component values in the
typical application circuit are used. These parameters are not specified by production testing.
Symbol
Parameter
TSTARTUP Time for VOUT to rise to
3.4V in PWM mode
Conditions
VIN = 4.2V, COUT = 4.7µF,
RLOAD = 10Ω
L = 3.3uH (ISAT > 0.94A)
EN = Low to High
Min
Typ
Max
Units
50
µs
30
µs
TRESPONSE Time for VOUT to Rise
from 0.8V to 3.6V in
PWM Mode
VIN = 4.2V, COUT = 4.7µF,
RLOAD = 10Ω
L = 3.3uH (ISAT > 0.94A)
CCON
VCON Input Capacitance
VCON = 1V,
Test frequency = 100kHz
15
pF
TON_BYP
Bypass FET Turn On
Time In Bypass Mode
VIN = 3.6V, VCON = 0.267V,
COUT = 4.7µF, RLOAD = 10Ω
BYP = Low to High
30
µs
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM3203
5
LM3203
SNVS355D – MAY 2005 – REVISED APRIL 2013
www.ti.com
TYPICAL PERFORMANCE CHARACTERISTICS
(Circuit in Figure 31, PVIN = VDD = EN = 3.6V, BYP = 0V, TA = 25°C, unless otherwise noted)
Quiescent Current
vs
Supply Voltage
(VCON = 0.267V, FB = 2V, No Load)
Shutdown Current
vs
Temperature
(EN = 0V)
1.0
SHUTDOWN CURRENT (PA)
0.9
0.8
EN = 0V
VCON = 0V
FB = SW = 0V
VIN = 5.5V
0.7
0.6
VIN = 3.6V
0.5
0.4
VIN = 4.2V
0.3
0.2
VIN = 2.7V
0.1
0.0
-40 -20
0
20
40
60
80 100 120 140
JUNCTION TEMPERATURE (oC)
Figure 3.
Figure 4.
Switching Frequency Variation
vs
Temperature
(VOUT = 1.5V, IOUT = 200 mA)
Output Voltage
vs
Supply Voltage
(VOUT = 1.5V, VCON = 0.5V)
Figure 5.
Figure 6.
(VIN
Output Voltage
vs
Temperature
= 3.6V, VOUT = 1.5V, VCON = 0.5V)
Figure 7.
6
(VIN
Output Voltage
vs
Temperature
= 4.2V, VOUT = 3.4V, VCON = 1.13V)
Figure 8.
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM3203
LM3203
www.ti.com
SNVS355D – MAY 2005 – REVISED APRIL 2013
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
(Circuit in Figure 31, PVIN = VDD = EN = 3.6V, BYP = 0V, TA = 25°C, unless otherwise noted)
Open/Closed Loop Current Limit
vs
Temperature
(PWM Mode)
Output Voltage
vs
Output Current
(BYP Mode, VIN = BYP = 3.6V)
DROPOUT VOLTAGE (V)
0.0
0.2
TA = 85°C
0.4
TA = -30°C
0.6
TA = 25°C
0.8
Max Load
Capability
500 mA
ILIM-BYP
= 965 mA
1.0
0
200
400
600
800
1000
1200
OUTPUT CURRENT (mA)
Figure 9.
Figure 10.
Low VCON Voltage
vs
Output Voltage
(RLOAD = 15Ω)
Efficiency
vs
Output Voltage
(VIN = 3.9V)
1.6
OUTPUT VOLTAGE (V)
1.4
1.2
1
0.8
VIN = 5.5V
0.6
0.4
VIN = 5.0V
0.2
VIN = 4.7V
0
0
0.1
0.2
0.3
0.4
0.5
0.6
VCON VOLTAGE (V)
Figure 11.
Figure 12.
Efficiency
vs
Output Current
(VOUT = 1.5V, VCON = 0.5V)
Efficiency
vs
Output Current
(VOUT = 3.25V, VCON = 1.08V)
Figure 13.
Figure 14.
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM3203
7
LM3203
SNVS355D – MAY 2005 – REVISED APRIL 2013
www.ti.com
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
(Circuit in Figure 31, PVIN = VDD = EN = 3.6V, BYP = 0V, TA = 25°C, unless otherwise noted)
8
Logic High Threshold Voltage
Forced Bypass Operation
(VIN = 3.0V)
Figure 15.
Figure 16.
Load Transient Response
(VOUT = 1.5V, VCON = 0.5V)
Load Transient Response
(VOUT = 3.4V, VCON = 1.13V)
Figure 17.
Figure 18.
Startup
(VIN = 4.2V, VOUT = 3.4V, 10Ω)
Shutdown Response
(VIN = 4.2V, VOUT = 3.4V, 10Ω)
Figure 19.
Figure 20.
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM3203
LM3203
www.ti.com
SNVS355D – MAY 2005 – REVISED APRIL 2013
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
(Circuit in Figure 31, PVIN = VDD = EN = 3.6V, BYP = 0V, TA = 25°C, unless otherwise noted)
Line Transient Response
(VIN = 3.0V to 3.6V)
VCON Voltage Response
(VIN = 4.2V, VCON = 0.5V/1.13V)
Figure 21.
Figure 22.
Timed Current Limit Response
(normal operation to short circuit)
Output Voltage Ripple
(VOUT = 1.5V, VCON = 0.5V)
VSW
2V/DIV
VOUT
1V/DIV
IL
500 mA/DIV
VSW
2V/DIV
VOUT
10 mV/DIV
AC Coupled
IL
200 mA/DIV
VIN = 3.6V
VOUT = 1.5V
RLOAD = 15:
VOUT = 1.5V
IOUT = 200 mA
400 ns/DIV
10 Ps/DIV
Figure 23.
Figure 24.
Output Voltage Ripple
(VOUT = 3.25V, VCON = 1.08V)
Output Voltage Ripple in Dropout
(VIN = 3.57V, VOUT = 3.25V, ILOAD = 200 mA)
VSW
2V/DIV
VSW
2V/DIV
VOUT
10 mV/DIV
AC Coupled
VOUT
10 mV/DIV
AC Coupled
IL
200 mA/DIV
IL
200 mA/DIV
VIN = 4.2V
VOUT = 3.25V
VIN = 3.57V
IOUT = 300 mA
VOUT = 3.25V
400 ns/DIV
IOUT = 200 mA
400 ns/DIV
Figure 25.
Figure 26.
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM3203
9
LM3203
SNVS355D – MAY 2005 – REVISED APRIL 2013
www.ti.com
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
(Circuit in Figure 31, PVIN = VDD = EN = 3.6V, BYP = 0V, TA = 25°C, unless otherwise noted)
RDSON
vs
Temperature
(P-FET)
RDSON
vs
Temperature
(N-FET)
600
600
ISW = 500 mA
ISW = - 200 mA
VIN = 2.7V
500
RDS(ON) (m )
RDS(ON) (mO)
500
400
300
VIN = 4.2V
200
VIN = 3.6V
100
-40
-20
0
20
40
60
80
100
AMBIENT TEMPERATURE (°C)
VIN = 3.6V
VIN = 2.7V
400
300
200
VIN = 4.2V
100
-40
-20
0
20
40
60
80
100
AMBIENT TEMPERATURE (°C)
Figure 27.
Figure 28.
RDSON
vs
Temperature
(Bypass FET)
Dropout Voltage
vs
Output Current
(RDC : Inductor DC Resistance)
160
IBYPOUT = 500 mA
140
RDS(ON) (m:)
VIN = 3.6V
120
VIN = 2.7V
100
80
60
40
-40
VIN = 4.2V
-20
0
20
40
60
80
100
AMBIENT TEMPERATURE (oC)
Figure 29.
10
Figure 30.
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM3203
LM3203
www.ti.com
SNVS355D – MAY 2005 – REVISED APRIL 2013
BLOCK DIAGRAM
PVIN
VDD
BYPOUT
CURRENT
SENSE
OSCILLATOR
ERROR
AMPLIFIER
FB
~
OVP
COMP
VCON
PWM
COMP
MOSFET
CONTROL
LOGIC
SW
VCON Low Voltage
DETECTOR
0.15V
BYP
MAIN CONTROL
EN
SHUTDOWN
CONTROL
SGND
PGND
OPERATION DESCRIPTION
The LM3203 is a simple, step-down DC-DC converter with a bypass switch, optimized for powering RF power
amplifiers (PAs) in mobile phones, portable communicators, and similar battery powered RF devices. It is
designed to allow the RF PA to operate at maximum efficiency over a wide range of power levels from a single
Li-Ion battery cell. It is based on current-mode buck architecture, with synchronous rectification for high
efficiency. It is designed for a maximum load capability of 500mA. Maximum load range may vary from this
depending on input voltage, output voltage and the inductor chosen.
The device has all three of the pin-selectable operating modes required for powering RF PAs in mobile phones
and other sophisticated portable device with complex power management needs. Fixed-frequency PWM
operation offers regulated output at high efficiency while minimizing interference with sensitive IF and data
acquisition circuits. Bypass mode turns on an internal FET bypass switch to power the PA directly from the
battery. This helps the RF power amplifier maintain its operating power during low battery conditions by reducing
the dropout voltage across the LM3203. Shutdown mode turns the device off and reduces battery consumption to
0.1µA (typ.).
DC PWM mode output voltage precision is +/-2% for 1.2VOUT. Efficiency is typically around 96% for a 150mA
load with 3.2V output, 3.6V input. PWM mode quiescent current is 0.675 mA (typ.). The FB pin voltage is
dynamically programmable from 0.267V to 1.2V by adjusting the voltage on the VCON. External divider resistors
can change the output voltge range. This ensures longer battery life by being able to change the PA supply
voltage dynamically depending on its transmitting power.
Additional features include current overload protection, over voltage protection and thermal shutdown.
The LM3203 is constructed using a chip-scale 10-pin DSBGA package. This package offers the smallest
possible size, for space-critical applications such as cell phones, where board area is an important design
consideration. Use of a high switching frequency (2MHz typ.) reduces the size of external components. Use of a
DSBGA package requires special design considerations for implementation. (See DSBGA Package Assembly
and Use section.) Its fine bump-pitch requires careful board design and precision assembly equipment. Use of
this package is best suited for opaque-case applications, where its edges are not subject to high-intensity
ambient red or infrared light. Also, the system controller should set EN low during power-up and other low supply
voltage conditions. (See Shutdown Mode section.)
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM3203
11
LM3203
SNVS355D – MAY 2005 – REVISED APRIL 2013
www.ti.com
VIN
2.7V to 5.5V
C1*
10 PF
C5*
0.1 PF
VDD
PVIN
BYPOUT
VOUT
0.8V to 3.6V
L1
3.3 PH
SW
SYSTEM
CONTROLLER
DAC = 0.267V-1.2V
ON/OFF
C3
10 pF
LM3203
BYP
R1
267k
FB
VCON
R2
133k
EN
SGND
C2
4.7 PF
PGND
* Place C1 close to PVIN.
** Place C5 close to VDD.
Figure 31. Typical Operating System Circuit where baseband controls the output voltage using a DAC
Circuit Operation
Referring to Figure 31, the LM3203 operates as follows. During the first part of each switching cycle, the control
block in the LM3203 turns on the internal PFET (P-channel MOSFET) switch. This allows current to flow from the
input through the inductor to the output filter capacitor and load. The inductor limits the current to a ramp with a
slope of around ( VIN - VOUT ) / L, by storing energy in a magnetic field. During the second part of each cycle, the
controller turns the PFET switch off, blocking current flow from the input, and then turns the NFET (N-channel
MOSFET) synchronous rectifier on. In response, the inductor’s magnetic field collapses, generating a voltage
that forces current from ground through the synchronous rectifier to the output filter capacitor and load. As the
stored energy is transferred back into the circuit and depleted, the inductor current ramps down with a slope
around VOUT / L. The output filter capacitor stores charge when the inductor current is going high, and releases it
when inductor current is going low, smoothing the voltage across the load.
The output voltage is regulated by modulating the PFET switch on time to control the average current sent to the
load. The effect is identical to sending a duty-cycle modulated rectangular wave formed by the switch and
synchronous rectifier at SW to a low-pass filter formed by the inductor and output filter capacitor. The output
voltage is equal to the average voltage at the SW pin.
PWM Mode
While in PWM (Pulse Width Modulation) mode, the output voltage is regulated by switching at a constant
frequency and then modulating the energy per cycle to control power to the load. Energy per cycle is set by
modulating the PFET switch on-time pulse width to control the peak inductor current. This is done by comparing
the PFET drain current to a slope-compensated reference current generated by the error amplifier. At the
beginning of each cycle, the clock turns on the PFET switch, causing the inductor current to ramp up. When the
current sense signal ramps past the error amplifier signal, the PWM comparator turns off the PFET switch and
turns on the NFET synchronous rectifier, ending the first part of the cycle. If an increase in load pulls the output
down, the error amplifier output increases, which allows the inductor current to ramp higher before the
comparator turns off the PFET. This increases the average current sent to the output and adjusts for the increase
in the load. The minimum on-time of PFET in PWM mode is 50ns (typ.).
Bypass Mode
The LM3203 contains an internal PFET switch for bypassing the PWM DC-DC converter during Bypass mode. In
Bypass mode, this PFET is turned on to power the PA directly from the battery for maximum RF output power.
Bypass mode is more efficient than operating in PWM mode at 100% duty cycle because the resistance of the
bypass PFET is less than the series resistance of the PWM PFET and inductor. This translates into higher
voltage available on the output in Bypass mode, for a given battery voltage. The part can be placed in bypass
mode by sending BYP pin high. It remains in bypass mode until BYP pin goes low.
It is recommended to connect BYPOUT pin directly to the output capacitor with a separate trace and not to the
FB pin. Connect the BYPOUT pin to the VDD pin when Bypass mode is not required.
If VCON is less than approx. 0.15V, the Bypass FET is turned off.
12
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM3203
LM3203
www.ti.com
SNVS355D – MAY 2005 – REVISED APRIL 2013
Operating Mode Selection Control
The LM3203 is designed for digital control of the operating modes using the BYP pin. Setting the BYP pin high
(>1.2V) places the device in Bypass mode. Setting BYP pin low (
工商网监
湘ICP备2023018690号
